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RealTimeTouch.com RealTimeTouch.com Patent US9639150 RealTimeTouch.com message RealTimeTouch.com RealTimeTouch.com

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Stec Inc
Stec Inc A California Corporation
Stec Inc_20100128
  

Stec Inc patents

Recent patent applications related to Stec Inc. Stec Inc is listed as an Agent/Assignee. Note: Stec Inc may have other listings under different names/spellings. We're not affiliated with Stec Inc, we're just tracking patents.

ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "S" | Stec Inc-related inventors




Date Stec Inc patents (updated weekly) - BOOKMARK this page
04/21/16Methods for managing failure of a solid state device in a caching storage
09/17/15Setting operating parameters for memory cells based on wordline address and cycle information
09/10/15High speed input/output performance in solid state devices
09/10/15System and method to cache hypervisor data
07/02/15Multi-layer pad ring for integrated circuit
03/19/15Ack-less protocol for noticing completion of read requests
03/19/15Doorbell-less endpoint-initiated protocol for storage devices
08/14/14Apparatus and determining an operating condition of a memory cell based on cycle information
08/07/14Flash storage device with read disturb mitigation
11/28/13Methods for managing failure of a solid state device in a caching storage
11/28/13Read level adjustment using soft information
10/31/13Soft information module
09/26/13System and scanning flash memories
09/26/13Power arbitration for storage devices
09/19/13System and accessing and storing interleaved data
08/29/13Determining bias information for offsetting operating variations in memory cells based on wordline address
08/29/13Systems and methods of using dynamic data for wear leveling in solid-state devices
08/15/13Reduced complexity non-binary ldpc decoding algorithm
08/01/13Systems and methods for auto-calibration of a storage memory controller
07/25/13Multi-layer input/output pad ring for solid state device controller
07/18/13Programming algorithm for improved flash memory endurance and retention
07/11/13Adjusting operating parameters for memory cells based on wordline address and cycle information
07/11/13System and operating a clustered file system using a standalone operation log
06/27/13Word-line inter-cell interference detector in flash system
06/27/13Inter-cell interference algorithms for soft decoding of ldpc codes
06/27/13System and streaming data in flash memory applications
06/20/13Systems and methods for providing load isolation in a solid-state device
06/20/13Method and system for hash key memory footprint reduction
06/06/13Data storage system with primary and secondary compression engines
05/23/13Optimized garbage collection algorithm to improve solid state drive reliability
05/16/13Erase-suspend system and method
05/16/13Transmission error detector for flash memory controller
05/16/13Dynamic ldpc code rate solution
05/09/13System and reducing memory in a multi-channel parallel encoder system
05/02/13Apparatus and stacking integrated circuits
05/02/13System and storing data using a flexible data format
05/02/13System and method to cache hypervisor data
04/18/13Reducing a number of close operations on open blocks in a flash memory
04/18/13Systems and methods for dynamic resource management in solid state drive system
02/28/13Systems and methods for reducing a number of close operations in a flash memory
02/21/13Optimal programming levels for ldpc
02/21/13Error indicator from ecc decoder
02/21/13High speed hard ldpc decoder
01/31/13Backend organization of stored data
01/31/13Multi-rate ldpc decoding
01/24/13Methods for optimizing data movement in solid state devices
12/20/12System and recovering data in a flash storage system
12/20/12Flash storage wear leveling device and method
12/13/12Flash storage accessing a boot program
11/22/12Solid-state device with load isolation
11/15/12Secure memory devices and methods of managing secure memory devices
11/15/12Managing security in solid-state devices
10/11/12Flash storage device with data integrity protection
10/11/12Data storage system with compression/decompression
10/04/12Erase-suspend system and method
09/20/12Solid state storage device with removable power backup
09/20/12Interleaved flash storage system and method
09/20/12System and determining data dependent noise calculation for a flash channel
09/20/12Apparatus and determining a read level of a memory cell based on cycle information
09/20/12Prioritized erasure of data blocks in a flash storage device
09/20/12High speed input/output performance in solid state devices
09/20/12Solid state device with allocated flash cache
09/20/12Solid-state storage device with multi-level addressing
09/20/12Apparatus and determining an operating condition of a memory cell based on cycle information
09/20/12Apparatus and determining a read level of a flash memory after an inactive period of time
Patent Packs
09/20/12Flash storage device with read disturb mitigation
09/20/12Apparatus and determining an operating condition of a memory cell based on cycle information
09/20/12Trellis-coded modulation in a multi-level cell flash memory device
09/20/12Ldpc decoding for solid state storage devices
09/20/12Apparatus and multi-mode operation of a flash memory device
09/20/12Flash storage device with read cache
09/06/12Isolation devices for high performance solid state drives
08/02/12Flash backed dram module including logic for isolating the dram
05/31/12Methods and systems for object level de-duplication for solid state devices
02/03/11System and maintaining data integrity in a flash storage device
02/03/11System and recovering data in a flash storage system
02/03/11Flash storage device with flexible data format
02/03/11System and wear-leveling in flash storage
01/27/11Interleaved flash storage system and method
01/27/11System and direct memory access in a flash storage
Patent Packs
01/27/11Flash storage with array of attached devices
01/27/11Flash storage with increased throughput
01/27/11Flash storage accessing a boot program
12/30/10Apparatus and stacking integrated circuits
08/12/10Flash backed dram module storing parameter information of the dram module in the flash
08/12/10Flash backed dram module with a selectable number of flash chips
08/12/10Flash backed dram module including logic for isolating the dram
08/12/10Staged-backup flash backed dram module
08/12/10State of health monitored flash backed dram module
08/12/10Segmented-memory flash backed dram module
08/12/10Flash backed dram module with state of health and/or status information accessible through a configuration data bus
02/18/10Supporting variable sector sizes in flash storage devices
01/28/10Parallel data storage system
12/31/09Table journaling in flash storage devices
12/31/09Enhanced mlc solid state device
12/31/09Slc-mlc combination flash storage device
12/31/09Wear leveling in flash storage devices
12/31/09Redundant data distribution in a flash storage device
12/03/09Enhanced data access in a storage device
05/14/09Removable storage device
02/19/09Enhanced erase for flash storage device
01/28/10Parallel data storage system
09/20/12Asymmetric log-likelihood ratio for mlc flash channel







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