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Stmicroelectronics Inc patents

Recent patent applications related to Stmicroelectronics Inc. Stmicroelectronics Inc is listed as an Agent/Assignee. Note: Stmicroelectronics Inc may have other listings under different names/spellings. We're not affiliated with Stmicroelectronics Inc, we're just tracking patents.

ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "S" | Stmicroelectronics Inc-related inventors




Date Stmicroelectronics Inc patents (updated weekly) - BOOKMARK this page
11/16/17 new patent  Method of making inkjet print heads by filling residual slotted recesses and related devices
11/02/17Low power biological sensing system
10/26/17Ceramic board with memory formed in the ceramic
10/19/17Microfluidic system with single drive signal for multiple nozzles
10/05/17Method of forming sige channel formation region
09/28/17Transistors incorporating metal quantum dots into doped source and drain regions
09/14/17Co-manufacturing zones with different uniaxial stresses
09/14/17Method for fabricating a device with a tensile-strained nmos transistor and a uniaxial compression strained pmos transistor
09/14/17Method for making a shielded integrated circuit (ic) package with an electrically conductive polymer layer
09/14/17Microfluidic assembly with mechanical bonds
09/07/17System and an arc fault detector
08/31/17Object speed weighted motion compensated interpolation
08/31/17Method for manufacturing a transistor having a sharp junction by forming raised source-drain regions before forming gate regions and corresponding transistor produced by said method
08/24/17Managing burst transmit times for a buffered data stream over bonded upstream channels
08/17/17Microfluidic assembly and methods of forming same
08/17/17Fin formation for semiconductor device
08/17/17Mosfet devices with asymmetric structural configurations introducing different electrical characteristics
08/17/17Integrated circuit devices and fabrication techniques
08/10/17Cancellation of noise due to capacitance mismatch in mems sensors
08/10/17Method for making semiconductor device with stacked analog components in back end of line (beol) regions
08/03/17Hybrid photonic and electronic integrated circuits
08/03/17Method to form localized relaxed substrate by using condensation
08/03/17Self-aligned bottom up gate contact and top down source-drain contact structure in the premetallization dielectric or interlevel dielectric layer of an integrated circuit
07/27/17Vertical gate-all-around tfet
07/20/17Process for manufacturing a nozzle plate
07/13/17Co-integration of tensile silicon and compressive silicon germanium
07/13/17Self aligned gate shape preventing void formation
07/13/17Method for making semiconductor device with filled gate line end recesses
07/06/17Aeroponics system with microfluidic die and sensors for feedback control
07/06/17Support substrates for microfluidic die
07/06/17Microfluidic die on a support with at least one other die
07/06/17Via, trench or contact structure in the metallization, prematallization dielectric or interlevel dielectric layers of an integrated circuit
07/06/17Silicon germanium fin channel formation
07/06/17Multipath switching using per-hop virtual local area network classification
06/29/17Microelectromechanical gyroscope with rejection of disturbances and sensing an angular rate
06/29/17Battery pack management
06/29/17Electronic package having electromagnetic interference shielding and associated method
06/29/17Enhanced powerline communication methods and devices
06/22/17Method for calibration of magnetic sensor
06/22/17Optical image stabilization actuator driver power distribution control
06/22/17Optical image stabilization actuator driver power distribution control
06/22/17Self aligned gate shape preventing void formation
06/22/17Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon region
06/15/17Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon-germanium region
06/08/17Semiconductor device with frame having arms and related methods
06/08/17Self-aligned three dimensional chip stack and making the same
06/08/17Structure and process for overturned thin film device with self-aligned gate and s/d contacts
06/01/17Integrated tensile strained silicon nfet and compressive strained silicon-germanium pfet implemented in finfet technology
05/25/17Dual medium filter for ion and particle filtering during semiconductor processing
05/18/17Semiconductor package with integrated heatsink
04/27/17Optical image stabilization synchronization of gyroscope and actuator drive circuit
04/20/17Post-cmp hybrid wafer cleaning technique
04/20/17Leadframe package with pre-applied filler material
04/20/17High doped iii-v source/drain junctions for field effect transistors
04/13/17Forming replacement low-k spacer in tight pitch fin field effect transistors
04/13/17Forming replacement low-k spacer in tight pitch fin field effect transistors
04/13/17Directional motion vector filtering
03/30/17Encapsulated pressure sensor
03/30/17Gate all around vacuum channel transistor
03/23/17Method for making ic with stepped sidewall and related ic devices
03/23/17Self-aligned sige finfet
03/23/17Power efficient ps-poll
03/16/17Vertical junction finfet device and manufacture
03/16/17Vertical slit transistor with optimized ac performance
03/09/17Method for manufacturing a transistor having a sharp junction by forming raised source-drain regions before forming gate regions and corresponding transistor produced by said method
Patent Packs
03/02/17Co-integration of tensile silicon and compressive silicon germanium
02/23/17Fully substrate-isolated finfet transistor
02/23/17Series resistance reduction in vertically stacked silicon nanowire transistors
02/16/17Transistor with self-aligned source and drain contacts and making same
02/16/17Silicon germanium fin channel formation
02/16/17Early pts with buffer for channel doping control
02/16/17Visible light and power-line communication-based system with location-based services
02/09/17Method of making a semiconductor device using a dummy gate
02/09/17Intelligent lighting and sensor system and implementation
02/02/17Determining reflectance of a target using a time of flight ranging system
02/02/17High doped iii-v source/drain junctions for field effect transistors
02/02/17High doped iii-v source/drain junctions for field effect transistors
02/02/17High density resistive random access memory (rram)
01/19/17Silicon germanium and silicon fins on oxide from bulk wafer
01/19/17Silicon germanium fin channel formation
Patent Packs
01/12/17Methods and devices for enhancing mobility of charge carriers
01/12/17Bridging local semiconductor interconnects
01/12/17Process for integrated circuit fabrication including a uniform depth tungsten recess technique
01/12/17Semiconductor device with fin and related methods
01/12/17Large area contacts for small transistors
01/05/17Mosfet devices with asymmetric structural configurations introducing different electrical characteristics
01/05/17Stacked short and long channel finfets
01/05/17Leadframe package with stable extended leads
01/05/17Modular interconnects for gate-all-around transistors
01/05/17Method of using a sacrifical gate structure to make a metal gate finfet transistor
12/29/16Semiconductor packages separated using a sacrificial material
12/29/16Silicon germanium-on-insulator finfet
12/29/16Integrated circuits with self aligned contacts and methods of manufacturing the same
12/29/16Method for making semiconductor device with sidewall recess and related devices
12/29/16Self aligned via in integrated circuit
12/29/16Lateral bipolar junction transistor (bjt) on a silicon-on-insulator (soi) substrate
12/29/16Integrated cantilever switch
12/22/16Siarc removal with plasma etch and fluorinated wet chemical solution combination
12/22/16Dual channel finfet with relaxed pfet region
12/15/16Self-aligned bottom up gate contact and top down source-drain contact structure in the premetallization dielectric or interlevel dielectric layer of an integrated circuit
12/15/16Series resistance reduction in vertically stacked silicon nanowire transistors
12/15/16Semi-floating gate fet
12/08/16Via formation using sidewall image tranfer process to define lateral dimension
12/01/16Heating microfluidic and micromechanical applications
12/01/16Via, trench or contact structure in the metallization, premetallization dielectric or interlevel dielectric layers of an integrated circuit
12/01/16Max-log-map equivalence log likelihood ratio generation soft viterbi architecture system and method
11/17/16Via formation using sidewall image transfer process to define lateral dimension
11/10/16Integrated tensile strained silicon nfet and compressive strained silicon-germanium pfet implemented in finfet technology
11/10/16Power efficient ps-poll
11/03/16Multi-fin finfet device including epitaxial growth barrier on outside surfaces of outermost fins and related methods
Social Network Patent Pack
11/03/16Tunneling field effect transistor (tfet) having a semiconductor fin structure
10/20/16Method to induce strain in finfet channels from an adjacent region
10/20/16High density resistive random access memory (rram)
10/20/16High density resistive random access memory (rram)
10/13/16Junctionless finfet device and manufacture
10/06/16Integrated cantilever switch
10/06/16Semiconductor device with sloped sidewall and related methods
10/06/16Method for making strained semiconductor device and related methods
10/06/16Semiconductor device including conductive clip with flexible leads and related methods
10/06/16Technique for fabrication of microelectronic capacitors and resistors
Patent Packs
10/06/16Vertical junction finfet device and manufacture
10/06/16Finfet device having a high germanium content fin structure and making same
10/06/16Dual width finfet
10/06/16Vertical gate-all-around tfet
10/06/16Vertical tunneling finfet
10/06/16Finfets having strained channels, and methods of fabricating finfets having strained channels
09/29/16Buried source-drain contact for integrated circuit transistor devices and making same
09/29/16Macro to monitor n-p bump
09/29/16Dual channel finfet with relaxed pfet region
09/29/16Method for making a semiconductor device with sidewal spacers for confinig epitaxial growth
09/29/16Upstream signal capture and processing in a subscriber device
09/22/16Finfet including tunable fin height and tunable fin width ratio
09/22/16Method for the formation of a finfet device having a partially dielectric isolated fin structure
09/22/16Method and structure of making enhanced utbb fdsoi devices
09/22/16Method and structure of making enhanced utbb fdsoi devices
09/15/16Method of making a cmos semiconductor device using a stressed silicon-on-insulator (soi) wafer
09/08/16Semiconductor devices having fins, and methods of forming semiconductor devices having fins
09/08/16Fin isolation structures facilitating different fin isolation schemes
09/01/16Reconfigurable sensor unit for electronic device
09/01/16Method and determining probabilistic context awreness of a mobile device user using a single sensor and/or multi-sensor data fusion
09/01/16Method for making semiconductor device with stacked analog components in back end of line (beol) regions
09/01/16Reconfigurable sensor unit for electronic device
08/25/16Interconnect structure having large self-aligned vias
08/18/16Microfluidic delivery member with filter and forming same
08/18/16Electronic device for communicating between a microcontroller unit (mcu) and a host processor and related methods
08/04/16Inrush current limiting circuit
08/04/16Scheduling for orthogonal frequency division multiple access (ofdma) transmissions in a wireless local area network (wlan)
07/28/16Multilayer structure in an integrated circuit for damage prevention and detection and methods of creating the same
07/28/16Integration of strained silicon germanium pfet device and silicon nfet device for finfet structures
07/28/16Integration of strained silicon germanium pfet device and silicon nfet device for finfet structures
Patent Packs
07/21/16Control of wafer surface charge during cmp
07/21/16Method to protect against contact related shorts on utbb
07/21/16Method to form localized relaxed substrate by using condensation
07/07/16Semiconductor device with different fin sets
06/30/16Braking intensity indicator system including selective adjustment of brake pedal light and related methods
06/30/16Device for determining the distance to an outer surface of a roll of material and related method
06/30/16Integrated circuit layout wiring for multi-core chips
06/30/16Asymmetrical driver
06/30/16Semiconductor package with cantilever pads
06/30/16Stacked semiconductor packages with cantilever pads
06/30/16Method and structure of making enhanced utbb fdsoi devices
06/30/16Silicon germanium-on-insulator finfet
06/30/16Defect-free strain relaxed buffer layer
06/30/16Vertical gate all-around transistor
06/30/16Vertical slit transistor with optimized ac performance
06/30/16Method and structure of making enhanced utbb fdsoi devices
06/30/16Hetero-channel finfet
06/30/16Large area contacts for small transistors
06/30/16High-reliability, low-resistance contacts for nanoscale transistors
06/30/16Integrated circuit layout wiring for multi-core chips
Social Network Patent Pack
06/30/16Device and fm demodulation with threshold extension
06/23/16Dual accelerometer detector for clamshell devices
06/23/16Trench epitaxial growth for a finfet device having reduced capacitance
06/23/16Reduced trench profile for a gate
06/23/16Semiconductor devices having low contact resistance and low current leakage
06/23/16Finfet device having a high germanium content fin structure and making same
06/23/16Dac with sub-dacs and related methods
06/23/16Multi-acked multicast protocol
06/23/16Multi-destination burst protocol
06/23/16Leadframe package with pre-applied filler material
06/16/16Method for residue-free block pattern transfer onto metal interconnects for air gap formation
06/16/16Method to induce strain in 3-d microfabricated structures
06/09/16Protective circuit for an apparatus
06/09/16Ldmos finfet device and manufacture using a trench confined epitaxial growth process
06/02/16Interconnect structure for an integrated circuit and fabricating an interconnect structure
05/26/16Package for semiconductor devices sensitive to mechanical and thermo-mechanical stresses, such as mems pressure sensors
05/26/16Offset cancellation device for micro-electromechanical system
05/26/16Method to introduce stress in a channel of a transistor using sacrificial sources and drain region and gate replacement
05/26/16Facet-free strained silicon transistor
05/26/16Transistors incorporating small metal elements into doped source and drain regions
Social Network Patent Pack
05/26/16High power factor primary regulated offline led driver
05/12/16Wireless strain gauge/flow sensor
05/12/16Hybrid photonic and electronic integrated circuits
05/12/16Uniaxially-strained fd-soi finfet
05/12/16Silicon carbide static induction transistor and process for making a silicon carbide static induction transistor
04/28/16Method of making inkjet print heads by filling residual slotted recesses and related devices
04/28/16Process for integrated circuit fabrication including a liner silicide with low contact resistance
04/28/16Methods and devices for enhancing mobility of charge carriers
04/28/16Semiconductor device with a buried oxide stack for dual channel regions and associated methods
04/28/16Method to form strained channel in thin box soi structures by elastic strain relaxation of the substrate
04/28/16High dose implantation for ultrathin semiconductor-on-insulator substrates
04/28/16Zero standby power for powerline communication devices
04/21/16Microfluidic system with single drive signal for multiple nozzles
04/21/16Method of making inkjet print heads having inkjet chambers and orifices formed in a wafer and related devices
04/21/16Microfluidic delivery member with filter and forming same
04/21/16Method to co-integrate sige and si channels for finfet devices
04/21/16Multi-channel gate-all-around fet
04/21/16Threshold adjustment for quantum dot array devices with metal source and drain
04/21/16Method and improving connector security and device coexistance
04/21/16Apparatus for forming digital images
04/14/16Microfluidic delivery system and method
04/14/16Microfluidic system with single drive signal for multiple nozzles
04/14/16Process for integrated circuit fabrication including a uniform depth tungsten recess technique
04/14/16Method of making a semiconductor device using a dummy gate
04/07/16Novel embedded shape sige for strained channel transistors
04/07/16Fixed gain amplifier circuit
04/07/16Client accessible secure area in a mobile device security module
04/07/16Wga sta power saving
03/31/16Semiconductor-on-insulator (soi) device and related methods for making same using non-oxidizing thermal treatment
03/31/16Finfet semiconductor device with isolated channel regions
Social Network Patent Pack
03/24/16Application identifier (aid) prioritization of security module applications
03/24/16Portable mobile subscription
03/24/16Multiple mac addresses in a device
03/17/16Method and a wireless charging system
03/17/16Identifying a defect in a data-storage medium
03/17/16Method to co-integrate oppositely strained semiconductor devices on a same substrate
03/17/16Device and alignment of vertically stacked wafers and die
03/17/16Single-ssid and dual-ssid enhancements
03/10/16Methods of making an inkjet print head by sawing discontinuous slotted recesses
03/10/16Method for the formation of nano-scale on-chip optical waveguide structures
03/10/16Packet-based digital display interface signal mapping to micro serial interface
03/10/16Method for the formation of a finfet device with epitaxially grown source-drain regions having a reduced leakage path
03/03/16Modular fuses and antifuses for integrated circuits
03/03/16Method of making a semiconductor device using spacers for source/drain confinement
03/03/16Size-controllable opening and making same
03/03/16Frequency domain multiband dynamics compressor with spectral balance compensation
02/25/16Backside source-drain contact for integrated circuit transistor devices and making same
02/18/16Semiconductor device having fins with in-situ doped, punch-through stopper layer and related methods
02/11/16Semiconductor device with thinned channel region and related methods
02/04/16Cmos in situ doped flow with independently tunable spacer thickness
02/04/16Uniaxially-strained fd-soi finfet
02/04/16Method for the formation of silicon and silicon-germanium fin structures for finfet devices
01/21/16Method for controlling the profile of an etched metallic layer
01/21/16Microstructure and electronic device
01/21/16Simplified multi-threshold voltage scheme for fully depleted soi mosfets
01/14/16Dual shallow trench isolation liner for preventing electrical shorts
01/14/16Dual sti integrated circuit including fdsoi transistors and manufacturing the same
01/14/16Low leakage dual sti integrated circuit including fdsoi transistors
01/14/16Methods of forming isolated channel regions for a finfet semiconductor device and the resulting device







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