Real Time Touch



new TOP 200 Companies filing patents this week

new Companies with the Most Patent Filings (2010+)




Real Time Touch

Similar
Filing Names

Stmicroelectronics Inc
Stmicroelectronics Inc a Corporation Of The State Of Delaware
Stmicroelectronics Inc_20131212
Stmicroelectronics Inc_20100128

Stmicroelectronics Inc patents


Recent patent applications related to Stmicroelectronics Inc. Stmicroelectronics Inc is listed as an Agent/Assignee. Note: Stmicroelectronics Inc may have other listings under different names/spellings. We're not affiliated with Stmicroelectronics Inc, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "S" | Stmicroelectronics Inc-related inventors


 new patent  Bottom package exposed die mems pressure sensor integrated circuit package design

A MEMS pressure sensor packaged with a molding compound. The MEMS pressure sensor features a lead frame, a MEMS semiconductor die, a second semiconductor die, multiple pluralities of bonding wires, and a molding compound. The MEMS semiconductor die has an internal chamber, a sensing component, and apertures. The MEMS semiconductor... Stmicroelectronics Inc

Time of flight user identification based control systems and methods

A user identification based control system includes a time of flight ranging sensor configured to sense a distance to a person, where the time of flight ranging sensor is positioned so the sensed distance is a function of a height of the person. Processing circuitry is coupled to the time... Stmicroelectronics Inc

Self-aligned three dimensional chip stack and making the same

Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips supported by a scaffolding structure, the scaffolding structure defined by a first scaffolding trench and at least one additional scaffolding trench, the first scaffolding trench comprising a bottom surface... Stmicroelectronics Inc

Integration of strained silicon germanium pfet device and silicon nfet device for finfet structures

A method of forming a finFET transistor device includes forming a crystalline, compressive strained silicon germanium (cSiGe) layer over a substrate; masking a first region of the cSiGe layer so as to expose a second region of the cSiGe layer; subjecting the exposed second region of the cSiGe layer to... Stmicroelectronics Inc

Glass detection with time of flight sensor

A device includes a time-of-flight ranging sensor configured to transmit optical pulse signals and to receive return optical pulse signals. The time-of-flight ranging sensor processes the return optical pulse signals to sense distances to a plurality of objects and to generate a confidence value indicating whether one of the plurality... Stmicroelectronics Inc

Adaptive laser power and ranging limit for time of flight sensor

A time of flight range detection device includes a laser configured to transmit an optical pulse into an image scene, a return single-photon avalanche diode (SPAD) array, a reference SPAD array, a range detection circuit coupled to the return SPAD array and the reference SPAD array, and a laser driver... Stmicroelectronics Inc

Stacked semiconductor package with compliant corners on folded substrate

One or more embodiments are directed to stacked packages, such as Package-on-Package (PoP) packages, that are stacked on a flexible folded substrate. The stacked packages have compliant corners. In particular, the stacked packages include an adhesive material at the corners between layers of the folded substrate. The adhesive material has... Stmicroelectronics Inc

Time of flight based gesture control devices, systems and methods

A device includes a time-of-flight sensor configured to transmit an optical pulse signal and to receive a return optical pulse signal corresponding to a portion of the transmitted optical pulse signal that has reflected off an object within a field of view of the time-of-flight sensor. The time-of-flight sensor generates... Stmicroelectronics Inc

Novel embedded shape sige for strained channel transistors

An integrated circuit die includes a silicon substrate. PMOS and NMOS transistors are formed on the silicon substrate. The carrier mobilities of the PMOS and NMOS transistors are increased by introducing tensile stress into the channel regions of the NMOS transistors and compressive stress into the channel regions of the... Stmicroelectronics Inc

Time of flight ranging for flash control in image capture devices

A flash control circuit of an image capture device includes a time-of-flight ranging sensor configured to sense distances to a plurality of objects within an overall field of view of the time-of-flight ranging sensor. The time-of-flight sensor is configured to generate a range estimation signal including a plurality of sensed... Stmicroelectronics Inc

Method to form strained channel in thin box soi structures by elastic strain relaxation of the substrate

Methods and structures for forming strained-channel FETs are described. A strain-inducing layer may be formed under stress in a silicon-on-insulator substrate below the insulator. Stress-relief cuts may be formed in the strain-inducing layer to relieve stress in the strain-inducing layer. The relief of stress can impart strain to an adjacent... Stmicroelectronics Inc

Wireless power transmitting/receiving devices and methods

A wireless power transmitting/receiving device includes a power transmitting/receiving element, a plurality of switches, a current sensor and a controller. Each of the plurality of switches has a control terminal and a conduction terminal, with the conduction terminal being coupled to the power transmitting/receiving element. The current sensor senses a... Stmicroelectronics Inc

Method of making inkjet print heads by filling residual slotted recesses and related devices

An inkjet print head includes a semiconductor substrate having a plurality of continuous slotted recesses in a first surface. The plurality of continuous slotted recesses is arranged in parallel, spaced apart relation. Each continuous slotted recess extends continuously across the first surface. The semiconductor substrate also has a plurality of... Stmicroelectronics Inc

Low power biological sensing system

It is recognized that, because of its unique properties, graphene can serve as an interface with biological cells that communicate by an electrical impulse, or action potential. Responding to a sensed signal can be accomplished by coupling a graphene sensor to a low power digital electronic switch that is activatable... Stmicroelectronics Inc

Ceramic board with memory formed in the ceramic

The present disclosure is directed to a ceramic substrate that includes a plurality of contact pads, a plurality of electrical traces, and a microelectromechanical die. Contacts on the die are coupled to the plurality of contact pads through the plurality of electrical traces. The substrate also includes a plurality of... Stmicroelectronics Inc

Microfluidic system with single drive signal for multiple nozzles

The present disclosure is directed to a microfluidic die that includes a plurality of heaters above a substrate, a plurality of chambers and nozzles above the heaters, a plurality of first contacts coupled to the heaters, and a plurality of second contacts coupled to the heaters. The plurality of second... Stmicroelectronics Inc

Method of forming sige channel formation region

A method comprising: forming an SiGe layer on sidewalls of one or more fins of a semiconductor device by a non-selective deposition of amorphous SiGe, the fins being formed of Si or SiGe; depositing a silicon oxide layer over the SiGe layer; and forming an SiGe channel formation region within... Stmicroelectronics Inc

Transistors incorporating metal quantum dots into doped source and drain regions

Metal quantum dots are incorporated into doped source and drain regions of a MOSFET array to assist in controlling transistor performance by altering the energy gap of the semiconductor crystal. In a first example, the quantum dots are incorporated into ion-doped source and drain regions. In a second example, the... Stmicroelectronics Inc

Co-manufacturing zones with different uniaxial stresses

b) making a second semiconducting material grow with a mesh parameter different from the mesh parameter of the first semiconducting material, so as to form one or several first semiconducting blocks strained along the first direction, on said one or several first oblong semiconducting portions.... Stmicroelectronics Inc

Method for fabricating a device with a tensile-strained nmos transistor and a uniaxial compression strained pmos transistor

Manufacture of a transistor device with at least one P type transistor with channel structure strained in uniaxial compression strain starting from a silicon layer strained in biaxial tension, by amorphisation recrystallisation then germanium condensation.... Stmicroelectronics Inc

Method for making a shielded integrated circuit (ic) package with an electrically conductive polymer layer

A method for making shielded integrated circuit (IC) packages includes providing spaced apart IC dies carried by a substrate and covered by a common encapsulating material, and cutting through the common encapsulating material between adjacent IC dies to define spaced apart IC packages carried by the substrate. An electrically conductive... Stmicroelectronics Inc

Microfluidic assembly with mechanical bonds

Embodiments of the present disclosure are directed to a microfluidic delivery system that includes a microfluidic semiconductor die coupled to a flexible interconnect substrate to form an assembly. At least one embodiment is directed to a semiconductor die having an active surface that includes a layout that has electrically active... Stmicroelectronics Inc

System and an arc fault detector

Embodiments of the present disclosure include a method of operating an arc fault detection system, an arc fault detection system, and a system. An embodiment is a method of operating an arc fault detection system coupled to a power line, the method including determining one or more arc fault detection... Stmicroelectronics Inc

Object speed weighted motion compensated interpolation

In one embodiment of the present invention, a method is provided for performing motion compensated interpolation using a previous frame and a current frame of a displayable output, the method comprising: detecting the speed of an object in the displayable output relative to the speed of a background in the... Stmicroelectronics Inc

Method for manufacturing a transistor having a sharp junction by forming raised source-drain regions before forming gate regions and corresponding transistor produced by said method

A transistor is fabricated by growing an epitaxial layer of semiconductor material on a semiconductor layer and forming an opening extending through the epitaxial layer at the gate location. This opening provides, from the epitaxial layer, a source epitaxial region on one side of the opening and a drain epitaxial... Stmicroelectronics Inc

Managing burst transmit times for a buffered data stream over bonded upstream channels

Upstream burst transmit times are dynamically communicated to the transmit unit in grants issued over time and in any order. A critical parameter is when to trigger the operation to order the buffered data stream for transmission. If the ordering operation is triggered too soon, a later grant of an... Stmicroelectronics Inc

Microfluidic assembly and methods of forming same

One or more embodiments are directed to a microfluidic assembly that includes an interconnect substrate coupled to a microfluidic die. In one embodiment, the microfluidic die includes a ledge with a plurality of bond pads. The microfluidic assembly further includes an interconnect substrate having an end resting on the ledge... Stmicroelectronics Inc

Fin formation for semiconductor device

A method of fabricating a semiconductor structure includes forming a plurality of semiconductor fins disposed on a semiconductor substrate, wherein at least one of the fins is an unwanted fin including a semiconductor material; providing a conformal protective layer over the plurality of semiconductor fins; forming a mask having an... Stmicroelectronics Inc

Mosfet devices with asymmetric structural configurations introducing different electrical characteristics

First and second transistors with different electrical characteristics are supported by a substrate having a first-type dopant. The first transistor includes a well region within the substrate having the first-type dopant, a first body region within the well region having a second-type dopant and a first source region within the... Stmicroelectronics Inc

Integrated circuit devices and fabrication techniques

Single gate and dual gate FinFET devices suitable for use in an SRAM memory array have respective fins, source regions, and drain regions that are formed from portions of a single, contiguous layer on the semiconductor substrate, so that STI is unnecessary. Pairs of FinFETs can be configured as dependent-gate... Stmicroelectronics Inc

Cancellation of noise due to capacitance mismatch in mems sensors

Disclosed herein is a device including a MEMS sensor configured to generate a first differential capacitance representing a change in capacitance from a first original sensing capacitance value and a second differential capacitance representing a change in capacitance from a second original sensing capacitance value, with the first and second... Stmicroelectronics Inc

Method for making semiconductor device with stacked analog components in back end of line (beol) regions

A method for making a semiconductor device may include forming a first dielectric layer above a semiconductor substrate, forming a first trench in the first dielectric layer, filling the first trench with electrically conductive material, removing upper portions of the electrically conductive material to define a lower conductive member with... Stmicroelectronics Inc

Hybrid photonic and electronic integrated circuits

A sequence of processing steps presented herein is used to embed an optical signal path within an array of nanowires, using only one lithography step. Using the techniques disclosed, it is not necessary to mask electrical features while forming optical features, and vice versa. Instead, optical and electrical signal paths... Stmicroelectronics Inc

Method to form localized relaxed substrate by using condensation

Methods and structures for forming a localized, strained region of a substrate are described. Trenches may be formed at boundaries of a localized region of a substrate. An upper portion of sidewalls at the localized region may be covered with a covering layer, and a lower portion of the sidewalls... Stmicroelectronics Inc

Self-aligned bottom up gate contact and top down source-drain contact structure in the premetallization dielectric or interlevel dielectric layer of an integrated circuit

An integrated circuit includes a source-drain region, a channel region adjacent to the source-drain region, a gate structure extending over the channel region and a sidewall spacer on a side of the gate structure and which extends over the source-drain region. A dielectric layer is provided in contact with the... Stmicroelectronics Inc

07/27/17 / #20170213836

Vertical gate-all-around tfet

A vertical tunneling FET (TFET) provides low-power, high-speed switching performance for transistors having critical dimensions below 7 nm. The vertical TFET uses a gate-all-around (GAA) device architecture having a cylindrical structure that extends above the surface of a doped well formed in a silicon substrate. The cylindrical structure includes a... Stmicroelectronics Inc

07/20/17 / #20170203568

Process for manufacturing a nozzle plate

... Stmicroelectronics Inc

07/13/17 / #20170200653

Co-integration of tensile silicon and compressive silicon germanium

Integrated circuits are disclosed in which the strain properties of adjacent pFETs and nFETs are independently adjustable. The pFETs include compressive-strained SiGe on a silicon substrate, while the nFETs include tensile-strained silicon on a strain-relaxed SiGe substrate. Adjacent n-type and p-type FinFETs are separated by electrically insulating regions formed by... Stmicroelectronics Inc

07/13/17 / #20170200807

Self aligned gate shape preventing void formation

A semiconductor device that includes a first fin structure in a first portion of a substrate, and a second fin structure in a second portion of the substrate, wherein the first portion of the substrate is separated from the second portion of the substrate by at least one isolation region.... Stmicroelectronics Inc

07/13/17 / #20170200812

Method for making semiconductor device with filled gate line end recesses

A method for making a semiconductor device may include forming first and second spaced apart semiconductor active regions with an insulating region therebetween, forming at least one sacrificial gate line extending between the first and second spaced apart semiconductor active regions and over the insulating region, and forming sidewall spacers... Stmicroelectronics Inc

07/06/17 / #20170188526

Aeroponics system with microfluidic die and sensors for feedback control

The present disclosure is directed to a greenhouse or single container for plant growth coupled to the Internet of Things and including a microfluidic die for water or nutrient distribution. The microfluidic die is controllable automatically or with instructions from a remote user, based on sensors included within a growth... Stmicroelectronics Inc

07/06/17 / #20170190174

Support substrates for microfluidic die

The present disclosure provides supports for microfluidic die that allow for nozzles of the microfluidic die to be on a different plane or face a different direction from electrical contacts on the same support. This includes a rigid support having electrical contacts on a different side of the rigid support... Stmicroelectronics Inc

07/06/17 / #20170190175

Microfluidic die on a support with at least one other die

The present disclosure provides supports for a microfluidic die and one or more additional die including, but not limited to, microfluidic die, ASICs, MEMS devices, and sensors. This includes semi-flexible supports that allow a microfluidic die to be at a 90 degree angle with respect to another die and rigid... Stmicroelectronics Inc

07/06/17 / #20170194244

Via, trench or contact structure in the metallization, prematallization dielectric or interlevel dielectric layers of an integrated circuit

A semiconductor substrate includes a doped region. A premetallization dielectric layer extends over the semiconductor substrate. A first metallization layer is disposed on a top surface of the premetallization dielectric layer. A metal contact extends from the first metallization layer to the doped region. The premetallization dielectric layer includes sub-layers,... Stmicroelectronics Inc

07/06/17 / #20170194481

Silicon germanium fin channel formation

A method for channel formation in a fin transistor includes removing a dummy gate and dielectric from a dummy gate structure to expose a region of an underlying fin and depositing an amorphous layer including Ge over the region of the underlying fin. The amorphous layer is oxidized to condense... Stmicroelectronics Inc

07/06/17 / #20170195213

Multipath switching using per-hop virtual local area network classification

A method and apparatus for multipath switching using per-hop virtual local area network (VLAN) remapping is disclosed. In the method and apparatus, a data packet is forwarded for transmission over one of a first port and a second port. The device identifies a VLAN ID of the data packet as... Stmicroelectronics Inc

06/29/17 / #20170184400

Microelectromechanical gyroscope with rejection of disturbances and sensing an angular rate

A gyroscope includes a substrate, a first structure, a second structure and a third structure elastically coupled to the substrate and movable along a first axis. The first and second structure are arranged at opposite sides of the third structure with respect to the first axis A driving system is... Stmicroelectronics Inc

06/29/17 / #20170184681

Battery pack management

An electronic device includes a processor coupled to a battery and to determine whether the battery is being charged or discharged. If the battery being is being discharged, the processor operates to calculate an amount by which the battery has discharged since a preceding calculation of remaining capacity of the... Stmicroelectronics Inc

06/29/17 / #20170186698

Electronic package having electromagnetic interference shielding and associated method

An electronic package includes a substrate having opposing first and second surfaces. Conductive areas are on a first surface of the substrate and include at least one edge conductive area. A plurality of conductive bumps are on the second surface of the substrate and coupled to respective ones of the... Stmicroelectronics Inc

06/29/17 / #20170187420

Enhanced powerline communication methods and devices

A powerline communication system includes a plurality of rail segments. Each of the rail segments is electrically isolated from other rail segments, and each receives power from a rail segment power supply. At least one cart operates on the rail segments. The cart has a powerline communications controller. Each rail... Stmicroelectronics Inc

06/22/17 / #20170176546

Method for calibration of magnetic sensor

A method includes acquiring magnetic data from a magnetometer, processing the magnetic data to perform robust calibration, and generating optimum calibration parameters using a calibration status indicator. To that end, the method includes generating a calibration status indicator as a function of time elapsed since a last calibration and variation... Stmicroelectronics Inc

06/22/17 / #20170176763

Optical image stabilization actuator driver power distribution control

Various embodiments provide an optical image stabilization circuit including a drive circuit having a power waveform generator and a power waveform conversion circuit. The power waveform generator generates a power waveform. The power waveform conversion circuit converts the power waveform to a power drive signal. An actuator is then driven... Stmicroelectronics Inc

06/22/17 / #20170176764

Optical image stabilization actuator driver power distribution control

Various embodiments provide an optical image stabilization circuit including a drive circuit having a power waveform generator and a power waveform conversion circuit. The power waveform generator generates a power waveform. The power waveform conversion circuit converts the power waveform to a power drive signal. An actuator is then driven... Stmicroelectronics Inc

06/22/17 / #20170178967

Self aligned gate shape preventing void formation

A semiconductor device that includes a first fin structure in a first portion of a substrate, and a second fin structure in a second portion of the substrate, wherein the first portion of the substrate is separated from the second portion of the substrate by at least one isolation region.... Stmicroelectronics Inc

06/22/17 / #20170179137

Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon region

An improved transistor with channel epitaxial silicon. In one aspect, a method of fabrication includes: forming a gate stack structure on an epitaxial silicon region disposed on a substrate, a width dimension of the epitaxial silicon region approximating a width dimension of the gate stack structure; and growing a raised... Stmicroelectronics Inc

06/15/17 / #20170170299

Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon-germanium region

An improved transistor with channel epitaxial silicon and methods for fabrication thereof. In one aspect, a method for fabricating a transistor includes: forming a gate stack structure on an epitaxial silicon region, a width dimension of the epitaxial silicon region approximating a width dimension of the gate stack structure; encapsulating... Stmicroelectronics Inc

06/08/17 / #20170162479

Semiconductor device with frame having arms and related methods

A semiconductor device may include a circuit board having an opening, and a frame. The frame may have an IC die pad in the opening, and arms extending outwardly from the IC die pad and coupled to the circuit board. The semiconductor device may include an IC mounted on the... Stmicroelectronics Inc

06/08/17 / #20170162554

Self-aligned three dimensional chip stack and making the same

Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips supported by a scaffolding structure, the scaffolding structure defined by a first scaffolding trench and at least one additional scaffolding trench, the first scaffolding trench comprising a bottom surface... Stmicroelectronics Inc

06/08/17 / #20170162711

Structure and process for overturned thin film device with self-aligned gate and s/d contacts

Processes and overturned thin film device structures generally include a metal gate having a concave shape defined by three faces. The processes generally include forming the overturned thin film device structures such that the channel self-aligns to the metal gate and the contacts can be self-aligned to the sacrificial material.... Stmicroelectronics Inc

06/01/17 / #20170154900

Integrated tensile strained silicon nfet and compressive strained silicon-germanium pfet implemented in finfet technology

A tensile strained silicon layer is patterned to form a first group of fins in a first substrate area and a second group of fins in a second substrate area. The second group of fins is covered with a tensile strained material, and an anneal is performed to relax the... Stmicroelectronics Inc

05/25/17 / #20170148647

Dual medium filter for ion and particle filtering during semiconductor processing

The present disclosure is directed to fluid filtering systems and methods for use during semiconductor processing. One or more embodiments are directed to fluid filtering systems and methods for filtering ions and particles from a fluid as the fluid is being provided to a semiconductor wafer processing tool, such as... Stmicroelectronics Inc

05/18/17 / #20170141014

Semiconductor package with integrated heatsink

One or more embodiments are directed to semiconductor packages having an integrated heatsink and methods of forming same. In one embodiment, a package includes a plurality of leads that support and enclose periphery portions of the semiconductor die. The leads have first and second, opposing surfaces that form outer surfaces... Stmicroelectronics Inc

04/27/17 / #20170115502

Optical image stabilization synchronization of gyroscope and actuator drive circuit

Various embodiments provide an optical image stabilization circuit that synchronizes its gyroscope and drive circuit using gyroscope data ready signals and gyroscope reset signals. In response to a gyroscope data ready signal, the optical image stabilization circuit synchronously obtains position measurements of a camera lens when power drive signals are... Stmicroelectronics Inc

04/20/17 / #20170110317

Post-cmp hybrid wafer cleaning technique

A brush-cleaning apparatus is disclosed for use in cleaning a semiconductor wafer after polishing. Embodiments of the brush-cleaning apparatus implemented with a multi-branch chemical dispensing unit are applied beneficially to clean semiconductor wafers, post-polish, using a hybrid cleaning method. An exemplary hybrid cleaning method employs a two-chemical sequence in which... Stmicroelectronics Inc

04/20/17 / #20170110340

Leadframe package with pre-applied filler material

Embodiments of the present disclosure are directed to a leadframe package with recesses formed in outer surface of the leads. The recesses are filled with a filler material, such as solder. The filler material in the recesses provides a wetable surface for filler material, such as solder, to adhere to... Stmicroelectronics Inc

Patent Packs
04/20/17 / #20170110583

High doped iii-v source/drain junctions for field effect transistors

A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a III-V material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under... Stmicroelectronics Inc

04/13/17 / #20170103917

Forming replacement low-k spacer in tight pitch fin field effect transistors

A semiconductor device that a fin structure, and a gate structure present on a channel region of the fin structure. A composite spacer is present on a sidewall of the gate structure including an upper portion having a first dielectric constant, a lower portion having a second dielectric constant that... Stmicroelectronics Inc

04/13/17 / #20170104082

Forming replacement low-k spacer in tight pitch fin field effect transistors

A semiconductor device that a fin structure, and a gate structure present on a channel region of the fin structure. A composite spacer is present on a sidewall of the gate structure including an upper portion having a first dielectric constant, a lower portion having a second dielectric constant that... Stmicroelectronics Inc

04/13/17 / #20170105024

Directional motion vector filtering

An appropriate motion vector to assign to a pixel in a digital video frame is performed by a comparison of motion vectors of particular surrounding pixels. Direction of at least one of color transition or color brightness transition in the digital video frame is detected to detect direction of object... Stmicroelectronics Inc

03/30/17 / #20170090604

Encapsulated pressure sensor

An encapsulated pressure sensor includes a pressure sensor having a pressure sensing surface and a mounting surface. The mounting surface is attached to a mounting substrate. A fluid contacts the pressure sensing surface of the pressure sensor. A deformable encapsulating member is attached to the mounting substrate and encapsulates the... Stmicroelectronics Inc

03/30/17 / #20170092778

Gate all around vacuum channel transistor

A vacuum channel transistor having a vertical gate-all-around (GAA) architecture provides high performance for high-frequency applications, and features a small footprint compared with existing planar devices. The GAA vacuum channel transistor features stacked, tapered source and drain regions that are formed by notching a doped silicon pillar using a lateral... Stmicroelectronics Inc

03/23/17 / #20170084490

Method for making ic with stepped sidewall and related ic devices

A method is for making an integrated circuit (IC) device. The method may include dicing a wafer into IC dies, each IC die having an active surface, a back surface opposite the active surface, and a sidewall with a step defining a smaller periphery adjacent the back surface and a... Stmicroelectronics Inc

03/23/17 / #20170084733

Self-aligned sige finfet

A self-aligned SiGe FinFET device features a relaxed channel region having a high germanium concentration. Instead of first introducing germanium into the channel and then attempting to relax the resulting strained film, a relaxed channel is formed initially to accept the germanium. In this way, a presence of germanium can... Stmicroelectronics Inc

03/23/17 / #20170086139

Power efficient ps-poll

A IEEE 802.11 Wireless Local Area Network (WLAN) system of an access point (AP) and one or more stations (STAs) reduces power consumption and increases battery life of power efficient low power STAs by decreasing the amount of time that a power efficient low power STA remains in an awake... Stmicroelectronics Inc

03/16/17 / #20170077270

Vertical junction finfet device and manufacture

A vertical junction field effect transistor (JFET) is supported by a semiconductor substrate that includes a source region within the semiconductor substrate doped with a first conductivity-type dopant. A fin of semiconductor material doped with the first conductivity-type dopant has a first end in contact with the source region and... Stmicroelectronics Inc

03/16/17 / #20170077306

Vertical slit transistor with optimized ac performance

A vertical slit transistor includes raised source, drain, and channel regions in a semiconductor substrate. Two gate electrodes are positioned adjacent respective sidewalls of the semiconductor substrate. A dielectric material separates the gate electrodes from the source and drain regions.... Stmicroelectronics Inc

03/09/17 / #20170069661

Method for manufacturing a transistor having a sharp junction by forming raised source-drain regions before forming gate regions and corresponding transistor produced by said method

A transistor device is fabricated by growing an epitaxial layer of semiconductor material on a semiconductor layer and forming an opening extending through the epitaxial layer at a position where a gate is to be located. This opening provides, from the epitaxial layer, a source epitaxial region on one side... Stmicroelectronics Inc

03/02/17 / #20170062426

Co-integration of tensile silicon and compressive silicon germanium

Integrated circuits are disclosed in which the strain properties of adjacent pFETs and nFETs are independently adjustable. The pFETs include compressive-strained SiGe on a silicon substrate, while the nFETs include tensile-strained silicon on a strain-relaxed SiGe substrate. Adjacent n-type and p-type FinFETs are separated by electrically insulating regions formed by... Stmicroelectronics Inc

02/23/17 / #20170053981

Fully substrate-isolated finfet transistor

Channel-to-substrate leakage in a FinFET device is prevented by inserting an insulating layer between the semiconducting channel and the substrate during fabrication of the device. Similarly, source/drain-to-substrate leakage in a FinFET device is prevented by isolating the source/drain regions from the substrate by inserting an insulating layer between the source/drain... Stmicroelectronics Inc

02/23/17 / #20170053982

Series resistance reduction in vertically stacked silicon nanowire transistors

Embodiments are directed to a method of fabricating a portion of a nanowire field effect transistor (FET). The method includes forming a sacrificial layer and a nanowire layer, removing a sidewall portion of the sacrificial layer and forming a diffusion block in a space that was occupied by the removed... Stmicroelectronics Inc

Patent Packs
02/16/17 / #20170047349

Transistor with self-aligned source and drain contacts and making same

A transistor includes an active region supported by a substrate and having a source region, a channel region and a drain region. A gate stack extends over the channel region and a first sidewall surrounds the gate stack. A raised source region and a raised drain region are provided over... Stmicroelectronics Inc

02/16/17 / #20170047406

Silicon germanium fin channel formation

A method for channel formation in a fin transistor includes removing a dummy gate and dielectric from a dummy gate structure to expose a region of an underlying fin and depositing an amorphous layer including Ge over the region of the underlying fin. The amorphous layer is oxidized to condense... Stmicroelectronics Inc

02/16/17 / #20170047425

Early pts with buffer for channel doping control

A method of performing an early PTS implant and forming a buffer layer under a bulk or fin channel to control doping in the channel and the resulting bulk or fin device are provided. Embodiments include forming a recess in a substrate; forming a PTS layer below a bottom surface... Stmicroelectronics Inc

02/16/17 / #20170047994

Visible light and power-line communication-based system with location-based services

A hybrid communications network system uses the propagation limitations of Visible Light Communications (VLC) to define location data for portable VLC devices. The location data can be used with specific location-based profiles to provide location-based services to functional zones. The hybrid communications allow location data and connectivity to be available... Stmicroelectronics Inc

02/09/17 / #20170040427

Method of making a semiconductor device using a dummy gate

A method of making a semiconductor device includes forming a fin mask layer on a semiconductor layer, forming a dummy gate over the fin mask layer, and forming source and drain regions on opposite sides of the dummy gate. The dummy gate is removed and the underlying fin mask layer... Stmicroelectronics Inc

02/09/17 / #20170042003

Intelligent lighting and sensor system and implementation

An intelligent lighting and sensor system is disclosed that includes a processor, a memory arranged to store program logic software, the program logic software executable by the processor, a light control module in communication with at least one light source in which the operation of the light control module is... Stmicroelectronics Inc

02/02/17 / #20170031007

Determining reflectance of a target using a time of flight ranging system

An electronic device includes a ranging light source and a reflected light detector. A logic circuit causes the ranging light source to emit ranging light at a target. Reflected light from the target is detected using the reflected light detector, with the reflected light being a portion of the ranging... Stmicroelectronics Inc

02/02/17 / #20170033197

High doped iii-v source/drain junctions for field effect transistors

A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a III-V material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under... Stmicroelectronics Inc

02/02/17 / #20170033221

High doped iii-v source/drain junctions for field effect transistors

A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a III-V material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under... Stmicroelectronics Inc

02/02/17 / #20170033284

High density resistive random access memory (rram)

A memory cell includes a substrate layer, with a plurality of silicided semiconductor fins stacked on the substrate layer and spaced apart from one another. A first metal liner layer is stacked on the plurality of silicided semiconductor fins and on the substrate layer. A plurality of first contact pillars... Stmicroelectronics Inc

01/19/17 / #20170018465

Silicon germanium and silicon fins on oxide from bulk wafer

A method for forming fins includes growing a SiGe layer and a silicon layer over a surface of a bulk Si substrate, patterning fin structures from the silicon layer and the SiGe layer and filling between the fin structures with a dielectric fill. Trenches are formed to expose end portions... Stmicroelectronics Inc

01/19/17 / #20170018630

Silicon germanium fin channel formation

A method for channel formation in a fin transistor includes removing a dummy gate and dielectric from a dummy gate structure to expose a region of an underlying fin and depositing an amorphous layer including Ge over the region of the underlying fin. The amorphous layer is oxidized to condense... Stmicroelectronics Inc

01/12/17 / #20170011971

Methods and devices for enhancing mobility of charge carriers

Methods and devices for enhancing mobility of charge carriers. An integrated circuit may include semiconductor devices of two types. The first type of device may include a metallic gate and a channel strained in a first manner. The second type of device may include a metallic gate and a channel... Stmicroelectronics Inc

01/12/17 / #20170012061

Bridging local semiconductor interconnects

A semiconductor device includes a plurality of gates formed upon a semiconductor substrate that includes a plurality of outer active areas (e.g. CMOS/PMOS areas, source/drain regions, etc.) and one or more inner active areas. An isolator is formed upon one or more inner gates associated with the one or more... Stmicroelectronics Inc

01/12/17 / #20170012105

Process for integrated circuit fabrication including a uniform depth tungsten recess technique

Dummy gates are removed from a pre-metal layer to produce a first opening (with a first length) and a second opening (with a second length longer than the first length). Work function metal for a metal gate electrode is provided in the first and second openings. Tungsten is deposited to... Stmicroelectronics Inc

01/12/17 / #20170012127

Semiconductor device with fin and related methods

A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, and source and drain regions adjacent the channel region to generate shear and normal strain on the channel region. A semiconductor device may include a substrate, a fin above the substrate and... Stmicroelectronics Inc

01/12/17 / #20170012130

Large area contacts for small transistors

A large area electrical contact for use in integrated circuits features a non-planar, sloped bottom profile. The sloped bottom profile provides a larger electrical contact area, thus reducing the contact resistance, while maintaining a small contact footprint. The sloped bottom profile can be formed by recessing an underlying layer, wherein... Stmicroelectronics Inc

01/05/17 / #20170005009

Mosfet devices with asymmetric structural configurations introducing different electrical characteristics

First and second transistors with different electrical characteristics are supported by a substrate having a first-type dopant. The first transistor includes a well region within the substrate having the first-type dopant, a first body region within the well region having a second-type dopant and a first source region within the... Stmicroelectronics Inc

01/05/17 / #20170005012

Stacked short and long channel finfets

An analog integrated circuit is disclosed in which short channel transistors are stacked on top of long channel transistors, vertically separated by an insulating layer. With such a design, it is possible to produce a high density, high power, and high performance analog integrated circuit chip including both short and... Stmicroelectronics Inc

01/05/17 / #20170005028

Leadframe package with stable extended leads

Embodiments of the present disclosure are directed to leadframes having the cantilevered extension that includes an integral support on the end of the lead nearest the die pad. A support integral to the leadframe allows the support to be built to the proper height to support the cantilevered lead in... Stmicroelectronics Inc

01/05/17 / #20170005106

Modular interconnects for gate-all-around transistors

A modular interconnect structure facilitates building complex, yet compact, integrated circuits from vertical GAA FETs. The modular interconnect structure includes annular metal contacts to the transistor terminals, sectors of stacked discs extending radially outward from the vertical nanowires, and vias in the form of rods. Extension tabs mounted onto the... Stmicroelectronics Inc

01/05/17 / #20170005169

Method of using a sacrifical gate structure to make a metal gate finfet transistor

A self-aligned SiGe FinFET device features a relaxed channel region having a high germanium concentration. Instead of first introducing germanium into the channel and then attempting to relax the resulting strained film, a relaxed channel is formed initially to accept the germanium. In this way, a presence of germanium can... Stmicroelectronics Inc








ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009



###

This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. Freshpatents.com is not affiliated or associated with Stmicroelectronics Inc in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Stmicroelectronics Inc with additional patents listed. Browse our Agent directory for other possible listings. Page by FreshPatents.com

###