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Stmicroelectronics Pvt Ltd
Stmicroelectronics Pvt Ltd india
Stmicroelectronics Pvt Ltd_20100128
Stmicroelectronics Pvt Ltd_20100121

Stmicroelectronics Pvt Ltd patents

Recent patent applications related to Stmicroelectronics Pvt Ltd. Stmicroelectronics Pvt Ltd is listed as an Agent/Assignee. Note: Stmicroelectronics Pvt Ltd may have other listings under different names/spellings. We're not affiliated with Stmicroelectronics Pvt Ltd, we're just tracking patents.

ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "S" | Stmicroelectronics Pvt Ltd-related inventors

Date Stmicroelectronics Pvt Ltd patents (updated weekly) - BOOKMARK this page
05/05/16Programmable hysteresis comparator
10/22/15Capless on chip voltage regulator using adaptive bulk bias
12/25/14Operating conditions compensation circuit
11/20/14Radiation hardened circuit
07/03/14Video window detection
01/16/14Phase locked loop circuit with reduced jitter
01/09/14Configurable lane architecture in source synchronous systems
01/09/14On-chip functional debugger and a providing on-chip functional debugging
11/21/13Read self timing circuitry for self-timed memory
11/21/13Write self timing circuitry for self-timed memory
08/15/13Area-efficient distributed device structure for integrated voltage regulators
08/08/13Gop-independent dynamic bit-rate controller
07/18/13High jitter and frequency drift tolerant clock data recovery
07/04/13Trigger circuit and using same
07/04/13Dual port sram having reduced cell size and rectangular shape
07/04/13Dual port register file memory cell with reduced susceptibility to noise during same row access
07/04/13Low voltage write time enhanced sram cell and circuit extensions
07/04/13Memory architecture and design methodology with adaptive read
06/27/13Incoming bus traffic storage system
06/06/13Stress reduced cascoded cmos output driver circuit
06/06/13Dual clock edge triggered memory
06/06/13Calibration method and circuit
05/30/13Xy ternary content addressable memory (tcam) cell and array
05/23/13Sram memory device and testing method thereof
05/23/13Level translator
05/23/13Multiplying digital-to-analog converter (dac)
05/16/13Battery pack management
05/16/13Video window detection
05/16/13Adaptive pal field comber
04/04/13Compression error handling for temporal noise reduction
04/04/13Video decoder
04/04/13Differential amplifier
02/07/13Input and output buffer including a dynamic driver reference generator
01/24/13Automatic clock-activity based chip/io ring design - a novel architecture to reduce standby consumption
01/03/13Canary based sram adaptive voltage scaling (avs) architecture and canary cells for the same
01/03/13Partial write on a low power memory architecture
01/03/13Voltage regulator structure
01/03/13Pre-emphasis circuit
01/03/13Transition detector
01/03/13Automatic test-pattern generation for memory-shadow-logic testing
12/27/12System and switching between a first supply voltage and a second supply voltage of a load
09/06/12Detection of single bit upset at dynamic logic due to soft error in real time
08/30/12System and on-chip jitter and duty cycle measurement
08/02/12Locally synchronous shared bist architecture for testing embedded memories with asynchronous interfaces
07/19/12Negative voltage level shifter circuit
07/12/12Adaptive multi-stage slack borrowing for high performance error resilient computing
07/12/12Advance video coding with perceptual quality scalability for regions of interest
07/05/12Flip chip device having simplified routing
07/05/12Hdmi receiver
07/05/12Differential data sensing
07/05/12Processing clock signals
07/05/12Power harvesting in open drain transmitters
07/05/12Technique to minimize vds mismatch driven voltage swing variation in open drain transmitter
07/05/12Memory device with boost compensation
07/05/12Generic bus de-multiplexer/port expander with inherent bus signals as selectors
07/05/12Advance video coding with perceptual quality scalability for regions of interest
06/28/12Complementary read-only memory (rom) cell and manufacturing the same
06/28/12Sequential on-chip clock controller with dynamic bypass for multi-clock domain testing
06/28/12Frequency division of an input clock signal
06/28/12Area efficient emi reduction technique for h-bridge current mode transmitter
06/28/12Coupled ring oscillator
06/28/12Crystal oscillator circuit
06/28/12Memory device
Patent Packs
06/28/12Memory device with robust write assist
06/28/12Integrated device test circuits and methods
06/28/12Signal synchronizing systems and methods
06/28/12Testing circuits
06/21/12Calibration arrangement
06/07/12Differential successive approximation analog to digital converter
06/07/12Write circuitry for hierarchical memory architectures
05/31/12Method and testing of a memory with redundancy elements
04/26/12Methods and decoding multiple independent audio streams using a single audio decoder
04/26/12Portable video player
04/12/12Reduction of signal skew
03/08/12Testing of non stuck-at faults in memory
02/23/12Fail safe adaptive voltage/frequency system
02/23/12Image processing arrangement
01/19/12Level shifter
Patent Packs
01/19/12Circuit for testing integrated circuits
12/22/11System for entropy decoding of h.264 video for real time hdtv applications
12/08/11Word line driver for memory
12/01/11Power measurement circuit
11/17/11Glitch free dynamic element matching scheme
11/10/11High jitter and frequency drift tolerant clock data recovery
11/10/11Sense amplifier using reference signal through standard mos and dram capacitor
11/03/11Multi-threshold complementary metal-oxide semiconductor master slave flip-flop
11/03/11Apparatus and testing shadow logic
10/27/11Testing of multi-clock domains
09/15/11Current steering dac with switched cascode output current source/sink
08/18/11Architecture incorporating configurable controller for reducing on chip power leakage
07/21/11Low consumption flip-flop circuit with data retention and method thereof
07/14/11Area-efficient distributed device structure for integrated voltage regulators
06/23/11Memory device and writing data to a memory device
06/23/11Memory device and operation thereof
06/23/11Parallelization of variable length decoding
06/23/11Memory card and communication method between a memory card and a host unit
06/16/11Frequency modulated signal decoding using a driver
06/16/11Synthesizable dll on system-on-chip
06/16/11On-the-fly frequency switching while maintaining phase and frequency lock
06/16/11Gop-independent dynamic bit-rate controller
06/16/11Quadrature signal decoding using a driver
06/16/11Protocol sequence generator
06/16/11Noise removal system
05/26/11Parallel decoding for scalable video coding
05/19/11Output common mode voltage stabilizer over large common mode input range in a high speed differential amplifier
05/12/11Acknowledgement management technique for supported command set of smbus/pmbus slave applications
05/05/11Multi-supply voltage compatible i/o ring
04/21/11High voltage tolerance of external pad connected mos in power-off mode
Social Network Patent Pack
04/14/11Wear leveling in storage devices based on flash memories and related circuit, system, and method
03/24/11Fail safe adaptive voltage/frequency system
03/17/11Reducing switching noise
03/10/11System and object based parametric video coding
02/24/11Reduced area schmitt trigger circuit
02/10/11Reduction in kickback effect in comparators
02/03/11Self-timed write boost for sram cell with self mode control
01/06/11Voltage regulator
01/06/11Operating a switched-capacitor circuit with reduced noise
01/06/11Offset-free sinc interpolator and related methods
Patent Packs
12/23/10Retention of data during stand-by mode
12/16/10Shared fuse wrapper architecture for memory repair
09/30/10Clock recovery from data streams containing embedded reference clock values
08/26/10Architecture for efficient usage of io
08/19/10Overlaying videos on a display device
07/08/10Balanced sense amplifier for single ended bitline memory architecture
07/08/10System and on-chip jitter and duty cycle
07/08/10Data storage element sensing device
07/01/10Signal synchronization in multi-voltage domains
07/01/10On-chip power management
07/01/10Base cell for engineering change order (eco) implementation
07/01/10Single-ended bit line based storage system
06/24/10High voltage switch with reduced voltage stress at output stage
06/24/10Pulse filtering module circuit, system, and method
06/24/10Matrix structure oscillator
06/24/10Write circuitry for hierarchical memory architecture
06/24/10Noise tolerant sense circuit
06/24/10System and optimizing electrical power consumption
06/17/10Reduction of power consumption in a memory device during sleep mode of operation
06/10/10Routing system
06/10/10Routing system
06/03/10Assistance in reset of data storage array
05/27/10System and a generating time bases in low power domain
05/13/10Switched charge storage element network
05/06/10Detecting data-access-element-selection errors during data access in data-storage arrays
04/15/10Method and designing a communication mechanism between embedded cable modem and embedded set-top box
03/11/10Fail-safe high speed level shifter for wide supply voltage range
01/28/10System and on-chip duty cycle measurement
01/21/10System and efficient detection and restoration of data storage array defects
10/22/09Method and system for channel selection in a digital broadcast reception terminal
Patent Packs
09/10/09Low pin interface testing module
07/02/09Reduction of signal skew
05/21/09Fully integrated on-chip low dropout voltage regulator
04/30/09Arbiter module providing low metastability failure probability
04/09/09Compensated output buffer for improving slew control rate
03/19/09Flexible on chip testing circuit for i/o's characterization
01/28/10System and on-chip duty cycle measurement
01/21/10System and efficient detection and restoration of data storage array defects
07/04/13System and a low voltage bandgap reference
07/04/13System and a successive approximation analog to digital converter
09/06/12Memory device and writing data to a memory device
07/12/12Glitch free dynamic element matching scheme

ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009


This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. is not affiliated or associated with Stmicroelectronics Pvt Ltd in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Stmicroelectronics Pvt Ltd with additional patents listed. Browse our Agent directory for other possible listings. Page by