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Stmicroelectronics crolles 2 Sas patents

Recent patent applications related to Stmicroelectronics crolles 2 Sas. Stmicroelectronics crolles 2 Sas is listed as an Agent/Assignee. Note: Stmicroelectronics crolles 2 Sas may have other listings under different names/spellings. We're not affiliated with Stmicroelectronics crolles 2 Sas, we're just tracking patents.

ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "S" | Stmicroelectronics crolles 2 Sas-related inventors




Date Stmicroelectronics crolles 2 Sas patents (updated weekly) - BOOKMARK this page
10/19/17 new patent  Method and device for monitoring a critical path of an integrated circuit
10/19/17 new patent  Electro-optic device with multiple photonic layers and related methods
10/12/17Method for forming an electrical contact between a semiconductor film and a bulk handle wafer, and resulting structure
10/05/17Electronic device provided with a thermal dissipation member
10/05/17Multi-orientation integrated cell, in particular input/output cell of an integrated circuit
10/05/17Higher order optical pam modulation using a mach-zehnder interferometer (mzi) type optical modulator having a bent optical path
09/28/17Insulating wall and manufacturing the same
09/21/17Method of forming mos and bipolar transistors
09/21/17Method for fabrication of a field-effect with reduced stray capacitance
09/07/17Process for forming a layer of equiaxed titanium nitride and a mosfet device having a metal gate electrode including a layer of equiaxed titanium nitride
08/31/17High-sensitivity electronic detector
08/10/17Method and device for testing a chain of flip-flops
08/03/17Image sensor
08/03/17Image sensor with reduced spectral and optical crosstalk and making the image sensor
07/27/17Method of localized modification of the stresses in a substrate of the soi type, in particular fd soi type, and corresponding device
07/20/17Method for managing the operation of a test mode of a logic component with restoration of the pre-test state
07/13/17Three-dimensional integrated photonic structure with improved optical properties
07/13/17Electronic chip manufacturing method
07/06/17Time-of-flight detection pixel
07/06/17Method for making photonic chip with multi-thickness electro-optic devices and related devices
07/06/17Low-noise mos transistors and corresponding circuit
07/06/17Time-of-flight detection pixel
07/06/17Method of forming strained mos transistors
06/29/17Electro-optic device with grating period variation and related methods
06/29/17Method for producing low-permittivity spacers
06/29/17Integrated circuit and manufacturing the same
06/29/17Back-side illuminated pixel
06/29/17High-dynamic-range pixel
06/22/17Method of planarizing recesses filled with copper
06/22/17Routing for three-dimensional integrated structures
06/22/17Method for fabricating a jfet transistor within an integrated circuit and corresponding integrated circuit
06/22/17Integrated circuit cointegrating a fet transistor and a rram memory point
06/22/17Process for forming a layer of equiaxed titanium nitride and a mosfet device having a metal gate electrode including a layer of equiaxed titanium nitride
06/15/17Event detector
06/08/17Sbfet transistor and corresponding fabrication process
06/01/17Plasmonic filter
05/11/17Assembly of an integrated circuit chip and of a plate
05/11/17Global-shutter image sensor
05/04/17Image sensor
04/27/17Process for producing a contact on an active zone of an integrated circuit, for example produced on an soi substrate, in particular an fdsoi substrate, and corresponding integrated circuit
04/27/17Method of manufacturing a device with mos transistors
04/27/17System for converting thermal energy into electrical power
03/30/17Method of manufacturing a nanostructured spectral filter
03/16/17Integrated electro-optic modulator
03/16/17Method for causing tensile strain in a semiconductor film
03/09/17Mos transistor and manufacturing the same
03/02/17Integrated circuit including an active device for confinement of a light flux
03/02/17Arrayed waveguide grating multiplexer-demultiplexer and related control method
03/02/17Method for aligning electro-optic device with optical fiber array with optical grating couplers
03/02/17Electro-optic (e/o) device with an e/o amplitude modulator and associated methods
03/02/17Formation of ohmic contacts for a device provided with a region made of iii-v material and a region made of another semiconductor material
03/02/17Image sensor with reduced spectral and optical crosstalk
02/09/17Wafer planarization method
02/02/17Electrode for a metal-insulator-metal structure, capacitor of metal-insulator-metal type, and fabricating one such electrode and one such capacitor.
01/05/17Electro-optic device with semiconductor junction area and related methods
01/05/17Method for aligning electro-optic device with optical fiber array with optical grating couplers
01/05/17Integrated optical modulator of the mach-zehnder type
01/05/17Image sensor device with first and second source followers and related methods
01/05/17Image sensor device with first and second source followers and related methods
12/29/16Resistive memory cell having a compact structure
12/29/16Phase-change memory cell having a compact structure
12/22/16Optoelectronic device, in particular memory device
12/22/16Electronic component and manufacturing the same
12/22/16Process for producing a contact on an active zone of an integrated circuit, for example produced on an soi substrate, in particular an fdsoi substrate, and corresponding integrated circuit
12/15/16Electronic device with hollowed-out rear plate
Patent Packs
12/01/16Low reflectance back-side imager
12/01/16Method for local isolation between transistors produced on an soi substrate, in particular an fdsoi substrate, and corresponding integrated circuit
12/01/16Process for producing mos transistors having a larger channel width from an soi and in particular fdsoi substrate, and corresponding integrated circuit
11/24/16Transistor with a low-k sidewall spacer and making same
11/03/16Integrated circuit chip assembled on an interposer
09/29/16Method of formation of a substrate of the soi, in particular the fdsoi, type adapted to transistors having gate dielectrics of different thicknesses, corresponding substrate and integrated circuit
09/22/16Process for producing, from an soi and in particular an fdsoi type substrate, transistors having gate oxides of different thicknesses, and corresponding integrated circuit
09/22/16Method and structure of making enhanced utbb fdsoi devices
09/22/16Method and structure of making enhanced utbb fdsoi devices
09/08/16Method and structure to reduce parasitic capacitance in raised source/drain silicon-on-insulator devices
08/18/16Thermal energy harvesting device
08/11/16Color image sensor and manufacturing the same
08/11/16Integrated hybrid laser source compatible with a silicon technology platform, and fabrication process
07/28/16Process for assembling two wafers and corresponding device
06/30/16Image sensor device with first and second source followers and related methods
Patent Packs
06/30/16Method and structure of making enhanced utbb fdsoi devices
06/30/16Method and structure of making enhanced utbb fdsoi devices
06/30/16Ic image sensor device with twisted pixel lines and related methods
06/23/16Method for fabricating a transistor with a raised source-drain structure
06/16/16Assembly of an integrated circuit chip and of a plate
06/16/16Image sensor illuminated and connected on its back side
06/16/16Device for converting thermal energy into electrical energy
06/09/16High frequency attenuator
06/02/16Thermo-electric generator
05/12/16Nanowire and planar transistors co-integrated on utbox soi substrate
05/12/16Multi-orientation integrated cell, in particular input/output cell of an integrated circuit
04/28/16Image sensor with vertical electrodes
04/28/16Transformer of the balanced-unbalanced type
04/21/16Oxide capacitor electro-optical phase shifter
04/14/16Pinned photodiode with a low dark current
04/14/16Photodiode insulation structure
04/07/16Method for relaxing the transverse mechanical stresses within the active region of a mos transistor, and corresponding integrated circuit
04/07/16Back-illuminated integrated imaging device with simplified interconnect routing
04/07/16Method for making an integrated circuit
03/17/16Production of spacers at flanks of a transistor gate
03/17/16Device for generating a clock signal by frequency multiplication
03/10/16Method for the formation of a finfet device with epitaxially grown source-drain regions having a reduced leakage path
02/25/16Vertical gate transistor and pixel structure comprising such a transistor
02/25/16Laser device and process for fabricating such a laser device
02/18/16Method of manufacturing a photonic integrated circuit optically coupled to a laser of iii-v material
02/11/16Method of making a transistor
01/07/16Generation of localized strain in a soi substrate
12/31/15Method for managing the operation of a circuit with triple modular redundancy and associated device
11/26/15Method of planarizing recesses filled with copper
10/29/15Arrayed waveguide grating multiplexer-demultiplexer and related control method
Social Network Patent Pack
10/29/15Pmos transistor with improved mobility of the carriers
10/29/15Fabrication a transistor with improved field effect
10/22/15Thermoelectric generator comprising a deformable by-layer membrane exhibiting magnetic properties
10/22/15Method for measuring thickness variations in a layer of a multilayer semiconductor structure
10/15/15Insulating trench forming method
10/08/15Integrated circuit chip and fabrication method
10/08/15Method for producing at least one pad assembly on a support for the self-assembly of an integrated circuit chip on the support by the formation of a fluorinated material surrounding the pad and exposure of the pad and the fluorinated material to an ultraviolet treatment in the presence of ozone
10/01/15Isolation structure adapted to electro-optical devices and use in an scr protection device
10/01/15Esd protection thyristor adapted to electro-optical devices
10/01/15Photodiode insulation structure
Patent Packs
10/01/15Vertical gate transistor and pixel structure comprising such a transistor
09/24/15Integrated circuit chip assembled on an interposer
09/17/15Large bandwidth multi-mode interference device
09/17/15Method for the formation of different gate metal regions of mos transistors
09/17/15Heat pipe and manufacturing the same
09/10/15Dynamic esd protection device adapted to electro-optical devices
09/10/15Method of manufacturing bistable strips having different curvatures
07/16/15Transistor having a gate comprising a titanium nitride layer and depositing this layer
07/16/15Device comprising a three-dimensional integrated structure with simplified thermal dissipation, and corresponding fabrication method
06/11/15Method for the formation of a finfet device with epitaxially grown source-drain regions having a reduced leakage path
06/04/15Method for producing an integrated imaging device with front face illumination comprising at least one metal optical filter, and corresponding device
05/21/15Forming of a heavily-doped silicon layer on a more lightly-doped silicon substrate
05/21/15Insulation wall between transistors on soi
05/21/15Method for estimating the diffusion length of metallic species within a three-dimensional integrated structure, and corresponding three-dimensional integrated structure
05/21/15Heterojunction bipolar transistor reliability simulation method
04/30/15System for conversing thermal energy into electrical energy
04/30/15Optoelectronic device, in particular memory device
04/30/15Method of forming stressed semiconductor layer
04/30/15Method of stressing a semiconductor layer
04/30/15Method of forming stressed soi layer
04/23/15Method for fabricating nmos and pmos transistors on a substrate of the soi, in particular fdsoi, type and corresponding integrated circuit
04/09/15Method for relaxing the transverse mechanical stresses within the active region of a mos transistor, and corresponding integrated circuit
04/02/15Air-spacer mos transistor
04/02/15Method for making an integrated circuit
04/02/15Oxide capacitor elecro-optical phase shifter
03/26/15Proximity sensor including reference detector for stray radiation detection
03/19/15Integrated circuit chip cooling device
03/19/15Method for producing an optical filter in an integrated circuit, and corresponding integrated circuit
02/26/15Spad photodiode of high quantum efficiency
02/26/15Photodiode of high quantum efficiency
Patent Packs
02/26/15Stack of semiconductor structures and corresponding manufacturing method
02/26/15Method for forming integrated circuits on a strained semiconductor substrate
02/12/15Transistors with various levels of threshold voltages and absence of distortions between nmos and pmos
02/12/15Device for converting thermal power into electric power
02/05/15Back side illumination image sensor with low dark current
01/22/15Dual conversion gain image sensor cell
01/22/15Photosensitive cell of an image sensor
01/22/15Method of localized modification of the stresses in a substrate of the soi type, in particular fd soi type, and corresponding device
01/22/15Thermal energy harvesting optimisation with bistable elements and collaborative behavior
01/22/15Electronic device comprising an integrated circuit chip provided with projecting electrical connection pads
01/15/15Thermo-mechano-electrical converter
01/01/15Device for recovering and converting heat energy into electrical energy
01/01/15System and variable frequency clock generation
12/25/14Method for determining a three-dimensional stress field of an object, an integrated structure in particular, and corresponding system
12/25/14Forming of a nanostructured spectral filter
12/25/14Operating conditions compensation circuit
12/25/14Photonic integrated circuit and fabrication process
12/18/14Process for producing a through-silicon via and a through-silicon capacitor in a substrate, and corresponding device
12/18/14Method of making a semiconductor layer having at least two different thicknesses
12/18/14Method of making a transitor
Social Network Patent Pack
12/11/14Process for fabricating a three-dimensional integrated structure with improved heat dissipation, and corresponding three-dimensional integrated structure
12/11/14Process for producing at least one through-silicon via with improved heat dissipation, and corresponding three-dimensional integrated structure
11/20/14Integrated circuit comprising an isolating trench and corresponding method
11/06/14Planar transistors with nanowires cointegrated on a soi utbox substrate
10/30/14Method for producing a metal-gate mos transistor, in particular a pmos transistor, and corresponding integrated circuit
08/14/14Interconnection structure for an integrated circuit
08/07/14Air-spacer mos transistor
08/07/14Back-side illuminated image sensor with a junction insulation
05/29/14Method for forming an insulating trench in a semiconductor substrate and structure, especially cmos image sensor, obtained by said method
05/08/14Integrated circuit comprising a mos transistor having a sigmoid response and corresponding fabrication
04/03/14Semiconductor device comprising a crack stop structure
03/13/14Phase-change memory cell
03/13/14Phase-change memory cell
03/13/14Method for manufacturing a suspended membrane and dual-gate mos transistor
01/30/14Method of fabricating a device with a concentration gradient and the corresponding device
01/23/14Method for manufacturing a polycrystalline dielectric layer
11/07/13Stack of semiconductor structures and corresponding manufacturing method
11/07/13Device for converting thermal energy into electric energy in the presence of a hot source
10/31/13Shallow trench forming method
10/24/13Curved plate and forming the same
Social Network Patent Pack
10/17/13Image sensor of curved surface
10/03/13Energy harvesting device
09/19/13Effecting selectivity of silicon or silicon-germanium deposition on a silicon or silicon-germanium substrate by doping
08/15/13Chip assembly system
08/15/13Method for manufacturing an integrated circuit comprising vias crossing the substrate
07/18/13Tunnel-effect power converter
07/18/13Method for estimating the diffusion length of metallic species within a three-dimensional integrated structure, and corresponding three-dimensional integrated structure
06/27/13Process and system for designing a photolithography mask and a light source
06/20/13Method for forming a deep trench in a microelectronic component substrate
05/16/13Memory device
05/09/13Method for determining the local stress induced in a semiconductor material wafer by through vias
04/25/13Method for manufacturing insulated-gate transistors
04/25/13Method for manufacturing insulated-gate mos transistors
04/25/13Variable impedance device
04/18/13Process for producing at least one deep trench isolation
04/04/13Integrated circuit with a self-programmed identification key
04/04/13Method for formation of an electrically conducting through via
03/28/13Method for protection of a layer of a vertical stack and corresponding device
03/21/13Method for depositing a silicon oxide layer of same thickness on silicon and on silicon-germanium
03/14/13Method for forming a silicide layer at the bottom of a hole and device for implementing said method
03/07/13Method for forming an isolation trench
03/07/13Sram dimensioned to provide beta ratio supporting read stability and reduced write time
03/07/13Photolithography method using a chemically-amplified resist
02/28/13Method for producing a deep trench in a microelectronic component substrate
02/14/13Integrated dram memory device
02/14/13Method of determining focus and dose of an apparatus of optical micro-lithography
01/31/13Integrated circuit comprising an isolating trench and corresponding method
01/31/13Electronic chip comprising connection pillars and manufacturing method
01/31/13Transformer of the balanced-unbalanced type
01/31/13Integrated millimeter wave transceiver
Social Network Patent Pack
12/20/12Integrated circuit comprising an isolating trench and corresponding method
12/13/12Electronic component comprising a number of mosfet transistors and manufacturing method
12/06/12Matrix imaging device comprising at least one set of photosites with multiple integration times
12/06/12Process for fabricating a backside-illuminated imaging device and corresponding device
11/08/12Effecting selectivity of silicon or silicon-germanium deposition on a silicon or silicon-germanium substrate by doping
10/04/12Method for controlling the electrical conduction between two metallic portions and associated device
09/13/12Thermoelectric generator
09/06/12Manufacturing integrated circuits based on formation of lines and trenches
08/23/12Device and measuring light energy received by at least one photosite
08/09/12Method for manufacturing and reoxidizing a tin/ta2o5/tin capacitor
07/05/12Method for manufacturing a polycrystalline dielectric layer
07/05/12Integrated circuit chip and fabrication method
06/28/12Matrix imaging device having photosites with global shutter charge transfer
06/28/12Low-crosstalk front-side illuminated image sensor
06/21/12Image sensor with reduced optical crosstalk
06/21/12Process for fabricating integrated-circuit chips
06/21/12Method of assembling two integrated circuits and corresponding structure
06/21/12Interconnection structure for an integrated circuit
06/21/12Electrical energy generation device
06/21/12Process for fabricating integrated-circuit chips
06/14/12Integrated circuit chip and fabrication method
05/10/12Integrated circuit with protection from copper extrusion
04/19/12Method for forming integrated circuits on a strained semiconductor substrate
04/05/12Method for manufacturing mos transistors with different types of gate stacks
03/15/12Method and device for measuring the reliability of an integrated circuit
03/01/12Single-port memory access control device
02/16/12Method of synthesis of an electronic circuit
02/09/12Stand-alone device
01/26/12Process for generating electrical energy in a semiconductor device and the corresponding device







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