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Synopsys Inc
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Synopsys Inc patents

Recent patent applications related to Synopsys Inc. Synopsys Inc is listed as an Agent/Assignee. Note: Synopsys Inc may have other listings under different names/spellings. We're not affiliated with Synopsys Inc, we're just tracking patents.

ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "S" | Synopsys Inc-related inventors

Date Synopsys Inc patents (updated weekly) - BOOKMARK this page
10/12/17 new patent  Modeling a bus for a system design incorporating one or more programmable processors
10/12/17 new patent  Incrementally distributing logical wires onto physical sockets by reducing critical path delay
10/05/17Parasitic-aware blockage
10/05/17Scheme and design markup language for interoperability of electronic design application tool and browser
10/05/17Custom layout of integrated circuit (ic) designs
10/05/17Power harvesting for integrated circuits
09/28/17Method for testing computer program product
09/21/17Security remediation
09/14/17Analyzing delay variations and transition time variations for electronic circuits
09/07/17Detecting errors for function calls with an implicit receiver object
09/07/17Signal reconstruction in sequential logic circuitry
09/07/17Circuit verification on a distributed database processing system
09/07/17Capturing time-slice of emulation data for offline embedded software debug
08/31/17Reuse of extracted layout-dependent effects for circuit design using circuit stencils
08/31/17Testbench chaining for multiple blocks in hierarchical circuit design
08/31/17Interactive routing of connections in circuit using auto welding and auto cloning
08/31/17Creating and reusing customizable structured interconnects
08/31/17In-design real-time electrical impact verification flow
08/31/17Integrated circuit design using generation and instantiation of circuit stencils
08/31/17Image processing method
08/17/17Static timing analysis with improved accuracy and efficiency
08/17/17Configurable and programmable multi-core architecture with a specialized instruction set for embedded application based on neural networks
08/17/17Integrated circuit system with memory support and manufacture thereof
08/10/17Layer class relative density for technology modeling in ic technology
08/03/173d resist profile aware resolution enhancement techniques
08/03/17Entry finder for single layer differential group routing
07/20/17Incremental multi-patterning validation
07/20/17Pessimism reduction in static timing analysis
07/06/17Separating test coverage in software processes using shared memory
07/06/17Isolated debugging in an fpga based emulation environment
06/29/17Selective execution for partitioned parallel simulations
06/29/17Tined gate to control threshold voltage in a device formed of materials having piezoelectric properties
06/01/17Power-aware dynamic encoding
05/25/17Annotating isolated signals
05/25/17Topography simulation of etching and/or deposition on a physical structure
05/25/17Clock jitter emulation
05/25/17Floating node reduction using random walk method
05/25/17Multiple patterning layout decomposition considering complex coloring rules
05/11/17Scheme for masking output of scan chains in test circuit
05/11/17Memory tamper detection
05/11/17Dynamically loaded system-level simulation
05/11/17Interleaved analog-to-digital converter and calibrating an interleaved analog-to-digital converter
05/04/17Constructing fill shapes for double-patterning technology
05/04/17Buffer chain management for alleviating routing congestion
05/04/17Knowledge-based analog layout generator
05/04/17Atomic structure optimization
05/04/17Deterministic identifiers for source code elements
04/27/17Automatic control a true random number generator
04/27/17Automatically generated schematics and visualization
04/20/17Overlaying of clock and data propagation in emulation
04/20/17Determining slack estimates for multiple instances of a cell in a hierarchical circuit design
04/20/17Logic yield learning vehicle with phased design windows
04/13/17Signal reconstruction in sequential logic circuitry
03/30/17Waveform based reconstruction for emulation
03/30/17Alternative hierarchical views of a circuit design
03/23/17Method to approximate chemical potential in a ternary or quaternary semiconductor
03/23/17Equivalence checking of analog models
03/23/17Saving and restoring an emulation environment
03/23/17Placing and routing debugging logic
03/02/17Identifying failure indicating scan test cells of a circuit-under-test
03/02/17In-design real-time electrical impact verification flow
03/02/17Adaptive content dependent intra prediction mode coding
02/23/17Identifying failure mechanisms based on a population of scan diagnostic reports
02/23/17Accurate glitch detection
02/23/17Using sense amplifier as a write booster in memory operating with a large dual rail voltage supply differential
Patent Packs
02/16/17Evaluation of voltage domains in the presence of leakage and/or dynamic switching
02/16/17Protection scheme for embedded code
02/16/17Reference voltage generator for an analog-digital converter and analog-digital conversion
02/09/17Pre-silicon design rule evaluation
02/09/172d material super capacitors
02/02/17Sub-resolution assist feature implementation for shot generation
02/02/17Identifying software components in a software codebase
02/02/17Low power voltage regulator
01/26/17System and managing and composing verification engines
01/26/17Internet of things (iot) power and performance management technique and circuit methodology
01/26/17Semi-local ballistic mobility model
01/26/17Method to program bitcells of a rom array
01/26/17Methods for manufacturing integrated circuit devices having features with reduced edge curvature
01/19/17Software and hardware emulation system
01/19/17Power-and-ground (pg) network characterization and distributed pg network creation for hierarchical circuit designs
Patent Packs
01/12/17System and hierarchical power verification
01/12/17Method and word-level netlist preprocessing and analysis using same
01/05/17System and debugging multi-threaded processes
01/05/17Netlist abstraction for circuit design floorplanning
01/05/17Look-ahead timing prediction for multi-instance module (mim) engineering change order (eco)
01/05/17Validating a clock tree delay
01/05/17Detecting and displaying multi-patterning fix guidance
12/22/16Isolated debugging in an fpga based emulation environment
12/08/16Method for generating workload models from execution traces
12/08/16Simulation modeling frameworks for controller designs
12/08/16Integrated circuit on corrugated substrate
12/01/16Integrated mask-aware lithography modeling to support off-axis illumination and multi-tone masks
12/01/16Determining eco aggressor nets during incremental extraction
11/24/16Scheme for masking output of scan chains in test circuit
11/24/16Placing and routing debugging logic
11/24/16Isolation of ip units during emulation of a system on a chip
11/24/16Method and system for checking and correcting shoot-through in rtl simulation
11/24/16Method and cipher detection
11/17/16Method and automatic relative placement generation for clock trees
11/17/16Multi-scale simulation including first principles band structure extraction
11/17/163d resist profile aware etch-bias model
11/17/16Design tools for converting a finfet circuit into a circuit including nanowires and 2d material strips
11/17/16Sensing scheme for high speed memory circuits with single ended sensing
11/10/16Efficient event detection
11/10/16Efficient waveform generation for emulation
11/10/16Cells having transistors and interconnects including nanowires or 2d material strips
11/03/16Generating a circuit description for a multi-die field-programmable gate array
10/27/16Fpga trace memory
10/27/16Efficient resolution of latch race conditions in emulation
10/13/16System and reactive initialization based formal verification of electronic logic design
Social Network Patent Pack
10/13/16Area-delay-power efficient multibit flip-flop
10/06/16Clock-domain-crossing specific design mutations to model silicon behavior and measure verification robustness
10/06/16Method and modeling delays in emulation
10/06/16System and power verification using efficient merging of power state tables
09/29/16Scalable chip placement
09/29/16Nanowire or 2d material strips interconnects in an integrated circuit cell
09/22/16Transparent editing of physical data in hierarchical integrated circuit design
09/15/16Integrity protection for data storage
09/15/16Management of placement constraint regions in an electronic design automation (eda) system
09/15/16Method for achieving uniform etch depth using ion implantation and a timed etch
Patent Packs
09/08/16System and netlist clock domain crossing verification
08/25/16Methods for processing a computer simulation program and computer program product for implementing such a method
08/25/16Estimation of effective channel length for finfets and nano-wires
08/11/16First principles design automation tool
08/04/16Visual quality measure for real-time video processing
07/28/16Parameter extraction of dft
07/28/16X-propagation in emulation
07/28/16X-propagation in emulation using efficient memory
07/28/16Method and system for selecting stimulation signals for power estimation
07/14/16Circuit placement based on fuzzy clustering
07/14/16Asymmetric dense floating gate nonvolatile memory with decoupled capacitor
07/07/16Approximate functional matching in electronic systems
06/30/16Circuit design and optimization
06/30/16Methods and systems of detecting and analyzing correlated operations in a common storage
06/23/16Optimization of parasitic capacitance extraction using statistical variance reduction technique
06/23/16Low power verification a circuit description and system for automating a minimization of a circuit description
06/23/16Circuit technique to enhance slew rate for high speed applications
06/09/16Mapping intermediate material properties to target properties to screen materials
06/02/16Selective annotation of circuits for efficient formal verification with low power design considerations
06/02/16System for testing computer application
05/19/16System on chip i/o connectivity verification in presence of low power design considerations
05/05/16Managing model checks of sequential designs
05/05/16Automatic generation of properties to assist hardware emulation
05/05/16Methodology using fin-fet transistors
05/05/16Drc-based hotspot detection considering edge tolerance and incomplete specification
05/05/16Data storage element and signal processing method
04/21/16Method and transaction recording and visualization
04/21/16Simplifying modes of an electronic circuit by reducing constraints
04/14/16Buffer chain management for alleviating routing congestion
04/14/16Method and emulation and prototyping with variable cycle speed
Patent Packs
04/07/16Efficient power analysis
04/07/16Efficient emulation and logic analysis
04/07/16Matrix reduction for lithography simulation
03/31/16Optimizing designs of integrated circuits
03/31/16Method for organizing, controlling, and reporting on design mismatch information in ic physical design data
03/24/16Organization for virtual-flat expansion of physical data in physically-hierarchical ic designs
03/24/16Linear complexity prioritization of timing engineering change order failures
03/24/16Finfet with heterojunction and improved channel control
03/17/16Ic physical design using a tiling engine
03/10/16Selectively reducing graph based analysis pessimism
03/10/16Atomic scale grid for modeling semiconductor structures and fabrication processes
03/10/16Exponentially fitted approximation for anisotropic semiconductor equations
03/10/16Augmented simulation waveform propagation in delay calculation
03/03/16System and method using pass/fail test results to prioritize electronic design verification review
03/03/16Arrays with compact series connection for vertical nanowires realizations
02/18/16Memory data transfer method and system
02/18/16Generating a circuit description for a multi-die field-programmable gate array
02/18/16Integrated circuit for storing data
02/11/16Periodic signal measurement using statistical sampling
02/11/16Path-based floorplan analysis
Social Network Patent Pack
02/11/16Fixing of semiconductor hold time
02/11/16Sub-resolution assist feature implementation with shot optimization
02/11/16Finfet cell architecture with power traces
02/11/16Methods for manufacturing integrated circuit devices having features with reduced edge curvature
02/04/16Memory power supply load management
02/04/16Latch-up suppression and substrate noise coupling reduction through a substrate back-tie for 3d integrated circuits
02/04/16Optimizing constraint solving by rewriting at least one bit-slice constraint
02/04/16Delay-locked loop arrangement and operating a delay-locked loop circuit
01/28/16Diagnosis and debug with truncated simulation
01/28/16Calibration unit for calibrating an oscillator, oscillator arrangement and calibrating an oscillator
01/21/16Chip cross-section identification and rendering analysis
01/14/16Ground offset monitor and compensator
01/14/16Incremental slack margin propagation
01/14/16Elimination of illegal states within equivalence checking
01/14/16Method for modeling a photoresist profile
01/14/16Equivalence checking between two or more circuit designs that include square root circuits
12/31/15Scheduling in a multicore architecture
12/31/15Sub-module physical refinement flow
12/31/15Method for inserting and removing padding from packets
12/24/15Evaluation of thermal instability stress testing
Social Network Patent Pack
12/24/15Measurement of aggressor/victim capacitive coupling impact on timing
12/24/15Design tools for integrated circuit components including nanowires and 2d material strips
12/24/15Memory cells having transistors with different numbers of nanowires or 2d material strips
12/24/15Nanowire or 2d material strips interconnects in an integrated circuit cell
12/24/15Array with intercell conductors including nanowires or 2d material strips
12/24/15Cells having transistors and interconnects including nanowires or 2d material strips
12/17/15Command coverage analyzer
12/17/15Circuit skew compensation trigger system
12/10/15Efficient mechanism in hardware and software co-simulation system
12/10/15Method and system for generating a circuit design, calibration of an inspection process control and yield management
12/03/15Debug in a multicore architecture
11/26/15Negative plane usage with a virtual hierarchical layer
11/26/15Virtual hierarchical layer usage
11/26/15Virtual hierarchical layer patterning
11/26/15Virtual cell model geometry compression
11/26/15Virtual cell model usage
11/26/15Virtual hierarchical layer propagation
11/26/15Resolution enhancement techniques based on holographic imaging technology
11/12/15Floating metal fill capacitance calculation
11/12/15Phase interpolator with phase traversing for delay-locked loop
11/05/15Static analysis of computer code to determine impact of change to a code component upon a dependent code component
11/05/153d tcad simulation
11/05/15Sequential structure extraction by functional specification
11/05/15Multi-bit standard cells for consolidating transistors with selective sourcing
10/29/15Modifying a virtual processor model for hardware/software simulation
10/22/15Mask3d model accuracy enhancement for small feature coupling effect
10/22/15Finfet cell architecture with power traces
10/15/15Incremental functional verification of a circuit design
10/15/15Systems and methods for increasing debugging visibility of prototyping systems
10/15/15Integrated circuit devices having features with reduced edge curvature and methods for manufacturing the same
Social Network Patent Pack
10/08/15Categorized stitching guidance for triple-patterning technology
10/01/15Most activated memory portion handling
09/24/15Network flow based framework for clock tree optimization
09/24/15Goal-based cell partitioning in the presence of obstacles
09/17/15Finfet cell architecture with insulator structure
09/17/15Quality of results system
09/17/15Notch detection and correction in mask design data
09/10/15Extreme ultraviolet/soft x-ray laser nano-scale patterning using the demagnified talbot effect
09/10/15Determining a user-specified location in a graphical user interface of an electronic design automation tool
09/10/15High voltage switch with two or more outputs
09/03/15Hollow backlight unit
09/03/15Multi mode address spaces for pc to device transfer optimization
09/03/15Automatic layout modification tool with non-uniform grids
08/27/15Assertion extraction from design and its signal traces
08/13/15Identifying layout pattern candidates
08/13/15Placement of single-bit and multi-bit flip-flops
08/13/15Configurable fpga sockets
08/13/15Dynamically loaded system-level simulation
08/06/15Protection scheme for embedded code
07/30/15Method and automatic relative placement generation for clock trees
07/30/15Invariant sharing to speed up formal verification
07/30/15Virtual layer generation during failure analysis
07/23/15Placing transistors in proximity to through-silicon vias
07/09/15N-channel and p-channel end-to-end finfet cell architecture with relaxed gate pitch
06/25/15Generating hardware accelerators and processor offloads
06/18/15Controlling timing of negative charge injection to generate reliable negative bitline voltage
06/11/15Integrated mask-aware lithography modeling to support off-axis illumination and multi-tone masks
06/11/15Fault insertion for system verification
06/11/15Method and floating or applying voltage to a well of an integrated circuit

ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009


This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. is not affiliated or associated with Synopsys Inc in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Synopsys Inc with additional patents listed. Browse our Agent directory for other possible listings. Page by