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Synopsys Inc patents


Recent patent applications related to Synopsys Inc. Synopsys Inc is listed as an Agent/Assignee. Note: Synopsys Inc may have other listings under different names/spellings. We're not affiliated with Synopsys Inc, we're just tracking patents.

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Phase locked loop circuit with charge pump up-down current mismatch adjustment and static phase error reduction

A magnitude difference between intrinsic positive and negative current components forming a PLL's charge pump output current is determined by simultaneously outputting the intrinsic positive and negative pump current components, and incrementally increasing a bias current added to one of the intrinsic current components (e.g., such that the total positive... Synopsys Inc

Cell-aware defect characterization and waveform analysis using multiple strobe points

A computer-implemented method for characterizing a circuit is presented. The method includes receiving, by the computer, data representative of the circuit and at least one defect of the circuit. The method further includes simulating, using the computer, the circuit to obtain a first timing characteristic, and simulating, using the computer,... Synopsys Inc

Guarded memory access in a multi-thread safe system level modeling simulation

Methods, systems, and machine readable medium for multi-thread safe system level modeling simulation (SLMS) of a target system on a host system. An example of a SLMS is a SYSTEMC simulation. During the SLMS, SLMS processes are executed in parallel via a plurality of threads. SLMS processes represent functional behaviors... Synopsys Inc

Placing and routing debugging logic

Embodiments relate an emulation environment that places debugging logic in a manner that connections between the debugging logic and logic components outputs can be efficiently routed. In one embodiment, the host system places the debugging logic after placing the logic components of the DUT, but before routing the logic components.... Synopsys Inc

One-time programmable bitcell with native anti-fuse

An OTP memory device includes a first and a second doped region of the same polarity in a semiconductor substrate. The second doped region has a higher doping concentration than the first doped region. A source region and a drain region of an opposite polarity are also in the semiconductor... Synopsys Inc

Static code testing of active code

A code deployment system deploys code to a set of application systems that execute the application, which may be across several tiers of systems that service requests related to the application. At each system, the application executes and is analyzed during execution to determine active code that is loaded by... Synopsys Inc

Automated http user flows simulator

A testing method and system for automatic Hypertext Transfer Protocol (HTTP) testing, the system including a memory configured to store sequences of user requests, a program store storing code for emulating a sequence of user requests, and at least one processor coupled to the program store and to the memory... Synopsys Inc

Optimizing the ordering of the inputs to large commutative-associative trees of logic gates

A method of optimizing a netlist for a circuit comprising identifying a logic tree with a single output and a plurality of interchangeable inputs, and calculate the optimal permutation of the plurality of inputs. The method further comprising modify the netlist based on the optimal permutation, and optimizing the modified... Synopsys Inc

Reset domain crossing management using unified power format

Information from a circuit design's unified power format (UPF) description is utilized to automate the management of reset domain crossings (RDCs). The UPF description is utilized to identify signals that generate both RDC and power domain crossings (PDCs), thereby allowing a circuit designer to efficiently utilize a common (shared) isolation... Synopsys Inc

Method and collecting signal values in fpga based emulation machine

Systems and methods for collecting signal values in FPGA based emulation machine. A single LUT is used to observe three observable points within a VLSI. A 6-input LUT is used to implement scan cells. Each scan cell implements a 4:1 multiplexer using the 6-input LUT. Each scan cell also uses... Synopsys Inc

Logic timing and reliability repair for nanowire circuits

A method for improving an integrated circuit design having transistors with nanowire channels comprises identifying a particular device having a particular transistor with a nanowire channel; and adding to the integrated circuit design a controller which, when activated, repairs the particular transistor by self-heating. A critical path in logic circuitry... Synopsys Inc

Enhancing memory yield and performance through utilizing nanowire self-heating

A method for improving an integrated circuit design which has transistors with nanowire channels comprises identifying a particular device having a particular transistor with a nanowire channel; and adding to the integrated circuit design circuitry which, when activated, repairs the particular transistor by self-heating. The method can comprise determining a... Synopsys Inc

2d material super capacitors

Devices and methods are described relating to capacitor energy storage devices that are small in size and have a high energy stored to volume ratio. The capacitor devices include 2D material electrodes. The capacitor devices offer very fine granularity with high stacking possibilities which may be used in super capacitors... Synopsys Inc

Integrated circuit devices having features with reduced edge curvature and methods for manufacturing the same

A structure such as an integrated circuit device is described having a line of material with critical dimensions which vary within a distribution substantially less than that of a mask element, such as a patterned resist element, used in manufacturing the line of material.... Synopsys Inc

Partitioning and routing multi-slr fpga for emulation and prototyping

A computer-implemented method for configuring a hardware verification system includes receiving, in the computer, a first data representative of a first design. The method further includes performing a first mapping of the first data to generate a second data in accordance with a first cost function and one or more... Synopsys Inc

Efficient emulation of circuits

When a communication unit of an FPGA receives emulated signals of a design under test that are to be transmitted to another FPGA, the communication unit analyzes each signal to determine whether a signal event has occurred for the signal. The communication unit transmits to the other DUT FPGA a... Synopsys Inc

Context aware clock tree synthesis

Systems and techniques are described for context aware clock tree synthesis (CTS). A probability value can be computed for each clock sink in the set of clock sinks, wherein each probability value represents a probability that the corresponding clock sink has a critical clock latency. Next, the set of clock... Synopsys Inc

Robust negative bit-line and reliability aware write assist

A reliability aware negative bit-line write assist (RA-NBL) circuit comprises a coupling capacitor to provide a negative bump for write assist, and a control input generator control charging of the coupling capacitor, such that the negative bump is high at a low voltage, and the negative bump is low at... Synopsys Inc

Communication between threads of multi-thread processor

Embodiments of the present disclosure support hardware based thread switching in a multithreading environment. The tread switching is implemented on a multithread microprocessor by utilizing thread mailbox registers and other auxiliary registers that can be pre-programmed for hardware based thread switching. A set of mailbox registers can be allocated to... Synopsys Inc

Thread switching in microprocessor without full save and restore of register file

Certain embodiments of the present disclosure support a method and apparatus for efficient multithreading on a single core microprocessor. Thread switching in the single core microprocessor presented herein is based on a reserved space in a memory allocated to each thread for storing and restoring of registers in a register... Synopsys Inc

Modulization of cache structure in microprocessor

Embodiments of the present disclosure support implementation of a Level-1 (L1) cache in a microprocessor based on independently accessed data and tag arrays. Presented implementations of L1 cache do not require any stall pipeline mechanism for stalling execution of instructions, leading to improved microprocessor performance. A data array in the... Synopsys Inc

Determining the resistance of a conducting structure

Systems and techniques are described for determining a resistance of a conducting structure. The conducting structure can be partitioned into a set of polygons based on (1) equipotential lines and (2) boundaries of the conducting structure. Next, a matrix equation can be constructed, wherein for at least one polygon in... Synopsys Inc

Automatic generation of properties to assist hardware emulation

Analysis of a first verification test suite automatically generates properties that may be directly used in a subsequent verification test suite. For example, an IP module may be verified by executing a software simulation test suite. The resulting data is accessed and analyzed to detect a set of properties of... Synopsys Inc

Schematic overlay for design and verification

Embodiments relate to schematic overlays describing modification to a base design for exploring modification or verification of the base design. Test circuitry may be modified or inserted without effecting the change in a base design schematics. The modifications to the base design schematics are also highlighted in views at a... Synopsys Inc

Placement of circuit elements in regions with customized placement grids

Embodiments relate to using placement grids corresponding to repeating track patterns of metal layers in a region to place circuit elements. Each placement grid is defined by as a vertical pitch of a repeating track pattern of one metal layer and a horizontal pitch of another repeating track pattern of... Synopsys Inc

Categorized stitching guidance for triple-patterning technology

A method for making a multitude of masks for manufacturing an integrated circuit includes receiving the integrated circuit design printable using a multiple-patterning process. The design includes shapes and at least one layout conflict preventing decomposition of the design into the multitude of masks. The method further includes forming a... Synopsys Inc

X-propagation in emulation using efficient memory

Embodiments relate to the emulation of circuits, and representation of unknown states of signals. A disclosed system (and method and computer program product) includes an emulation environment to convert a digital signal of a DUT in a form capable of representing an unknown state. In addition, the disclosed system converts... Synopsys Inc

Always-on tie cells for low power designs and manufacture thereof

Always-on (AO) tie cells, whose power supply has to remain on when the primary supply to the power domain is off, are used to implement logic constants. In accordance with embodiments of the present disclosure, insulated and non-insulated AO tie cells improve the QoR of the layout design and lower... Synopsys Inc

Heterojunction field effect transistor device with serially connected enhancement mode and depletion mode gate regions

Roughly described, a heterojunction field effect transistor device includes a first piezoelectric layer supporting a channel region, a second piezoelectric layer over the first, and a source and drain. A dielectric layer over the second piezoelectric layer electrically separates the source and drain, and has a plurality of segments, two... Synopsys Inc

High-performance content reconstruction of merged and removed cells in integrated circuit layout verification process

Various methods, apparatus, systems, and non-transitory computer-readable storage medium are provided for facilitating content reconstruction of merged and removed cells in an integrated circuit layout verification process. An example method comprises identifying one or more particular cells comprising original cell content requested by cell-specific operations, determining a set of cells... Synopsys Inc

Systems and methods for model-based analysis of software

Disclosed herein are methods, systems, and computer program products directed to a guidance engine. The guidance engine is configured to query a knowledge base for guidance with respect to a property of a software application. The guidance engine receives a responsive query from the knowledge base that is based on... Synopsys Inc

Systems and methods for using semantic queries to analyze software

Systems and methods for software verification. In some embodiments, a statement is identified from a discovery query written in a query language, comprising a semantic operator with at least a first parameter and a second parameter, wherein: the first parameter comprises a first syntactic pattern; the second parameter comprises a... Synopsys Inc

System and methods for model-based analysis of software

Systems and methods for software verification. In some embodiments, an application architecture model is generated for a software application, wherein: the application architecture model is generated based on source code of the software application and a framework model representing a software framework using which the software application is developed; and... Synopsys Inc

Systems and methods for incremental analysis of software

Systems and methods for software verification. In some embodiments, a first application architecture model is generated for a software application, wherein: the first application architecture model is generated based on a first version of source code of the software application; and the first application architecture model comprises a plurality of... Synopsys Inc

Detecting mistyped identifiers and suggesting corrections using other program identifiers

A code testing system determines mistyped identifiers in computer language code. For identifiers of objects in the code, such as variables and functions, the instances of the identifiers are identified in the code and recorded in an occurrence table. Uses of an identifier may be identified as copies of one... Synopsys Inc

11/16/17 / #20170329723

Protection scheme for embedded code

A code protection scheme for controlling access to a memory region in an integrated circuit includes a processor with an instruction pipeline that includes multiple processing stages. A first processing stage receives one or more instructions. A second processing stage receives address information identifying a protected memory region of the... Synopsys Inc

11/16/17 / #20170329882

Parameter extraction of dft

Electronic design automation to simulate the behavior of structures and materials at multiple simulation scales with different simulators.... Synopsys Inc

11/16/17 / #20170329974

Systems and methods for adaptive analysis of software

Systems and methods for software verification. In some embodiments, an application architecture model is generated for a software application, wherein: the application architecture model is generated based on source code of the software application; and the application architecture model comprises a plurality of component models. A property model type may... Synopsys Inc

11/16/17 / #20170330613

Sram and periphery specialized device sensors

A system to enable detection of the process corner of each of the P and N devices of an SRAM array (of bitcells) and of peripheral devices. This permits more focused (optimized and compensated) design of non-SRAM peripheral circuits and of read and write assist circuits for better handling of... Synopsys Inc

11/16/17 / #20170330872

Method and floating or applying voltage to a well of an integrated circuit

In one well bias arrangement, no well bias voltage is applied to the n-well, and no well bias voltage is applied to the p-well. Because no external well bias voltage is applied, the n-well and the p-well are floating, even during operation of the devices in the n-well and the... Synopsys Inc

11/16/17 / #20170331850

Systems and methods for analyzing software using queries

Systems and methods for software verification. In some embodiments, a first statement is identified, from a discovery query written in a query language, the first statement comprising a side-effect construct with at least a first parameter and a second parameter, wherein: the first parameter of the side-effect construct comprises at... Synopsys Inc

11/02/17 / #20170316118

Graphical view and debug for coverage-point negative hint

The present invention provides a graphical view of this connected network that allows the user to navigate throughout a network. The graph view consists of a series of nodes that correspond to a set of test, testbench, design or coverage items in the simulation. Various nodes in the network are... Synopsys Inc

10/26/17 / #20170308629

Sliding time window control mechanism for parallel execution of multiple processor core models in a virtual platform simulation

Embodiments of the present disclosure support a simulation of a plurality of processor core models. The processor core models are executed in parallel within a sliding time window of a defined size. Each processor core model is executed in a different corresponding thread and advances a local core time within... Synopsys Inc

10/12/17 / #20170293702

Modeling a bus for a system design incorporating one or more programmable processors

Systems and methods for modeling a bus for a system design are provided. In an embodiment, the method operates by accepting a virtual bus model, wherein the model simulates behavior for a bus master and slave device, such that the model accurately simulates the timing and behavior of the transfer... Synopsys Inc

10/12/17 / #20170293708

Incrementally distributing logical wires onto physical sockets by reducing critical path delay

Configuring a hardware system includes providing a first data representative of a first assignment of a multitude of wires to a multitude of physical connections between a multitude of logic circuits of the hardware system, and transforming the first data into a second data representative of a second assignment of... Synopsys Inc

10/05/17 / #20170286576

Parasitic-aware blockage

A parasitic-aware blockage structure is provided to replace a detailed blockage structure for use in connection with a capacitance extraction operation. The parasitic-aware blockage structure includes one or more parasitic-aware blockage polygons, each representing a plurality of polygons of the detailed blockage structure. The parasitic-aware blockage polygons can be formed... Synopsys Inc

10/05/17 / #20170286581

Scheme and design markup language for interoperability of electronic design application tool and browser

A bi-directional EDA-browser bridge mechanism enables an EDA system and its related (external) tools to interact with a browser. The EDA-browser bridge uses a design markup language (DML) to communicate with the browser, using a document-based approach rather than a more traditional programming/API-based approach to extending (e.g., integrating tools) the... Synopsys Inc

10/05/17 / #20170286584

Custom layout of integrated circuit (ic) designs

Systems and techniques for facilitating layout of an integrated circuit (IC) design are described. A distinct color pattern can be assigned to a set of shapes in a layout of the IC design that correspond to a net. Next, the layout of the IC design can be displayed in a... Synopsys Inc

10/05/17 / #20170287977

Power harvesting for integrated circuits

Integrated circuit devices which include a thermoelectric generator which recycles heat generated by operation of an integrated circuit, into electrical energy that is then used to help support the power requirements of that integrated circuit. Roughly described, the device includes an integrated circuit die having an integrated circuit thereon, the... Synopsys Inc

09/28/17 / #20170277890

Method for testing computer program product

This document discloses a solution for detecting, by a computer apparatus, computer program library in a binary computer program code. A method according to an embodiment of the solution comprises in the computer apparatus: acquiring a reference computer program library file in a binary form; and determining at least one... Synopsys Inc

09/21/17 / #20170270302

Security remediation

A method is provided to remediate defects in first computer program code that can be used to configure a computer to produce code for use by the same or a different computer configured using second computer program code to use the produced code to produce output information, the method comprising:... Synopsys Inc

09/14/17 / #20170262569

Analyzing delay variations and transition time variations for electronic circuits

A system receives a circuit description and measures of intrinsic delay, intrinsic delay variation, transition time and transition time variation for each stage and determines stage delay variation of each stage. The system receives a circuit description and derate factors and determines an intrinsic delay standard deviation and a correlation... Synopsys Inc

09/07/17 / #20170255543

Detecting errors for function calls with an implicit receiver object

A code testing system identifies possible code errors that may generate unexpected application behaviors. The code testing system identifies function calls in the system by identifying function call sites that do not specify a receiver object but may invoke a function that uses a receiver object. To identify these call... Synopsys Inc

09/07/17 / #20170255726

Signal reconstruction in sequential logic circuitry

A method for reconstructing at least one output signal associated to a sequential logic circuitry block of a circuit is disclosed. At least one input signal is associated to the sequential logic circuitry block. The method comprises determining a value of the at least one output signal depending on the... Synopsys Inc

09/07/17 / #20170255727

Circuit verification on a distributed database processing system

Example embodiments of disclosed configurations include a process (and system and non-transitory computer storage readable medium) for verifying an operation or a functionality of a design under test (DUT) through a distributed database processing system. In one or more embodiments, the emulator performs emulation of a DUT, and traces signals... Synopsys Inc

09/07/17 / #20170255728

Capturing time-slice of emulation data for offline embedded software debug

Disclosed is a method (or a system or a non-transitory computer readable medium) for recreating states of an embedded processing unit of a design under test (DUT). In one aspect, a host system configures an emulator to implement the DUT. The DUT includes the embedded processing unit and a memory... Synopsys Inc

08/31/17 / #20170249400

Reuse of extracted layout-dependent effects for circuit design using circuit stencils

A method for reuse of extracted layout-dependent effects for circuit design using circuit stencils includes receiving a schematic of an integrated circuit including a circuit segment. A circuit stencil corresponding to the circuit segment is instantiated in a schematic of a second integrated circuit. The circuit stencil includes layout-dependent effects... Synopsys Inc

08/31/17 / #20170249411

Testbench chaining for multiple blocks in hierarchical circuit design

A selection of a source testbench is received from a user. The source testbench includes a description of one or more source parameters, a description of one or more source measurements, and a plurality of source entries, each of the source entries including a value for each of the one... Synopsys Inc

08/31/17 / #20170249413

Interactive routing of connections in circuit using auto welding and auto cloning

Embodiments relate to an interactive routing of connections in a circuit where connections associated with an initial pin of a circuit element (e.g., a row of FinFETs) are replicated in association with at least one other pin of the same circuit element or a different circuit element in the circuit.... Synopsys Inc

08/31/17 / #20170249414

Creating and reusing customizable structured interconnects

A customizable routing system allows designers to create custom connection layouts that can be stored, turned into templates, reused, and further customized. The system describes designer-input custom connection layouts in terms of “structural directives” that specify its patterns and properties instead of using precise dimensions. Structural directives may describe particular... Synopsys Inc

08/31/17 / #20170249415
08/31/17 / #20170249416

Integrated circuit design using generation and instantiation of circuit stencils

Embodiments relate to designing of integrated circuits using generation and instantiation of circuit stencils. The circuit stencil represents an abstracted version of the circuit segment. The circuit stencils include collapsed versions of the connectivity information of components and nodes of the integrated circuit. The collapsed version of the connectivity information... Synopsys Inc

08/31/17 / #20170249529

Image processing method

A computer-implemented image processing technique for selectively recovering the features of an original CAD model after the original CAD model has been converted to a digitized image and a new CAD model generated from the digitized image. The original boundary representation provides a template to transform the representation through processing... Synopsys Inc

08/17/17 / #20170235868

Static timing analysis with improved accuracy and efficiency

A method for performing static timing analysis of an integrated circuit design, wherein at least two timing paths share a shared node comprises propagating along the at least two timing paths a plurality of timing signals characterized by a set of timing parameters and determining respective values of the timing... Synopsys Inc

08/17/17 / #20170236053

Configurable and programmable multi-core architecture with a specialized instruction set for embedded application based on neural networks

A programmable architecture specialized for convolutional neural networks (CNNs) processing such that different applications of CNNs may be supported by the presently disclosed method and apparatus by reprogramming the processing elements therein. The architecture may include an optimized architecture that provides a low-area or footprint and low-power solution desired for... Synopsys Inc

Patent Packs
08/17/17 / #20170236870

Integrated circuit system with memory support and manufacture thereof

A method of manufacturing an integrated circuit system, includes, in part, providing a planar surface on an insulator, forming first and second bottom electrodes over the insulator substrate, forming a first electrolyte over the first and second bottom electrodes, forming a first top electrode over the first electrolyte, forming and... Synopsys Inc

08/10/17 / #20170228492

Layer class relative density for technology modeling in ic technology

A method and apparatus of a novel modeling scheme for performing optical lithography simulation for a multi-color layer fabrication process is described. The method interpolates for simulation use between test or experimental data or descriptions to more accurately apply color differentiated parameters to the model creation and lithography simulation.... Synopsys Inc

08/03/17 / #20170220723

3d resist profile aware resolution enhancement techniques

Systems and techniques for three-dimension (3D) resist profile aware resolution enhancement techniques are described. 3D resist profile aware resolution enhancement models can be calibrated based on empirical data. Next, the 3D resist profile aware resolution enhancement models can be used in one or more applications, including, but not limited to,... Synopsys Inc

08/03/17 / #20170220724

Entry finder for single layer differential group routing

A method, apparatus and computer program products are provided for determining an entry finder from a plurality of merge points of a bounding box for optimal performance of differential group pattern match routing. One example method includes identifying each of a plurality of merge point candidates, performing a routability determination... Synopsys Inc

07/20/17 / #20170206300

Incremental multi-patterning validation

A computer-implemented method for validating a design characterized by a multi-patterning layer is presented. The method includes receiving the multi-patterning layer in a memory of the computer when the computer is invoked to validate the design. The method further includes correcting, using the computer, a first error in a first... Synopsys Inc

07/20/17 / #20170206301

Pessimism reduction in static timing analysis

A method for performing graph-based static timing analysis comprises reading in a design of an integrated circuit having a subset of timing paths, each timing path of the subset having a common point, wherein the common point is identical for all timing paths of the subset. The method comprises initiating... Synopsys Inc

07/06/17 / #20170192878

Separating test coverage in software processes using shared memory

A Remote Test Separation (RTS) system comprising an original software product instrumented for testing and a shared memory accessible to the original software product, the shared memory including a plurality of coverage counters. The RTS system further comprising an agent, capable of accessing the shared memory, the agent to read... Synopsys Inc

07/06/17 / #20170193146

Isolated debugging in an fpga based emulation environment

For a design under test (DUT) that is to be emulated, a host system partitions the DUT into multiple partitions and maps each partition to an FPGA of an emulator which will emulate the partition. The host system stores information describing to which FPGAs each component of the DUT has... Synopsys Inc

06/29/17 / #20170185700

Selective execution for partitioned parallel simulations

Computer implemented techniques for the partitioned simulation of parallel architectures are disclosed. A high-level design for simulation is obtained. A graph representation for the high-level design is determined. The graph for the high-level design is partitioned into sub-graphs. A subset of the sub-graphs is selected for simulation based on input-change... Synopsys Inc

06/29/17 / #20170186860

Tined gate to control threshold voltage in a device formed of materials having piezoelectric properties

Roughly described, a field effect transistor has a first piezoelectric layer supporting a channel, a second piezoelectric layer over the first piezoelectric layer, a dielectric layer having a plurality of dielectric segments separated by a plurality of gaps, the dielectric layer over the second piezoelectric layer, and a gate having... Synopsys Inc

06/01/17 / #20170154132

Power-aware dynamic encoding

Dynamic power-aware encoding method and apparatus is presented based on a various embodiments described herein. The experimental results confirmed that a desirable reduction in the toggling rate in the decompressed test stimulus is achievable by reasonable overhead (ATPG time, hardware overhead and pattern inflation) typically without degradation of a compression... Synopsys Inc

05/25/17 / #20170147720

Annotating isolated signals

Systems and techniques for creating and displaying a circuit design view are described. A hardware description language (HDL) specification and a power intent specification of the circuit design can be analyzed to determine a correspondence between one or more signals in the HDL specification and one or more isolation cells... Synopsys Inc

05/25/17 / #20170147724

Topography simulation of etching and/or deposition on a physical structure

Systems and techniques are described for topography simulation of etching and/or deposition on a physical structure. The structural information can be represented using a three-dimensional (3D) voxel grid data structure. For each particle emitted by a Monte-Carlo particle emission model, a topographical modification caused by the particle can be determined... Synopsys Inc

05/25/17 / #20170147725

Clock jitter emulation

An emulator emulating a DUT emulates a clock generator for generating clock signals of the DUT with jitter. As part of generating clock signals, the emulator generates a jitter clock value for each clock signal. To generate a jitter clock value for a clock signal, the emulator identifies a clock... Synopsys Inc

05/25/17 / #20170147729

Floating node reduction using random walk method

A method for floating node reduction uses a capacitance matrix that specifies coupling capacitances between signal nodes and floating nodes of an interconnect structure. Random walks are performed from a first signal node to the other signal nodes, wherein each of the random walks traverses one or more of the... Synopsys Inc

Patent Packs
05/25/17 / #20170147740

Multiple patterning layout decomposition considering complex coloring rules

A computer implemented method for decomposing a layout of a portion of an integrated circuit is presented. The layout includes a first multitude of polygons. The method includes constructing, using the computer, a first matrix representative of a first multitude of constraints. Each of the first multitude of constraints is... Synopsys Inc

05/11/17 / #20170131354

Scheme for masking output of scan chains in test circuit

A method for masking scan chains in a test circuit of an integrated circuit is disclosed. A test pattern to be fed into the test circuit of the integrated circuit is generated. The generated test pattern can be used for detecting a primary fault, one or more secondary faults, and... Synopsys Inc

05/11/17 / #20170132160

Memory tamper detection

A method and system for detecting tampering of authenticated memory blocks that are accessible by an untrusted host processor, by (1) periodically re-authenticating the memory blocks from a trusted computing environment, and (2) disabling accessing of the memory blocks by the untrusted host processor when the re-authenticating fails. In one... Synopsys Inc

05/11/17 / #20170132345

Dynamically loaded system-level simulation

A system-level simulation includes generating netlist information including component library information, which describes instances of the hardware components, and component instance information, which describes component dynamic libraries that include models of hardware components. The simulation is generated at simulation run-time based on the netlist information. Component dynamic libraries corresponding to... Synopsys Inc

05/11/17 / #20170134033

Interleaved analog-to-digital converter and calibrating an interleaved analog-to-digital converter

An interleaved analog-to-digital converter, ADC, comprises a first and a second sub-ADC (ADC1, ADC2) and a timing control unit (TC). The first sub-ADC (ADC1) is configured to convert a first calibration signal (V1cal) into a first calibration code (CC1) depending on a first sub-clock signal (Φ1). The second sub-ADC (ADC2)... Synopsys Inc

05/04/17 / #20170124242

Constructing fill shapes for double-patterning technology

A computer-implemented method for constructing a design characterized by a double patterning layer is presented. The method includes receiving the design in a memory of the computer when the computer is invoked to construct the design. The method further includes generating, using the computer, a multitude of fill shapes along... Synopsys Inc

05/04/17 / #20170124244

Buffer chain management for alleviating routing congestion

Systems and techniques for alleviating congestion are described. A set of buffer chains that pass through a congested region of the circuit design can be identified. Next, the set of the buffer chains can be removed from the circuit design. A placement blockage in the circuit design can then be... Synopsys Inc

05/04/17 / #20170124245

Knowledge-based analog layout generator

A computer-implemented method for generating a layout of a design includes invoking the computer to receive a schematic representation of the design, generating a connection graph associated with the design, comparing the connection graph with a plurality of connection graphs stored in a database and selecting a layout associated with... Synopsys Inc

05/04/17 / #20170124293

Atomic structure optimization

Electronic design automation modules simulate the behavior of structures and materials at atomic scale with parameters or a configuration that varies across iterative transformations.... Synopsys Inc

05/04/17 / #20170124305

Deterministic identifiers for source code elements

Multiple computer systems each include at least one EDA tool that performs certain EDA functions. Each computer system also includes source code of a design with the names of source code elements and an encoding module that generates unique identifiers for the source code elements according to a specific encoding... Synopsys Inc

04/27/17 / #20170115959

Automatic control a true random number generator

A system for reseeding a pseudo random number generator to generate pseudo random numbers includes a true random number generator generating a true random number, a storage device storing the generated true random number, a pseudo random number generator generating pseudo random numbers using the stored true random number as... Synopsys Inc

04/27/17 / #20170116364

Automatically generated schematics and visualization

An automated visualization tool in a command line environment allows complex log data to be represented by symbols and associated information for clarity of communication and better understanding of the associated design.... Synopsys Inc

04/20/17 / #20170109466

Overlaying of clock and data propagation in emulation

A computer-implemented method for configuring a hardware verification system is presented. The method includes receiving, in the computer, a first data representative of a first design including a first sequential element configured to be evaluated in accordance with a first signal, when the computer is invoked to configure the verification... Synopsys Inc

04/20/17 / #20170109468

Determining slack estimates for multiple instances of a cell in a hierarchical circuit design

Embodiments perform static timing analysis using a digital representation of a circuit. The digital representation of the circuit includes multiple instances of a cell in a hierarchical cell block circuit. Timing context information is determined for each instance of the cell included in the circuit. A merged timing context information... Synopsys Inc

04/20/17 / #20170109470

Logic yield learning vehicle with phased design windows

Techniques for providing improved semiconductor yield learning are discussed herein. Some embodiments may include a yield learning vehicle (YLV), including a communication fabric and a plurality of circuit blocks connected with the communication fabric. The plurality of circuit blocks may include circuit blocks having different design window sizes, and may... Synopsys Inc

04/13/17 / #20170103152

Signal reconstruction in sequential logic circuitry

A method for reconstructing at least one output signal associated to a sequential logic circuitry block of a circuit is disclosed. At least one input signal is associated to the sequential logic circuitry block. The method comprises simulating a value of the at least one output signal depending on the... Synopsys Inc

03/30/17 / #20170091360

Waveform based reconstruction for emulation

A disclosed system of an emulation environment performs a simulation to construct a waveform of a target signal based on signals traced by an emulator for a time frame including multiple clock cycles. In one embodiment, a simulation is performed in a manner that an input of the logic gate,... Synopsys Inc

03/30/17 / #20170091367

Alternative hierarchical views of a circuit design

Methods and apparatuses are described for creating, editing, and viewing a floorplan of a circuit design. Specifically, some embodiments enable a user to perform a graphical operation at an inference point in a circuit design layout, wherein the location of the inference point is determined based on existing graphical objects... Synopsys Inc

03/23/17 / #20170083644

Method to approximate chemical potential in a ternary or quaternary semiconductor

Roughly described, a method is provided to approximate chemical potentials of elements in ternary and quaternary compound semiconductors, for example III-V semiconductors. In embodiments of the present invention, three, four, or more relationships are solved together to find approximated chemical potentials for each group III element and each group V... Synopsys Inc

03/23/17 / #20170083651

Equivalence checking of analog models

Techniques for equivalence checking of analog models are disclosed. The models include transistor level representations. The representations are used for simulation and verification of the circuit and are required to give similar output results in response to a given input stimulus. A common input stimulus is created for a first... Synopsys Inc

03/23/17 / #20170083652

Saving and restoring an emulation environment

An emulator configured to emulate a DUT is connected to a client device. The client device includes a virtual machine that executes emulation processes against the emulated DUT. When a request is received to save the current state of the emulation environment, the virtual machine stops the execution of the... Synopsys Inc

03/23/17 / #20170083655

Placing and routing debugging logic

Embodiments relate an emulation environment that places debugging logic in a manner that connections between the debugging logic and logic components outputs can be efficiently routed. In one embodiment, the host system places the debugging logic after placing the logic components of the DUT, but before routing the logic components.... Synopsys Inc








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