Real Time Touch



new TOP 200 Companies filing patents this week

new Companies with the Most Patent Filings (2010+)




Real Time Touch

Synopsys Inc patents


Recent patent applications related to Synopsys Inc. Synopsys Inc is listed as an Agent/Assignee. Note: Synopsys Inc may have other listings under different names/spellings. We're not affiliated with Synopsys Inc, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "S" | Synopsys Inc-related inventors


 new patent  Context-dependent useful skew estimation for optimization, placement, and clock tree synthesis

A method for optimizing a circuit design includes computing clock latency estimates for a set of sequential circuit elements, modifying the clock latency estimates based on relative optimizability of (1) a set of input data paths that are electrically coupled to one or more inputs of the sequential circuit element and (2) a set of output data paths that are electrically coupled to one or more outputs of the sequential circuit element, and optimizing the circuit design based on the modified clock latencies.. . ... Synopsys Inc

 new patent  Waveform based reconstruction for emulation

A process is disclosed to identify the minimal set of sequential and combinational signals needed to fully reconstruct the combinational layout after emulation is complete. A minimal subset of sequential and combinational elements is output from the emulator to maximize the emulator speed and limit the utilization of emulator resources, e.g., fpga resources. ... Synopsys Inc

Finfet-based memory testing using multiple read operations

A test methodologies for detecting both known and potentially unknown finfet-specific faults by way of implementing an efficient and reliable base set of march elements in which multiple sequential march-type read operations are performed immediately after logic values (i.e., logic-0 or logic-1) are written into each finfet cell of a memory array. For example, a march-type write-1 operation is performed, followed immediately by multiple sequentially-executed march-type read-1 operations, then a march-type write-0 operation is performed followed immediately by multiple sequentially-executed march-type read-0 operations. ... Synopsys Inc

Virtual cell model geometry compression

Semiconductor designs are large and complex, typically consisting of numerous circuits called cells. To handle complexity, hierarchical structures are imposed on the semiconductor design to help accomplish analysis, simulation, verification, and so on. ... Synopsys Inc

Method and apparatus for soc with optimal rsma

A method for determining redundancy usage rate from a group of memory parameters and a memory yield of a system on a chip (soc), using the probabilistic redundancy usage rate and using that rate to calculate an optimal rsma size. An soc is then fabricated with the optimal rsma size.. ... Synopsys Inc

Analog centric current modeling within a digital testbench in mixed-signal verification

A method includes operating a digital simulator to mimic loading effects of digital circuit blocks of a circuit design on analog circuit blocks of the circuit design. The digital simulator sets a current signal timing and a current level value at an analog/digital boundary between the digital circuit aspects and the analog circuit aspects. ... Synopsys Inc

Clock jitter emulation

An emulator emulating a dut emulates a clock generator for generating clock signals of the dut with jitter. As part of generating clock signals, the emulator generates a jitter clock value for each clock signal. ... Synopsys Inc

Systems and methods for providing approximate electronic-structure models from calculated band structure data

Computer-aided methods for simulating confined nanodevices are disclosed. In example implementations, atomic-scale model of the nanodevices are generated so that dimensions and materials are specified. ... Synopsys Inc

Memory cells including vertical nanowire transistors

A circuit including an sram cell with a set of vertical nanowire transistor columns is provided. Each member of the set includes a vertical nanowire transistor and at least one member of the set is a vertical nanowire transistor column including two vertical nanowire transistors in series. ... Synopsys Inc

Drc processing tool for early stage ic layout designs

A drc tool optimized for analyzing early-stage (“dirty”) ic layout designs by performing one or more of (a) automatically selectively focusing drc processing to selected regions (i.e., layers and/or cells) of a dirty ic layout design that are most likely to provide useful error information to a user, (b) automatically selectively ordering and/or limiting rule checks performed during drc processing to provide the user with a manageable amount of error data in a predetermined reasonable amount of time, and (c) automatically providing error data in a graphical manner using a contrasting dot to indicate the location of each rule violation, whereby relevant problem areas of the dirty ic layout design are easily identified for correction by a human user, and non-relevant areas (e.g., missing block regions) can be efficiently identified and ignored, thereby facilitating efficient modification of the ic layout design.. . ... Synopsys Inc

Placement-based congestion-aware logic restructuring

Systems and techniques for optimizing an integrated circuit (ic) design are described. Some embodiments can transform a circuit design into a logically-equivalent circuit design by: (1) creating a wire-length-area model (wlam) for a portion of a first circuit design, (2) creating a second circuit design by replacing the portion of the first circuit design by the wlam, (3) placing and routing the second circuit design to obtain a placed-and-routed second circuit design, and (4) creating a third circuit design that is logically-equivalent to the first circuit design based on the placed-and-routed second circuit design.. ... Synopsys Inc

Coupled-domains disturbance matrix generation for fast simulation of wafer topography proximity effects

A coupled-domains method for generating disturbance matrices used in correcting topography proximity effects (tpe) for integrated circuit (ic) designs that include inhomogeneous substrates. The ic design is modeled and divided into domains (z-direction regions), each domain defined by upper/lower horizontal domain boundaries and optical properties generated by its associated geometry and material composition. ... Synopsys Inc

Power computation logic

A computer-aided method for configuring a hardware verification system is presented. The method includes receiving, by the computer, a first data representative of a first design of an integrated circuit, when the computer is invoked to configure the verification system, and transforming, using the computer, the first data into a second data representative of a second design. ... Synopsys Inc

Managing resources for multiple trial distributed processing tasks

A computer-implemented method of managing resources for multiple trial distributed processing tasks is presented. The method includes estimating an expected time needed to process each of a set of mask patterns which can be independently processed. ... Synopsys Inc

04/19/18 / #20180108666

Asymmetric dense floating gate nonvolatile memory with decoupled capacitor

A nonvolatile memory (“nvm”) bitcell with one or more active regions capacitively coupled to the floating gate but that are separated from both the source and the drain. The inclusion of capacitors separated from the source and drain allows for improved control over the voltage of the floating gate. ... Synopsys Inc

04/19/18 / #20180107779

Multi-bit-mapping aware clock gating

Systems and techniques are described for optimizing an integrated circuit (ic) design. Some embodiments can select a wide-bus in the ic design. ... Synopsys Inc

04/19/18 / #20180107777

Optimizing an integrated circuit (ic) design comprising at least one wide-gate or wide-bus

Systems and techniques are described for optimizing an integrated circuit (ic) design. Some embodiment can perform enumeration on a hardware description language (hdl) description of an ic design to obtain a enumerated ic design that includes at least one technology-independent wide-gate or technology-independent wide-bus, wherein the technology-independent wide-gate represents a logical function that is performed on a variable number of inputs, and wherein the technology-independent wide-bus represents a variable number of signals that are part of a bus. ... Synopsys Inc

04/19/18 / #20180107587

Command coverage analyzer

A method and apparatus of a novel command coverage analyzer is disclosed. Combinations of commands, options, arguments, and values of a product are extracted, customer environment and uses are considered, and a more comprehensive and accurate quality of software process and metric is provided.. ... Synopsys Inc

04/05/18 / #20180095491

Band-gap reference circuit with chopping circuit

A bgr circuit for sub-1v ics utilizes a voltage chopping circuit and/or a current chopping circuit and a low-frequency filter to stabilize the output reference voltage that is generated by an op-amp, a current mirror circuit, a ctat stage, a ptat stage, and an output stage. The voltage chopping circuit reduces input offset and 1/f noise by periodically alternating (time-averaging) the negative temperature dependent and positive temperature dependent voltages supplied by the ctat and ptat stages to the op-amp's input terminals. ... Synopsys Inc

03/29/18 / #20180089353

Virtual terminals for linear-parameter extraction

A method to evaluate a resistor structure is described. In one embodiment, the method includes receiving an input file specifying a resistor structure, modifying at least one aspect of the resistor structure, and polishing data representing the modified resistor structure. ... Synopsys Inc

03/29/18 / #20180089340

Integrated circuit design using generation and instantiation of circuit stencils

Embodiments relate to designing of integrated circuits using generation and instantiation of circuit stencils. The circuit stencil represents an abstracted version of the circuit segment. ... Synopsys Inc

03/22/18 / #20180082004

Formal method for clock tree analysis and optimization

Configuring a hardware verification system includes receiving first data representing a first integrated circuit design configured to operate via a first clock signal derived from a second clock signal and a third signal generated by the second clock signal. The computer transforms the first data into second data representing a second design that includes functionality of the first design. ... Synopsys Inc

03/08/18 / #20180068428

Video overlay

A method includes automatically aligning a laser-based timing analysis image of a semiconductor device with an image of a layout of the device. The method further includes controlling a speed at which a multitude of images subsequently obtained by the laser-based timing analysis are compared to the layout of the device to create a video overlay. ... Synopsys Inc

03/08/18 / #20180068044

Partitioning using a correlation meta-heuristic

A method for partitioning for a hypergraph including a plurality of nodes into a plurality of bins includes assigning each node of the hypergraph to one of the plurality of bins to generate a candidate solution, and for each pair of nodes in the candidate solution, calculating a weighted covariance based on the bin assignment of each node of the pairs of nodes in the candidate solution. The assigning and the calculating are repeated to generate an accumulated weighted covariance for the pairs of nodes, from which a seed partition of the hypergraph is generated.. ... Synopsys Inc

03/08/18 / #20180068036

Reuse of extracted layout-dependent effects for circuit design using circuit stencils

A method for reuse of extracted layout-dependent effects for circuit design using circuit stencils includes receiving a schematic of an integrated circuit including a circuit segment. A circuit stencil corresponding to the circuit segment is instantiated in a schematic of a second integrated circuit. ... Synopsys Inc

03/01/18 / #20180060224

Distinguishing public and private code in testing environments

A code testing system identifies code for an application as being related to publically-available code, and modifies testing for the application for the code segments corresponding to the publically-available code. The code testing system identifies code segments in the application and generates a signature of the code segment. ... Synopsys Inc

03/01/18 / #20180059643

Electronic virtual layer

A method of performing virtual connectivity change between first and second nets associated with an integrated circuit is presented. The method includes generating a first top view and a first perspective views of a layout of the integrated circuit when a computer is invoked to perform the virtual connectivity change. ... Synopsys Inc

02/22/18 / #20180052690

Reorder buffer scoreboard

Various embodiments of a microprocessor include a scoreboard implementation that directs the microprocessor to the location of data values. For example, the scoreboard may include individual bits that instruct the microprocessor to retrieve the data from a re-order buffer, retire queue, result bus, or register file. ... Synopsys Inc

02/22/18 / #20180052684

Triple-pass execution

An execution pipeline architecture of a microprocessor employs a third-pass functional unit, for example, third-level of arithmetic logic unit (alu) or third short-latency execution unit to execute instructions with reduced complexity and area cost of out-of-order execution. The third-pass functional unit allows instructions with long latency execution to be moved into a retire queue. ... Synopsys Inc

02/15/18 / #20180048322

Phase locked loop circuit with charge pump up-down current mismatch adjustment and static phase error reduction

A magnitude difference between intrinsic positive and negative current components forming a pll's charge pump output current is determined by simultaneously outputting the intrinsic positive and negative pump current components, and incrementally increasing a bias current added to one of the intrinsic current components (e.g., such that the total positive current component is gradually increased). Calibration control voltages generated by the calibration pump output current are measured to determine when magnitudes of the adjusted (e.g., positive) current component and the non-adjusted/intrinsic (e.g., negative) current component are equal, and the bias current amount required to achieve equalization is stored as a digital converter code. ... Synopsys Inc

02/08/18 / #20180039721

Cell-aware defect characterization and waveform analysis using multiple strobe points

A computer-implemented method for characterizing a circuit is presented. The method includes receiving, by the computer, data representative of the circuit and at least one defect of the circuit. ... Synopsys Inc

02/01/18 / #20180033795

One-time programmable bitcell with native anti-fuse

An otp memory device includes a first and a second doped region of the same polarity in a semiconductor substrate. The second doped region has a higher doping concentration than the first doped region. ... Synopsys Inc

02/01/18 / #20180032659

Placing and routing debugging logic

Embodiments relate an emulation environment that places debugging logic in a manner that connections between the debugging logic and logic components outputs can be efficiently routed. In one embodiment, the host system places the debugging logic after placing the logic components of the dut, but before routing the logic components. ... Synopsys Inc

02/01/18 / #20180032448

Guarded memory access in a multi-thread safe system level modeling simulation

Methods, systems, and machine readable medium for multi-thread safe system level modeling simulation (slms) of a target system on a host system. An example of a slms is a systemc simulation. ... Synopsys Inc

01/11/18 / #20180011778

Static code testing of active code

A code deployment system deploys code to a set of application systems that execute the application, which may be across several tiers of systems that service requests related to the application. At each system, the application executes and is analyzed during execution to determine active code that is loaded by the application during execution, which may include dynamically-generated code. ... Synopsys Inc

01/04/18 / #20180005708

Enhancing memory yield and performance through utilizing nanowire self-heating

A method for improving an integrated circuit design which has transistors with nanowire channels comprises identifying a particular device having a particular transistor with a nanowire channel; and adding to the integrated circuit design circuitry which, when activated, repairs the particular transistor by self-heating. The method can comprise determining a memory cell that has a read current below a passing criteria, the memory cell having a transistor with a nanowire channel on a current path through which the read current flows; and applying a stress on the memory cell to repair the nanowire channel of the transistor in the memory cell on the current path. ... Synopsys Inc

01/04/18 / #20180005707

Logic timing and reliability repair for nanowire circuits

A method for improving an integrated circuit design having transistors with nanowire channels comprises identifying a particular device having a particular transistor with a nanowire channel; and adding to the integrated circuit design a controller which, when activated, repairs the particular transistor by self-heating. A critical path in logic circuitry in the design can be determined including a particular device having a transistor with a nanowire channel. ... Synopsys Inc

01/04/18 / #20180004877

Method and apparatus for collecting signal values in fpga based emulation machine

Systems and methods for collecting signal values in fpga based emulation machine. A single lut is used to observe three observable points within a vlsi. ... Synopsys Inc

01/04/18 / #20180004876

Reset domain crossing management using unified power format

Information from a circuit design's unified power format (upf) description is utilized to automate the management of reset domain crossings (rdcs). The upf description is utilized to identify signals that generate both rdc and power domain crossings (pdcs), thereby allowing a circuit designer to efficiently utilize a common (shared) isolation circuit that functions to manage both the rdc (i.e., during reset functions) and the pdc (i.e., during power management functions). ... Synopsys Inc

01/04/18 / #20180004862

Optimizing the ordering of the inputs to large commutative-associative trees of logic gates

A method of optimizing a netlist for a circuit comprising identifying a logic tree with a single output and a plurality of interchangeable inputs, and calculate the optimal permutation of the plurality of inputs. The method further comprising modify the netlist based on the optimal permutation, and optimizing the modified netlist.. ... Synopsys Inc

01/04/18 / #20180004640

Automated http user flows simulator

A testing method and system for automatic hypertext transfer protocol (http) testing, the system including a memory configured to store sequences of user requests, a program store storing code for emulating a sequence of user requests, and at least one processor coupled to the program store and to the memory for executing the stored code, the code including instructions for generating an emulated request based on a request from a user sequence of requests, transmitting the emulated request to an application, receiving a response to the emulated request from the application, calculating an adapted emulated sequence based on validity of the received response, and instructing transmission of the adapted emulated sequence.. . ... Synopsys Inc

12/28/17 / #20170373136

Integrated circuit devices having features with reduced edge curvature and methods for manufacturing the same

A structure such as an integrated circuit device is described having a line of material with critical dimensions which vary within a distribution substantially less than that of a mask element, such as a patterned resist element, used in manufacturing the line of material.. . ... Synopsys Inc

12/28/17 / #20170373134

2d material super capacitors

Devices and methods are described relating to capacitor energy storage devices that are small in size and have a high energy stored to volume ratio. The capacitor devices include 2d material electrodes. ... Synopsys Inc

12/21/17 / #20170364621

Partitioning and routing multi-slr fpga for emulation and prototyping

A computer-implemented method for configuring a hardware verification system includes receiving, in the computer, a first data representative of a first design. The method further includes performing a first mapping of the first data to generate a second data in accordance with a first cost function and one or more first delays each associated with a different one of a first multitude of paths. ... Synopsys Inc

12/14/17 / #20170358345

Robust negative bit-line and reliability aware write assist

A reliability aware negative bit-line write assist (ra-nbl) circuit comprises a coupling capacitor to provide a negative bump for write assist, and a control input generator control charging of the coupling capacitor, such that the negative bump is high at a low voltage, and the negative bump is low at a high voltage.. . ... Synopsys Inc

12/14/17 / #20170357746

Context aware clock tree synthesis

Systems and techniques are described for context aware clock tree synthesis (cts). A probability value can be computed for each clock sink in the set of clock sinks, wherein each probability value represents a probability that the corresponding clock sink has a critical clock latency. ... Synopsys Inc

12/14/17 / #20170357743

Efficient emulation of circuits

When a communication unit of an fpga receives emulated signals of a design under test that are to be transmitted to another fpga, the communication unit analyzes each signal to determine whether a signal event has occurred for the signal. The communication unit transmits to the other dut fpga a packet indicating for which signals a signal event has occurred. ... Synopsys Inc

12/07/17 / #20170351803

Determining the resistance of a conducting structure

Systems and techniques are described for determining a resistance of a conducting structure. The conducting structure can be partitioned into a set of polygons based on (1) equipotential lines and (2) boundaries of the conducting structure. ... Synopsys Inc

12/07/17 / #20170351610

Modulization of cache structure in microprocessor

Embodiments of the present disclosure support implementation of a level-1 (l1) cache in a microprocessor based on independently accessed data and tag arrays. Presented implementations of l1 cache do not require any stall pipeline mechanism for stalling execution of instructions, leading to improved microprocessor performance. ... Synopsys Inc

12/07/17 / #20170351520

Thread switching in microprocessor without full save and restore of register file

Certain embodiments of the present disclosure support a method and apparatus for efficient multithreading on a single core microprocessor. Thread switching in the single core microprocessor presented herein is based on a reserved space in a memory allocated to each thread for storing and restoring of registers in a register file. ... Synopsys Inc

12/07/17 / #20170351518

Communication between threads of multi-thread processor

Embodiments of the present disclosure support hardware based thread switching in a multithreading environment. The tread switching is implemented on a multithread microprocessor by utilizing thread mailbox registers and other auxiliary registers that can be pre-programmed for hardware based thread switching. ... Synopsys Inc

11/30/17 / #20170344689

Placement of circuit elements in regions with customized placement grids

Embodiments relate to using placement grids corresponding to repeating track patterns of metal layers in a region to place circuit elements. Each placement grid is defined by as a vertical pitch of a repeating track pattern of one metal layer and a horizontal pitch of another repeating track pattern of another metal layer. ... Synopsys Inc

11/30/17 / #20170344685

Schematic overlay for design and verification

Embodiments relate to schematic overlays describing modification to a base design for exploring modification or verification of the base design. Test circuitry may be modified or inserted without effecting the change in a base design schematics. ... Synopsys Inc

11/30/17 / #20170344681

Automatic generation of properties to assist hardware emulation

Analysis of a first verification test suite automatically generates properties that may be directly used in a subsequent verification test suite. For example, an ip module may be verified by executing a software simulation test suite. ... Synopsys Inc

11/23/17 / #20170339581

High-performance content reconstruction of merged and removed cells in integrated circuit layout verification process

Various methods, apparatus, systems, and non-transitory computer-readable storage medium are provided for facilitating content reconstruction of merged and removed cells in an integrated circuit layout verification process. An example method comprises identifying one or more particular cells comprising original cell content requested by cell-specific operations, determining a set of cells of interest, the set of cells of interest comprised of the one or more particular cells identified as comprising original cell content requested by cell-specific operations, preserving original cell information from the set of cells of interest, and subsequently, performing a cell optimization phase, wherein the subsequent cell optimization phase comprises producing a set of geometric locations from a merger of the set of cells of interest into a set of merged cells, each geometric location being a physical location in a circuit layout represented by a node id or coordinates and processing a final set of cells.. ... Synopsys Inc

11/23/17 / #20170338224

Heterojunction field effect transistor device with serially connected enhancement mode and depletion mode gate regions

Roughly described, a heterojunction field effect transistor device includes a first piezoelectric layer supporting a channel region, a second piezoelectric layer over the first, and a source and drain. A dielectric layer over the second piezoelectric layer electrically separates the source and drain, and has a plurality of segments, two of them separated by a first gap. ... Synopsys Inc

11/23/17 / #20170337315

Always-on tie cells for low power designs and method of manufacture thereof

Always-on (ao) tie cells, whose power supply has to remain on when the primary supply to the power domain is off, are used to implement logic constants. In accordance with embodiments of the present disclosure, insulated and non-insulated ao tie cells improve the qor of the layout design and lower the power consumption.. ... Synopsys Inc

11/23/17 / #20170337310

X-propagation in emulation using efficient memory

Embodiments relate to the emulation of circuits, and representation of unknown states of signals. A disclosed system (and method and computer program product) includes an emulation environment to convert a digital signal of a dut in a form capable of representing an unknown state. ... Synopsys Inc

11/23/17 / #20170336707

Categorized stitching guidance for triple-patterning technology

A method for making a multitude of masks for manufacturing an integrated circuit includes receiving the integrated circuit design printable using a multiple-patterning process. The design includes shapes and at least one layout conflict preventing decomposition of the design into the multitude of masks. ... Synopsys Inc

11/16/17 / #20170331850

Systems and methods for analyzing software using queries

Systems and methods for software verification. In some embodiments, a first statement is identified, from a discovery query written in a query language, the first statement comprising a side-effect construct with at least a first parameter and a second parameter, wherein: the first parameter of the side-effect construct comprises at least one second statement specifying one or more actions to be performed; and the second parameter of the side-effect construct comprises at least one condition specified based on a syntactic pattern. ... Synopsys Inc

11/16/17 / #20170330872

Method and apparatus for floating or applying voltage to a well of an integrated circuit

In one well bias arrangement, no well bias voltage is applied to the n-well, and no well bias voltage is applied to the p-well. Because no external well bias voltage is applied, the n-well and the p-well are floating, even during operation of the devices in the n-well and the p-well. ... Synopsys Inc

11/16/17 / #20170330613

Sram and periphery specialized device sensors

A system to enable detection of the process corner of each of the p and n devices of an sram array (of bitcells) and of peripheral devices. This permits more focused (optimized and compensated) design of non-sram peripheral circuits and of read and write assist circuits for better handling of process distribution impact on circuits improving functionality and yield.. ... Synopsys Inc

11/16/17 / #20170329974

Systems and methods for adaptive analysis of software

Systems and methods for software verification. In some embodiments, an application architecture model is generated for a software application, wherein: the application architecture model is generated based on source code of the software application; and the application architecture model comprises a plurality of component models. ... Synopsys Inc

11/16/17 / #20170329882

Parameter extraction of dft

Electronic design automation to simulate the behavior of structures and materials at multiple simulation scales with different simulators.. . ... Synopsys Inc

11/16/17 / #20170329723

Protection scheme for embedded code

A code protection scheme for controlling access to a memory region in an integrated circuit includes a processor with an instruction pipeline that includes multiple processing stages. A first processing stage receives one or more instructions. ... Synopsys Inc

11/16/17 / #20170329697

Detecting mistyped identifiers and suggesting corrections using other program identifiers

A code testing system determines mistyped identifiers in computer language code. For identifiers of objects in the code, such as variables and functions, the instances of the identifiers are identified in the code and recorded in an occurrence table. ... Synopsys Inc

11/16/17 / #20170329693

Systems and methods for incremental analysis of software

Systems and methods for software verification. In some embodiments, a first application architecture model is generated for a software application, wherein: the first application architecture model is generated based on a first version of source code of the software application; and the first application architecture model comprises a plurality of component models. ... Synopsys Inc

11/16/17 / #20170329692

System and methods for model-based analysis of software

Systems and methods for software verification. In some embodiments, an application architecture model is generated for a software application, wherein: the application architecture model is generated based on source code of the software application and a framework model representing a software framework using which the software application is developed; and the application architecture model comprises a plurality of component models. ... Synopsys Inc

11/16/17 / #20170329691

Systems and methods for using semantic queries to analyze software

Systems and methods for software verification. In some embodiments, a statement is identified from a discovery query written in a query language, comprising a semantic operator with at least a first parameter and a second parameter, wherein: the first parameter comprises a first syntactic pattern; the second parameter comprises a second syntactic pattern; and the semantic operator represents a semantic relationship between two program elements. ... Synopsys Inc

11/16/17 / #20170329582

Systems and methods for model-based analysis of software

Disclosed herein are methods, systems, and computer program products directed to a guidance engine. The guidance engine is configured to query a knowledge base for guidance with respect to a property of a software application. ... Synopsys Inc

10/26/17 / #20170308629

Sliding time window control mechanism for parallel execution of multiple processor core models in a virtual platform simulation

Embodiments of the present disclosure support a simulation of a plurality of processor core models. The processor core models are executed in parallel within a sliding time window of a defined size. ... Synopsys Inc

10/12/17 / #20170293708

Incrementally distributing logical wires onto physical sockets by reducing critical path delay

Configuring a hardware system includes providing a first data representative of a first assignment of a multitude of wires to a multitude of physical connections between a multitude of logic circuits of the hardware system, and transforming the first data into a second data representative of a second assignment of the multitude of wires to the multitude of physical connections. The transforming includes calculating a multitude of latencies each associated with a selected one of the multitude of wires, and assigning a first subset of the multitude of wires to at least one of the multitude of physical connections in accordance with a first improvement goal. ... Synopsys Inc

10/12/17 / #20170293702

Modeling a bus for a system design incorporating one or more programmable processors

Systems and methods for modeling a bus for a system design are provided. In an embodiment, the method operates by accepting a virtual bus model, wherein the model simulates behavior for a bus master and slave device, such that the model accurately simulates the timing and behavior of the transfer of data from master to slave, and, from slave to master devices. ... Synopsys Inc

10/05/17 / #20170287977

Power harvesting for integrated circuits

Integrated circuit devices which include a thermoelectric generator which recycles heat generated by operation of an integrated circuit, into electrical energy that is then used to help support the power requirements of that integrated circuit. Roughly described, the device includes an integrated circuit die having an integrated circuit thereon, the integrated circuit having power supply terminals for connection to a primary power source, and a thermoelectric generator structure disposed in sufficient thermal communication with the integrated circuit die so as to derive, from heat generated by the die, a voltage difference across first and second terminals of the thermoelectric generator structure. ... Synopsys Inc

10/05/17 / #20170286584

Custom layout of integrated circuit (ic) designs

Systems and techniques for facilitating layout of an integrated circuit (ic) design are described. A distinct color pattern can be assigned to a set of shapes in a layout of the ic design that correspond to a net. ... Synopsys Inc

10/05/17 / #20170286581

Scheme and design markup language for interoperability of electronic design application tool and browser

A bi-directional eda-browser bridge mechanism enables an eda system and its related (external) tools to interact with a browser. The eda-browser bridge uses a design markup language (dml) to communicate with the browser, using a document-based approach rather than a more traditional programming/api-based approach to extending (e.g., integrating tools) the eda system. ... Synopsys Inc

10/05/17 / #20170286576

Parasitic-aware blockage

A parasitic-aware blockage structure is provided to replace a detailed blockage structure for use in connection with a capacitance extraction operation. The parasitic-aware blockage structure includes one or more parasitic-aware blockage polygons, each representing a plurality of polygons of the detailed blockage structure. ... Synopsys Inc

09/28/17 / #20170277890

Method for testing computer program product

This document discloses a solution for detecting, by a computer apparatus, computer program library in a binary computer program code. A method according to an embodiment of the solution comprises in the computer apparatus: acquiring a reference computer program library file in a binary form; and determining at least one signature set of binary data from a read-only section of the reference computer program library, wherein the at least one signature set of binary data is determined to contain constant binary data that is unique to the reference computer program library; the method further comprising a testing phase comprising: acquiring binary computer program code and at least one signature set of binary data associated with each reference computer program library to be searched for; searching the binary computer program code for said at least one signature set of binary data; and upon determining that a signature set of binary data has been detected in the binary computer program code, determining that the binary computer program code comprises the computer program library associated with the detected signature set of binary data.. ... Synopsys Inc

09/21/17 / #20170270302

Security remediation

A method is provided to remediate defects in first computer program code that can be used to configure a computer to produce code for use by the same or a different computer configured using second computer program code to use the produced code to produce output information, the method comprising: configuring a computer to perform static analysis of the first program to produce an information structure in a non-transitory computer readable storage device that associates a respective code statement of the first program code with a respective context, wherein the context associates a parser state with a potential defect in the produced code; identify a defect in the first computer program code that is associated with the respective code statement; and determining a remediation for the identified defect.. . ... Synopsys Inc

09/14/17 / #20170262569

Analyzing delay variations and transition time variations for electronic circuits

A system receives a circuit description and measures of intrinsic delay, intrinsic delay variation, transition time and transition time variation for each stage and determines stage delay variation of each stage. The system receives a circuit description and derate factors and determines an intrinsic delay standard deviation and a correlation coefficient. ... Synopsys Inc

09/07/17 / #20170255728

Capturing time-slice of emulation data for offline embedded software debug

Disclosed is a method (or a system or a non-transitory computer readable medium) for recreating states of an embedded processing unit of a design under test (dut). In one aspect, a host system configures an emulator to implement the dut. ... Synopsys Inc

09/07/17 / #20170255727

Circuit verification on a distributed database processing system

Example embodiments of disclosed configurations include a process (and system and non-transitory computer storage readable medium) for verifying an operation or a functionality of a design under test (dut) through a distributed database processing system. In one or more embodiments, the emulator performs emulation of a dut, and traces signals of the dut based on the emulation. ... Synopsys Inc

09/07/17 / #20170255726

Signal reconstruction in sequential logic circuitry

A method for reconstructing at least one output signal associated to a sequential logic circuitry block of a circuit is disclosed. At least one input signal is associated to the sequential logic circuitry block. ... Synopsys Inc

09/07/17 / #20170255543

Detecting errors for function calls with an implicit receiver object

A code testing system identifies possible code errors that may generate unexpected application behaviors. The code testing system identifies function calls in the system by identifying function call sites that do not specify a receiver object but may invoke a function that uses a receiver object. ... Synopsys Inc

08/31/17 / #20170249529

Image processing method

A computer-implemented image processing technique for selectively recovering the features of an original cad model after the original cad model has been converted to a digitized image and a new cad model generated from the digitized image. The original boundary representation provides a template to transform the representation through processing under governance of a programmed processor so as to recover accuracy and reintroduce feature edges and feature corners as well as other detailed features to the cad model obtained from the digitized image, e.g., to enable detailed features to be retained that would otherwise have been lost due to the lossy conversion into image space. ... Synopsys Inc

08/31/17 / #20170249416

Integrated circuit design using generation and instantiation of circuit stencils

Embodiments relate to designing of integrated circuits using generation and instantiation of circuit stencils. The circuit stencil represents an abstracted version of the circuit segment. ... Synopsys Inc

08/31/17 / #20170249414

Creating and reusing customizable structured interconnects

A customizable routing system allows designers to create custom connection layouts that can be stored, turned into templates, reused, and further customized. The system describes designer-input custom connection layouts in terms of “structural directives” that specify its patterns and properties instead of using precise dimensions. ... Synopsys Inc

08/31/17 / #20170249413

Interactive routing of connections in circuit using auto welding and auto cloning

Embodiments relate to an interactive routing of connections in a circuit where connections associated with an initial pin of a circuit element (e.g., a row of finfets) are replicated in association with at least one other pin of the same circuit element or a different circuit element in the circuit. The replication of connections may be performed intelligently by taking into account the mapping of pins as well as design rules or other restrictions imposed on the circuit. ... Synopsys Inc

08/31/17 / #20170249411

Testbench chaining for multiple blocks in hierarchical circuit design

A selection of a source testbench is received from a user. The source testbench includes a description of one or more source parameters, a description of one or more source measurements, and a plurality of source entries, each of the source entries including a value for each of the one or more source parameters and each of the one or more source measurements. ... Synopsys Inc

08/31/17 / #20170249400

Reuse of extracted layout-dependent effects for circuit design using circuit stencils

A method for reuse of extracted layout-dependent effects for circuit design using circuit stencils includes receiving a schematic of an integrated circuit including a circuit segment. A circuit stencil corresponding to the circuit segment is instantiated in a schematic of a second integrated circuit. ... Synopsys Inc

08/17/17 / #20170236870

Integrated circuit system with memory support and method of manufacture thereof

A method of manufacturing an integrated circuit system, includes, in part, providing a planar surface on an insulator, forming first and second bottom electrodes over the insulator substrate, forming a first electrolyte over the first and second bottom electrodes, forming a first top electrode over the first electrolyte, forming and depositing a second bottom electrode over the insulator substrate, patterning and removing the first top electrode and the first electrolyte from regions above the second bottom electrode, forming a second electrolyte above the second bottom electrode and the first tope electrode, forming a second top electrode above the second electrolyte, and patterning and removing the second top electrode and the second electrolyte from regions above the first bottom electrode.. . ... Synopsys Inc

08/17/17 / #20170236053

Configurable and programmable multi-core architecture with a specialized instruction set for embedded application based on neural networks

A programmable architecture specialized for convolutional neural networks (cnns) processing such that different applications of cnns may be supported by the presently disclosed method and apparatus by reprogramming the processing elements therein. The architecture may include an optimized architecture that provides a low-area or footprint and low-power solution desired for embedded applications while still providing the computational capabilities required for cnn applications that may computationally intensive, requiring a huge number of convolution operations per seconds to process inputs such as video streams in real time.. ... Synopsys Inc

08/17/17 / #20170235868

Static timing analysis with improved accuracy and efficiency

A method for performing static timing analysis of an integrated circuit design, wherein at least two timing paths share a shared node comprises propagating along the at least two timing paths a plurality of timing signals characterized by a set of timing parameters and determining respective values of the timing parameters at the shared node. Subsets of timing signals are defined based on relations between the determined parameter values of different timing signals. ... Synopsys Inc

08/10/17 / #20170228492

Layer class relative density for technology modeling in ic technology

A method and apparatus of a novel modeling scheme for performing optical lithography simulation for a multi-color layer fabrication process is described. The method interpolates for simulation use between test or experimental data or descriptions to more accurately apply color differentiated parameters to the model creation and lithography simulation.. ... Synopsys Inc

08/03/17 / #20170220724

Entry finder for single layer differential group routing

A method, apparatus and computer program products are provided for determining an entry finder from a plurality of merge points of a bounding box for optimal performance of differential group pattern match routing. One example method includes identifying each of a plurality of merge point candidates, performing a routability determination process, the results of the routability determination process comprising a remaining subset of the plurality of merge point candidates, routing each remaining merge point from the remaining subset of the plurality of merge point candidates, calculating a routing cost for each remaining merge point from the remaining subset of the plurality of merge point candidates, and determining a merge point having a lowest calculated cost.. ... Synopsys Inc

08/03/17 / #20170220723

3d resist profile aware resolution enhancement techniques

Systems and techniques for three-dimension (3d) resist profile aware resolution enhancement techniques are described. 3d resist profile aware resolution enhancement models can be calibrated based on empirical data. ... Synopsys Inc

07/20/17 / #20170206301

Pessimism reduction in static timing analysis

A method for performing graph-based static timing analysis comprises reading in a design of an integrated circuit having a subset of timing paths, each timing path of the subset having a common point, wherein the common point is identical for all timing paths of the subset. The method comprises initiating a timing signal at the common point, the timing signal propagating along a plurality of timing arcs of the subset. ... Synopsys Inc

07/20/17 / #20170206300

Incremental multi-patterning validation

A computer-implemented method for validating a design characterized by a multi-patterning layer is presented. The method includes receiving the multi-patterning layer in a memory of the computer when the computer is invoked to validate the design. ... Synopsys Inc

07/06/17 / #20170193146

Isolated debugging in an fpga based emulation environment

For a design under test (dut) that is to be emulated, a host system partitions the dut into multiple partitions and maps each partition to an fpga of an emulator which will emulate the partition. The host system stores information describing to which fpgas each component of the dut has been mapped. ... Synopsys Inc

07/06/17 / #20170192878

Separating test coverage in software processes using shared memory

A remote test separation (rts) system comprising an original software product instrumented for testing and a shared memory accessible to the original software product, the shared memory including a plurality of coverage counters. The rts system further comprising an agent, capable of accessing the shared memory, the agent to read the plurality of coverage counters, the agent to read the plurality of coverage counters at an end of a test, and write coverage data to another memory. ... Synopsys Inc

06/29/17 / #20170186860

Tined gate to control threshold voltage in a device formed of materials having piezoelectric properties

Roughly described, a field effect transistor has a first piezoelectric layer supporting a channel, a second piezoelectric layer over the first piezoelectric layer, a dielectric layer having a plurality of dielectric segments separated by a plurality of gaps, the dielectric layer over the second piezoelectric layer, and a gate having a main body and a plurality of tines. The main body of the gate covers at least one dielectric segment of the plurality of dielectric segments and at least two gaps of the plurality of gaps. ... Synopsys Inc

06/29/17 / #20170185700

Selective execution for partitioned parallel simulations

Computer implemented techniques for the partitioned simulation of parallel architectures are disclosed. A high-level design for simulation is obtained. ... Synopsys Inc

06/01/17 / #20170154132

Power-aware dynamic encoding

Dynamic power-aware encoding method and apparatus is presented based on a various embodiments described herein. The experimental results confirmed that a desirable reduction in the toggling rate in the decompressed test stimulus is achievable by reasonable overhead (atpg time, hardware overhead and pattern inflation) typically without degradation of a compression ratio. ... Synopsys Inc

05/11/17 / #20170134033

Interleaved analog-to-digital converter and method for calibrating an interleaved analog-to-digital converter

An interleaved analog-to-digital converter, adc, comprises a first and a second sub-adc (adc1, adc2) and a timing control unit (tc). The first sub-adc (adc1) is configured to convert a first calibration signal (v1cal) into a first calibration code (cc1) depending on a first sub-clock signal (Φ1). ... Synopsys Inc

05/11/17 / #20170132345

Dynamically loaded system-level simulation

A system-level simulation includes generating netlist information including component library information, which describes instances of the hardware components, and component instance information, which describes component dynamic libraries that include models of hardware components. The simulation is generated at simulation run-time based on the netlist information. ... Synopsys Inc

05/11/17 / #20170132160

Memory tamper detection

A method and system for detecting tampering of authenticated memory blocks that are accessible by an untrusted host processor, by (1) periodically re-authenticating the memory blocks from a trusted computing environment, and (2) disabling accessing of the memory blocks by the untrusted host processor when the re-authenticating fails. In one implementation, each of the memory blocks has an authentication code, and the accessing of the memory blocks is disabled by disabling the untrusted host processor. ... Synopsys Inc

05/11/17 / #20170131354

Scheme for masking output of scan chains in test circuit

A method for masking scan chains in a test circuit of an integrated circuit is disclosed. A test pattern to be fed into the test circuit of the integrated circuit is generated. ... Synopsys Inc

05/04/17 / #20170124305

Deterministic identifiers for source code elements

Multiple computer systems each include at least one eda tool that performs certain eda functions. Each computer system also includes source code of a design with the names of source code elements and an encoding module that generates unique identifiers for the source code elements according to a specific encoding algorithm. ... Synopsys Inc

05/04/17 / #20170124293

Atomic structure optimization

Electronic design automation modules simulate the behavior of structures and materials at atomic scale with parameters or a configuration that varies across iterative transformations.. . ... Synopsys Inc

05/04/17 / #20170124245

Knowledge-based analog layout generator

A computer-implemented method for generating a layout of a design includes invoking the computer to receive a schematic representation of the design, generating a connection graph associated with the design, comparing the connection graph with a plurality of connection graphs stored in a database and selecting a layout associated with the matching connection graph in generating the layout of the design.. . ... Synopsys Inc

05/04/17 / #20170124244

Buffer chain management for alleviating routing congestion

Systems and techniques for alleviating congestion are described. A set of buffer chains that pass through a congested region of the circuit design can be identified. ... Synopsys Inc

05/04/17 / #20170124242

Constructing fill shapes for double-patterning technology

A computer-implemented method for constructing a design characterized by a double patterning layer is presented. The method includes receiving the design in a memory of the computer when the computer is invoked to construct the design. ... Synopsys Inc

04/27/17 / #20170116364

Automatically generated schematics and visualization

An automated visualization tool in a command line environment allows complex log data to be represented by symbols and associated information for clarity of communication and better understanding of the associated design.. . ... Synopsys Inc

04/27/17 / #20170115959

Automatic control system and method for a true random number generator

A system for reseeding a pseudo random number generator to generate pseudo random numbers includes a true random number generator generating a true random number, a storage device storing the generated true random number, a pseudo random number generator generating pseudo random numbers using the stored true random number as a seed, and a controller coupled to the true random number generator and the pseudo random number generator to (1) generate a new true random number concurrently with the operation of the pseudo random number generator, and storing the new true random number, and (2) reseed the pseudo random number generator with the new true random number.. . ... Synopsys Inc

04/20/17 / #20170109470

Logic yield learning vehicle with phased design windows

Techniques for providing improved semiconductor yield learning are discussed herein. Some embodiments may include a yield learning vehicle (ylv), including a communication fabric and a plurality of circuit blocks connected with the communication fabric. ... Synopsys Inc

04/20/17 / #20170109468

Determining slack estimates for multiple instances of a cell in a hierarchical circuit design

Embodiments perform static timing analysis using a digital representation of a circuit. The digital representation of the circuit includes multiple instances of a cell in a hierarchical cell block circuit. ... Synopsys Inc

04/20/17 / #20170109466

Overlaying of clock and data propagation in emulation

A computer-implemented method for configuring a hardware verification system is presented. The method includes receiving, in the computer, a first data representative of a first design including a first sequential element configured to be evaluated in accordance with a first signal, when the computer is invoked to configure the verification system. ... Synopsys Inc

04/13/17 / #20170103152

Signal reconstruction in sequential logic circuitry

A method for reconstructing at least one output signal associated to a sequential logic circuitry block of a circuit is disclosed. At least one input signal is associated to the sequential logic circuitry block. ... Synopsys Inc

03/30/17 / #20170091367

Alternative hierarchical views of a circuit design

Methods and apparatuses are described for creating, editing, and viewing a floorplan of a circuit design. Specifically, some embodiments enable a user to perform a graphical operation at an inference point in a circuit design layout, wherein the location of the inference point is determined based on existing graphical objects in the circuit design layout. ... Synopsys Inc

03/30/17 / #20170091360

Waveform based reconstruction for emulation

A disclosed system of an emulation environment performs a simulation to construct a waveform of a target signal based on signals traced by an emulator for a time frame including multiple clock cycles. In one embodiment, a simulation is performed in a manner that an input of the logic gate, in a first duration of the time frame at which an output of the logic gate depends on the input, is analyzed to obtain the output, and the input of the logic gate, in a second duration of the time frame at which the output of the logic gate is independent, is omitted. ... Synopsys Inc

03/23/17 / #20170083655

Placing and routing debugging logic

Embodiments relate an emulation environment that places debugging logic in a manner that connections between the debugging logic and logic components outputs can be efficiently routed. In one embodiment, the host system places the debugging logic after placing the logic components of the dut, but before routing the logic components. ... Synopsys Inc

03/23/17 / #20170083652

Saving and restoring an emulation environment

An emulator configured to emulate a dut is connected to a client device. The client device includes a virtual machine that executes emulation processes against the emulated dut. ... Synopsys Inc

03/23/17 / #20170083651

Equivalence checking of analog models

Techniques for equivalence checking of analog models are disclosed. The models include transistor level representations. ... Synopsys Inc

03/23/17 / #20170083644

Method to approximate chemical potential in a ternary or quaternary semiconductor

Roughly described, a method is provided to approximate chemical potentials of elements in ternary and quaternary compound semiconductors, for example iii-v semiconductors. In embodiments of the present invention, three, four, or more relationships are solved together to find approximated chemical potentials for each group iii element and each group v element. ... Synopsys Inc

03/02/17 / #20170064331

Adaptive content dependent intra prediction mode coding

A system and a method are disclosed for encoding and decoding a video frame using spatial prediction. The video frame is separated into a plurality of image blocks, and a plurality of spatial predictors is created for an image block using methods well-known in the art. ... Synopsys Inc

03/02/17 / #20170061064

In-design real-time electrical impact verification flow

Techniques for analyzing a routed interconnection of a net of a circuit are discussed herein. Some embodiments may include a method comprising with a computer, analyzing the circuit to determine a performance parameter of the net, wherein the circuit is analyzed based at least in part on applying pre-layout simulation data of the net to layout data of the circuit. ... Synopsys Inc

03/02/17 / #20170059651

Identifying failure indicating scan test cells of a circuit-under-test

A disclosed configuration is for identifying at least one failure indicating scan test cell of a circuit-under-test, cut, the cut having a plurality of scan test cells, is provided. The configuration comprises generating a plurality of error signatures by means of a compactor of the cut, wherein each of the error signatures of the plurality of error signatures consist of a respective sequence of bits comprising at least one failure indicating bit, assigning each error signature to at least a first, a second and a third signature type according to a total number of failure indicating bits of the respective error signature and mapping at least a predefined minimum number of error signatures to respective scan test cells of the plurality of scan test cells. ... Synopsys Inc

02/23/17 / #20170053695

Using sense amplifier as a write booster in memory operating with a large dual rail voltage supply differential

A memory includes a memory cell that operates in response to an array supply voltage, and a corresponding pair of bit lines that are pre-charged to a periphery supply voltage prior to each access of the memory cell. A sense amplifier coupled to the bit lines operates in response to the periphery supply voltage. ... Synopsys Inc

02/23/17 / #20170053051

Accurate glitch detection

Systems and techniques for detecting design problems in a circuit design are described. A higher-level abstraction of the circuit design can be synthesized to obtain a lower-level abstraction of the circuit design, and a mapping between signals in the higher-level abstraction and the signals in the lower-level abstraction. ... Synopsys Inc

02/23/17 / #20170052861

Identifying failure mechanisms based on a population of scan diagnostic reports

Systems and techniques for identifying failure mechanisms based on a population of scan diagnostic reports is described. Given a population of scan diagnostic reports, a mixed membership model can be used for computing a topic distribution for each portion of each scan diagnostic report and a feature distribution for each topic. ... Synopsys Inc

02/16/17 / #20170047940

Reference voltage generator for an analog-digital converter and method for analog-digital conversion

Analog-digital converter configured for conversion of an input voltage, represented by a pair of input potentials, into a binary code using successive approximation. The analog-digital converter comprises a reference voltage generator (rvg) supplying a first pair of reference potentials and a second pair of reference potentials. ... Synopsys Inc

02/16/17 / #20170046282

Protection scheme for embedded code

A code protection scheme for controlling access to a memory region in an integrated circuit includes a processor with an instruction pipeline that includes multiple processing stages. A first processing stage receives one or more instructions. ... Synopsys Inc

02/16/17 / #20170045557

Evaluation of voltage domains in the presence of leakage and/or dynamic switching

An automated circuitry that can co-exist in any chip and that allows for a accurate characterization of i*r drops at a block and/or whole chip level is described.. . ... Synopsys Inc

02/09/17 / #20170040411

2d material super capacitors

Devices and methods are described relating to capacitor energy storage devices that are small in size and have a high energy stored to volume ratio. The capacitor devices include 2d material electrodes. ... Synopsys Inc

02/09/17 / #20170039308

Pre-silicon design rule evaluation

Roughly described, a method for developing a set of design rules for a fabrication process in development includes, for each of several candidate druts for the fabrication process, laying our a logic cell based on the drut, the logic cell having at least one transistor and at least one interconnect, simulating fabrication of the logic cell according to the fabrication process and the layout, simulating behavior of the logic cell structure, including characterizing the combined behavior of both the first transistor and the first interconnect, evaluating performance of the logic cell structure in dependence upon the behavior as characterized, and recording in a database, in association with an indication of the drut, values indicating performance of the logic cell. The database can be used to select the best drut for the fabrication process.. ... Synopsys Inc

02/02/17 / #20170033687

Low power voltage regulator

A circuit provides a regulated voltage supply for other circuits. The circuit includes a bias current source and a reference voltage source. ... Synopsys Inc

02/02/17 / #20170032117

Identifying software components in a software codebase

Systems, methods, and computer program embodiments are disclosed for detecting software components in a software codebase. In an embodiment, a source file containing source code may be received, and a code signature may be generated for the source file based on a determined structure of the source code. ... Synopsys Inc

02/02/17 / #20170032076

Sub-resolution assist feature implementation for shot generation

A design layout for a semiconductor chip includes information on shapes desired to be fabricated. Clusters of photolithographic exposure “shots” are generated and subject to a measure of shot density to approximate a mask shape that generates the desired fabricated shapes when exposed during wafer fabrication. ... Synopsys Inc

01/26/17 / #20170025496

Methods for manufacturing integrated circuit devices having features with reduced edge curvature

A structure, such as an integrated circuit device, is described that includes a line of material with critical dimensions which vary within a distribution substantially less than that of a mask element, such as a patterned resist element, used in etching the line. Techniques are described for processing a line of crystalline phase material which has already been etched using the mask element, in a manner which straightens an etched sidewall surface of the line. ... Synopsys Inc

01/26/17 / #20170025185

Method to program bitcells of a rom array

A method to program bitcells of a rom array uses different programming cells for programming the bitcells with a first or second data item. A first bitcell is programmed by means of a selected programming cell, wherein the programming cell is selected in dependence on operating the memory array as a flipped or a non-flipped memory in multi-bank instance. ... Synopsys Inc

01/26/17 / #20170024508

System and method for managing and composing verification engines

A system and method for managing and composing verification engines and simultaneously applying such compositions to verify properties with design constraints allocates computing resources to verification engines based upon properties to be checked and optionally a user-specified budget. The verification engines are run in order to verify a received register transfer level (rtl) design description of a circuit according to user-specified assertions and constraints received by the system. ... Synopsys Inc

01/26/17 / #20170024503

Semi-local ballistic mobility model

A transistor model defines the carrier mobility as a combination of both drift-diffusion mobility and ballistic mobility. The ballistic mobility is calculated based on the assumption that the kinetic energy of carriers near an injection point is no greater than the potential energy difference of carriers near that injection point. ... Synopsys Inc

01/26/17 / #20170024003

Internet of things (iot) power and performance management technique and circuit methodology

Energy consumption is reduced within an internet of things (iot) device, without degrading operating performance of the corresponding internal circuitry. A first internal supply voltage (vdda) used to supply the internal circuitry is reduced from a vdd supply voltage to a lower voltage during an idle state, thereby reducing leakage currents in the internal circuitry. ... Synopsys Inc

01/19/17 / #20170017746

Power-and-ground (pg) network characterization and distributed pg network creation for hierarchical circuit designs

A chip layout can include a top-level portion and a set of blocks. The power-and-ground (pg) network for the chip layout can be specified by a set of chip-level pg constraints that is defined using a pg constraint definition language. ... Synopsys Inc

01/19/17 / #20170017506

Software and hardware emulation system

A method to emulate a system represented by one or more of hardware portions and software portions is described. The method comprises determining whether a subset of the one or more hardware portions and software portions have been tested, and identifying whether the system has performed to a specification based on the testing. ... Synopsys Inc

01/12/17 / #20170011140

Method and apparatus for word-level netlist preprocessing and analysis using same

A computer implemented representation of a circuit design is reduced by representing the circuit design as a data structure defining a netlist. A first set of nodes is identified in the netlist that includes datapath nodes, preferably nodes that do not intermingle data and control. ... Synopsys Inc

01/12/17 / #20170011138

System and method for hierarchical power verification

A hierarchical power verification system and method creates abstract models of power behavior of modules that it successfully verifies. The abstract models simplify the module definition by omitting internal module details but provide sufficient information for power verification of higher level modules that incorporate this abstracted module. ... Synopsys Inc

01/05/17 / #20170004251

Detecting and displaying multi-patterning fix guidance

A computer implemented method for validating a design is presented. The method includes generating, using the computer, a graph non-decomposable to a colored graph representative of the design, when the computer is invoked to validate the design. ... Synopsys Inc

01/05/17 / #20170004249

Validating a clock tree delay

A computer implemented method for validating a clock tree includes estimating a first number of a multitude of first buffers disposed in the clock tree path, and selecting a first scaling coefficient in accordance with the first number. The computer implemented method further includes scaling a first delay associated with the multitude of first buffers in accordance with the selected first scaling coefficient, and generating a second multitude of second buffers disposed in the clock tree path defined by a second number greater than the first number.. ... Synopsys Inc

01/05/17 / #20170004244

Look-ahead timing prediction for multi-instance module (mim) engineering change order (eco)

Some embodiments determine a merged timing graph for a multi-instance module (mim), wherein each node in the merged timing graph corresponds to a pin in the mim, and wherein each node in the merged timing graph stores timing information associated with the corresponding pins in multiple instances of the mim in a circuit design. The embodiments can then determine an eco for the mim based on the merged timing graph.. ... Synopsys Inc








ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009



###

This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. Freshpatents.com is not affiliated or associated with Synopsys Inc in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Synopsys Inc with additional patents listed. Browse our Agent directory for other possible listings. Page by FreshPatents.com

###