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Syntest Technologies Inc patents

Recent patent applications related to Syntest Technologies Inc. Syntest Technologies Inc is listed as an Agent/Assignee. Note: Syntest Technologies Inc may have other listings under different names/spellings. We're not affiliated with Syntest Technologies Inc, we're just tracking patents.

ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "S" | Syntest Technologies Inc-related inventors




Date Syntest Technologies Inc patents (updated weekly) - BOOKMARK this page
05/12/16Multiple-capture dft detecting or locating crossing clock-domain faults during self-test or scan-test
11/26/15Method and broadcasting scan patterns in a scan-based integrated circuit
11/26/15Multiple-capture dft system for detecting or locating crossing clock-domain faults during scan-test
11/05/15Multiple-capture dft system for detecting or locating crossing clock-domain faults during scan-test
11/20/14Method and broadcasting scan patterns in a scan-based integrated circuit
08/07/14Multiple-capture dft system for detecting or locating crossing clock-domain faults during scan-test
05/29/14Method and broadcasting scan patterns in a scan-based integrated circuit
05/22/14Method and low-pin-count scan compression
03/20/14Multiple-capture dft system for detecting or locating crossing clock-domain faults during self-test or scan-test
03/13/14Multiple-capture dft system for detecting or locating crossing clock-domain faults during self-test or scan-test
03/13/14Computer-aided design (cad) multiple-capture dft system for detecting or locating crossing clock-domain faults
02/07/13Method and hybrid ring generator design
12/27/12Method and broadcasting scan patterns in a scan-based integrated circuit
10/18/12Method and low-pin-count scan compression
09/27/12Computer-aided design system to automate scan synthesis at register-transfer level
06/28/12Multiple-capture dft system to reduce peak capture power during self-test or scan test
05/03/12Method and testing 3d integrated circuits
08/11/11Computer-aided design system to automate scan synthesis at register-transfer level
11/11/10Multiple-capture dft system to reduce peak capture power during self-test or scan test
09/17/09Method and broadcasting scan patterns in a scan-based integrated circuit
05/21/09Multiple-capture dft system for detecting or locating crossing clock-domain faults during self-test or scan-test
03/12/09Multiple-capture dft system for scan-based integrated circuits
02/05/09Method and unifying self-test with scan-test during prototype debug and production test







ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009



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