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Taiwan Semiconductor Manufacturing Co Ltd
Taiwan Semiconductor Manufacturing Co Ltd_20100114
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Taiwan Semiconductor Manufacturing Co Ltd_20100128
Taiwan Semiconductor Manufacturing Co Ltd_20131212

Taiwan Semiconductor Manufacturing Co Ltd patents


Recent patent applications related to Taiwan Semiconductor Manufacturing Co Ltd. Taiwan Semiconductor Manufacturing Co Ltd is listed as an Agent/Assignee. Note: Taiwan Semiconductor Manufacturing Co Ltd may have other listings under different names/spellings. We're not affiliated with Taiwan Semiconductor Manufacturing Co Ltd, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "T" | Taiwan Semiconductor Manufacturing Co Ltd-related inventors


Silicon-containing photoresist for lithography

A photoresist includes a polymer backbone, an acid labile group (ALG) chemically bonded to the polymer backbone, a photo-acid generator (PAG), a solvent, and a silicon-containing unit that is chemically bonded to the ALG. A method of using the photoresist composition includes forming a layer of the photoresist over a... Taiwan Semiconductor Manufacturing Co Ltd

Systems and methods for a narrow band high transmittance interference filter

The present disclosure provides an interference filter, a lithography system incorporating an interference filter, and a method of fabricating an interference filter. The interference filter includes a transparent substrate having a front surface and a back surface, a plurality of alternating material layers formed over the front surface of the... Taiwan Semiconductor Manufacturing Co Ltd

Sram-based authentication circuit

A memory device includes a memory cell array comprising a plurality of memory cells wherein each of the plurality of memory cells is configured to be in a data state, and a physically unclonable function (PUF) generator. The PUF generator further includes a first sense amplifier, coupled to the plurality... Taiwan Semiconductor Manufacturing Co Ltd

Memory device sensing circuit

A memory device includes a first memory array comprising a first bit cell configured to store a first logical state; and a reference signal provision (RSP) unit, coupled to the first memory array, and configured to provide a first reference signal that represents an average of a discharging rate and... Taiwan Semiconductor Manufacturing Co Ltd

Rram array with current limiting element

In some embodiments, the present disclosure relates to a resistive random access memory (RRAM) circuit. The RRAM circuit has a plurality of RRAM cells. A bit-line decoder is configured to concurrently apply a forming signal to the plurality of RRAM cells. A current limiting element is configured to concurrently limit... Taiwan Semiconductor Manufacturing Co Ltd

Memory circuit with assist circuit trimming

A method includes: examining, by a test engine, whether a first bit of a memory array is functional; in response to the first bit being not functional, storing, by the test engine, address information of the first bit into a memory device; and retrieving, by an assist circuit trimming (ACT)... Taiwan Semiconductor Manufacturing Co Ltd

Semiconductor device and manufacturing method thereof

A semiconductor device includes a fin structure disposed over a substrate, a gate structure and a source. The fin structure includes an upper layer being exposed from an isolation insulating layer. The gate structure disposed over part of the upper layer of the fin structure. The source includes the upper... Taiwan Semiconductor Manufacturing Co Ltd

Mechanisms for forming finfets with different fin heights

A semiconductor device is provided. The semiconductor device includes a doped isolation structure formed above a substrate, and the doped isolation structure includes a first doped portion and a second doped portion, and a doped concentration of the second doped portion is different from a doped concentration of the first... Taiwan Semiconductor Manufacturing Co Ltd

Semiconductor device and manufacturing method thereof

A semiconductor device includes an isolation layer disposed over a substrate, first and second fin structures, a gate structure, a source/drain structure and a dielectric layer disposed on an upper surface of the isolation insulating layer. Both the first fin structure and the second fin structure are disposed over the... Taiwan Semiconductor Manufacturing Co Ltd

Reducing metal gate overhang by forming a top-wide bottom-narrow dummy gate electrode

A polysilicon layer is formed over a substrate. The polysilicon layer is etched to form a dummy gate electrode having a top portion with a first lateral dimension and a bottom portion with a second lateral dimension. The first lateral dimension is greater than, or equal to, the second lateral... Taiwan Semiconductor Manufacturing Co Ltd

Semiconductor fin fet device with epitaxial source/drain

A semiconductor device includes a substrate, a fin structure disposed over the substrate and including a channel region and a source/drain region, a gate structure disposed over at least a portion of the fin structure, the channel region being beneath the gate structure and the source/drain region being outside of... Taiwan Semiconductor Manufacturing Co Ltd

Sram-based authentication circuit

A memory device includes a memory block that includes a plurality of memory bits, wherein each bit is configured to present a first logical state; and an authentication circuit, coupled to the plurality of memory bits, wherein the authentication circuit is configured to access a first bit under either a... Taiwan Semiconductor Manufacturing Co Ltd

Method for improving circuit layout for manufacturability

A method of manufacturing an integrated circuit (IC) includes receiving a layout of the IC having a first region interposed between two second regions. The layout includes a first layer having first features and second and third layer having second and third features in the first region. The second and... Taiwan Semiconductor Manufacturing Co Ltd

Source beam optimization improving lithography printability

Source beam optimization (SBO) methods are disclosed herein for enhancing lithography printability. An exemplary method includes receiving an integrated circuit (IC) design layout and performing an SBO process using the IC design layout to generate a mask shot map and an illumination source map. The SBO process uses an SBO... Taiwan Semiconductor Manufacturing Co Ltd

Self-destruct sram-based authentication circuit

A memory device is disclosed. The memory device includes a memory bit array comprising a plurality of memory bits, wherein each memory bit is configured to present an initial logic state when the memory device is powered on, and an erasion circuit, coupled to the memory bit array, and configured... Taiwan Semiconductor Manufacturing Co Ltd

Memory device with strap cells

A device includes a memory array including a first sub-bank, a second sub-bank, a first strap cell and a data line. The first strap cell is arranged between the first sub-bank and the second sub-bank. The data line includes a first portion and a second portion. The first portion is... Taiwan Semiconductor Manufacturing Co Ltd

3d ic bump height metrology apc

In some embodiments, the present disclosure relates to a method of bump metrology The method is performed by forming a through-substrate-via within a substrate, forming a plurality of metal interconnect layers within a dielectric structure over the substrate, and forming a bump on the plurality of metal interconnect layers. One... Taiwan Semiconductor Manufacturing Co Ltd

Method of semiconductor integrated circuit fabrication

A method of semiconductor device fabrication includes providing a substrate including a first fin element and a second fin element extending from the substrate. A first layer is formed over the first and second fin elements, where the first layer includes a gap. A laser anneal process is performed to... Taiwan Semiconductor Manufacturing Co Ltd

Semiconductor device and manufacturing method thereof

In a method of manufacturing a semiconductor device, a thermal treatment is performed on a substrate, thereby forming a defect free layer in an upper layer of the substrate, where a remaining layer of the substrate is a bulk layer. A density of defects in the bulk layer is equal... Taiwan Semiconductor Manufacturing Co Ltd

Middle-end-of-line strap for standard cell

A method is disclosed that includes disposing a first conductive metal segment; disposing a second conductive metal segment over an active area; disposing a local conductive segment to couple the first conductive metal segment and the second conductive metal segment; disposing a first conductive via on the first conductive metal... Taiwan Semiconductor Manufacturing Co Ltd

Dielectric film for semiconductor fabrication

A method for semiconductor manufacturing is disclosed. The method includes receiving a device having a first surface through which a first metal or an oxide of the first metal is exposed. The method further includes depositing a dielectric film having Si, N, C, and O over the first surface such... Taiwan Semiconductor Manufacturing Co Ltd

Package structure with bump

A package structure is provided. The package structure includes a molding compound. The package structure also includes an integrated circuit chip having a chip edge in the molding compound. The package structure further includes a passivation layer below the integrated circuit chip and the molding compound. In addition, the package... Taiwan Semiconductor Manufacturing Co Ltd

Integrated fan-out package and fabricating the same

An integrated fan-out package including a die attach film, an integrated circuit component, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit component is disposed on the die attach film and includes a plurality of conductive terminals. The die attach film includes an uplifted edge which... Taiwan Semiconductor Manufacturing Co Ltd

Integrated fan-out package and fabricating the same

An integrated fan-out package including a die attach film, an integrated circuit component, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit component is disposed on the die attach film and includes a plurality of conductive terminals. The die attach film includes an uplifted edge which... Taiwan Semiconductor Manufacturing Co Ltd

Semiconductor device including tungsten gate and manufacturing method thereof

In a method of manufacturing a tungsten layer by an atomic layer deposition, a seed layer on an underlying layer is formed on a substrate by supplying a boron containing gas and a dilute gas, and a tungsten layer is formed on the seed layer by supplying a tungsten containing... Taiwan Semiconductor Manufacturing Co Ltd

Semiconductor device and manufacturing method thereof

A field effect transistor includes a channel layer made of a semiconductor and a metal gate structure. The metal gate structure includes a gate dielectric layer, a barrier layer formed on the gate dielectric layer, a work function adjustment layer formed on the barrier layer and made of one of... Taiwan Semiconductor Manufacturing Co Ltd

Memory device having a single bottom electrode layer

The present disclosure relates to a method of manufacturing a memory device. The method is performed by forming an inter-layer dielectric (ILD) layer over a substrate, and forming an opening within a dielectric protection layer over the ILD layer. A bottom electrode layer is formed within the opening and over... Taiwan Semiconductor Manufacturing Co Ltd

Mram device and fabricating the same

A semiconductor device structure is provided. The semiconductor device structure includes a magnetoresistive random access memory (MRAM) device in an insulating layer. The MRAM device includes a first electrode, a magnetic tunnel junction (MTJ) over the first electrode, a second electrode over the MTJ, and an insulating spacer surrounding sidewalls... Taiwan Semiconductor Manufacturing Co Ltd

Techniques for mram mtj top electrode connection

Some embodiments relate to an integrated circuit including a magnetoresistive random-access memory (MRAM) cell. The integrated circuit includes a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes a plurality of dielectric layers and a plurality of metal layers that are stacked over one... Taiwan Semiconductor Manufacturing Co Ltd

Metal landing on top electrode of rram

Some embodiments relate to a method. A semiconductor substrate is received. The semiconductor substrate has an interconnect structure disposed over a memory region and a logic region of the semiconductor substrate. A bottom electrode and a top electrode are formed over the interconnect structure over the memory region. The bottom... Taiwan Semiconductor Manufacturing Co Ltd

Damping component and integrated-circuit testing apparatus using the same

A damping component includes a housing, at least one sliding piece, a fluid, and at least one damping elastomer. The housing may have at least one opening. The sliding piece is slidably sealed the opening, and partially protruded outside the opening, to form an accommodation space within the housing. The... Taiwan Semiconductor Manufacturing Co Ltd

Semiconductor device and manufacturing method thereof

A method of manufacturing a source structure for a p-type metal-oxide-semiconductor (PMOS) field effect transistor (FET) is provided. In the method, a first epitaxial layer comprising Si1−xGex is formed on a source region of an FET, a second epitaxial layer comprising Si1−yGey is formed on the first epitaxial layer, a... Taiwan Semiconductor Manufacturing Co Ltd

Directional patterning methods

Directional patterning methods are disclosed herein. An exemplary method includes performing a lithography process to form a pattered hard mask layer over a wafer, wherein the patterned hard mask layer includes a hard mask feature having an associated horizontally-defined characteristic; tuning an etching process to direct etching species in a... Taiwan Semiconductor Manufacturing Co Ltd

Method of manufacturing a semiconductor device having deep wells

A semiconductor device includes first and second voltage device regions and a deep well common to the first and second voltage device regions. An operation voltage of electronic devices in the second voltage device region is higher than that of electronic devices in the first voltage device region. The deep... Taiwan Semiconductor Manufacturing Co Ltd

Method for forming semiconductor package using carbon nano material in molding compound

A method of forming a semiconductor package includes growing a layer of carbon nano material on a chip. The chip has a first surface and a second surface and the layer of carbon nano material is grown on the first surface of the chip. The layer of carbon nano material... Taiwan Semiconductor Manufacturing Co Ltd

03/29/18 / #20180090431

Semiconductor structure

A semiconductor structure includes a substrate, a dielectric layer, a metal layer, and a tungsten layer. The dielectric layer is on the substrate and has a recess feature therein. The metal layer is in the recess feature. The metal layer has an oxygen content less than about 0.1 atomic percent.... Taiwan Semiconductor Manufacturing Co Ltd

03/29/18 / #20180090439

Hybrid copper structure for advance interconnect usage

The present disclosure, in some embodiments, relates to an integrated chip having a back-end-of-the-line interconnect stack. The integrated chip has a dielectric structure arranged over a substrate. A first interconnect structure is arranged within the dielectric structure and has sidewalls and a horizontally extending surface that define a recess within... Taiwan Semiconductor Manufacturing Co Ltd

03/29/18 / #20180090445

Integrated fan-out package

A method for fabricating an integrated fan-out package is provided. The method includes the following steps. A plurality of conductive posts are placed in apertures of a substrate. A carrier having an adhesive thereon is provided. The conductive posts are transferred to the carrier in a standing orientation by adhering... Taiwan Semiconductor Manufacturing Co Ltd

03/29/18 / #20180090561

Structure and formation semiconductor device structure with gate stack

Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The gate stack includes a gate dielectric layer and a work function layer. The gate dielectric layer is between the semiconductor substrate and... Taiwan Semiconductor Manufacturing Co Ltd

03/29/18 / #20180090631

Dielectric sidewall structure for quality improvement in ge and sige devices

Some embodiments relate to an integrated circuit (IC) disposed on a silicon substrate, which includes a well region having a first conductivity type. A dielectric layer is arranged over an upper surface of the silicon substrate, and extends over outer edges of the well region and includes an opening that... Taiwan Semiconductor Manufacturing Co Ltd

03/22/18 / #20180082876

Method for charging gas into cassette pod

A method for transporting a cassette pod for containing semiconductor waters is provided. The method includes transporting a cassette pod configured to receive a semiconductor wafer with a transporting apparatus. The method further includes supplying a gas from a cylinder into a housing of the cassette pod. The cylinder is... Taiwan Semiconductor Manufacturing Co Ltd

03/22/18 / #20180082834

Method and system for wet chemical bath process

A method for performing a wet chemical process over a semiconductor wafer is provided. The method includes moving the semiconductor wafer into a chemical solution. The method further includes leaving the semiconductor wafer in the chemical solution for a processing time period. The method also includes turning the semiconductor wafer... Taiwan Semiconductor Manufacturing Co Ltd

03/22/18 / #20180082908

Semiconductor device and manufacturing method thereof

A semiconductor device includes a first semiconductor channel, a second semiconductor channel, a first gate stack and a second gate stack. The first gate stack includes N-work function metal present on the first semiconductor channel. The second gate stack includes N-work function metal present on the second semiconductor channel. The... Taiwan Semiconductor Manufacturing Co Ltd

03/22/18 / #20180082961

Semiconductor device package with warpage control structure

Between an adhesive surface of a heat spreader lid and a top surface of a semiconductor package, in addition to a spreader adhesive layer, several warpage control adhesive layers are also provided. The warpage control adhesive layers are disposed on corner areas of the adhesive surface of the heat spreader... Taiwan Semiconductor Manufacturing Co Ltd

03/22/18 / #20180082987

Package structure with dummy die

A package structure and method for forming the same are provided. The package structure includes a substrate, and a device die formed over the substrate. The device die has a first height. The package structure includes a dummy die formed over the substrate and adjacent to the device die, and... Taiwan Semiconductor Manufacturing Co Ltd

03/22/18 / #20180083001

Semiconductor device and manufacturing method thereof

A semiconductor device includes a first semiconductor channel, a second semiconductor channel, a first gate stack and a second gate stack. The first gate stack is present on the first semiconductor channel. The second gate stack is present on the second semiconductor channel. The first gate stack and the second... Taiwan Semiconductor Manufacturing Co Ltd

03/22/18 / #20180083019

Semiconductor device and manufacturing method thereof

In a method of manufacturing a semiconductor device including a non-volatile memory formed in a memory cell area and a logic circuit formed in a peripheral area, a mask layer is formed over a substrate in the memory cell area and the peripheral area. A resist mask is formed over... Taiwan Semiconductor Manufacturing Co Ltd

03/22/18 / #20180083109

Semiconductor device with epitaxial source/drain

A semiconductor device and method of manufacturing the semiconductor device are provided. In some embodiments, the semiconductor device includes a fin extending from a substrate and a gate structure disposed over the fin. The gate structure includes a gate dielectric formed over the fin, a gate electrode formed over the... Taiwan Semiconductor Manufacturing Co Ltd

03/15/18 / #20180073934

Thermal detection circuit

A circuit is disclosed that includes a first differential input pair, a second differential input pair, and a capacitive element. The first differential input pair is configured to be activated according to an output of the second differential input pair, and the second differential input pair is configured to be... Taiwan Semiconductor Manufacturing Co Ltd

03/15/18 / #20180076081

Method of planarizating film

A method includes forming a patterned layer on a substrate having a first region and a second region being adjacent each other. The patterned layer includes first features in the first region. The second region is free of the patterned layer. The method further includes forming a material layer on... Taiwan Semiconductor Manufacturing Co Ltd

03/15/18 / #20180076091

Finfet gate structure and fabricating the same

A semiconductor device includes a n-type gate structure over a first semiconductor fin, in which the n-type gate structure is fluorine incorporated and includes a n-type work function metal layer overlying the first high-k dielectric layer. The n-type work function metal layer includes a TiAl (titanium aluminum) alloy, in which... Taiwan Semiconductor Manufacturing Co Ltd

03/15/18 / #20180076109

Interconnect arrangement with stress-reducing structure and fabricating the same

A semiconductor device structure and a method of fabricating the same are provided. The method for manufacturing a semiconductor structure includes forming a dielectric layer over a substrate and forming a first structure through the dielectric layer such that a first portion of the dielectric layer is disposed in between... Taiwan Semiconductor Manufacturing Co Ltd

03/15/18 / #20180076141

Semiconductor device and manufacturing method thereof

In a method for manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, first recesses are formed in the first dielectric layer. Metal wirings extending is a first direction are formed in the first recesses. A mask layer is formed over the metal wirings and the... Taiwan Semiconductor Manufacturing Co Ltd

03/15/18 / #20180076198

Techniques providing metal gate devices with multiple barrier layers

A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK... Taiwan Semiconductor Manufacturing Co Ltd

03/15/18 / #20180076203

Structure and semiconductor device

A semiconductor device includes a substrate; an isolation structure over the substrate; and two fins in a first region of the semiconductor device extending from the substrate and through the isolation structure. Each of the two fins has a channel region and two source/drain (S/D) regions sandwiching the channel region.... Taiwan Semiconductor Manufacturing Co Ltd

03/15/18 / #20180076314

Method for fabricating finfet with p/n stacked fins

A semiconductor device is provided and includes a semiconductor fin protruding from a semiconductor substrate. The semiconductor fin includes plural pairs of semiconductor layers on the semiconductor substrate, each pair of semiconductor layers consists of a first semiconductor layer of a first conductivity type, and a second semiconductor layer of... Taiwan Semiconductor Manufacturing Co Ltd

03/08/18 / #20180066939

Method for validating measurement data

A method includes receiving, into a measurement tool, a substrate having a material feature, wherein the material feature is formed on the substrate according to a design feature. The method further includes applying a source signal on the material feature, collecting a response signal from the material feature by using... Taiwan Semiconductor Manufacturing Co Ltd

03/08/18 / #20180067395

System and supplying and dispensing bubble-free photolithography chemical solutions

A photolithography system includes a variable-volume buffer tank, a dispensing system connected to the buffer tank, and a valve configured to release gas from a head space of the buffer tank while blocking the release of liquid from the head space. A storage container has an opening at the bottom... Taiwan Semiconductor Manufacturing Co Ltd

03/08/18 / #20180068049

Multi-patterning graph reduction and checking flow method

A method of generating a plurality of photomasks includes generating a circuit graph. The circuit graph comprises a plurality of vertices and a plurality of edges. Each of the plurality of vertices is representative of one of a plurality of conductive lines. The plurality of edges are representative of a... Taiwan Semiconductor Manufacturing Co Ltd

03/08/18 / #20180068963

Semiconductor structure and manufacturing method thereof

A mechanism of a semiconductor structure with composite barrier layer under redistribution layer is provided. A semiconductor structure includes a substrate comprising a top metal layer on the substrate; a passivation layer over the top metal layer having an opening therein exposing the top metal layer; a composite barrier layer... Taiwan Semiconductor Manufacturing Co Ltd

03/08/18 / #20180068967

Semiconductor device structure and manufacturing method

A semiconductor device structure and a manufacturing method are provided. The semiconductor device structure includes a semiconductor substrate and a dielectric layer over the semiconductor substrate. The semiconductor device structure also includes a conductive trace over the dielectric layer. The semiconductor device structure further includes a conductive feature over the... Taiwan Semiconductor Manufacturing Co Ltd

03/08/18 / #20180069043

Semiconductor device structure and manufacturing process thereof

A semiconductor device structure for sensing an incident light includes a substrate, a wiring structure, and at least one passivation layer. The substrate has a device. The at least one passivation layer is disposed above the wiring structure. The at least one passivation layer includes a plurality of microstructures, and... Taiwan Semiconductor Manufacturing Co Ltd

03/08/18 / #20180069095

Semiconductor structure with unleveled gate structure

Semiconductor structures are provided. The semiconductor structure includes a fin structure formed over a substrate and a gate structure formed across the fin structure. In addition, the gate structure includes a gate dielectric layer formed over the substrate and a work function metal layer formed over a portion of the... Taiwan Semiconductor Manufacturing Co Ltd

03/08/18 / #20180069101

Method for manufacturing semiconductor fin structure with extending gate structure

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a fin structure formed over the substrate. The semiconductor structure further includes an isolation structure formed around the fin structure and a gate structure formed across the fin structure. In addition,... Taiwan Semiconductor Manufacturing Co Ltd

03/08/18 / #20180069114

Semiconductor device and manufacturing method thereof

A semiconductor device including a Fin FET device includes a fin structure extending in a first direction and protruding from a substrate layer. The fin structure includes a bulk stressor layer formed on the substrate layer and a channel layer disposed over the bulk stressor layer. An oxide layer is... Taiwan Semiconductor Manufacturing Co Ltd

Patent Packs
03/08/18 / #20180069120

Semiconductor device and manufacturing method thereof

A semiconductor device includes a substrate, a liner, and an epitaxy structure. The substrate has a recess. The liner is disposed in the recess. The liner is denser than the substrate. The epitaxy structure is disposed in the recess. The liner is disposed between the epitaxy structure and the substrate.... Taiwan Semiconductor Manufacturing Co Ltd

03/08/18 / #20180069554

Clock and data recovery module

A clock and data recovery module includes a clock and data recovery loop and a spread spectrum clock tracking circuit. The clock and data recovery loop includes a clock and data recovery unit and a first phase interpolator. The first phase interpolator is coupled to the clock and data recovery... Taiwan Semiconductor Manufacturing Co Ltd

03/08/18 / #20180069711

Sram-based authentication circuit

A memory device includes a memory block comprises a plurality of bits, wherein at least a first bit of the plurality of bits presents an initial logic state each time it is powered on; a start-up circuit configured to power on and off the memory block N times, where N... Taiwan Semiconductor Manufacturing Co Ltd

03/01/18 / #20180061987

Fabrication of semiconductor device

A method of fabricating a semiconductor device includes following steps. A trench is formed in a substrate. A barrier layer and an epitaxy layer are formed in sequence in the trench. The barrier layer has a first dopant. A source/drain recess cavity is formed by etching at least the epitaxial... Taiwan Semiconductor Manufacturing Co Ltd

03/01/18 / #20180059531

Chromeless phase shift mask structure and process

The present disclosure provides a phase shift mask. The phase shift mask includes a transparent substrate; an etch stop layer disposed on the substrate; and a tunable transparent material layer disposed on the etch stop layer and patterned to have an opening, wherein the tunable transparent material layer is designed... Taiwan Semiconductor Manufacturing Co Ltd

03/01/18 / #20180059534

Graphene pellicle for extreme ultraviolet lithography

A method includes depositing a first material layer over a first substrate; and depositing a graphene layer over the first material layer. The method further includes depositing an amorphous silicon layer over the graphene layer and bonding the amorphous silicon layer to a second substrate, thereby forming an assembly. The... Taiwan Semiconductor Manufacturing Co Ltd

03/01/18 / #20180059535

Graphene pellicle for extreme ultraviolet lithography

A method includes depositing a first material layer over a substrate; and depositing a graphene layer over the first material layer, thereby forming a first assembly. The method further includes attaching a carrier to the graphene layer; removing the substrate from the first assembly; and removing the first material layer... Taiwan Semiconductor Manufacturing Co Ltd

03/01/18 / #20180059992

3d cross-bar nonvolatile memory

Semiconductor structures and methods for crystalline junctionless transistors used in nonvolatile memory arrays are introduced. Various embodiments in accordance with this disclosure provide a method of fabricating a monolithic 3D cross-bar nonvolatile memory array with low thermal budget. The method incorporates crystalline junctionless transistors into nonvolatile memory structures by transferring... Taiwan Semiconductor Manufacturing Co Ltd

03/01/18 / #20180060479

Integrated fan-out package and layout method thereof

An integrated fan-out package and a layout method thereof are provided. One integrated fan-out package includes a die and a fan-out substrate. The die has an interconnect structure therein. The fan-out substrate has a redistribution layer structure therein and a plurality of first conductive bumps on a first surface thereof.... Taiwan Semiconductor Manufacturing Co Ltd

03/01/18 / #20180061487

Two-port sram connection structure

A static random access memory (SRAM) device is provided in accordance with some embodiments. The SRAM device comprises a plurality of two-port SRAM arrays, which comprise a plurality of two-port SRAM cells. Each two-port SRAM cell comprises a write port portion, a read port portion, a first plurality of metal... Taiwan Semiconductor Manufacturing Co Ltd

03/01/18 / #20180061488

Write assist circuit of memory device

A device including a memory cell and write assist circuit is disclosed. The memory cell includes a first inverter and a second inverter cross-coupled with the first inverter. The first inverter is operated with a first operational voltage and a third operational voltage, and the second inverter is operated with... Taiwan Semiconductor Manufacturing Co Ltd

03/01/18 / #20180061642

Method of manufacturing a semiconductor device

A method of manufacturing a semiconductor device includes forming a first metal layer on a semiconductor substrate and forming a second metal layer on the first metal layer. The second metal layer is formed of a different metal than the first metal layer. Microwave radiation is applied to the semiconductor... Taiwan Semiconductor Manufacturing Co Ltd

03/01/18 / #20180061685

Curing apparatus and method using the same

A UV curing apparatus includes a processing chamber, a UV light source disposed above the processing chamber, a window disposed between the processing chamber and the UV light source for allowing a UV light from the UV light source passing through and entering the processing chamber, a sealing ring disposed... Taiwan Semiconductor Manufacturing Co Ltd

03/01/18 / #20180061698

Semiconductor structure and related method

A method and structure for providing a semiconductor-on-insulator (SCOI) wafer having a buried low-K dielectric layer includes forming a device layer on a first semiconductor substrate. In various embodiments, at least a portion of the device layer is separated from the first semiconductor substrate, where the separating forms a cleaved... Taiwan Semiconductor Manufacturing Co Ltd

03/01/18 / #20180061753

Interconnect structure and methods thereof

A method and structure for forming a local interconnect, without routing the local interconnect through an overlying metal layer. In various embodiments, a first dielectric layer is formed over a gate stack of at least one device and a second dielectric layer is formed over a contact metal layer of... Taiwan Semiconductor Manufacturing Co Ltd

Patent Packs
03/01/18 / #20180061808

Package structure and manufacturing thereof

A package structure includes a package, at least one second molding material, and at least one electronic component. The package includes at least one first semiconductor device therein, a first molding material, at least one dielectric layer and at least one redistribution line. The first molding material is at least... Taiwan Semiconductor Manufacturing Co Ltd

03/01/18 / #20180061847

Semiconductor memory device and manufacturing method thereof

A memory device includes a substrate. An insulation layer is disposed in a recess in the substrate. A first gate structure is disposed over the substrate and the insulation layer. A first etch stop layer is disposed over the first gate structure. A first oxide layer is disposed over the... Taiwan Semiconductor Manufacturing Co Ltd

03/01/18 / #20180061877

Photodiode gate dielectric protection layer

In some embodiments, the present disclosure relates to a method of forming an integrated chip. The method is performed by forming a gate dielectric layer over a substrate, and selectively forming a gate material over the gate dielectric layer. A gate dielectric protection layer is formed over the gate dielectric... Taiwan Semiconductor Manufacturing Co Ltd

03/01/18 / #20180061957

Atomic layer deposition methods and structures thereof

A method and structure for providing a pre-deposition treatment (e.g., of a work-function layer) to accomplish work function tuning. In various embodiments, a gate dielectric layer is formed over a substrate and a work-function metal layer is deposited over the gate dielectric layer. Thereafter, a fluorine-based treatment of the work-function... Taiwan Semiconductor Manufacturing Co Ltd

03/01/18 / #20180061977

Device and fabricating a semiconductor device having a t-shape in the metal gate line-end

A method of fabricating a metal gate structure in a semiconductor device is disclosed. The method comprises removing a dummy poly gate, removing IL oxide and STI using a dry etch process and a wet lateral etch process to form a T-shape void in the semiconductor device, and depositing metal... Taiwan Semiconductor Manufacturing Co Ltd

02/22/18 / #20180050425

Tool and reflow

A tool and a method of reflow are provided. In various embodiments, the tool includes a chamber unit, a wafer lifting system, a heater, and an exhausting unit. The wafer lifting system is disposed in the chamber unit. The heater is coupled to the chamber unit, and configured to heat... Taiwan Semiconductor Manufacturing Co Ltd

02/22/18 / #20180053695

System and measuring and improving overlay using electronic microscopic imaging and digital processing

An SEM image is acquired. The SEM image shows a metal line and a via hole disposed above the metal line. The via hole exposes a portion of the metal line vertically aligned with the via hole. A first portion and a second portion of the via hole are each... Taiwan Semiconductor Manufacturing Co Ltd

02/22/18 / #20180053741

Bump structure having a side recess and semiconductor structure including the same

In some embodiments, the present disclosure relates to a method of integrated chip bonding. The method is performed by forming a metal layer on a substrate, and forming a solder layer on the metal layer. The solder layer is reflowed. The metal layer and the solder layer have sidewalls defining... Taiwan Semiconductor Manufacturing Co Ltd

02/22/18 / #20180053745

Method for forming a package structure including forming a molding compound on first larger bumps surrounding a semiconductor die and second smaller bumps formed under the semiconductor die

Package structures and methods for forming the same are provided. The method includes providing a first integrated circuit die and forming a redistribution structure over the first integrated circuit die. The method also includes forming a base layer over the redistribution structure. The base layer has first and second openings.... Taiwan Semiconductor Manufacturing Co Ltd

02/22/18 / #20180053800

Method for forming cmos image sensor structure

A semiconductor device is operated for sensing incident light and includes a substrate, a device layer, a semiconductor layer and a color filter layer. The device layer is disposed on the substrate and includes light-sensing regions. The semiconductor layer overlies the device layer and has a first surface and a... Taiwan Semiconductor Manufacturing Co Ltd

02/22/18 / #20180053850

Junction fet semiconductor device with dummy mask structures for improved dimension control and forming the same

A method for semiconductor devices on a substrate includes using gate structures which serve as active gate structures in a MOSFET region, as dummy gate structures in a JFET region of the device. The dummy gate electrodes are used as masks and determine the spacing between gate regions and source/drain... Taiwan Semiconductor Manufacturing Co Ltd

02/15/18 / #20180043495

Advanced polishing system

A method for polishing a polishing pad includes detecting a presence of a defect formed on a groove of a polishing pad; removing the defect from the groove of the polishing pad; after removing the defect, measuring a remaining depth of the groove; and based on the measured remaining depth... Taiwan Semiconductor Manufacturing Co Ltd

02/15/18 / #20180046436

Sram-based true random number generator

A random number generator (RNG) is disclosed. The RNG comprises a memory bit array having a plurality of bits, wherein each bit is configured to present an initial logic state when the memory bit array is powered on; and a first folding circuit coupled to the memory bit array, wherein... Taiwan Semiconductor Manufacturing Co Ltd

02/15/18 / #20180047442

Memory with keeper circuit

A memory device with a keeper circuit is disclosed herein. The memory device (i) improves current tracking between the device's memory cells and the keeper circuit, (ii) improves Vccmin for memory operations, and (iii) has an efficient circuit layout. The memory device includes a memory array with a plurality of... Taiwan Semiconductor Manufacturing Co Ltd

02/15/18 / #20180047561

Lithography method with surface modification layer

A lithography method is provided in accordance with some embodiments. The lithography method includes forming a surface modification layer on a substrate, the surface modification layer including a hydrophilic top surface; coating a photoresist layer on the surface modification layer; and developing the photoresist layer, thereby forming a patterned photoresist... Taiwan Semiconductor Manufacturing Co Ltd

02/15/18 / #20180047674

Method of manufacturing redistribution circuit structure and manufacturing integrated fan-out package

A method of manufacturing a redistribution circuit structure and a method of manufacturing an INFO package at least include the following steps. An inter-dielectric layer is formed over a substrate. A seed layer is formed over the inter-dielectric layer. A plurality of conductive patterns are formed over the seed layer.... Taiwan Semiconductor Manufacturing Co Ltd

02/15/18 / #20180047682

Composite bond structure in stacked semiconductor structure

A semiconductor device includes a substrate, a dielectric structure, a top metal layer and a bonding structure. The dielectric structure is disposed on the substrate. The top metal layer is disposed in the dielectric structure. The bonding structure is disposed on the dielectric structure and the top metal layer. The... Taiwan Semiconductor Manufacturing Co Ltd

02/15/18 / #20180047703

Formation chip package

Formation methods of a chip package are provided. The method includes bonding a first chip structure and a second chip structure over a substrate. The method also includes forming a release film to cover top surfaces of the first chip structure and the second chip structure. The method further includes... Taiwan Semiconductor Manufacturing Co Ltd

02/15/18 / #20180047740

Semiconductor structure and forming the same

A semiconductor structure includes a semiconductor substrate, at least one raised dummy feature, and at least one memory cell. The raised dummy feature is present on the semiconductor substrate and defines a cell region and a non-cell region outside of the cell region on the semiconductor substrate, and the raised... Taiwan Semiconductor Manufacturing Co Ltd

02/15/18 / #20180047837

Bipolar junction transistor (bjt) base conductor pullback

Some embodiments are directed to a bipolar junction transistor (BJT) with a collector region formed within a body of a semiconductor substrate, and an emitter region arranged over an upper surface of the semiconductor substrate. The BJT includes a base region arranged over the upper surface of the semiconductor substrate,... Taiwan Semiconductor Manufacturing Co Ltd

02/15/18 / #20180047895

Storage device with composite spacer and manufacturing the same

A storage device includes a first electrode, a stacked feature, a spacer and a barrier structure. The stacked feature is position over the first electrode, and includes a storage element and a second electrode over the storage element. The spacer is positioned on a sidewall of the stacked feature, the... Taiwan Semiconductor Manufacturing Co Ltd

02/15/18 / #20180046744

Systems and methods for cell abutment

The present disclosure is directed to systems and methods for cell placement. In embodiments, the methods include placing a plurality of cells selected from a cell library in a chip design to produce a first cell placement and determining whether the first cell placement satisfies design demands. In further embodiments,... Taiwan Semiconductor Manufacturing Co Ltd








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