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Taiwan Semiconductor Manufacturing Co Ltd
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Taiwan Semiconductor Manufacturing Co Ltd patents


Recent patent applications related to Taiwan Semiconductor Manufacturing Co Ltd. Taiwan Semiconductor Manufacturing Co Ltd is listed as an Agent/Assignee. Note: Taiwan Semiconductor Manufacturing Co Ltd may have other listings under different names/spellings. We're not affiliated with Taiwan Semiconductor Manufacturing Co Ltd, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "T" | Taiwan Semiconductor Manufacturing Co Ltd-related inventors


 new patent  Method of manufacturing semiconductor structure

A semiconductor structure includes a substrate, at least one active semiconductor fin, at least one insulating structure, a gate electrode, and a gate dielectric. The active semiconductor fin is disposed on the substrate. The insulating structure is disposed on the substrate and adjacent to the active semiconductor fin. A top... Taiwan Semiconductor Manufacturing Co Ltd

 new patent  Individually-tunable heat reflectors in an epi-growth system

A semiconductor fabrication system includes a wafer carrier configured to carry a wafer thereon. A radiation source is positioned above the wafer carrier. The radiation source is configured to emit thermal radiation. A plurality of reflectors is positioned above, and aligned with, an edge region of the wafer. The reflectors... Taiwan Semiconductor Manufacturing Co Ltd

 new patent  Reticle purging system and method thereof

A reticle purging system includes an automated pod opener, a reticle holding device, a reticle transporting device and at least one purging device. The reticle holding device has a reticle occupiable zone thereon. The reticle transporting device is assigned with a transportation path from the automated pod opener to the... Taiwan Semiconductor Manufacturing Co Ltd

 new patent  Chip package with thermal dissipation structure and forming the same

Structures and formation methods of a chip package are provided. The chip package includes a first package structure including a first semiconductor die that has a first side and a second side opposite thereto. The chip package also includes a package layer partially or completely encapsulating the first semiconductor die,... Taiwan Semiconductor Manufacturing Co Ltd

 new patent  Dual power structure with connection pins

In some embodiments, the present disclosure relates to an integrated chip having a lower power rail continuously extending over a plurality of gate structures. A first set of connection pins straddle a first edge of the lower power rail, and a second set of connection pins straddle a second edge... Taiwan Semiconductor Manufacturing Co Ltd

 new patent  Semiconductor device structure and forming the same

A semiconductor device structure is provided. The semiconductor device structure includes a first device. The semiconductor device structure includes a conductive element over the first device. The semiconductor device structure includes a first conductive shielding layer between the first device and the conductive element. The first conductive shielding layer has... Taiwan Semiconductor Manufacturing Co Ltd

 new patent  Integrated circuit package assembly

An integrated circuit package assembly includes a first integrated circuit package and a second integrated circuit package. The first integrated circuit package includes a first integrated circuit die mounted on a first substrate. The second integrated circuit package includes a second integrated circuit die mounted on a second substrate. The... Taiwan Semiconductor Manufacturing Co Ltd

 new patent  Fin-type field effect transistor structure and manufacturing method thereof

A fin-type field effect transistor comprising a substrate, at least one gate structure, spacers and source and drain regions is described. The substrate has a plurality of fins and a plurality of insulators disposed between the fins. The source and drain regions are disposed on two opposite sides of the... Taiwan Semiconductor Manufacturing Co Ltd

 new patent  Semiconductor device and manufacturing method thereof

A semiconductor device manufacturing method includes forming fins in first and second regions defined on a substrate. The fins include first fin, second fin, third fin, and fourth fin. A dielectric layer is formed over fins and a work function adjustment layer is formed over dielectric layer. A hard mask... Taiwan Semiconductor Manufacturing Co Ltd

 new patent  Semiconductor device and manufacturing method thereof

A semiconductor device includes a non-volatile memory and a logic circuit. The non-volatile memory includes a stacked structure comprising a first insulating layer, a floating gate, a second insulating layer, a control gate and a third insulating layer stacked in this order from a substrate; an erase gate line; and... Taiwan Semiconductor Manufacturing Co Ltd

 new patent  Semiconductor device including field effect transistor and a fabricating the same

In a method of fabricating a field effect transistor, a fin structure made of a first semiconductor material is formed so that the fin structure protrudes from an isolation insulating layer disposed over a substrate. A gate structure is formed over a part of the fin structure, thereby defining a... Taiwan Semiconductor Manufacturing Co Ltd

 new patent  Semiconductor device structure and forming the same

A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base and a fin structure over the base. The fin structure has sidewalls. The semiconductor device structure includes a passivation layer over the sidewalls. The passivation layer includes dopants. The dopants include at least one... Taiwan Semiconductor Manufacturing Co Ltd

 new patent  Method and structure for finfet devices

A method includes providing a semiconductor substrate having first and second regions that are doped with first and second dopants respectively. The first and second dopants are of opposite types. The method further includes epitaxially growing a first semiconductor layer that is doped with a third dopant. The first and... Taiwan Semiconductor Manufacturing Co Ltd

 new patent  Method for reducing contact resistance in semiconductor structures

Semiconductor structures and methods reduce contact resistance, while retaining cost effectiveness for integration into the process flow by introducing a heavily-doped contact layer disposed between two adjacent layers. The heavily-doped contact layer may be formed through a solid-phase epitaxial regrowth method. The contact resistance may be tuned by adjusting dopant... Taiwan Semiconductor Manufacturing Co Ltd

 new patent  Fin field effect transistor

A substrate is patterned to form trenches and a semiconductor fin between the trenches. Insulators are formed in the trenches and a dielectric layer is formed to cover the semiconductor fin and the insulators. A dummy gate strip is formed on the dielectric layer. Spacers are formed on sidewalls of... Taiwan Semiconductor Manufacturing Co Ltd

 new patent  Top electrode for device structures in interconnect

Some embodiments relate to an integrated circuit device, which includes a bottom electrode, a dielectric layer, and top electrode. The dielectric layer is disposed over the bottom electrode. The top electrode is disposed over the dielectric layer, and an upper surface of the top electrode exhibits a recess. A via... Taiwan Semiconductor Manufacturing Co Ltd

Chemical mechanical polishing head

To provide improved planarization, techniques in accordance with this disclosure include a CMP station that includes a support plate having a plurality of apertures. An aperture of the plurality of apertures has a first opening and a second opening connected by a slot. Other systems and methods are also disclosed.... Taiwan Semiconductor Manufacturing Co Ltd

Rram cell with pmos access transistor

In some embodiments, the present disclosure relates to a method of operating an RRAM cell having a PMOS access transistor. The method may be performed by turning on a PMOS transistor having a drain terminal coupled to a lower electrode of an RRAM device. A first voltage is provided to... Taiwan Semiconductor Manufacturing Co Ltd

Structure and formation semiconductor device structure

Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure. The semiconductor device structure further includes a spacer element over a... Taiwan Semiconductor Manufacturing Co Ltd

Integrated antenna on interposer substrate

Some embodiments relate to a semiconductor module having an integrated antenna structure. The semiconductor module has an excitable element and a first ground plane disposed between a substrate and the excitable element. A second ground plane is separated from the first ground plane by the substrate. The second ground plane... Taiwan Semiconductor Manufacturing Co Ltd

Semiconductor device and a fabricating the same

In a method of manufacturing a semiconductor device, a dummy gate structure is formed over a substrate. A first insulating layer is formed over the dummy gate structure. The dummy gate structure is removed so as to form a gate space in the first insulating layer. A first conductive layer... Taiwan Semiconductor Manufacturing Co Ltd

Systems and methods to enhance passivation integrity

Some embodiments relate to a semiconductor device. The semiconductor device includes a layer disposed over a substrate. A conductive body extends through the layer. A plurality of bar or pillar structures are spaced apart from one another and laterally surround the conductive body. The plurality of bar or pillar structures... Taiwan Semiconductor Manufacturing Co Ltd

Package structure

Package structures are provided. The package structure includes an integrated circuit die. The package structure also includes a package layer surrounding the integrated circuit die. There is an interface between the integrated circuit die and the package layer. The package structure further includes a redistribution structure below the integrated circuit... Taiwan Semiconductor Manufacturing Co Ltd

Trap layer substrate stacking technique to improve performance for rf devices

Some embodiments of the present disclosure are directed to a device. The device includes a substrate comprising a silicon layer disposed over an insulating layer. The substrate includes a transistor device region and a radio-frequency (RF) region. An interconnect structure is disposed over the substrate and includes a plurality of... Taiwan Semiconductor Manufacturing Co Ltd

Package assembly

In some embodiments, the present disclosure relates to a package assembly having a bump on a first substrate. A molding compound is on the first substrate and contacts sidewalls of the bump. A no-flow underfill layer is on a conductive region of a second substrate. The no-flow underfill layer and... Taiwan Semiconductor Manufacturing Co Ltd

Semicondcutor package and manufacturing method thereof

A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package has a first redistribution layer, a first die over the first redistribution layer, a molding compound encapsulating at least one second die and at least one third die disposed on the first redistribution layer,... Taiwan Semiconductor Manufacturing Co Ltd

Three-dimensional stacking structure

A three-dimensional stacking structure is described. The stacking structure includes at least a bottom die, a top die and a spacer protective structure. The bottom die includes contact pads in the non-bonding region. The top die is stacked on the bottom die without covering the contact pads of the bottom... Taiwan Semiconductor Manufacturing Co Ltd

Thinning process using metal-assisted chemical etching

Methods for forming a chip package are provided. The method includes providing at least one carrier substrate including first semiconductor dies mounted thereon. The method also includes forming a first noble metal layer including nanopores irregularly distributed therein to cover each one of the first semiconductor dies. The method further... Taiwan Semiconductor Manufacturing Co Ltd

Nvm memory hkmg integration technology

The present disclosure relates to an integrated circuit (IC) that includes a HKMG hybrid non-volatile memory (NVM) device and that provides small scale and high performance, and a method of formation. In some embodiments, the integrated circuit includes a memory region having a NVM device with a pair of control... Taiwan Semiconductor Manufacturing Co Ltd

Field-effect transistors having contacts to 2d material active region

Exemplary FET devices having 2D material layer active regions and methods of fabricating thereof are described. For example, a black phosphorus active region has a first thickness in the channel region and a second, greater, thickness in the source/drain (S/D) region. The BP in the S/D region has a sidewall... Taiwan Semiconductor Manufacturing Co Ltd

Metallic channel device and manufacturing method thereof

In a method for manufacturing a metallic-channel device, a metallic layer is formed on a substrate. The metallic layer is formed by an atomic layer deposition technique and has a first thickness. An insulating layer is formed over the metallic layer. A gate contact layer is formed over the insulating... Taiwan Semiconductor Manufacturing Co Ltd

Analog-to-digital conversion device

An analog-to-digital conversion device is provided that includes a front SAR ADC and a plurality of rear SAR ADCs. The front SAR ADC is configured to convert an analog input signal into a group of higher bits of a digital output signal in response to different time periods. Each of... Taiwan Semiconductor Manufacturing Co Ltd

Unlock detector, unlock-detecting method and clock and data recovery circuit

An unlock detector includes a checker, an accumulator, and a comparator. The accumulator is electrically connected to the checker, and the comparator is electrically connected to the accumulator. The checker includes several checking units. The checker is configured to receive a sampled data signal and a sampled edge signal, and... Taiwan Semiconductor Manufacturing Co Ltd

Dummy fin cell placement in an integrated circuit layout

In a method of forming an integrated circuit (IC) layout, an empty region in the IC layout is identified by a processor circuit, wherein the empty region is a region of the IC layout not including any active fins. A first portion of the empty region is filled with a... Taiwan Semiconductor Manufacturing Co Ltd

Cell structure for dual-port static random access memory

A dual port static random access memory cell includes a write port portion and a read port portion. The write port further includes a WPU1 and a WPU2; a WPD1 and a WPD2; and a WPG1 and a WPG2. The WPU1, WPU2, WPD1 and WPD2 are configured to form two... Taiwan Semiconductor Manufacturing Co Ltd

01/04/18 / #20180005824

A field effect transistor using transition metal dichalcogenide and a forming the same

In a method of fabricating a field effect transistor, a Mo layer is formed on the substrate. The Mo layer is sulfurized to convert it into a MoS2 layer. Source and drain electrodes are formed on the MoS2 layer. The MoS2 layer is treated with low-power oxygen plasma. A gate... Taiwan Semiconductor Manufacturing Co Ltd

01/04/18 / #20180005869

Method of semiconductor integrated circuit fabrication

A method of semiconductor device fabrication includes providing a substrate having a hardmask layer thereover. The hardmask layer is patterned to expose the substrate. The substrate is etched through the patterned hardmask layer to form a first fin element and a second fin element extending from the substrate. An isolation... Taiwan Semiconductor Manufacturing Co Ltd

01/04/18 / #20180005876

Etch stop layer for semiconductor devices

A semiconductor device includes a substrate, a first conductive feature over a portion of the substrate, and an etch stop layer over the substrate and the first conductive feature. The etch stop layer includes a silicon-containing dielectric (SCD) layer and a metal-containing dielectric (MCD) layer over the SCD layer. The... Taiwan Semiconductor Manufacturing Co Ltd

01/04/18 / #20180005877

Semiconductor devices, finfet devices and methods of forming the same

Semiconductor devices, FinFET devices and methods of forming the same are provided. In accordance with some embodiments, a semiconductor device includes a substrate, a first gate stack, a spacer, a first dielectric layer, a shielding layer and a connector. The first gate stack is over the substrate. The spacer is... Taiwan Semiconductor Manufacturing Co Ltd

01/04/18 / #20180005882

Low-k dielectric interconnect systems

A method of fabricating a semiconductor device includes forming a low-k dielectric layer over a substrate and depositing a cap layer over the low-k dielectric layer. A treatment process is performed to the cap layer. After the treatment process to the cap layer is performed, the low-k dielectric layer is... Taiwan Semiconductor Manufacturing Co Ltd

01/04/18 / #20180005897

Semiconductor device and a fabricating the same

In a method of manufacturing a semiconductor device, an isolation region is formed in a substrate, such that the isolation region surrounds an active region of the substrate in plan view. A first dielectric layer is formed over the active region. A mask layer is formed on a gate region... Taiwan Semiconductor Manufacturing Co Ltd

01/04/18 / #20180005938

Memory array structure and methods of fabricating thereof

Provided is a memory device including an array of memory cells. A first bit-line coupled to memory cells of a first column of the array of memory cells. The first bit-line is disposed on a first metal layer. A second bit-line is coupled to the first bit-line. The second bit-line... Taiwan Semiconductor Manufacturing Co Ltd

01/04/18 / #20180005955

Package structure and forming the same

A package structure and method for forming the same are provided. The package structure includes a substrate and a package layer formed over the substrate. The package structure further includes an alignment structure formed over the package layer, and the alignment structure includes a first alignment mark formed in a... Taiwan Semiconductor Manufacturing Co Ltd

01/04/18 / #20180005977

Method for forming hybrid bonding with through substrate via (tsv)

A method for forming a semiconductor device structure and method for forming the same are provided. The method includes hybrid bonding a first wafer and a second wafer to form a hybrid bonding structure, and the hybrid bonding structure comprises a metallic bonding interface and a polymer-to-polymer bonding structure. The... Taiwan Semiconductor Manufacturing Co Ltd

01/04/18 / #20180005996

Input output for an integrated circuit

A three-dimensional integrated circuit has a plurality of layers disposed in a stacked relationship. Logic circuitry is embodied in a first layer of the three-dimensional integrated circuit. An input output circuit is electrically coupled to the logic circuitry and has a plurality of transistors embodied in at least two layers... Taiwan Semiconductor Manufacturing Co Ltd

01/04/18 / #20180006005

Semicondcutor package and manufacturing method thereof

A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package has a redistribution layer, at least one die over the redistribution layer, through interlayer vias on the redistribution layer and aside the die and a molding compound encapsulating the die and the through interlayer... Taiwan Semiconductor Manufacturing Co Ltd

01/04/18 / #20180006009

Integrated circuit layout and configuring the same

An integrated circuit includes at least one first active region, at least one second active region adjacent to the first active region, and a plurality of third active regions. The first active region and the second active region are staggered. The third active regions are present adjacent to the first... Taiwan Semiconductor Manufacturing Co Ltd

01/04/18 / #20180006010

Integrated circuit filler and method thereof

Provided is a method for inserting a pre-designed filler cell, as a replacement to a standard filler cell, including identifying at least one gap among a plurality of functional cells. In some embodiments, a pre-designed filler cell is inserted within the at least one gap. By way of example, the... Taiwan Semiconductor Manufacturing Co Ltd

01/04/18 / #20180006039

Semiconductor device, static random access memory cell and manufacturing semiconductor device

A semiconductor device includes a substrate, a first semiconductor fin, a second semiconductor fin, an n-type epitaxy structure, a p-type epitaxy structure, and a plurality of dielectric fin sidewall structures. The first semiconductor fin is disposed on the substrate. The second semiconductor fin is disposed on the substrate and adjacent... Taiwan Semiconductor Manufacturing Co Ltd

01/04/18 / #20180006695

Multi-layer wireless streaming with adaptive constellation mapping (acm)

Systems and method for adaptive constellation mapping determine transmission formats for simultaneous transmission from multiple transmitter chains. The adaptive constellation mapping can select a winning combination of mappings using distance metrics. The distance metrics can be calculated from estimated received signal constellations at a multi-layer receiver. The multi-layer receiver can... Taiwan Semiconductor Manufacturing Co Ltd

12/28/17 / #20170369308

Semiconductor structure for mems device

The present disclosure relates to a semiconductor structure for a MEMS device. In some embodiments, the structure includes an interlayer dielectric (ILD) region positioned over a substrate. Further the structure includes an inter-metal dielectric region. The IMD region includes a passivation layer overlying a stacked structure. The stacked structure includes... Taiwan Semiconductor Manufacturing Co Ltd

12/28/17 / #20170372917

Pattern transfer technique and manufacturing the same

A photo-free lithography process with low cost, high throughput, and high reliability is provided. A template mask is bonded to a production workpiece and comprises a plurality of openings defining a pattern. An etch is performed into the production workpiece, through the plurality of openings, to transfer the pattern of... Taiwan Semiconductor Manufacturing Co Ltd

12/28/17 / #20170372932

Integrated chip die carrier exchanger

The present disclosure relates to an integrated chip (IC) processing tool having a die exchanger configured to automatically transfer a plurality of IC die between a die tray and a die boat, and an associated method. The integrated chip processing tool has a die exchanger configured to receive a die... Taiwan Semiconductor Manufacturing Co Ltd

12/28/17 / #20170372969

System and widening fin widths for small pitch finfet devices

A FinFET includes a semiconductor layer having a fin structure that protrudes out of the semiconductor layer. The fin structure includes a first segment and a second segment disposed over the first segment. A dielectric layer is disposed over the semiconductor layer. The first segment of the fin structure is... Taiwan Semiconductor Manufacturing Co Ltd

12/28/17 / #20170372974

Method and structure for mandrel and spacer patterning

An IC manufacturing method includes forming first mandrels and second mandrels over a substrate; and forming first spacers on sidewalls of the first mandrels and second spacers on sidewalls of the second mandrels. Each of the first and second spacers has a loop structure with two curvy portions connected by... Taiwan Semiconductor Manufacturing Co Ltd

12/28/17 / #20170372999

Conductive terminal on integrated circuit

A conductive terminal on an integrated circuit is provided. The conductive terminal includes a conductive pad, a dielectric layer, and a conductive via. The conductive pad is disposed on and electrically to the integrated circuit. The dielectric layer covers the integrated circuit and the conductive pad, the dielectric layer includes... Taiwan Semiconductor Manufacturing Co Ltd

12/28/17 / #20170373016

Packaged semiconductor device and fabricating a packaged semiconductor device

In accordance with some embodiments of the present disclosure, a packaged semiconductor device includes a first package structure, at least one outer conductive bump, a second package structure, a sealing material, and an electromagnetic interference (EMI) shielding layer. The first package structure has a first cut edge. The outer conductive... Taiwan Semiconductor Manufacturing Co Ltd

12/28/17 / #20170373037

Integrated fan-out package and fabricating the same

An integrated fan-out package including an integrated circuit, a plurality of memory devices, an insulating encapsulation, and a redistribution circuit structure is provided. The memory devices are electrically connected to the integrated circuit. The integrated circuit and the memory devices are stacked, and the memory devices are embedded in the... Taiwan Semiconductor Manufacturing Co Ltd

12/28/17 / #20170373056

Vertical metal insulator metal capacitor having a high-k dielectric material

A vertical metal-insulator-metal (MIM) capacitor is formed within multiple layers of a multi-level metal interconnect system of a chip. The vertical MIM capacitor has a first electrode, a second electrode, and a high-k capacitor dielectric material disposed therebetween. The dielectric constant of the capacitor dielectric material is greater than the... Taiwan Semiconductor Manufacturing Co Ltd

12/28/17 / #20170373058

Methods of gate replacement in semiconductor devices

A method of forming a semiconductor device includes forming a plurality of fins on a substrate, forming a polysilicon gate structure, and replacing the polysilicon gate structure with a metal gate structure. Replacing the polysilicon gate structure includes depositing a work function metal layer over the plurality of fins, forming... Taiwan Semiconductor Manufacturing Co Ltd

12/28/17 / #20170373133

Magnetic core inductors for integrated voltage regulator

A device includes an insulating layer disposed over a silicon substrate. The insulating layer includes a core insulating area and a peripheral insulating area. A trench laterally encloses the core insulating area and separates the core insulating area from the peripheral insulating area. A magnetic winding coil is disposed within... Taiwan Semiconductor Manufacturing Co Ltd

12/28/17 / #20170373143

Method of manufacturing semiconductor structure

A method of manufacturing a semiconductor structure includes the following steps. A first raised portion is formed on a semiconductor substrate. The height of the first raised portion is reduced, and a dielectric material is formed over the first raised portion. The dielectric material is annealed such that the first... Taiwan Semiconductor Manufacturing Co Ltd

12/28/17 / #20170373163

Method for manufacturing horizontal-gate-all-around devices with different number of nanowires

A method includes the following operations: (i) receiving a FET precursor including a first fin and a second fin, each of the first fin and the second fin having nanowire channels and sacrificial layers; (ii) forming a dummy gate traversing the first and second fins, thereby defining channel regions of... Taiwan Semiconductor Manufacturing Co Ltd

12/28/17 / #20170373189

Method for semiconductor device fabrication with improved source drain epitaxy

A semiconductor structure includes a substrate, first gate structures and second gate structures over the substrate, third epitaxial semiconductor features proximate the first gate structures, and fourth epitaxial semiconductor features proximate the second gate structures. The first gate structures have a greater pitch than the second gate structures. The third... Taiwan Semiconductor Manufacturing Co Ltd

12/21/17 / #20170363704

Biosensor calibration system and related method

A device includes a first biosensor of a biosensor array; a second biosensor of a biosensor array; a readout circuit electrically connected to the biosensor array; a decoder electrically connected to the biosensor array; a voltage generator electrically connected to the biosensor array; and a decision system electrically connected to... Taiwan Semiconductor Manufacturing Co Ltd

Patent Packs
12/21/17 / #20170365314

Magnetic tunnel junction memory device

Various memory devices are disclosed herein. An exemplary memory device includes a first electrode, a first magnetic layer disposed over the first electrode, a second magnetic layer disposed over the first magnetic layer, a barrier layer disposed between the first magnetic layer and the second magnetic layer, and a second... Taiwan Semiconductor Manufacturing Co Ltd

12/21/17 / #20170365472

Cut last self-aligned litho-etch patterning

The present disclosure relates to a method of performing a semiconductor fabrication process. The method may be performed by forming a spacer material having vertically extending segments along sidewalls of a masking layer and a horizontally extending segment connecting the vertically extending segments. A cut material is formed over a... Taiwan Semiconductor Manufacturing Co Ltd

12/21/17 / #20170365552

Semiconductor device and a fabricating the same

A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer,... Taiwan Semiconductor Manufacturing Co Ltd

12/21/17 / #20170365561

Method for preventing bottom layer wrinkling in a semiconductor device

A method for manufacturing a semiconductor device includes forming a first insulating film over a semiconductor substrate and forming a second insulating film on the first insulating film. The first insulating film is a tensile film having a first tensile stress and the second insulating film is either a tensile... Taiwan Semiconductor Manufacturing Co Ltd

12/21/17 / #20170365610

Formation semiconductor device with embedded capacitor

A method for forming a semiconductor device is provided. The method includes forming a dielectric layer over a semiconductor substrate and forming a contact plug in the dielectric layer. The method also includes partially removing the contact plug to form a recess over the contact plug. The method further includes... Taiwan Semiconductor Manufacturing Co Ltd

12/21/17 / #20170365691

Method of forming a contact

A method includes forming a first gate structure in a dielectric layer over a substrate, wherein the first gate structure includes a first gate stack and spacers along sidewalls of the first gate stack; recessing the first gate stack to form a first trench defined by the spacers, wherein upper... Taiwan Semiconductor Manufacturing Co Ltd

12/21/17 / #20170365705

Structure and formation semiconductor device structure with gate stacks

Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a first gate stack over the semiconductor substrate. The first gate stack includes a metal electrode. The semiconductor device structure also includes a second gate stack over the semiconductor substrate,... Taiwan Semiconductor Manufacturing Co Ltd

12/21/17 / #20170365707

Semiconductor device including fin-fet and manufacturing method thereof

A semiconductor device includes a first fin structure for a first fin field effect transistor (PET). The first fin structure includes a first base layer protruding from a substrate, a first intermediate layer disposed over the first base layer and a first channel layer disposed over the first intermediate layer.... Taiwan Semiconductor Manufacturing Co Ltd

12/21/17 / #20170365719

Negative capacitance field effect transistor

A gate structure of a negative capacitance field effect transistor (NCFET) is disclosed. The NCFET includes a gate stack disposed over a substrate. The gate stack includes a dielectric material layer, a ferroelectric ZrO2 layer and a first conductive layer. The NCFET also includes a source/drain feature disposed in the... Taiwan Semiconductor Manufacturing Co Ltd

12/14/17 / #20170355598

Structure to reduce backside silicon damage

An integrated circuit (IC) device is provided. The IC device includes a first die including a first substrate and a second die including a second substrate. A plasma-reflecting layer is included on an upper surface of the first die. The plasma-reflecting layer is configured to reflect a plasma therefrom. The... Taiwan Semiconductor Manufacturing Co Ltd

12/14/17 / #20170356953

In-line device electrical property estimating method and test structure of the same

A method for estimating at least one electrical property of a semiconductor device is provided. The method includes forming the semiconductor device and at least one testing unit on a substrate, irradiating the testing unit with at least one electron beam, estimating electrons from the testing unit induced by the... Taiwan Semiconductor Manufacturing Co Ltd

12/14/17 / #20170357284

Calibration of a resistor in a current mirror circuit

A reference stage includes a first transistor, a second transistor and a resistor that are connected in series from a voltage rail to a reference load. The resistor has (i) a resistance that is a function of a digital resistance-controlling value, (ii) a first terminal coupled to a gate of... Taiwan Semiconductor Manufacturing Co Ltd

12/14/17 / #20170358430

Aluminum apparatus with aluminum oxide layer and forming the same

In a method, an aluminum body is chemically treated with at least one of an alkaline solution and an acid solution. Anode-oxidization is performed on the chemically treated aluminum body to form an aluminum oxide layer. The aluminum oxide layer is treated with hot water at a temperature more than... Taiwan Semiconductor Manufacturing Co Ltd

12/14/17 / #20170358446

Wafer processing apparatus and wafer processing method using the same

A wafer processing apparatus includes at least one pedestal, at least one ultraviolet (UV) light source, and a window. The pedestal is configured to support a wafer. The UV light source is configured to generate UV radiation to the wafer. The window is present between the pedestal and the UV... Taiwan Semiconductor Manufacturing Co Ltd

12/14/17 / #20170358471

Wafer container with dampening mechanism

A wafer container is provided. The wafer container includes a pod base having a top surface and a bottom surface, a cassette disposed on the top surface, and a damping device, disposed on the bottom surface. The damping device includes a housing disposed in the pod base, and a damping... Taiwan Semiconductor Manufacturing Co Ltd

Patent Packs
12/14/17 / #20170358474

Wafer support device and removing lift pin therefrom

A wafer support device includes a susceptor, at least one lift pin, at least one lift pin support base and at least one pad. The susceptor has a bottom surface and a top surface configured to support a wafer. The susceptor has at least one through hole extending between the... Taiwan Semiconductor Manufacturing Co Ltd

12/14/17 / #20170358485

Semiconductor structure

A semiconductor structure includes a substrate, first and second conductors, a passivation material, and a passivation sidewall block. The first and second conductors are on the substrate. The passivation material is between the first and second conductors. The passivation sidewall block is on sidewalls of the first and second conductors... Taiwan Semiconductor Manufacturing Co Ltd

12/14/17 / #20170358493

Through substrate via structure for noise reduction

A semiconductor device includes a substrate and a through substrate via structure. The substrate has a through via hole. The through substrate via structure is disposed in the through via hole. The through substrate via structure disposed in the through via hole includes a liner structure and a metal layer.... Taiwan Semiconductor Manufacturing Co Ltd

12/14/17 / #20170358542

Structure and formation chip package with lid

Structures and formation methods of a chip package are provided. The chip package includes a substrate and a semiconductor die over a surface of the substrate. The chip package also includes a lid over the semiconductor die. The lid has a number of support structures bonded with the substrate, and... Taiwan Semiconductor Manufacturing Co Ltd

12/14/17 / #20170358569

Electrostatic discharge device

An integrated circuit device includes at least two epitaxially grown active regions grown onto a substrate, the active regions being placed between a first gate device and a second gate device. The integrated circuit device includes at least one dummy gate between the two epitaxially grown active regions and between... Taiwan Semiconductor Manufacturing Co Ltd

12/14/17 / #20170358620

Complementary metal-oxide-semiconductor (cmos) image sensor

A complementary metal-oxide-semiconductor (CMOS) image sensor having a passivation layer is provided. The CMOS image sensor includes a sensing device substrate. Isolation structures are positioned within trenches of the sensing device substrate. The isolation structures are arranged along opposing sides of a plurality of image sensing devices. The CMOS image... Taiwan Semiconductor Manufacturing Co Ltd

12/14/17 / #20170358646

Semiconductor device and manufacturing method thereof

A semiconductor device includes one nanowire structure disposed on semiconductor substrate and extending in first direction on semiconductor substrate. Each nanowire structure includes plurality of nanowires extending along first direction and arranged in second direction, the second direction being substantially perpendicular to first direction. Each nanowire is spaced-apart from immediately... Taiwan Semiconductor Manufacturing Co Ltd

12/14/17 / #20170358653

Semiconductor structure with enlarged gate electrode structure and forming the same

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate stack structure formed over a substrate. The gate stack structure includes a gate electrode structure having a first portion and a second portion and a first conductive layer below the gate electrode... Taiwan Semiconductor Manufacturing Co Ltd

12/14/17 / #20170358654

Semiconductor device and forming vertical structure

According to an exemplary embodiment, a method of forming a vertical structure is provided. The method includes the following operations: providing a substrate; providing the vertical structure having a source, a channel, and a drain over the substrate; shrinking the source and the channel by oxidation; forming a metal layer... Taiwan Semiconductor Manufacturing Co Ltd

12/14/17 / #20170358663

Method for manufacturing a semiconductor device

A method for manufacturing a semiconductor device is provided, including forming a fin field effect transistor (FinFET) structure on a semiconductor substrate. The FinFET structure includes at least one fin, and a gate electrode structure and source/drain regions on the at least one fin. A dielectric film is formed over... Taiwan Semiconductor Manufacturing Co Ltd

12/14/17 / #20170358678

Fin-type field effect transistor structure and manufacturing method thereof

A fin-type field effect transistor comprising a substrate, a plurality of insulators, at least one gate stack and strained material portions is described. The substrate has a plurality of fins thereon and the fin comprises a stop layer embedded therein. The plurality of insulators is disposed on the substrate and... Taiwan Semiconductor Manufacturing Co Ltd

12/14/17 / #20170358681

Structure and formation semiconductor device structure

Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure. The gate stack includes a first portion and a second portion... Taiwan Semiconductor Manufacturing Co Ltd

12/07/17 / #20170350938

Ic degradation management circuit, system and method

An IC degradation sensor is disclosed. The IC degradation management sensor includes an odd number of first logic gates electrically connected in a ring oscillator configuration, each first logic gate having an input and an output. Each first logic gate further includes a first PMOS transistor, a first NMOS transistor... Taiwan Semiconductor Manufacturing Co Ltd

12/07/17 / #20170350939

Scan architecture for interconnect testing in 3d integrated circuits

A device comprises a first die; and a second die stacked below the first die with interconnections between the first die and the second die. A least one of the first die or the second die has a circuit for performing a function and provides a functional path. Each of... Taiwan Semiconductor Manufacturing Co Ltd

12/07/17 / #20170351169

High durability extreme ultraviolet photomask

The present disclosure provides an embodiment of a reflective mask that includes a substrate; a reflective multilayer disposed on the substrate; an anti-oxidation barrier layer disposed on the reflective multilayer and the anti-oxidation barrier layer is in amorphous structure with an average interatomic distance less than an oxygen diameter; and... Taiwan Semiconductor Manufacturing Co Ltd

12/07/17 / #20170352144

Method for repairing a mask

A method includes inspecting a mask to locate a defect region for a defect of the mask. A phase distribution of an aerial image of the defect region is acquired. A point spread function of an imaging system is determined. One or more repair regions of the mask are identified... Taiwan Semiconductor Manufacturing Co Ltd

12/07/17 / #20170352524

Advanced exhaust system

An apparatus for a semiconductor process includes an exhaust pipe coupled to a reaction chamber and a pump; a pressure control valve that is coupled to the exhaust pipe and configured to control a pressure value in the reaction chamber; a first pipe that is coupled to the exhaust pipe... Taiwan Semiconductor Manufacturing Co Ltd

12/07/17 / #20170352539

Material having single crystal perovskite, device including the same, and manufacturing method thereof

A method for forming a material having a Perovskite single crystal structure includes alternately growing, on a substrate, each of a plurality of first layers and each of a plurality of second layers having compositions different from the plurality of first layers and forming a material having a Perovskite single... Taiwan Semiconductor Manufacturing Co Ltd

12/07/17 / #20170352548

Cmp-friendly coatings for planar recessing or removing of variable-height layers

A method of manufacturing an integrated circuit device is provided. A first feature, which has a first susceptibility to damage by chemical mechanical processing (CMP), is formed at a first height as measured from an upper surface of the substrate. A second feature, which has a second susceptibility to damage... Taiwan Semiconductor Manufacturing Co Ltd

12/07/17 / #20170352559

Fluorine contamination control in semiconductor manufacturing process

A method of forming a semiconductor device includes forming a fin over a substrate, forming a polysilicon gate structure over the fin, and replacing the polysilicon gate structure with a metal gate structure. Replacing of the polysilicon gate structure includes depositing a work function metal layer over the fin, performing... Taiwan Semiconductor Manufacturing Co Ltd

12/07/17 / #20170352574

Apparatus and treating wafer

An apparatus for treating a wafer is provided. The apparatus includes a platen, a chamber, an etch gas supplier and a tilting mechanism. The chamber has at least one aperture at least partially facing to the platen. The etch gas supplier is fluidly connected to the chamber. The tilting mechanism... Taiwan Semiconductor Manufacturing Co Ltd

12/07/17 / #20170352623

Integrated circuit having staggered conductive features

An integrated circuit includes at least one first conductive feature and at least one second conductive feature. The second conductive feature has at least one extension portion, and the extension portion of the second conductive feature is protruded from the projection of the first conductive feature on the second conductive... Taiwan Semiconductor Manufacturing Co Ltd

12/07/17 / #20170352626

Integrated fan-out structure with rugged interconnect

A method of forming a package assembly includes forming a first dielectric layer over a carrier substrate; forming a conductive through-via over the first dielectric layer; treating the conductive through-via with a first chemical, thereby roughening surfaces of the conductive through-via; and molding a device die and the conductive through-via... Taiwan Semiconductor Manufacturing Co Ltd

12/07/17 / #20170352641

Method and system for mounting components in semiconductor fabrication process

A method for mounting components on a substrate is provided. The method includes providing a positioning plate which has a plurality of through holes. The method further includes supplying components each having a longitudinal portion on the positioning plate. The method also includes performing a component alignment process to put... Taiwan Semiconductor Manufacturing Co Ltd

12/07/17 / #20170352652

Over-voltage protection circuit

A device is disclosed that includes a first transistor, a second transistor, and a first PODE device. The second transistor is electrically coupled to the first transistor. The first PODE device is adjacent to a drain/source region of the second transistor. A control end of the first PODE device is... Taiwan Semiconductor Manufacturing Co Ltd

12/07/17 / #20170352655

Semiconductor device structure and forming the same

A method includes forming a gate, a first dielectric layer, a first contact structure, and a second contact structure over a substrate. The first contact structure and the second contact structure are over a source region and a drain region respectively. The first dielectric layer surrounds the gate, the first... Taiwan Semiconductor Manufacturing Co Ltd

12/07/17 / #20170352656

Fin field effect transistor (finfet) device structure with different gate profile and forming the same

A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate and an isolation structure formed over the substrate. The FinFET device structure includes a first gate structure and a second gate structure formed over the fin structure. The first gate structure has... Taiwan Semiconductor Manufacturing Co Ltd

12/07/17 / #20170352660

Buried channel semiconductor device and manufacturing the same

A method for manufacturing a semiconductor device includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant... Taiwan Semiconductor Manufacturing Co Ltd

12/07/17 / #20170352670

Read-only memory (rom) device structure and forming the same

A read-only memory (ROM) structure is provided. The ROM device structure includes an active region formed over a substrate and a first group of word lines formed over the active region. The first group of word lines includes at least two word lines. The ROM device structure includes a second... Taiwan Semiconductor Manufacturing Co Ltd

12/07/17 / #20170352731

Thin poly field plate design

The present disclosure relates to a high voltage transistor device having a thin polysilicon film field plate, and an associated method of formation. In some embodiments, the high voltage transistor device has a gate electrode disposed between source and drain regions and separated from a substrate by a gate dielectric.... Taiwan Semiconductor Manufacturing Co Ltd

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12/07/17 / #20170352740

Semiconductor device structure with fin structure and forming the same

A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first fin structure and a second fin structure over the substrate. There is a gap between the first fin structure and the second fin structure. The semiconductor device structure includes an... Taiwan Semiconductor Manufacturing Co Ltd

12/07/17 / #20170352762

Methods for reducing contact resistance in semiconductor manufacturing process

A method of forming a semiconductor device includes forming a fin on a substrate and forming a source/drain region on the fin. The method further includes forming a doped metal silicide layer on the source/drain region and forming a super-saturated doped interface between the doped metal silicide and the source/drain... Taiwan Semiconductor Manufacturing Co Ltd








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