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Taiwan Semiconductor Manufacturing Company Ltd
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Taiwan Semiconductor Manufacturing Company Ltd patents


Recent patent applications related to Taiwan Semiconductor Manufacturing Company Ltd. Taiwan Semiconductor Manufacturing Company Ltd is listed as an Agent/Assignee. Note: Taiwan Semiconductor Manufacturing Company Ltd may have other listings under different names/spellings. We're not affiliated with Taiwan Semiconductor Manufacturing Company Ltd, we're just tracking patents.

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Semiconductor mems structure

The present disclosure provides a structure. The structure comprises a cavity enclosed by a first substrate and a second substrate opposite to the first substrate. The structure also includes a movable membrane in the cavity. Further, the structure includes a mesa in the cavity and the mesa is protruded from... Taiwan Semiconductor Manufacturing Company Ltd

Methods of forming an interconnect structure

A method of forming an interconnect structure is provided. The method includes forming a first dielectric layer, and forming an opening in the first dielectric layer. The method also includes applying a gas to the first dielectric layer adjacent to the opening, where after applying the gas to the first... Taiwan Semiconductor Manufacturing Company Ltd

Underfill control structures and method

A semiconductor device and method of reducing the risk of underbump metallization poisoning from the application of underfill material is provided. In an embodiment a spacer is located between a first underbump metallization and a second underbump metallization. When an underfill material is dispensed between the first underbump metallization and... Taiwan Semiconductor Manufacturing Company Ltd

Methods for reducing dual damascene distortion

An integrated circuit structure includes a first low-k dielectric layer having a first k value, and a second low-k dielectric layer having a second k value lower than the first k value. The second low-k dielectric layer is overlying the first low-k dielectric layer. A dual damascene structure includes a... Taiwan Semiconductor Manufacturing Company Ltd

Semiconductor device and manufacture

An integrated fan out package on package architecture is utilized along with a reference via in order to provide a reference voltage that extends through the InFO-POP architecture. If desired, the reference via may be exposed and then connected to a shield coating that can be used to shield the... Taiwan Semiconductor Manufacturing Company Ltd

Semiconductor devices and methods of manufacture thereof

Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a first semiconductor chip including a first substrate and a first conductive feature formed over the first substrate, and a second semiconductor chip bonded to the first semiconductor chip. The second semiconductor chip includes... Taiwan Semiconductor Manufacturing Company Ltd

Structure and finfet device with buried sige oxide

A semiconductor device includes a substrate and a fin feature over the substrate. The fin feature includes a first portion having a first semiconductor material and a second portion having a second semiconductor material over the first portion. The second semiconductor material is different from the first semiconductor material. The... Taiwan Semiconductor Manufacturing Company Ltd

Mosfets with multiple dislocation planes

A method includes forming a metal-oxide-semiconductor field-effect transistor (MOSFET). The Method includes performing an implantation to form a pre-amorphization implantation (PAI) region adjacent to a gate electrode of the MOSFET, forming a strained capping layer over the PAI region, and performing an annealing on the strained capping layer and the... Taiwan Semiconductor Manufacturing Company Ltd

Semiconductor device including integrated fan out antenna and forming the same

A semiconductor device includes an active device. The semiconductor device further includes a plurality of antenna grounds electrically connected to the active device. The semiconductor device further includes a plurality of patch antennas, wherein each patch antenna of the plurality of patch antennas is over a corresponding antenna ground of... Taiwan Semiconductor Manufacturing Company Ltd

Design method

A method performed by a processor, the method including preparing a netlist describing a first circuit including an active component, obtaining an original electrical characteristic of the active component, wherein an electrical characteristic of the active component is the original electrical characteristic in a condition that the active component has... Taiwan Semiconductor Manufacturing Company Ltd

Adaptive level shifter

A level shifter operating between a first power domain under a first supply voltage and a second power domain under a second supply voltage is provided. The level shifter includes a latch, formed by a first transistor and a second transistor, configured to store data and operate in the second... Taiwan Semiconductor Manufacturing Company Ltd

Circuit and writing to a bit cell

A circuit includes a bit line, a power node having a first power voltage level, a reference node having a reference voltage level, a pass gate coupled between the bit line and the power node, and a driver coupled between the bit line and the reference node. The pass gate... Taiwan Semiconductor Manufacturing Company Ltd

Method and structure for semiconductor device having gate spacer protection layer

A method of forming a semiconductor device includes providing a precursor. The precursor includes a substrate; a gate stack over the substrate; a first dielectric layer over the gate stack; a gate spacer on sidewalls of the gate stack and on sidewalls of the first dielectric layer; and source and... Taiwan Semiconductor Manufacturing Company Ltd

Solution for reducing poor contact in info package

A package includes a first package including a device die, a molding compound molding the device die therein, a through-via penetrating through the molding compound, and a first plurality of Redistribution Lines (RDLs) and a second plurality of RDLs on opposite sides of the molding compound. The through-via electrically couples... Taiwan Semiconductor Manufacturing Company Ltd

Standard cell layout, semiconductor device having engineering change order (eco) cells and method

A method of designing, for a semiconductor device, a layout which includes standard spare cells. Such a method includes: generating a set of possible values for a first pitch of standard spare cells based on a second pitch of strap lines of a metallization layer; selecting one member of the... Taiwan Semiconductor Manufacturing Company Ltd

Finfet device and fabricating same

An integrated circuit structure includes a semiconductor substrate, and isolation regions extending into the semiconductor substrate, wherein the isolation regions have opposite sidewalls facing each other. A fin structure includes a silicon fin higher than top surfaces of the isolation regions, a germanium-containing semiconductor region overlapped by the silicon fin,... Taiwan Semiconductor Manufacturing Company Ltd

Finfet with a semiconductor strip as a base

A method includes forming a first hard mask over a semiconductor substrate, etching the semiconductor substrate to form recesses, with a semiconductor strip located between two neighboring ones of the recesses, forming a second hard mask on sidewalls of the semiconductor strip, performing a first anisotropic etch on the second... Taiwan Semiconductor Manufacturing Company Ltd

Digtial circuit structures

In accordance with some embodiments of the present disclosure, a circuit structure is provided. The circuit structure comprises a first transistor, a second transistor, a storage node and a word-line. Each of the two transistors comprises a gate, a source and a drain. The storage node is connected to the... Taiwan Semiconductor Manufacturing Company Ltd

Method of manufacturing wafer level chip scale package

A method of manufacturing a semiconductor device includes receiving a die including a top surface, a die pad exposed from the top surface, and sacrificial layer covering the top surface and the die pad; disposing the die on a substrate, disposing a molding surrounding the die and covering the sacrificial... Taiwan Semiconductor Manufacturing Company Ltd

Mems device and manufacturing method thereof

A MEMS device includes a substrate, a supporter, a first back plate, a second back plate and a diaphragm. The substrate has a cavity. The supporter is over the substrate. The first back plate is over the cavity and fixed on the supporter. The second back plate is over the... Taiwan Semiconductor Manufacturing Company Ltd

Method to fabricate mask-pellicle system

A method for fabricating a pellicle assembly for a lithography process includes providing a carrier. A membrane layer is fabricated over the carrier. A pellicle frame is attached to the membrane layer. The carrier is then separated from the membrane layer using a release treatment process.... Taiwan Semiconductor Manufacturing Company Ltd

Multi-threshold voltage field effect transistor and manufacturing method thereof

The present disclosure provides an FET structure including a transistor of a first conductive type. The transistor includes a substrate having a region of a second conductive type, a channel between source and drain, and a gate over the channel. The channel includes dopants of the first conductive type. The... Taiwan Semiconductor Manufacturing Company Ltd

Esd testing structure, using same and forming same

An electrostatic discharge (ESD) testing structure includes a measurement device in a first die. The ESD testing structure further includes a fuse in a second die. The ESD testing structure further includes a plurality of bonds electrically connecting the first die to the second die, wherein a first bond of... Taiwan Semiconductor Manufacturing Company Ltd

Wafer processing method and apparatus

An apparatus for and a method of bonding a first substrate and a second substrate are provided. In an embodiment a first wafer chuck has a first curved surface and a second wafer chuck has a second curved surface. A first wafer is placed on the first wafer chuck and... Taiwan Semiconductor Manufacturing Company Ltd

Semiconductor device and manufacture

A semiconductor device has a top metal layer, a first passivation layer over the top metal layer, a first redistribution layer over the first passivation layer, a first polymer layer, and a first conductive via extending through the first polymer layer. The first polymer layer is in physical contact with... Taiwan Semiconductor Manufacturing Company Ltd

Discrete polymer in fan-out packages

A package includes a first molding material, a lower-level device die in the first molding material, a dielectric layer over the lower-level device die and the first molding material, and a plurality of redistribution lines extending into the first dielectric layer to electrically couple to the lower-level device die. The... Taiwan Semiconductor Manufacturing Company Ltd

Finfet cut-last process using oxide trench fill

A cut-last process for cutting fin segments of a FinFET structure on a substrate utilizes a two-step process. After the fins are formed, an oxide material is deposited in the trenches of the FinFET structure. The oxide material can be an STI oxide or a low-stress dummy gapfill material. A... Taiwan Semiconductor Manufacturing Company Ltd

Strained nanowire cmos device and forming

Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type... Taiwan Semiconductor Manufacturing Company Ltd

Metal gate process for finfet device improvement

In a method for manufacturing a semiconductor device, a substrate is provided. A dummy gate is formed on the substrate. A first dielectric layer is formed to peripherally enclose the dummy gate over the substrate. A second dielectric layer is formed to peripherally enclose the first dielectric layer over the... Taiwan Semiconductor Manufacturing Company Ltd

Finfet device

A fin-type field-effect transistor (FinFET) device includes a plurality of fins formed over a substrate. The semiconductor device further includes a dielectric layer filled in a space between each fin and over a first portion of the plurality of fins and a dielectric trench formed in the dielectric layer. The... Taiwan Semiconductor Manufacturing Company Ltd

Finfet with rounded source/drain profile

A method of forming a FinFET with a rounded source/drain profile comprises forming a fin in a substrate, etching a source/drain recess in the fin, forming a plurality of source/drain layers in the source/drain recess; and etching at least one of the plurality of source/drain layers. The source/drain layers may... Taiwan Semiconductor Manufacturing Company Ltd

Multi-gate device and fabrication thereof

A method of semiconductor device fabrication is described that includes forming a fin extending from a substrate and having a source/drain region and a channel region. The fin includes a first epitaxial layer having a first composition and a second epitaxial layer on the first epitaxial layer, the second epitaxial... Taiwan Semiconductor Manufacturing Company Ltd

Memory cell having resistance variable film and making the same

A manufacture includes a first electrode having an upper surface and a side surface, a resistance variable film over the first electrode, and a second electrode over the resistance variable film. The resistance variable film extends along the upper surface and the side surface of the first electrode. The second... Taiwan Semiconductor Manufacturing Company Ltd

Semiconductor structure and manufacuting the same

The present disclosure provides a semiconductor structure. The structure includes a first substrate; a first dielectric layer having a first surface in proximity to the first substrate and a second surface away from the first substrate; a first interconnect penetrating the first surface of the first dielectric layer; and a... Taiwan Semiconductor Manufacturing Company Ltd

Manufacuting semiconductor structure

The present disclosure provides a semiconductor structure. The structure includes a first substrate; a first dielectric layer having a first surface in proximity to the first substrate and a second surface away from the first substrate; a first interconnect penetrating the first surface of the first dielectric layer; and a... Taiwan Semiconductor Manufacturing Company Ltd

03/22/18 / #20180082954

Semiconductor package

The present disclosure provides a manufacturing method of a semiconductor packaging, including forming a redistribution layer (RDL) on a carrier, defining an active portion and a dummy portion of the RDL, and placing a semiconductor die over the dummy portion of the RDL. The present disclosure also provides a manufacturing... Taiwan Semiconductor Manufacturing Company Ltd

03/22/18 / #20180082970

Semiconductor device

A semiconductor device includes a substrate including a surface, a plurality of pads disposing on the surface of the substrate, the plurality of pads includes a non-solder mask defined (NSMD) pad and a solder mask defined (SMD) pad, and the NSMD pad is arranged at a predetermined location. Further, a... Taiwan Semiconductor Manufacturing Company Ltd

03/22/18 / #20180082883

Fets and methods of forming fets

An embodiment is a structure including a first fin over a substrate, a second fin over the substrate, the second fin being adjacent the first fin, an isolation region surrounding the first fin and the second fin, a gate structure along sidewalls and over upper surfaces of the first fin... Taiwan Semiconductor Manufacturing Company Ltd

03/22/18 / #20180082917

Info structure with copper pillar having reversed profile

A method includes forming a first polymer layer to cover a metal pad of a wafer, and patterning the first polymer layer to form a first opening. A first sidewall of the first polymer layer exposed to the first opening has a first tilt angle where the first sidewall is... Taiwan Semiconductor Manufacturing Company Ltd

03/22/18 / #20180082964

Semiconductor package and forming the same

An embodiment is a method including forming a first passive device in a first wafer, forming a first dielectric layer over a first side of the first wafer, forming a first plurality of bond pads in the first dielectric layer, planarizing the first dielectric layer and the first plurality of... Taiwan Semiconductor Manufacturing Company Ltd

03/22/18 / #20180082966

Package with passive devices and forming the same

An embodiment is a device comprising a substrate, a metal pad over the substrate, and a passivation layer comprising a portion over the metal pad. The device further comprises a metal pillar over and electrically coupled to the metal pad, and a passive device comprising a first portion at a... Taiwan Semiconductor Manufacturing Company Ltd

03/22/18 / #20180082978

Integrated fan-out package including voltage regulators and methods forming same

A method includes adhering a voltage regulator die over a carrier through a die-attach film, with the die-attach film being in the voltage regulator die and encircles metal pillars of the voltage regulator die, encapsulating the voltage regulator die in an encapsulating material, and planarizing the encapsulating material. A back... Taiwan Semiconductor Manufacturing Company Ltd

03/22/18 / #20180082988

Package structure and forming the same

An embodiment is a structure including a first package including a first die, and a molding compound at least laterally encapsulating the first die, a second package bonded to the first package with a first set of conductive connectors, the second package comprising a second die, and an underfill between... Taiwan Semiconductor Manufacturing Company Ltd

03/22/18 / #20180083103

Finfets with strained well regions

A device includes a substrate and insulation regions over a portion of the substrate. A first semiconductor region is between the insulation regions and having a first conduction band. A second semiconductor region is over and adjoining the first semiconductor region, wherein the second semiconductor region includes an upper portion... Taiwan Semiconductor Manufacturing Company Ltd

03/22/18 / #20180083188

Resistance variable memory structure

A semiconductor structure includes a resistance variable memory structure. The semiconductor structure also includes a dielectric layer. The resistance variable memory structure is over the dielectric layer. The resistance variable memory structure includes a first electrode disposed over the dielectric layer. The first electrode has a sidewall surface. A resistance... Taiwan Semiconductor Manufacturing Company Ltd

03/22/18 / #20180083416

Apparatus and forming chip package with waveguide for light coupling

An apparatus and method of forming a chip package with a waveguide for light coupling is disclosed. The method includes depositing an adhesive layer over a carrier. The method further includes depositing a laser diode (LD) die having a laser emitting area onto the adhesive layer and depositing a molding... Taiwan Semiconductor Manufacturing Company Ltd

03/22/18 / #20180083605

Clock generation circuit and charge pumping system

A clock generation circuit includes: a two-phase clock generation circuit configured to generate a first phase clock signal and a second phase clock signal based correspondingly on a non-inverted clock signal and an inverted clock signal, the first phase clock signal and the second phase clock signal exhibiting non-overlapping logical... Taiwan Semiconductor Manufacturing Company Ltd

03/15/18 / #20180075181

Method and system for pin layout

A method performed by at least one processor includes selecting a pin in a cell, determining a type of the pin, assigning a first pin access and a second pin access of the pin to a same patterning group at different patterning tracks when the pin is determined to be... Taiwan Semiconductor Manufacturing Company Ltd

03/15/18 / #20180076129

Semiconductor structure and manufacturing method thereof

A semiconductor structure includes a substrate; a die disposed over the substrate, and including a die pad, a conductive via disposed over the die pad and a dielectric material surrounding the conductive via; a molding disposed over the substrate and surrounding the die; a lower dielectric layer disposed nearer the... Taiwan Semiconductor Manufacturing Company Ltd

03/15/18 / #20180076276

Semiconductor structure and manufacturing the same

The present disclosure provides a semiconductor structure, comprising a substrate, dielectric layers and conductive layers. A first dielectric layer is disposed on a bottom surface and sidewall surfaces of a filled trench of the substrate. A first conductive layer is disposed on the first dielectric layer and has a first... Taiwan Semiconductor Manufacturing Company Ltd

03/15/18 / #20180076322

Semiconductor structure and associated fabricating method

A semiconductor structure is disclosed. The semiconductor structure includes: a substrate of a first conductivity; a first region of the first conductivity formed in the substrate; a second region of the first conductivity formed in the first region, wherein the second region has a higher doping density than the first... Taiwan Semiconductor Manufacturing Company Ltd

03/15/18 / #20180073144

Control system for plasma chamber having controllable valve and using the same

A control system for a plasma treatment apparatus includes a wafer treatment device. The wafer treatment device includes a vapor chamber and an upper electrode assembly. The upper electrode assembly includes a gas distribution plate having a plurality of holes. The upper electrode assembly includes an upper electrode having at... Taiwan Semiconductor Manufacturing Company Ltd

03/15/18 / #20180075182

Integrated circuit and forming an integrated circuit

An IC structure includes a cell, a first rail and a second rail. The cell includes a first and a second active region and a first gate structure. The first and second active region extend in a first direction and is located at a first level. The second active region... Taiwan Semiconductor Manufacturing Company Ltd

03/15/18 / #20180076097

Nonplanar device and strain-generating channel dielectric

Various methods are disclosed herein for fabricating non-planar circuit devices having strain-producing features. An exemplary method includes forming a fin structure that includes a first portion that includes a first semiconductor material and a second portion that includes a second semiconductor material that is different than the first semiconductor material.... Taiwan Semiconductor Manufacturing Company Ltd

03/15/18 / #20180076132

Self-aligned interconnection structure and method

The present disclosure provides a method that includes providing a substrate having a first dielectric material layer and first conductive features that are laterally separated from each other by segments of the first dielectric material layer; depositing a first etch stop layer on the first dielectric material layer and the... Taiwan Semiconductor Manufacturing Company Ltd

03/15/18 / #20180076135

Inductor system and method

A system and method for providing and manufacturing an inductor is provided. In an embodiment similar masks are reutilized to form differently sized inductors. For example, a two turn inductor and a three turn inductor may share masks for interconnects and coils, while only masks necessary for connections between the... Taiwan Semiconductor Manufacturing Company Ltd

03/15/18 / #20180076144

Contact structure and forming

Contact structures and methods of forming contacts structures are contemplated by this disclosure. A structure includes a dielectric layer over a substrate, an adhesion layer, a silicide, a barrier layer, and a conductive material. The dielectric layer has an opening to a surface of the substrate. The adhesion layer is... Taiwan Semiconductor Manufacturing Company Ltd

03/15/18 / #20180076159

Pad design for reliability enhancement in packages

A package includes a corner, a device die, a molding material molding the device die therein, and a plurality of bonding features. The plurality of bonding features includes a corner bonding feature at the corner, wherein the corner bonding feature is elongated. The plurality of bonding features further includes an... Taiwan Semiconductor Manufacturing Company Ltd

03/15/18 / #20180076175

Redistribution layers in semiconductor packages and methods of forming same

An embodiment package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, and a conductive line electrically connecting a first conductive via to a second conductive via. The conductive line includes a first segment over the first integrated circuit die and having a first lengthwise... Taiwan Semiconductor Manufacturing Company Ltd

03/15/18 / #20180076184

Semiconductor packages having dummy connectors and methods of forming same

An embodiment package includes a first package. The first package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, and redistribution layers over the encapsulant and the first integrated circuit die. The package also includes a second package bonded to the first package by a... Taiwan Semiconductor Manufacturing Company Ltd

03/15/18 / #20180076190

Semiconductor device having engineering change order (eco) cells and using

A semiconductor device includes an array of Engineering Change Order (ECO) cells. Each of the ECO cells in the array includes a first metal pattern and a second metal pattern. Each of the ECO cells in the array further includes a plurality of active area patterns isolated from each other... Taiwan Semiconductor Manufacturing Company Ltd

03/08/18 / #20180065841

Semiconductor structure with cavity spacing monitoring functions

The present disclosure provides a semiconductor structure. The semiconductor structure includes a cavity disposed in a substrate and enclosed by a first surface and a second surface opposite to the first surface. The semiconductor structure also includes a first electrode pair having a first electrode on the first surface and... Taiwan Semiconductor Manufacturing Company Ltd

03/08/18 / #20180068949

Through via structure, semiconductor device and manufacturing method thereof

A through via structure includes a semiconductor substrate, an underlying insulation layer, a conductive via and a sidewall insulation layer. The underlying insulation layer is over the semiconductor substrate. The conductive via is through the semiconductor substrate and the underlying insulation layer. The sidewall insulation layer is between the semiconductor... Taiwan Semiconductor Manufacturing Company Ltd

03/08/18 / #20180068978

Semiconductor package structure and manufacturing the same

A semiconductor package structure includes a redistribution (RDL) layer, a first chip, at least one second chip, an encapsulant and a third chip. The redistribution layer has a first surface and a second surface opposite to each other. The first chip is over the first surface of the redistribution layer... Taiwan Semiconductor Manufacturing Company Ltd

03/08/18 / #20180069134

Jfet structure and manufacturing the same

The present disclosure provides a transistor structure, including a self-aligned source-drain structure surrounded by an insulating structure and a gate of a second conductive type separated from the source and the drain by the insulating structure. The self-aligned source-drain structure includes a source and a drain of a first conductive... Taiwan Semiconductor Manufacturing Company Ltd

Patent Packs
03/08/18 / #20180069807

Network-on-chip system and a generating the same

A network-on-chip (NoC) system includes a default communication path between a master device and a slave device, and a backup communication path between the master device and the slave device. The default communication path is configured to work in a normal operation state of the chip. The backup communication path... Taiwan Semiconductor Manufacturing Company Ltd

03/08/18 / #20180068046

Multiple patterning method, system for implementing the method and layout formed

A method of designing a layout includes assigning a first color group to a plurality of first routing tracks. The method includes assigning a second color group to a plurality of second routing tracks. A first routing track is between adjacent second routing tracks. The method includes assigning a color... Taiwan Semiconductor Manufacturing Company Ltd

03/08/18 / #20180068050

System for and manufacturing a layout design of an integrated circuit

A method of forming a layout design for fabricating an integrated circuit is disclosed. The method includes generating a first layout of the integrated circuit based on design criteria, generating a standard cell layout of the integrated circuit, generating a via color layout of the integrated circuit based on the... Taiwan Semiconductor Manufacturing Company Ltd

03/08/18 / #20180068851

Semiconductor devices comprising 2d-materials and methods of manufacture thereof

Semiconductor devices comprising two-dimensional (2D) materials and methods of manufacture thereof are described. In an embodiment, a method for manufacturing a semiconductor device comprising 2D materials may include: epitaxially forming a first 2D material layer on a substrate; and epitaxially forming a second 2D material layer over the first 2D... Taiwan Semiconductor Manufacturing Company Ltd

03/08/18 / #20180068900

Method and structure for finfet isolation

A semiconductor device includes a substrate; first and second fins over the substrate and extending lengthwise generally along a first direction; first and second gate stacks over the substrate and the first and second fins respectively; and a first isolation structure disposed between the first and second fins and extending... Taiwan Semiconductor Manufacturing Company Ltd

03/08/18 / #20180068960

Method of making package assembly including stress relief structures

A method of making a semiconductor package structure includes bonding a plurality of dies to a substrate, wherein a first die of the plurality of dies is larger than a second die of the plurality of dies. The method further includes adhering a first stress relief structure to the substrate... Taiwan Semiconductor Manufacturing Company Ltd

03/08/18 / #20180068965

Conductive pad structure for hybrid bonding and methods of forming same

A representative device includes a patterned opening through a layer at a surface of a device die. A liner is disposed on sidewalls of the opening and the device die is patterned to extend the opening further into the device die. After patterning, the liner is removed. A conductive pad... Taiwan Semiconductor Manufacturing Company Ltd

03/08/18 / #20180068968

Post-passivation interconnect structure and methods thereof

A method includes providing a die including a substrate and a bonding pad over the substrate, forming a connective layer over the die, and forming the landing pad over the connective layer. The forming the connective layer includes depositing a dielectric layer of a dielectric material over the die and... Taiwan Semiconductor Manufacturing Company Ltd

03/08/18 / #20180068979

Multi-stack package-on-package structures

Multi-stack package-on-package structures are disclosed. In a method, a first stacked semiconductor device is formed on a first carrier wafer. The first stacked semiconductor device is singulated. The first stacked semiconductor device is adhered to a second carrier wafer. A second semiconductor device is attached on the first stacked semiconductor... Taiwan Semiconductor Manufacturing Company Ltd

03/08/18 / #20180068985

Package-on-package structure and method

A method includes attaching a first semiconductor package on a carrier, wherein the first semiconductor package comprises a plurality of stacked semiconductor dies and a plurality of contact pads, depositing a first molding compound layer over the carrier, wherein the first semiconductor package is embedded in the first molding compound... Taiwan Semiconductor Manufacturing Company Ltd

03/08/18 / #20180068999

Leakage current suppression methods and related structures

A method and structure for suppressing band-to-band tunneling current in a semiconductor device having a high-mobility channel material includes forming a channel region adjacent to and in contact with one of a source region and a drain region. A tunnel barrier layer may be formed such that the tunnel barrier... Taiwan Semiconductor Manufacturing Company Ltd

03/08/18 / #20180069011

Semiconductor devices and methods of manufacture thereof

A method of forming an SRAM cell includes forming a first vertical pull-down transistor, a second vertical pull-down transistor, a first vertical pass-gate transistor, and a second vertical pass-gate transistor over a semiconductor substrate. The method includes forming a first conductive trace over a top surface of the first vertical... Taiwan Semiconductor Manufacturing Company Ltd

03/08/18 / #20180069012

Method for manufacturing static random access memory device

In a method of manufacturing an SRAM device, an insulating layer is formed over a substrate. First dummy patterns are formed over the insulating layer. Sidewall spacer layers, as second dummy patterns, are formed on sidewalls of the first dummy patterns. The first dummy patterns are removed, thereby leaving the... Taiwan Semiconductor Manufacturing Company Ltd

03/08/18 / #20180069094

Method of forming the gate electrode of field effect transistor

A method of fabricating a semiconductor device includes depositing a contact etch stop layer (CESL) over a dummy gate electrode, a source/drain (S/D) region and an isolation feature. The method further includes performing a first CMP to expose the dummy gate electrode. The method further includes removing an upper portion... Taiwan Semiconductor Manufacturing Company Ltd

03/08/18 / #20180069096

Vertical tunneling field-effect transistor cell and fabricating the same

A tunneling field-effect transistor (TFET) device is disclosed. A protrusion structure is disposed over the substrate and protrudes out of the plane of substrate. Isolation features are formed on the substrate. A drain region is disposed over the substrate adjacent to the protrusion structure and extends to a bottom portion... Taiwan Semiconductor Manufacturing Company Ltd

Patent Packs
03/08/18 / #20180069102

Fin field effect transistor and forming the same

A fin field effect transistor (FinFET) includes a substrate and a fin having a first height over a surface of the substrate. The fin includes a first portion comprising a first sidewall, wherein the first sidewall is angled with respect to the surface of the substrate at a first angle.... Taiwan Semiconductor Manufacturing Company Ltd

03/08/18 / #20180069103

Reduction of fin loss in the formation of finfets

A method includes forming a dummy gate stack on a top surface and a sidewall of a middle portion of a semiconductor fin, and forming a spacer layer. The spacer layer includes a first portion on a sidewall of the dummy gate stack, and a second portion on a top... Taiwan Semiconductor Manufacturing Company Ltd

03/08/18 / #20180069123

Mos devices having epitaxy regions with reduced facets

An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage.... Taiwan Semiconductor Manufacturing Company Ltd

03/01/18 / #20180061798

Semiconductor device and manufacturing method thereof

A semiconductor device includes a first carrier including a first pad, a second carrier including a second pad disposed opposite to the first pad, a joint coupled with and standing on the first pad, a joint encapsulating the post and bonding the first pad with the second pad, a first... Taiwan Semiconductor Manufacturing Company Ltd

03/01/18 / #20180062670

Memory system having flexible ecc scheme and the same

A memory system is disclosed. The memory system includes: a memory; a first ECC circuit used to encode information bits of a first length into a codeword of a first ECC scheme, and to decode a codeword of the first ECC scheme read from the memory into decoded information bits... Taiwan Semiconductor Manufacturing Company Ltd

03/01/18 / #20180056548

Vacuum carrier module, using and process of making the same

A vacuum carrier module includes a substrate having at least one hole and an edge region. There is at least one support on a top surface of the substrate. Further, a gel film is adhered to the edge region of the substrate. The at least one hole fluidly connects a... Taiwan Semiconductor Manufacturing Company Ltd

03/01/18 / #20180061668

Integrated circuit package pad and methods of forming

A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending... Taiwan Semiconductor Manufacturing Company Ltd

03/01/18 / #20180061669

Semiconductor device and method

A method of manufacturing a semiconductor device includes placing a polymer raw material mixture over a substrate. The polymer raw material may include a polymer precursor, a photosensitizer, and an additive. The polymer raw material mixture is exposed to radiation to form a dielectric layer and cured at a temperature... Taiwan Semiconductor Manufacturing Company Ltd

03/01/18 / #20180061715

Method of forming source/drain contact

Methods for fabricating semiconductor devices are disclosed. An exemplary method includes forming first spacers along sidewalls of a gate structure that is disposed over a substrate and between source/drain features. A first dielectric layer is formed over the substrate and recessed to expose upper portions of the first spacers. A... Taiwan Semiconductor Manufacturing Company Ltd

03/01/18 / #20180061717

Flowable cvd quality control in sti loop

A method for semiconductor processing includes forming a first dielectric layer comprising an N-type dopant over a first plurality of fins extending above a first region of a substrate, forming a second dielectric layer comprising a P-type dopant over the first plurality of fins and a second plurality of fins... Taiwan Semiconductor Manufacturing Company Ltd

03/01/18 / #20180061783

Lid structure for a semiconductor device package and forming the same

A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a die structure formed over the substrate. The semiconductor device structure also includes a lid structure formed over the die structure. The lid structure includes a top portion with a... Taiwan Semiconductor Manufacturing Company Ltd

03/01/18 / #20180061818

Semiconductor device and manufacturing

A semiconductor device includes a first chip, a dielectric layer over the first chip, and a second chip over the dielectric layer. A conductive layer is embedded in the dielectric layer and is electrically coupled to the first chip and the second chip. The second chip includes an optical component.... Taiwan Semiconductor Manufacturing Company Ltd

03/01/18 / #20180061819

Methods of manufacturing semiconductor devices

A method of manufacturing a semiconductor device includes forming a first masking layer and second masking layer over a substrate. The first masking layer includes an opening over an active area and a spacer in the substrate, and the second masking layer blocks a portion of the opening in the... Taiwan Semiconductor Manufacturing Company Ltd

03/01/18 / #20180061841

Memory metal scheme

A method of fabricating a memory array includes designing first layout sections in a row direction, each first layout section including first and second control lines in a first metal layer, and an upper conductive line in a third metal layer. A lower conductive line in a second metal layer... Taiwan Semiconductor Manufacturing Company Ltd

03/01/18 / #20180061880

Structure and 3d image sensor

An image sensor structure that includes a first semiconductor substrate having a plurality of imaging sensors; a first interconnect structure formed on the first semiconductor substrate; a second semiconductor substrate having a logic circuit; a second interconnect structure formed on the second semiconductor substrate, wherein the first and the second... Taiwan Semiconductor Manufacturing Company Ltd

03/01/18 / #20180061930

Semiconductor device and forming same

A system and method for forming a resistor system is provided. An embodiment comprises a resistor formed in a U-shape. The resistor may comprise multiple layers of conductive materials, with a dielectric layer filling the remainder of the U-shape. The resistor may be integrated with a dual metal gate manufacturing... Taiwan Semiconductor Manufacturing Company Ltd

03/01/18 / #20180061959

Purging deposition tools to reduce oxygen and moisture in wafers

A method includes placing a wafer in a wafer holder, placing the wafer holder on a loadport of a deposition tool, connecting the wafer holder to a front-end interface unit of the deposition tool, purging the front-end interface unit with nitrogen, and depositing a metal layer on the wafer in... Taiwan Semiconductor Manufacturing Company Ltd

03/01/18 / #20180061986

Structure and integrated circuit

The present disclosure provides many different embodiments of an IC device. The IC device includes a gate stack disposed over a surface of a substrate and a spacer disposed along a sidewall of the gate stack. The spacer has a tapered edge that faces the surface of the substrate while... Taiwan Semiconductor Manufacturing Company Ltd

03/01/18 / #20180061988

Fets and methods for forming the same

FETs and methods for forming FETs are disclosed. A structure comprises a substrate, a gate dielectric and a gate electrode. The substrate comprises a fin, and the fin comprises an epitaxial channel region. The epitaxial channel has a major surface portion of an exterior surface. The major surface portion comprising... Taiwan Semiconductor Manufacturing Company Ltd

03/01/18 / #20180062074

Resistance variable memory structure and forming the same

A memory structure includes a first dielectric layer, having a first top surface, over a conductive structure. A first opening in the first dielectric layer exposes an area of the conductive structure, and has an interior sidewall. A first electrode structure, having a first portion and a second portion, is... Taiwan Semiconductor Manufacturing Company Ltd

02/22/18 / #20180053756

Semiconductor device structure

A semiconductor device structure includes a first chip including a plurality of dielectric layers and a multi-layered metal structure embedded in the plurality of dielectric layer, a second chip bonded to the first chip to generate a bonding interface and including a metal structure, a first via structure extending through... Taiwan Semiconductor Manufacturing Company Ltd

02/22/18 / #20180053825

Finfet structure and manufacturing thereof

Present disclosure provides a FinFET structure, including a fin and a gate surrounding a first portion of the fin. A dopant concentration in the first portion of the fin is lower than about 1E17/cm3. The FinFET structure further includes an insulating layer surrounding a second portion of the fin. The... Taiwan Semiconductor Manufacturing Company Ltd

02/22/18 / #20180053839

Semiconductor structure, hemt structure and forming the same

A semiconductor structure includes: a channel layer; an active layer over the channel layer, wherein the active layer is configured to form a two-dimensional electron gas (2 DEG) to be formed in the channel layer along an interface between the channel layer and the active layer; a gate electrode over... Taiwan Semiconductor Manufacturing Company Ltd

02/22/18 / #20180053697

Semiconductor structure and forming the same

A semiconductor structure with a stop layer for planarization process therein and a method for forming the same is disclosed. The method includes the steps of: forming a trench in a substrate and between active areas; filling the trench with isolation layer; doping the isolation layer with an element to... Taiwan Semiconductor Manufacturing Company Ltd

02/22/18 / #20180053537

Memory macro and operating the same

A memory macro includes a first set of memory cells, a second set of memory cells, a third set of memory cells, a set of retention circuits and a set of conductive lines. The second set of memory cells arranged in a first row arranged in a second direction. The... Taiwan Semiconductor Manufacturing Company Ltd

02/22/18 / #20180053730

Semiconductor packages and methods of forming the same

Semiconductor packages and methods of forming the same are disclosed. Embodiments include forming a first recess in a first substrate, wherein a first area of an opening of the first recess is larger than a second area of a bottom of the first recess. The embodiments also include forming a... Taiwan Semiconductor Manufacturing Company Ltd

02/22/18 / #20180053746

Semiconductor packages with thermal-electrical-mechanical chips and methods of forming the same

In some embodiments, a device includes a thermal-electrical-mechanical (TEM) chip having a functional circuit, a first die attached to a first side of the TEM chip, and a first via on the first side of the TEM chip and adjacent to the first die, the first via being electrically coupled... Taiwan Semiconductor Manufacturing Company Ltd

02/22/18 / #20180053748

Buffer layer(s) on a stacked structure having a via

A structure includes first and second substrates, first and second stress buffer layers, and a post-passivation interconnect (PPI) structure. The first and second substrates include first and second semiconductor substrates and first and second interconnect structures on the first and second semiconductor substrates, respectively. The second interconnect structure is on... Taiwan Semiconductor Manufacturing Company Ltd

02/22/18 / #20180053763

Field effect transistor contact with reduced contact resistance

The present disclosure provides a method that includes providing a semiconductor substrate having a first region and a second region; forming a first gate within the first region and a second gate within the second region on the semiconductor substrate; forming first source/drain features of a first semiconductor material with... Taiwan Semiconductor Manufacturing Company Ltd

02/22/18 / #20180053824

Fin field effect transistor (finfet) device having position-dependent heat generation and making the same

A semiconductor apparatus including a substrate having a substrate major surface, a dielectric material on the substrate major surface and having a second major surface distanced from the substrate major surface, and a plurality of fins extending from the substrate major surface through the dielectric material where the plurality of... Taiwan Semiconductor Manufacturing Company Ltd

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02/22/18 / #20180053852

Reacted conductive gate electrodes and methods of making the same

A semiconductor device and a method for fabricating a semiconductor device involve a semiconductor layer that includes a first material and a second material. The first and second materials can be silicon and germanium. A contact of the device has a portion proximal to the semiconductor layer and a portion... Taiwan Semiconductor Manufacturing Company Ltd

02/22/18 / #20180053855

Semiconductor device and manufacturing method thereof

A semiconductor device includes a substrate, at least two gate spacers, and a gate stack. The substrate has at least one semiconductor fin. The gate spacers are disposed on the substrate. At least one of the gate spacers has a sidewall facing to another of the gate spacers. The gate... Taiwan Semiconductor Manufacturing Company Ltd








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