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Taiwan Semiconductor Manufacturing Company Ltd
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Taiwan Semiconductor Manufacturing Company Ltd_20100128
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Taiwan Semiconductor Manufacturing Company Ltd patents


Recent patent applications related to Taiwan Semiconductor Manufacturing Company Ltd. Taiwan Semiconductor Manufacturing Company Ltd is listed as an Agent/Assignee. Note: Taiwan Semiconductor Manufacturing Company Ltd may have other listings under different names/spellings. We're not affiliated with Taiwan Semiconductor Manufacturing Company Ltd, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "T" | Taiwan Semiconductor Manufacturing Company Ltd-related inventors


 new patent  Composition for chemical mechanical polishing and reducing chemical mechanical polishing surface defects

The present disclosure provides chemical mechanical polishing (CMP) slurry, including an abrasive, a chelator, an oxidizing agent, and a surface modificator. The surface modificator is configured to modify a surface from hydrophobic to hydrophilic. The present disclosure also provides a method for reducing chemical mechanical polishing (CMP) surface defects. The... Taiwan Semiconductor Manufacturing Company Ltd

 new patent  Integrated circuit design method and associated non-transitory computer-readable medium

An integrated circuit (IC) design method is disclosed. The method includes: using a computer to perform synthesis upon a register transfer level (RTL) IC design to generate a gate level netlist; performing place and route (P&R) upon the gate level netlist to generate a layout; determining a sink current distribution... Taiwan Semiconductor Manufacturing Company Ltd

 new patent  Semiconductor structure and manufacturing method thereof

The present disclosure provides a semiconductor structure having a semiconductor layer; a gate with a conductive portion and a sidewall spacer; an interlayer dielectric (ILD) surrounding the sidewall spacer; and a nitrogen-containing protection layer, positioning at least on the top surface of the conductive portion of the gate. A top... Taiwan Semiconductor Manufacturing Company Ltd

 new patent  Defect inspection and repairing method and associated system and non-transitory computer readable medium

A defect inspection and repairing method is disclosed. The method includes: providing a wafer including a semiconductor chip disposed on a surface of the wafer; disposing a layer over the semiconductor chip; obtaining a scanned image of the disposed layer; performing an image analysis upon the scanned image to obtain... Taiwan Semiconductor Manufacturing Company Ltd

 new patent  Apparatus and a forming a particle shield

An apparatus for generating at least one particle shield in photolithography includes a first component and a second component. The first component and the second component are operable to form a first particle shield of the at least one particle shield for blocking particles from contacting a proximate surface of... Taiwan Semiconductor Manufacturing Company Ltd

 new patent  Self-aligned insulated film for high-k metal gate device

An integrated circuit includes a semiconductor substrate, a gate dielectric over the substrate, and a metal gate structure over the semiconductor substrate and the gate dielectric. The metal gate structure includes a first metal material. The integrated circuit further includes a seal formed on sidewalls of the metal gate structure.... Taiwan Semiconductor Manufacturing Company Ltd

 new patent  Method of manufacturing a semiconductor device

A system and method for a semiconductor wafer carrier is disclosed. An embodiment comprises a semiconductor wafer carrier wherein conductive dopants are implanted into the carrier in order to amplify the coulombic forces between an electrostatic chuck and the carrier to compensate for reduced forces that result from thinner semiconductor... Taiwan Semiconductor Manufacturing Company Ltd

 new patent  Package-on-package structure

A method comprises forming a plurality of interconnect structures including a dielectric layer, a metal line and a redistribution line over a carrier, attaching a semiconductor die on a first side of the plurality of interconnect structures, forming an underfill layer between the semiconductor die and the plurality of interconnect... Taiwan Semiconductor Manufacturing Company Ltd

 new patent  Calibration kits for rf passive devices

A method includes measuring a first calibration kit in a wafer to obtain a first performance data. The wafer includes a substrate, and a plurality of dielectric layers over the substrate. The first calibration kit includes a first passive device over the plurality of dielectric layers, wherein substantially no metal... Taiwan Semiconductor Manufacturing Company Ltd

 new patent  Semiconductor device and manufacture

A semiconductor device and method that utilize a surface device are provided. In an embodiment a fuse line comprises an underbump metallization which has two separate, electrically isolated parts. The two parts are bridged by an external connector, such as a solder ball in order to electrically connect the surface... Taiwan Semiconductor Manufacturing Company Ltd

 new patent  Method and structure of three-dimensional chip stacking

A method includes placing a first plurality of device dies over a first carrier, with the first plurality of device dies and the first carrier in combination forming a first composite wafer. The first composite wafer is bonded to a second wafer, and the first plurality of device dies is... Taiwan Semiconductor Manufacturing Company Ltd

 new patent  Inp-based transistor fabrication

Methods of forming structures that include InP-based materials, such as a transistor operating as an inversion-type, enhancement-mode device are disclosed. A dielectric layer may be deposited by ALD over a semiconductor layer including In and P. A channel layer may be formed above a buffer layer having a lattice constant... Taiwan Semiconductor Manufacturing Company Ltd

 new patent  Finfet device including a stem region of a fin element

A finFET device having a substrate and a fin disposed on the substrate. The fin includes a passive region, a stem region overlying the passive region, and an active region overlying the stem region. The stem region has a first width and the active region has a second width. The... Taiwan Semiconductor Manufacturing Company Ltd

Semiconductor structure and forming the same

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a substrate; a fin structure protruding from the substrate, the fin structure extending along a first direction; isolation features disposed on both sides of the fin structure; a gate structure over the fin structure... Taiwan Semiconductor Manufacturing Company Ltd

Method of forming conductive lines in circuits

A method of forming conductive lines in a circuit is disclosed. The method includes arranging a plurality of signal traces in a first set of signal traces and a second set of signal traces, fabricating, using a first mask, a first conductive line for a first signal trace of the... Taiwan Semiconductor Manufacturing Company Ltd

Dual-port sram connection structure

The present disclosure provides a static random access memory (SRAM) cell. The SRAM cell includes first and second inverters cross-coupled for data storage, each inverter including at least one pull-up device and at least two pull-down devices; at least four pass gate devices configured with the two cross-coupled inverters; at... Taiwan Semiconductor Manufacturing Company Ltd

Lithography using high selectivity spacers for pitch reduction

A method embodiment for patterning a semiconductor device includes patterning a dummy layer over a hard mask to form one or more dummy lines. A sidewall aligned spacer is conformably formed over the one or more dummy lines and the hard mask. A first reverse material layer is formed over... Taiwan Semiconductor Manufacturing Company Ltd

Finfet device

The present disclosure provides many different embodiments of a FinFET device that provide one or more improvements over the prior art. In one embodiment, a FinFET includes a semiconductor substrate and a plurality of fins having a first height and a plurality of fin having a second height on the... Taiwan Semiconductor Manufacturing Company Ltd

Passivation structure and making the same

A passivation structure includes a bottom dielectric layer. The passivation structure further includes a doped dielectric layer over the bottom dielectric layer. The doped dielectric layer includes a first doped layer and a second doped layer. The passivation structure further includes a top dielectric layer over the doped dielectric layer.... Taiwan Semiconductor Manufacturing Company Ltd

Self-alignment for redistribution layer

An apparatus comprising a substrate with multiple electronic devices. An interconnect structure formed on a first side of the substrate interconnects the electronic devices. Dummy TSVs each extend through the substrate and form an alignment mark on a second side of the substrate. Functional TSVs each extend through the substrate... Taiwan Semiconductor Manufacturing Company Ltd

Semiconductor devices, methods of manufacture thereof, and semiconductor device packages

Semiconductor devices, methods of manufacture thereof, and semiconductor device packages are disclosed. In one embodiment, a semiconductor device includes an insulating material layer having openings on a surface of a substrate. One or more insertion bumps are disposed over the insulating material layer. The semiconductor device includes signal bumps having... Taiwan Semiconductor Manufacturing Company Ltd

Method and packaging pad structure

Methods and apparatus are disclosed for manufacturing metal contacts under ground-up contact pads within a device. A device may comprise a bottom metal layer with a bottom metal contact, a top metal layer with a top metal contact, and a plurality of middle metal layers. Any given metal layer of... Taiwan Semiconductor Manufacturing Company Ltd

Chip-on-wafer package and forming same

A method includes bonding a die to a substrate, where the substrate has a first redistribution structure, the die has a second redistribution structure, and the first redistribution structure is bonded to the second redistribution structure. A first isolation material is formed over the substrate and around the die. A... Taiwan Semiconductor Manufacturing Company Ltd

3dic interconnect apparatus and method

An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. A multi-layer dielectric film is formed along sidewalls of the first opening. One or more etch processes form one or more... Taiwan Semiconductor Manufacturing Company Ltd

Isolation structure of fin field effect transistor

A representative fin field effect transistor (FinFET) includes a substrate having a major surface; a fin structure protruding from the major surface having a lower portion comprising a first semiconductor material having a first lattice constant; an upper portion comprising the first semiconductor material. A bottom portion of the upper... Taiwan Semiconductor Manufacturing Company Ltd

Finfets with source/drain cladding

A device includes a semiconductor substrate, and isolation regions extending into the semiconductor substrate. A semiconductor fin is between opposite portions of the isolation regions, wherein the semiconductor fin is over top surfaces of the isolation regions. A gate stack overlaps the semiconductor fin. A source/drain region is on a... Taiwan Semiconductor Manufacturing Company Ltd

Source and drain stressors with recessed top surfaces

An integrated circuit structure includes a gate stack over a semiconductor substrate, and a silicon germanium region extending into the semiconductor substrate and adjacent to the gate stack. The silicon germanium region has a top surface, with a center portion of the top surface recessed from edge portions of the... Taiwan Semiconductor Manufacturing Company Ltd

Input-output circuits

A circuit includes a first circuit that operates at a first-circuit supply voltage value and generates at least one of a first reference voltage value or a second reference voltage value, based on a voltage rated for transistors in a second circuit. The second circuit operates at the first-circuit supply... Taiwan Semiconductor Manufacturing Company Ltd

Semiconductor structure and manufacturing method thereof

The present disclosure provides a semiconductor device. The semiconductor packaged device includes a first semiconductor die having a first surface. The semiconductor packaged device also includes a dielectric material surrounding the first semiconductor die, where the dielectric material comprises a surface substantially leveled with the first surface. The semiconductor packaged... Taiwan Semiconductor Manufacturing Company Ltd

Semiconductor structure and associated manufacturing the same

A method for manufacturing a semiconductor structure is disclosed. The method includes: providing a semiconductor substrate having a plurality of dies thereon; dispensing an underfill material and a molding compound to fill spaces beneath and between the dies; disposing a temporary carrier over the dies; thinning a thickness of the... Taiwan Semiconductor Manufacturing Company Ltd

Semiconductor package and manufacturing the same

The present disclosure provides a semiconductor package, including a first semiconductor structure, a first bonding dielectric over the first semiconductor structure and surrounding a first bonding metallization structure, a through via over the first bonding dielectric, and a passive device passive device electrically coupled to the through via and the... Taiwan Semiconductor Manufacturing Company Ltd

Semiconductor packaging device with heat sink

A semiconductor packaging device includes: a first chip disposed separately from the first chip on a substrate; a second chip disposed on the substrate, wherein the first chip and the second chip comprise a first heat energy producing rating and a second heat energy producing rating, respectively, the first heat... Taiwan Semiconductor Manufacturing Company Ltd

Semiconductor structure and a manufacturing method thereof

A semiconductor structure includes a substrate including a first surface, a second surface opposite to the first surface and a recess extending from the first surface towards the second surface, a first die at least partially disposed within the recess and including a first die substrate and a first bonding... Taiwan Semiconductor Manufacturing Company Ltd

Semiconductor memory device and fabricating the same

A method for fabricating a semiconductor memory device is provided. The method includes: etching a first region of the semiconductor memory device to expose a first capping layer; forming a second capping layer on the first capping layer; etching a portion of the first capping layer and a portion of... Taiwan Semiconductor Manufacturing Company Ltd

Mos capacitor, semiconductor fabrication method and mos capacitor circuit

A metal-oxide-semiconductor (MOS) capacitor is disclosed. The MOS capacitor includes a front-end-of-the-line (FEOL) field effect transistor (FET), and a plurality of middle-end-of-the-line (MEOL) conductive structures. The FEOL FET includes a source region and a drain region positioned in a semiconductor substrate, and a gate over the semiconductor substrate. The plurality... Taiwan Semiconductor Manufacturing Company Ltd

01/04/18 / #20180001099

Interconnect structure and forming same

A semiconductor device comprises a first chip bonded on a second chip. The first chip comprises a first substrate and first interconnection components formed in first IMD layers. The second chip comprises a second substrate and second interconnection components formed in second IMD layers. The device further comprises a first... Taiwan Semiconductor Manufacturing Company Ltd

01/04/18 / #20180002166

Mems device with multi pressure

Micro-electromechanical (MEMS) devices and methods of forming are provided. The MEMS device includes a first substrate including a first conductive feature, a first movable element positioned over the first conductive feature, a second conductive feature, and a second movable element positioned over the second conductive feature. The MEMS device also... Taiwan Semiconductor Manufacturing Company Ltd

01/04/18 / #20180004079

System for and seeding an optical proximity correction (opc) process

A method, of seeding an optical proximity correction (OPC) process, includes: receiving, at an input device of a computer, a subject pre-OPC design-signature for a subject pre-OPC design package; selecting, by the processor and via interaction with an OPC database operatively connected to the computer, one amongst archived post-OPC design... Taiwan Semiconductor Manufacturing Company Ltd

01/04/18 / #20180004602

Method of correcting errors in a memory array and a system for implementing the same

A method of correcting errors in a memory array. The method includes configuring a first memory array with a first error correction code (ECC) to provide error correction of data stored in the first memory array, configuring a second memory array with a second ECC to provide error correction of... Taiwan Semiconductor Manufacturing Company Ltd

01/04/18 / #20180004884

Integrated circuit and manufacturing same

A method includes positioning a first set of conductive traces in a first direction, manufacturing a second set of conductive traces by a first mask pattern, and electrically coupling, by at least a first via, at least one conductive trace of the first set of conductive traces to at least... Taiwan Semiconductor Manufacturing Company Ltd

01/04/18 / #20180004886

Method of reconfiguring uncrowned standard cells and semiconductor apparatus including uncrowned and crowned cells

A method is applied to reconfigure a set of uncrowned standard cells in a layout of a semiconductor apparatus. Each uncrowned standard cell includes a standard first array. Each standard first array includes a first stacked arrangement of vias interspersed with first segments of corresponding M(i)˜M(N) metallization layers. The M(N)... Taiwan Semiconductor Manufacturing Company Ltd

01/04/18 / #20180005832

Semiconductor device, method and tool of manufacture

A semiconductor manufacturing tool and process to form semiconductor devices is provided. An edge ring of the semiconductor manufacturing tool comprises a high electron mobility material in order to extend an electrical field and sheath such that curvature from the sheath is moved away from a semiconductor wafer so that... Taiwan Semiconductor Manufacturing Company Ltd

01/04/18 / #20180005840

Surface treatment in a chemical mechanical process

A method is presented that includes the step of polishing a wafer positioned on a platen. After polishing the wafer, the method includes initiating a high pressure rinse on the wafer while the wafer is positioned on the platen, wherein the high pressure rinse includes a hydrophilic solution. The wafer... Taiwan Semiconductor Manufacturing Company Ltd

01/04/18 / #20180005870

Integrated bi-layer sti deposition

A method includes etching a semiconductor substrate to form trenches extending into the semiconductor substrate, and depositing a first dielectric layer into the trenches. The first dielectric layer fills lower portions of the trenches. A Ultra-Violet (UV) treatment is performed on the first dielectric layer in an oxygen-containing process gas.... Taiwan Semiconductor Manufacturing Company Ltd

01/04/18 / #20180005930

Fan-out package structure and method

A method includes attaching a semiconductor structure on a carrier, depositing a molding compound layer over the carrier, wherein the semiconductor structure is embedded in the molding compound layer, exposing a first photo-sensitive material layer and a second photo-sensitive material layer to light, developing the first photo-sensitive material layer and... Taiwan Semiconductor Manufacturing Company Ltd

01/04/18 / #20180005973

Stud bump structure for semiconductor package assemblies

A semiconductor package structure comprises a substrate, a die bonded to the substrate, and one or more stud bump structures connecting the die to the substrate, wherein each of the stud bump structures having a stud bump and a solder ball encapsulating the stud bump to enhance thermal dissipation and... Taiwan Semiconductor Manufacturing Company Ltd

01/04/18 / #20180005976

Mechanisms for forming bonding structures

Embodiments of mechanisms for forming a package are provided. The package includes a substrate and a contact pad formed on the substrate. The package also includes a conductive pillar bonded to the contact pad through solder formed between the conductive pillar and the contact pad. The solder is in direct... Taiwan Semiconductor Manufacturing Company Ltd

01/04/18 / #20180005984

Methods of forming multi-die package structures including redistribution layers

A semiconductor device and a method of making the same are provided. A first die and a second die are placed over a carrier substrate. A first molding material is formed adjacent to the first die and the second die. A first redistribution layer is formed overlying the first molding... Taiwan Semiconductor Manufacturing Company Ltd

01/04/18 / #20180006017

Method of manufacturing interconnect layer and semiconductor device which includes interconnect layer

A semiconductor device includes an interconnect layer on an inter-layer dielectric (ILD) structure. The ILD structure includes: first contacts, extending through the ILD structure, electrically connected to corresponding first components located in a floor structure underlying the ILD structure; at least one second component located within the ILD structure and... Taiwan Semiconductor Manufacturing Company Ltd

01/04/18 / #20180006046

Semiconductor structure and forming the same

A semiconductor structure includes a semiconductor substrate, at least one raised dummy feature, at least one memory cell, and at least one word line. The raised dummy feature is present on the semiconductor substrate and defines a cell region on the semiconductor substrate. The memory cell is present on the... Taiwan Semiconductor Manufacturing Company Ltd

01/04/18 / #20180006117

Formation of dislocations in source and drain regions of finfet devices

Embodiments of mechanisms for forming dislocations in source and drain regions of finFET devices are provided. The mechanisms involve recessing fins and removing the dielectric material in the isolation structures neighboring fins to increase epitaxial regions for dislocation formation. The mechanisms also involve performing a pre-amorphous implantation (PAI) process either... Taiwan Semiconductor Manufacturing Company Ltd

01/04/18 / #20180006134

Doped poly-silicon for polycmp planarity improvement

A method includes forming a polysilicon layer with an uneven upper surface over a first region and a second region of a substrate, doping a top portion of the polysilicon layer to change its removal rate, thereby forming a doped layer, and removing the doped layer in the first region... Taiwan Semiconductor Manufacturing Company Ltd

01/04/18 / #20180006146

Semiconductor device and forming the same

A semiconductor device includes a plurality of fins over a substrate. Each fin of the plurality of fins extends in a first direction substantially perpendicular to a bottom surface of the substrate, and each fin of the plurality of fins comprises a first doped region having a first dopant type.... Taiwan Semiconductor Manufacturing Company Ltd

01/04/18 / #20180006153

Semiconductor device and method

A source/drain region of a semiconductor device is formed using an epitaxial growth process. In an embodiment a first step comprises forming a bulk region of the source/drain region using a first precursor, a second precursor, and an etching precursor. A second step comprises cleaning the bulk region with the... Taiwan Semiconductor Manufacturing Company Ltd

01/04/18 / #20180006156

Gradient ternary or quaternary multiple-gate transistor

An integrated circuit structure includes a semiconductor substrate; insulation regions over the semiconductor substrate; and an epitaxy region over the semiconductor substrate and having at least a portion in a space between the insulation regions. The epitaxy region includes a III-V compound semiconductor material. The epitaxy region also includes a... Taiwan Semiconductor Manufacturing Company Ltd

01/04/18 / #20180006682

Communication system and data communications

A communication system includes a demodulator configured to demodulate a modulated signal responsive to a first carrier signal. The demodulator includes a filter and a gain adjusting circuit. The filter is configured to generate a filtered first signal based on a first signal. The first signal is a product of... Taiwan Semiconductor Manufacturing Company Ltd

12/28/17 / #20170372772

Memory controlling device and method thereof

A memory controlling device includes: a control circuit arranged to generate a multi-pulse control signal with a first duration; and a memory cell coupled to a pair of bit lines and a word line, wherein the multi-pulse control signal is coupled to the word line, and the memory cell is... Taiwan Semiconductor Manufacturing Company Ltd

12/28/17 / #20170373039

Semiconductor package and manufacturing the same

The present disclosure provides a semiconductor including a first semiconductor die layer having an active surface, a conductive contact electrically coupled to the active surface, a sidewall of the conductive contact being surrounded by an. insulating layer, and a solder bump connected to the conductive contact. A seed layer s... Taiwan Semiconductor Manufacturing Company Ltd

12/28/17 / #20170372891

Mechanisms for forming patterns using multiple lithography processes

The present disclosure provides a method for forming patterns in a semiconductor device. The method includes providing a substrate and a patterning-target layer over the substrate; patterning the patterning-target layer to form a main pattern; forming a middle layer over the patterning-target layer and a hard mask layer over the... Taiwan Semiconductor Manufacturing Company Ltd

12/28/17 / #20170372892

Gap filling materials and methods

In accordance with an embodiment a bottom anti-reflective layer comprises a surface energy modification group which modifies the surface energy of the polymer resin to more closely match a surface energy of an underlying material in order to help fill gaps between structures. The surface energy of the polymer resin... Taiwan Semiconductor Manufacturing Company Ltd

12/28/17 / #20170372900

Multi-layer mask and forming same

A method includes forming a first insulating layer over a substrate, the first insulating layer having a non-planar top surface, the first insulating layer having a first etch rate. A second insulating layer is formed over the first insulating layer, the second insulating layer having a non-planar top surface, the... Taiwan Semiconductor Manufacturing Company Ltd

12/28/17 / #20170372948

Interconnect structure and method

A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for surrounding dielectric layers. The insert layer may be applied between two dielectric layers. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide... Taiwan Semiconductor Manufacturing Company Ltd

12/28/17 / #20170372963

Wafer partitioning formed

A method of partitioning a wafer includes defining a scribe line surrounding a set of dies. The method further includes etching a plurality of trenches into the wafer, wherein each trench of the plurality of trenches is located between adjacent dies of the set of dies, and a width of... Taiwan Semiconductor Manufacturing Company Ltd

12/28/17 / #20170372976

Packaging mechanisms for dies with different sizes of connectors

Embodiments of mechanisms for testing a die package with multiple packaged dies on a package substrate use an interconnect substrate to provide electrical connections between dies and the package substrate and to provide probing structures (or pads). Testing structures, including daisy-chain structures, with metal lines to connect bonding structures connected... Taiwan Semiconductor Manufacturing Company Ltd

12/28/17 / #20170373004

Wireless charging package with chip integrated in coil center

A package includes a device die, and an encapsulating material encapsulating the device die therein. The encapsulating material has a top surface coplanar with a top surface of the device die. A coil extends from the top surface to a bottom surface of the encapsulating material, and the device die... Taiwan Semiconductor Manufacturing Company Ltd

Patent Packs
12/28/17 / #20170373022

Forming large chips through stitching

A method includes performing a first light-exposure and a second a second light-exposure on a photo resist. The first light-exposure is performed using a first lithograph mask, which covers a first portion of the photo resist. The first portion of the photo resist has a first strip portion exposed in... Taiwan Semiconductor Manufacturing Company Ltd

12/28/17 / #20170373048

Multi-die structure and forming same

A device includes a semiconductor structure comprising a top package stacked on a bottom package, wherein the bottom package comprises a plurality of bottom package bumps on a bottom surface of the bottom package, a front side contact metal, a molding compound layer and a backside contact metal, and wherein... Taiwan Semiconductor Manufacturing Company Ltd

12/28/17 / #20170373050

Semiconductor devices and methods of manufacture thereof

Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a device includes coupling a first semiconductor device to a second semiconductor device by spacers. The first semiconductor device has first contact pads disposed thereon, and the second semiconductor device has second contact pads... Taiwan Semiconductor Manufacturing Company Ltd

12/28/17 / #20170373066

Method and structure for finfet device

The present disclosure describes a fin-like field-effect transistor (FinFET). The device includes one or more fin structures over a substrate, each with source/drain (S/D) features and a high-k/metal gate (HK/MG). A first HK/MG in a first gate region wraps over an upper portion of a first fin structure, the first... Taiwan Semiconductor Manufacturing Company Ltd

12/28/17 / #20170373116

Image sensor device and method

A system and method for reducing cross-talk between photosensitive diodes is provided. In an embodiment a first color filter is formed over a first photosensitive diode and a second color filter is formed over a second photosensitive diode, and a gap is formed between the first color filter and the... Taiwan Semiconductor Manufacturing Company Ltd

12/28/17 / #20170373117

Deep trench isolations and methods of forming the same

A method includes performing an anisotropic etching on a semiconductor substrate to form a trench. The trench has vertical sidewalls and a rounded bottom connected to the vertical sidewalls. A damage removal step is performed to remove a surface layer of the semiconductor substrate, with the surface layer exposed to... Taiwan Semiconductor Manufacturing Company Ltd

12/28/17 / #20170373190

Finfets with strained well regions

A device includes a substrate, insulation regions extending into the substrate, a first semiconductor region between the insulation regions and having a first valence band, and a second semiconductor region over and adjoining the first semiconductor region. The second semiconductor region has a compressive strain and a second valence band... Taiwan Semiconductor Manufacturing Company Ltd

12/21/17 / #20170361361

Apparatus for particle cleaning

The present disclosure provides a particle cleaning apparatus. The apparatus comprises an acoustic wave generator configured to apply an acoustic wave to particles external to the acoustic wave generator. The apparatus also includes a removing module configured to remove the applied particles.... Taiwan Semiconductor Manufacturing Company Ltd

12/21/17 / #20170365483

Atomic layer deposition manufacturing semiconductor structure

A method for manufacturing semiconductor structure is disclosed. The method includes: providing a semiconductor substrate; hydrogenizing a surface of the semiconductor substrate; supplying a precursor to the surface of the semiconductor substrate; and supplying a reactant to the surface of the semiconductor substrate. An associated method for performing an atomic... Taiwan Semiconductor Manufacturing Company Ltd

12/21/17 / #20170365514

Semiconductor device and fabrication method thereof

A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor structure, a dielectric layer, a metal-semiconductor compound film and a cover layer. The semiconductor structure has an upper surface and a lateral surface. The dielectric layer encloses the lateral surface of the semiconductor structure... Taiwan Semiconductor Manufacturing Company Ltd

12/21/17 / #20170365581

Semiconductor structure and manufacturing method thereof

A semiconductor structure includes a substrate, a redistribution layer (RDL) including a dielectric layer disposed over the substrate and a plurality of conductive members surrounded by the dielectric layer, a first conductive pillar disposed over and electrically connected with one of the plurality of conductive members, a second conductive pillar... Taiwan Semiconductor Manufacturing Company Ltd

12/21/17 / #20170365587

Semiconductor package and manufacturing the same

The present disclosure provides a semiconductor package, including a first layer, a second layer, and a conductive array. The first layer includes a packaged die having a carrier surface and a molding surface, and a first die structure in proximity to the carrier surface. An active region of the first... Taiwan Semiconductor Manufacturing Company Ltd

12/21/17 / #20170365592

Layout integrated circuit and layout of the integrated circuit

A layout method includes: selecting, by a processor or manual, a first layout device in a layout of an integrated circuit; selecting a second device abutting the first layout device at a boundary between the first layout device and the second layout device, wherein a conductive path is disposed across... Taiwan Semiconductor Manufacturing Company Ltd

12/21/17 / #20170363658

Probe card structure

A probe head and methods of testing a device using a probe head are provided. The probe head includes a first end connected to a first substrate. The first substrate is configured to be connected to a test head. The probe head also includes second end having a first inner... Taiwan Semiconductor Manufacturing Company Ltd

12/21/17 / #20170363668

Sensor and sensing a value of a parameter

A sensor for sensing a parameter includes a control circuit that outputs a clock signal, a converter that receives the clock signal, generates a parameter-dependent voltage, and outputs an output voltage based on a comparison of the parameter-dependent voltage to a reference voltage. The sensor also includes a filter that... Taiwan Semiconductor Manufacturing Company Ltd

Patent Packs
12/21/17 / #20170363974

Apparatus and a forming a particle shield

An apparatus for generating at least one particle shield. The at least one particle shield includes a first component and a second component. The first component and the second component are usable to form a first particle shield of the at least one particle shield for blocking particles from contacting... Taiwan Semiconductor Manufacturing Company Ltd

12/21/17 / #20170365488

Method for forming semiconductor device structure with fine line pitch and fine end-to-end space

A method for forming a semiconductor device structure is provided. The method includes providing a substrate and forming a bottom layer, a middle layer, and a top layer on the substrate. The method also includes patterning the top layer to form a patterned top layer and patterning the middle layer... Taiwan Semiconductor Manufacturing Company Ltd

12/21/17 / #20170365508

Via patterning using multiple photo multiple etch

A method includes forming a dielectric layer, forming a photo resist over the dielectric layer, forming a first mask layer over the photo resist, and forming a second mask layer over the first mask layer. A first-photo-first-etching is performed to form a first via pattern in the second mask layer,... Taiwan Semiconductor Manufacturing Company Ltd

12/21/17 / #20170365524

Nano wire structure and fabricating the same

A method includes depositing a sacrificial layer on a first dielectric layer over a substrate; applying a first patterning process, a second patterning process, a third patterning process to the sacrificial layer to form a first group of openings, a second group of openings and a third group of openings,... Taiwan Semiconductor Manufacturing Company Ltd

12/21/17 / #20170365564

Semiconductor device and method

A semiconductor device and method of manufacturing is provided, whereby a support structure is utilized to provide additional support for a conductive element in order to eliminate or reduce the formation of a defective surface such that the conductive element may be formed to have a thinner structure without suffering... Taiwan Semiconductor Manufacturing Company Ltd

12/21/17 / #20170365579

3d chip-on-wafer-on-substrate structure with via last process

Disclosed herein is a package comprising a first redistribution layer (RDL) disposed on a first side of a first semiconductor substrate and a second RDL disposed on a second semiconductor substrate, wherein the first RDL is bonded to the second RDL. First conductive elements are disposed in the first RDL... Taiwan Semiconductor Manufacturing Company Ltd

12/21/17 / #20170365597

Vertical nanowire transistor for input/output structure

An electrostatic discharge (ESD) protection circuit includes an input terminal, a transistor, and an output terminal. The input terminal is configured to receive an input signal. The transistor includes a first source/drain region, a second source/drain region, and a drift region that has a resistance in series between the first... Taiwan Semiconductor Manufacturing Company Ltd

12/21/17 / #20170365668

Semiconductor device channel system and method

A system and method for a channel region is disclosed. An embodiment comprises a channel region with multiple bi-layers comprising alternating complementary materials such as layers of InAs and layers of GaSb. The alternating layers of complementary materials provide desirable band gap characteristics for the channel region as a whole... Taiwan Semiconductor Manufacturing Company Ltd

12/21/17 / #20170365674

Self-aligned contact and manufacturing method thereof

A semiconductor device and a method of forming the semiconductor device is disclosed. A sacrificial film is used to pattern a contact to a semiconductor structure, such as a contact to a source/drain region of a transistor. The contact may include a tapered profile along an axis parallel to the... Taiwan Semiconductor Manufacturing Company Ltd

12/21/17 / #20170365686

Method and structure for finfet comprising patterned oxide and dielectric layer under spacer features

A semiconductor device includes a substrate having a fin projecting upwardly through an isolation structure over the substrate; a gate stack over the isolation structure and engaging the fin; and a gate spacer on a sidewall of the gate stack and in physical contact with the gate stack. The semiconductor... Taiwan Semiconductor Manufacturing Company Ltd

12/21/17 / #20170365906

Semiconductor device including transmission lines and forming the same

A semiconductor device includes a first transmission line and a second transmission line. The semiconductor device further includes a high-k dielectric material between the first transmission line and the second transmission line. The semiconductor device further includes a dielectric material directly contacting at least one of the first transmission line... Taiwan Semiconductor Manufacturing Company Ltd

12/21/17 / #20170366177

Integrated circuit and testing

An integrated circuit for testing a circuit includes a controller configured to select a loopback path of the circuit. The circuit includes a data path and an inverter, and each is electrically coupled to the selected loopback path. The integrated circuit includes a counter electrically coupled to the selected loopback... Taiwan Semiconductor Manufacturing Company Ltd

12/14/17 / #20170358671

Semiconductor device

A semiconductor device includes a transistor, a semiconductor layer, an active region and a conductive layer. The active region is in the semiconductor layer. The conductive layer is configured to maintain a channel in the active region when the transistor is triggered to be conducted.... Taiwan Semiconductor Manufacturing Company Ltd

12/14/17 / #20170357838

Fingerprint sensor in info structure and formation method

A package includes a sensor die, and an encapsulating material encapsulating the sensor die therein. A top surface of the encapsulating material is substantially coplanar with or higher than a top surface of the sensor die. A plurality of sensing electrodes is higher than the sensor die and the encapsulating... Taiwan Semiconductor Manufacturing Company Ltd

12/14/17 / #20170358343

Sram arrays and methods of manufacturing same

An embodiment static random access memory (SRAM) array includes a first SRAM mini array having a first plurality of functional SRAM cells in a first column of the SRAM array. Each of the first plurality of functional SRAM cells share a first bit line (BL). The SRAM array further includes... Taiwan Semiconductor Manufacturing Company Ltd

12/14/17 / #20170358481

Multi-barrier deposition for air gap formation

A method includes forming a first conductive line and a second conductive line in a dielectric layer, etching a portion of the dielectric layer to form a trench between the first conductive line and the second conductive line, and forming a first etch stop layer. The first etch stop layer... Taiwan Semiconductor Manufacturing Company Ltd

12/14/17 / #20170358500

Horizontal gate-all-around device having wrapped-around source and drain

Various semiconductor devices, such as horizontal gate-all-around devices, and methods of fabricating such are disclosed herein. An exemplary semiconductor device includes a fin structure having a channel region disposed between a first source/drain region and a second source/drain region. The fin structure includes a first nanowire and a second nanowire... Taiwan Semiconductor Manufacturing Company Ltd

12/14/17 / #20170358531

Interconnection structure, fabricating method thereof, and semiconductor device using the same

A semiconductor device includes a semiconductor substrate comprising a contact region, a silicide present on the contact region, a dielectric layer present on the semiconductor substrate, the dielectric layer comprising an opening to expose a portion of the contact region, a conductor present in the opening, a barrier layer present... Taiwan Semiconductor Manufacturing Company Ltd

12/14/17 / #20170358551

Hybrid bonding semiconductor wafers

Hybrid bonding systems and methods for semiconductor wafers are disclosed. In one embodiment, a hybrid bonding system for semiconductor wafers includes a chamber and a plurality of sub-chambers disposed within the chamber. A robotics handler is disposed within the chamber that is adapted to move a plurality of semiconductor wafers... Taiwan Semiconductor Manufacturing Company Ltd

12/14/17 / #20170358566

Systems and methods for a sequential spacer scheme

Semiconductor devices disclosed herein have minimum spacings that correlate with spacer widths. An exemplary semiconductor device includes a substrate and a target layer disposed over the substrate. The target layer includes a first target feature, a second target feature, and a third target feature. The second target feature is spaced... Taiwan Semiconductor Manufacturing Company Ltd

12/14/17 / #20170358572

Structure and cooling three-dimensional integrated circuits

A structure and method for cooling a three-dimensional integrated circuit (3DIC) are provided. A cooling element is configured for thermal connection to the 3DIC. The cooling element includes a plurality of individually controllable cooling modules disposed at a first plurality of locations relative to the 3DIC. Each of the cooling... Taiwan Semiconductor Manufacturing Company Ltd

12/14/17 / #20170358584

Semiconductor device and fabrication method therefor

A method of fabricating a semiconductor device. The method includes forming a dummy structure over a substrate, forming conductive features on opposite sides of the dummy gate structure, removing the dummy structure and a portion of the substrate beneath the dummy gate structure to form a trench, and filling the... Taiwan Semiconductor Manufacturing Company Ltd

12/14/17 / #20170358648

Strained channel field effect transistor

Various strained channel transistors are disclosed herein. An exemplary semiconductor device includes a substrate and a fin structure disposed over the substrate. The fin structure includes a first epitaxial layer disposed on the substrate, a second epitaxial layer disposed on the first epitaxial layer, and a third epitaxial layer disposed... Taiwan Semiconductor Manufacturing Company Ltd








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