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Filing Names

Taiwan Semiconductor Manufacturing Company Ltd
Taiwan Semiconductor Manufacturing Company Ltd tsmc
Taiwan Semiconductor Manufacturing Company Ltd tsmc_20131212
Taiwan Semiconductor Manufacturing Company Ltd x201c tsmc x201d
Taiwan Semiconductor Manufacturing Company Ltd_20100107
Taiwan Semiconductor Manufacturing Company Ltd_20100114
Taiwan Semiconductor Manufacturing Company Ltd_20131212
Taiwan Semiconductor Manufacturing Company Ltd_20100128
Taiwan Semiconductor Manufacturing Company Ltd_20100121

Taiwan Semiconductor Manufacturing Company Ltd patents

Recent patent applications related to Taiwan Semiconductor Manufacturing Company Ltd. Taiwan Semiconductor Manufacturing Company Ltd is listed as an Agent/Assignee. Note: Taiwan Semiconductor Manufacturing Company Ltd may have other listings under different names/spellings. We're not affiliated with Taiwan Semiconductor Manufacturing Company Ltd, we're just tracking patents.

ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "T" | Taiwan Semiconductor Manufacturing Company Ltd-related inventors

Date Taiwan Semiconductor Manufacturing Company Ltd patents (updated weekly) - BOOKMARK this page
05/18/17 new patent  Layout modification method and system
05/18/17 new patent  Semiconductor structure and manufacturing method thereof
05/18/17 new patent  Semiconductor package and forming the same
05/18/17 new patent  Cmp polishing head design for improving removal rate uniformity
05/18/17 new patent  Acoustic measurement of fabrication equipment clearance
05/18/17 new patent  Method for repairing a mask
05/18/17 new patent  Method and system for euv mask cleaning with non-thermal solution
05/18/17 new patent  Fingerprint sensor device and method
05/18/17 new patent  Compact vertical inductors extending in vertical planes
05/18/17 new patent  Treatment process and system
05/18/17 new patent  Method of forming ultra-thin nanowires
05/18/17 new patent  Method for forming stacked nanowire transistors
05/18/17 new patent  Self-aligned dual-metal silicide and germanide formation
05/18/17 new patent  Semiconductor device and method
05/18/17 new patent  Apparatus and wafer level bonding
05/18/17 new patent  Multi-barrier deposition for air gap formation
05/18/17 new patent  Horizontal gate-all-around device having wrapped-around source and drain
05/18/17 new patent  Active atomic reservoir for enhancing electromigration reliability in integrated circuits
05/18/17 new patent  Methods and structrues of novel contact feature
05/18/17 new patent  Methods and apparatus of guard rings for wafer-level-packaging
05/18/17 new patent  Seal rings structures in semiconductor device interconnect layers and methods of forming the same
05/18/17 new patent  Integrated fan-out structure and forming
05/18/17 new patent  Package with solder regions aligned to recesses
05/18/17 new patent  Chip packages and methods of manufacture thereof
05/18/17 new patent  Conductive external connector structure and forming
05/18/17 new patent  Post-passivation interconnect structure and forming same
05/18/17 new patent  Metal bump joint structure and methods of forming
05/18/17 new patent  Mechanisms for forming hybrid bonding structures with elongated bumps
05/18/17 new patent  Semiconductor device and manufacture
05/18/17 new patent  Finfet-based esd devices and methods for forming the same
05/18/17 new patent  Method and structure for semiconductor mid-end-of-line (meol) process
05/18/17 new patent  Multi-gate device and fabrication thereof
05/18/17 new patent  Discrete storage element formation for thin-film storage device
05/18/17 new patent  Method of cutting metal gate
05/18/17 new patent  Devices including gate spacer with gap or void and methods of forming the same
05/18/17 new patent  Integrated circuit structure with substrate isolation and un-doped channel
05/18/17 new patent  Negative capacitance field effect transistor with charged dielectric material
05/18/17 new patent  Resistive ram structure and fabrication thereof
05/18/17 new patent  Demodulator, receiver and data communications
05/18/17 new patent  Pixel unit cell having conversion circuit
05/18/17 new patent  Network-assisted channel selection and power control for mobile devices
05/11/17Semiconductor structure and manufacturing method thereof
05/11/17Semiconductor device and fabricating the same
05/11/17Semiconductor structure and manufacturing the same
05/11/17Interconnect structure with misaligned metal lines coupled using different interconnect layer
05/11/17Semiconductor device and forming the same
05/11/17High-electron-mobility transistor and manufacturing method thereof
05/11/17Fabrication and structures of crystalline material
05/11/17Apparatus and finfets
05/11/17Memory devices and fabricating same
05/11/17Inverters and manufacturing methods thereof
05/11/17Chip-on-wafer process control monitoring for chip-on-wafer-on-substrate packages
05/11/17Conductive structure and forming the same
05/11/17Pad structure design in fan-out package
05/11/17Bump structure for yield improvement
05/11/17Integrated circuit process having alignment marks for underfill
05/11/17Method and structure for finfet devices
05/11/17Integrated circuit having a vertical power mos transistor
05/11/17Semiconductor device and manufacturing method thereof
05/11/17Memory devices and fabricating same
05/11/17Capacitor and making same
05/11/17Circuit structure, transistor and semiconductor device
05/11/17Replacement gate process for finfet
05/11/17Structure and formation semiconductor device structure
05/11/17Source/drain regions for fin field effect transistors and methods of forming same
Patent Packs
05/11/17Delay line circuit
05/11/17Sensor having depth sensing pixel and using the same
05/04/17Probe head receiver and probe card assembly having the same
05/04/17Hybrid semiconductor structure on a common substrate
05/04/17Metal gate structure and manufacturing method thereof
05/04/17Method of fabricating semiconductor structure
05/04/17Semiconductor device having a guard ring
05/04/17Semiconductor device
05/04/17Non-volatile memory and manufacturing method thereof
05/04/17High voltage semiconductor device
05/04/17Schottky diode having a well with peripherial cathod regions and center andoe region
05/04/17Semiconductor structure and manufacturing method thereof
05/04/17Semiconductor device with discrete blocks
05/04/17Layout optimization of a main pattern and a cut pattern
05/04/17Circuit and generating a sense amplifier enable signal
Patent Packs
05/04/17Semiconductor device metallization systems and methods
05/04/17Finfet devices with unique fin shape and the fabrication thereof
05/04/17Moving pyrometer for use with a substrate chamber
05/04/17Polymer-based-semiconductor structure with cavity
05/04/17Self-aligned interconnection structure and method
05/04/17Package structures and methods of making the same
05/04/17Metal pad for laser marking
05/04/17Connector formation methods and packaged semiconductor devices
05/04/17Packages with solder ball revealed through layer
05/04/17Rework process and tool design for semiconductor package
05/04/17System on integrated chips and methods of forming same
05/04/17Stacked integrated circuit structure and forming
05/04/17Elongated semiconductor structure planarization
05/04/17Oxidation and etching post metal gate cmp
05/04/17Devices having a semiconductor material that is semimetal in bulk and methods of forming the same
05/04/17Field-effect transistor with dual vertical gates
05/04/17Channel strain control for nonplanar compound semiconductor devices
05/04/17Input/output circuit
05/04/17Digital code recovery with preamble
04/27/17Characterizing cell using input waveforms with different tail characteristics
04/27/17Network logic synthesis
04/27/17Methods of forming strained-semiconductor-on-insulator device structures
04/27/17Semiconductor devices with bump allocation
04/27/17Interconnection structure and forming same
04/27/17Semiconductor packages and methods of forming the same
04/27/17Contact resistance reduction technique
04/27/17Semiconductor liner of semiconductor device
04/27/17Fin structure of fin field effect transistor
04/27/17Method of reducing the heights of source-drain sidewall spacers of finfets through etching
04/27/17Structure and finfet device with buried sige oxide
Social Network Patent Pack
04/27/17Forming conductive sti liners for finfets
04/27/17Integrated circuit with radio frequency interconnect
04/20/17Semiconductor sensing structure
04/20/17Dual rail memory, memory macro and associated hybrid power supply method
04/20/17Package structure, fan-out package structure and the same
04/20/17Semiconductor device and manufacturing method thereof
04/20/17Semiconductor device with an anti-pad peeling structure and associated method
04/20/17Semiconductor device and manufacturing method thereof
04/20/17Transceiver group and associated router
04/20/17Treating a capping layer of a mask
Patent Packs
04/20/17Orientation layer for directed self-assembly patterning process
04/20/17Photomask for forming multiple layer patterns with a single exposure
04/20/17Method and forming self-aligned via with selectively deposited etching stop layer
04/20/17Bonding structures and methods forming the same
04/20/17Wafer level shielding in multi-stacked fan out packages and methods of forming same
04/20/17Semiconductor device and method
04/20/17Semiconductor die contact structure and method
04/20/17Integrated fan-out (info) package structures and methods of forming same
04/20/17Method of tuning source/drain proximity for input/output device reliability enhancement
04/20/17Interconnect apparatus and method
04/20/17Source/drain structure of semiconductor device
04/20/17Interlayer dielectric film in semiconductor devices
04/20/17Magnetic tunnel junction with reduced damage
04/13/17Sensor in an internet-of-things and manufacturing the same
04/13/17Semiconductor device and manufacturing the same
04/13/17Semiconductor structure and manufacturing method thereof
04/13/17Grid refinement method
04/13/17Method for forming aluminum-containing dielectric layer
04/13/17Deposited material and formation
04/13/17Method of using a wafer cassette to charge an electrostatic carrier
04/13/17Method for interconnect scheme
04/13/17Isolation rings for packages and the forming the same
04/13/17Cooling devices, packaged semiconductor devices, and methods of packaging semiconductor devices
04/13/17Forming interlayer dielectric material by spin-on metal oxide deposition
04/13/17Method and structure of three-dimensional chip stacking
04/13/17Strained nanowire cmos device and forming
04/13/17Finfet semiconductor device with germanium diffusion over silicon fins
04/13/17Surface treatment and passivation for high electron mobility transistors
04/13/17Decoupling finfet capacitors
04/13/17Wireless charging devices, methods of manufacture thereof, and charging methods
Patent Packs
04/06/17Power state coverage metric and estimating the same
04/06/17Semiconductor device and manufacturing method thereof
04/06/17Semiconductor structure with ultra thick metal and manufacturing method thereof
04/06/17Method and reducing in-process and in-use stiction for mems devices
04/06/17Electro-optic modulator device, optical device and making an optical device
04/06/17Slurry composition for chemical mechanical polishing of ge-based materials and devices
04/06/17Warpage control in the packaging of integrated circuits
04/06/17Methods of forming an integrated circuit chip having two types of memory cells
04/06/17Integrated circuit with conductive line having line-ends
04/06/17Finfet device
04/06/17Configurable routing for packaging applications
04/06/17Chip-on-substrate packaging on carrier
04/06/17Semiconductor structure and manufacturing method thereof
04/06/17Scrs with checker board layouts
04/06/17Structure and 3d image sensor
04/06/17Field effect transistors and methods of forming same
04/06/17Devices having transition metal dichalcogenide layers with different thicknesses and methods of manufacture
04/06/17Logic compatible rram structure and process
04/06/173d antenna for integrated circuits
03/30/17Semiconductor structure integrated with magnetic tunneling junction and manufacturing method thereof
Social Network Patent Pack
03/30/17Semiconductor integrated circuit and making the same
03/30/17Frequency scaling method, circuit and associated all-digital phase-locked loop
03/30/17Wafer susceptor with improved thermal characteristics
03/30/17Lithography alignment marks
03/30/17Method of parameter extraction and system thereof
03/30/17Memory with regulated ground nodes and retaining data therein
03/30/17Post-cmp cleaning and apparatus
03/30/17Treatment system and method
03/30/17Patterning process of a semiconductor structure with a middle layer
03/30/17Method of forming metal interconnection
03/30/17Structure and interconnection
03/30/17Integrated fan-out structure and forming
03/30/17Wafer level package (wlp) and forming the same
03/30/17Semiconductor device and manufacture
03/30/17Chip packages and methods of manufacture thereof
03/30/17Package structure and forming same
03/30/17Semiconductor die connection system and method
03/30/17Elevated photodiode with a stacked scheme
03/30/17Multiple gate field effect transistors having oxygen-scavenged gate stack
03/30/17Diode-based devices and methods for making the same
Social Network Patent Pack
03/30/17High electron mobility transistor and forming the same
03/30/17Method of forming ultra-thin nanowires
03/30/17Metal gate scheme for device and methods of forming
03/30/17Finfet structure and fabricating the same
03/30/17Electrochemical plating
03/23/17Mems devices and methods of manufacturing the same
03/23/17Dual rail memory, memory macro and associated hybrid power supply method
03/23/17Semiconductor device
03/23/17Semiconductor structure and the manufacturing method thereof
03/23/17Conditional correlated multiple sampling single slope analog-to-digital converter, and associated image sensor system and method
03/23/17Atomic layer deposition method
03/23/17Electro-plating and performing the same
03/23/17Method to fabricate mask-pellicle system
03/23/17Trench formation using horn shaped spacer
03/23/17Method of forming metal interconnection
03/23/17Device with through-substrate via structure and forming the same
03/23/17Guard rings including semiconductor fins and regrown regions
03/23/17Asymmetric source/drain depths
03/23/17Structure and formation semiconductor device structure
03/23/17Structure and overlay marks
03/23/17Semiconductor device with self-heat reducing layers
03/23/17Dummy metal with zigzagged edges
03/23/17Semiconductor device and manufacture
03/23/17Integrated circuit dies having alignment marks and methods of forming same
03/23/17Warpage control in package-on-package structures
03/23/17Backside redistribution layer (rdl) structure
03/23/17Integrated fan-out package and the methods of manufacturing
03/23/17Methods and solder connections
03/23/17Cu pillar bump with l-shaped non-metal sidewall protection structure
03/23/17Pillar design for conductive bump
Social Network Patent Pack
03/23/17Integrated fan-out stacked sip and the methods of manufacturing
03/23/17Package structures and forming the same
03/23/17Semiconductor die
03/23/17Raised epitaxial ldd in mugfets and methods for forming the same
03/23/17Source/drain regions for high electron mobility transistors (hemt) and methods of forming same
03/23/17Finfets having epitaxial capping layer on fin and methods for forming the same
03/23/17Top metal pads as local interconnectors of vertical transistors
03/23/17Magnetoresistive random access memory cell and fabricating the same
03/16/17Finfet structure and manufacturing thereof
03/16/17Reliability testing method
03/16/17Adhesion promoter apparatus and method
03/16/17Novel photoresist having sensitizer bonded to acid generator
03/16/17Sense amplifier circuits and methods of operation
03/16/17Ion collector for use in plasma systems
03/16/17Fin field effect transistor (finfet) device with controlled end-to-end critical dimension and forming the same
03/16/17Lid attach processes for semiconductor packages
03/16/17Method and structure for finfet isolation
03/16/17Debonding schemes
03/16/17Laser marking in packages
03/16/17Method of forming 3d integrated circuit package with panel type lid
03/16/17Multi-gate fets and methods for forming the same
03/16/17Finfet contact structure and forming the same
03/16/17Finfet memory device
03/16/17Method of forming high electron mobility transistor
03/16/17Photovoltaics on silicon
03/16/17Apparatus and forming chip package with waveguide for light coupling
03/16/17Auto frequency calibration method
03/16/17Fets and methods of forming fets
03/09/17Semiconductor structure and manufacturing method thereof

ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009


This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. is not affiliated or associated with Taiwan Semiconductor Manufacturing Company Ltd in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Taiwan Semiconductor Manufacturing Company Ltd with additional patents listed. Browse our Agent directory for other possible listings. Page by