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Filing Names

Taiwan Semiconductor Manufacturing Company Ltd
Taiwan Semiconductor Manufacturing Company Limited
Taiwan Semiconductor Manufacturing Company Ltd tsmc
Taiwan Semiconductor Manufacturing Company
Taiwan Semiconductor Manufacturing Company ltd
Taiwan Semiconductor Manufacturing Company Ltd tsmc_20131212
Taiwan Semiconductor Manufacturing Company Limited Limited
Taiwan Semiconductor Manufacturing Company Inc
Taiwan Semiconductor Manufacturing Company Ltd x201c tsmc x201d
Taiwan Semiconductor Manufacturing Company Ltd_20100114
Taiwan Semiconductor Manufacturing Company Tld
Taiwan Semiconductor Manufacturing Company Ltd_20131212
Taiwan Semiconductor Manufacturing Company Ltd_20100128
Taiwan Semiconductor Manufacturing Company Ltd_20100121
Taiwan Semiconductor Manufacturing Company Ltd_20100107

Taiwan Semiconductor Manufacturing Company patents

Recent patent applications related to Taiwan Semiconductor Manufacturing Company. Taiwan Semiconductor Manufacturing Company is listed as an Agent/Assignee. Note: Taiwan Semiconductor Manufacturing Company may have other listings under different names/spellings. We're not affiliated with Taiwan Semiconductor Manufacturing Company, we're just tracking patents.

ARCHIVE: New 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "T" | Taiwan Semiconductor Manufacturing Company-related inventors

Date Taiwan Semiconductor Manufacturing Company patents (updated weekly) - BOOKMARK this page
04/20/17Apparatus for manufacturing a thin film and a method therefor
03/16/17Semiconductor device including fin fet and manufacturing method thereof
03/02/17Semiconductor device and manufacturing method thereof
02/23/17Semiconductor device and manufacturing method thereof
02/02/17Semiconductor device including fin structures disposed over buffer structures and manufacturing method thereof
01/26/17Finfet with doped isolation insulating layer
01/26/17Semiconductor device and manufacturing method thereof
01/12/17Integrated thermoelectric devices in fin fet technology
10/20/16Finfet semiconductor device having fins with stronger structural strength
09/01/16Reduction of edge effects from aspect ratio trapping
07/28/16Semiconductor device including fin structure with two channel layers and manufacturing method thereof
07/16/15Packaging through pre-formed metal pins
05/29/14High voltage drain-extended mosfet having extra drain-od addition
10/03/13Enhanced euv lithography system
09/19/13Method of fabricating a semiconductor device
03/10/11Method for forming a reduced active area in a phase change memory structure
07/15/10Method to produce 3-d optical gyroscope my mems technology
07/08/10Robust tsv structure
05/27/10Method and cleaning semiconductor device fabrication equipment using supercritical fluids
12/03/09Method of yield management for semiconductor manufacture and apparatus thereof
09/04/14Integrated circuit using deep trench through silicon (dts)
02/06/14Method of fabricating a lithography mask
09/05/13Plasma doping to reduce dielectric loss during removal of dummy layers in a gate structure
06/17/10Strained channel transistor
10/24/13Reflective mask and making same
04/27/17 new patent  Characterizing cell using input waveforms with different tail characteristics
04/27/17 new patent  Network logic synthesis
04/27/17 new patent  Methods of forming strained-semiconductor-on-insulator device structures
04/27/17 new patent  Semiconductor devices with bump allocation
04/27/17 new patent  Interconnection structure and forming same
04/27/17 new patent  Semiconductor packages and methods of forming the same
04/27/17 new patent  Contact resistance reduction technique
04/27/17 new patent  Semiconductor liner of semiconductor device
04/27/17 new patent  Fin structure of fin field effect transistor
04/27/17 new patent  Method of reducing the heights of source-drain sidewall spacers of finfets through etching
04/27/17 new patent  Structure and finfet device with buried sige oxide
04/27/17 new patent  Forming conductive sti liners for finfets
04/27/17 new patent  Integrated circuit with radio frequency interconnect
04/20/17Semiconductor sensing structure
04/20/17Dual rail memory, memory macro and associated hybrid power supply method
04/20/17Package structure, fan-out package structure and the same
04/20/17Semiconductor device and manufacturing method thereof
04/20/17Semiconductor device with an anti-pad peeling structure and associated method
04/20/17Semiconductor device and manufacturing method thereof
04/20/17Transceiver group and associated router
04/20/17Treating a capping layer of a mask
04/20/17Orientation layer for directed self-assembly patterning process
04/20/17Photomask for forming multiple layer patterns with a single exposure
04/20/17Method and forming self-aligned via with selectively deposited etching stop layer
04/20/17Bonding structures and methods forming the same
04/20/17Wafer level shielding in multi-stacked fan out packages and methods of forming same
04/20/17Semiconductor device and method
04/20/17Semiconductor die contact structure and method
04/20/17Integrated fan-out (info) package structures and methods of forming same
04/20/17Method of tuning source/drain proximity for input/output device reliability enhancement
04/20/17Interconnect apparatus and method
04/20/17Source/drain structure of semiconductor device
04/20/17Interlayer dielectric film in semiconductor devices
04/20/17Magnetic tunnel junction with reduced damage
04/13/17Sensor in an internet-of-things and manufacturing the same
04/13/17Semiconductor device and manufacturing the same
04/13/17Semiconductor structure and manufacturing method thereof
04/13/17Grid refinement method
04/13/17Method for forming aluminum-containing dielectric layer
04/13/17Deposited material and formation
Patent Packs
04/13/17Method of using a wafer cassette to charge an electrostatic carrier
04/13/17Method for interconnect scheme
04/13/17Isolation rings for packages and the forming the same
04/13/17Cooling devices, packaged semiconductor devices, and methods of packaging semiconductor devices
04/13/17Forming interlayer dielectric material by spin-on metal oxide deposition
04/13/17Method and structure of three-dimensional chip stacking
04/13/17Strained nanowire cmos device and forming
04/13/17Finfet semiconductor device with germanium diffusion over silicon fins
04/13/17Surface treatment and passivation for high electron mobility transistors
04/13/17Decoupling finfet capacitors
04/13/17Wireless charging devices, methods of manufacture thereof, and charging methods
04/06/17Power state coverage metric and estimating the same
04/06/17Semiconductor device and manufacturing method thereof
04/06/17Semiconductor structure with ultra thick metal and manufacturing method thereof
04/06/17Method and reducing in-process and in-use stiction for mems devices
Patent Packs
04/06/17Electro-optic modulator device, optical device and making an optical device
04/06/17Slurry composition for chemical mechanical polishing of ge-based materials and devices
04/06/17Warpage control in the packaging of integrated circuits
04/06/17Methods of forming an integrated circuit chip having two types of memory cells
04/06/17Integrated circuit with conductive line having line-ends
04/06/17Finfet device
04/06/17Configurable routing for packaging applications
04/06/17Chip-on-substrate packaging on carrier
04/06/17Semiconductor structure and manufacturing method thereof
04/06/17Scrs with checker board layouts
04/06/17Structure and 3d image sensor
04/06/17Field effect transistors and methods of forming same
04/06/17Devices having transition metal dichalcogenide layers with different thicknesses and methods of manufacture
04/06/17Logic compatible rram structure and process
04/06/173d antenna for integrated circuits
03/30/17Semiconductor structure integrated with magnetic tunneling junction and manufacturing method thereof
03/30/17Semiconductor integrated circuit and making the same
03/30/17Frequency scaling method, circuit and associated all-digital phase-locked loop
03/30/17Wafer susceptor with improved thermal characteristics
03/30/17Lithography alignment marks
03/30/17Method of parameter extraction and system thereof
03/30/17Memory with regulated ground nodes and retaining data therein
03/30/17Post-cmp cleaning and apparatus
03/30/17Treatment system and method
03/30/17Patterning process of a semiconductor structure with a middle layer
03/30/17Method of forming metal interconnection
03/30/17Structure and interconnection
03/30/17Integrated fan-out structure and forming
03/30/17Wafer level package (wlp) and forming the same
03/30/17Semiconductor device and manufacture
Social Network Patent Pack
03/30/17Chip packages and methods of manufacture thereof
03/30/17Package structure and forming same
03/30/17Semiconductor die connection system and method
03/30/17Elevated photodiode with a stacked scheme
03/30/17Multiple gate field effect transistors having oxygen-scavenged gate stack
03/30/17Diode-based devices and methods for making the same
03/30/17High electron mobility transistor and forming the same
03/30/17Method of forming ultra-thin nanowires
03/30/17Metal gate scheme for device and methods of forming
03/30/17Finfet structure and fabricating the same
Patent Packs
03/30/17Electrochemical plating
03/23/17Mems devices and methods of manufacturing the same
03/23/17Dual rail memory, memory macro and associated hybrid power supply method
03/23/17Semiconductor device
03/23/17Semiconductor structure and the manufacturing method thereof
03/23/17Conditional correlated multiple sampling single slope analog-to-digital converter, and associated image sensor system and method
03/23/17Atomic layer deposition method
03/23/17Electro-plating and performing the same
03/23/17Method to fabricate mask-pellicle system
03/23/17Trench formation using horn shaped spacer
03/23/17Method of forming metal interconnection
03/23/17Device with through-substrate via structure and forming the same
03/23/17Guard rings including semiconductor fins and regrown regions
03/23/17Asymmetric source/drain depths
03/23/17Structure and formation semiconductor device structure
03/23/17Structure and overlay marks
03/23/17Semiconductor device with self-heat reducing layers
03/23/17Dummy metal with zigzagged edges
03/23/17Semiconductor device and manufacture
03/23/17Integrated circuit dies having alignment marks and methods of forming same
03/23/17Warpage control in package-on-package structures
03/23/17Backside redistribution layer (rdl) structure
03/23/17Integrated fan-out package and the methods of manufacturing
03/23/17Methods and solder connections
03/23/17Cu pillar bump with l-shaped non-metal sidewall protection structure
03/23/17Pillar design for conductive bump
03/23/17Integrated fan-out stacked sip and the methods of manufacturing
03/23/17Package structures and forming the same
03/23/17Semiconductor die
03/23/17Raised epitaxial ldd in mugfets and methods for forming the same
Patent Packs
03/23/17Source/drain regions for high electron mobility transistors (hemt) and methods of forming same
03/23/17Finfets having epitaxial capping layer on fin and methods for forming the same
03/23/17Top metal pads as local interconnectors of vertical transistors
03/23/17Magnetoresistive random access memory cell and fabricating the same
03/16/17Finfet structure and manufacturing thereof
03/16/17Reliability testing method
03/16/17Adhesion promoter apparatus and method
03/16/17Novel photoresist having sensitizer bonded to acid generator
03/16/17Sense amplifier circuits and methods of operation
03/16/17Ion collector for use in plasma systems
03/16/17Fin field effect transistor (finfet) device with controlled end-to-end critical dimension and forming the same
03/16/17Lid attach processes for semiconductor packages
03/16/17Method and structure for finfet isolation
03/16/17Debonding schemes
03/16/17Laser marking in packages
03/16/17Method of forming 3d integrated circuit package with panel type lid
03/16/17Multi-gate fets and methods for forming the same
03/16/17Finfet contact structure and forming the same
03/16/17Finfet memory device
03/16/17Method of forming high electron mobility transistor
Social Network Patent Pack
03/16/17Photovoltaics on silicon
03/16/17Apparatus and forming chip package with waveguide for light coupling
03/16/17Auto frequency calibration method
03/16/17Fets and methods of forming fets
03/09/17Semiconductor structure and manufacturing method thereof
03/09/17Finfet device having a channel defined in a diamond-like shape semiconductor structure
03/09/17Mems devices and methods of forming same
03/09/17On-chip disease diagnostic platform for dual-gate ion sensitive field effect transistor
03/09/17Layout of standard cells for predetermined function in integrated circuits
03/09/17Conformal middle layer for a lithography process
03/09/17Spacer etching process for integrated circuit design
03/09/17Integrated circuit with a sidewall layer and an ultra-thick metal layer and making
03/09/17Fabrication a metal gate structure
03/09/17Method of preventing pattern collapse
03/09/17Conductive contacts having varying widths and manufacturing same
03/09/17Air trench in packages incorporating hybrid bonding
03/09/17Warpage control of semiconductor die package
03/09/17Package-on-package structure with through molding via
03/09/17Finfet transistor with fin back biasing
03/09/17Memory devices and forming same
Social Network Patent Pack
03/09/17Coplanar metal-insulator-metal capacitive structure
03/09/17Fin structure for a finfet device
03/09/17Dco phase noise with pvt-insensitive calibration circuit in adpll applications
03/02/17Semiconductor structure and manufacturing method thereof
03/02/17Semiconductor device and manufacturing method thereof
03/02/17Semiconductor packaging and manufacturing method thereof
03/02/17Method of using integrated electro-microfluidic probe card
03/02/17Developer for lithography
03/02/17Mask cleaning
03/02/17Method for integrated circuit patterning
03/02/17Dicing in wafer level package
03/02/17Monolithic 3d integration inter-tier vias insertion scheme and associated layout structure
03/02/17Semiconductor device having a conductive via structure
03/02/17Integrated circuit with electrical fuse and forming the same
03/02/17Method of forming an interconnect structure having an air gap and structure thereof
03/02/17Semiconductor device having air gap structures and fabricating thereof
03/02/17Package structures and methods of making the same
03/02/173dic package and methods of forming the same
03/02/17Semiconductor device packages, packaging methods, and packaged semiconductor devices
03/02/17Contacts to transition metal dichalcogenide and manufacturing methods thereof
03/02/17Deep trench isolation structures and methods of forming same
03/02/17Deep trench isolations and methods of forming the same
03/02/17Substrate resistor and making same
03/02/17Metal gate with silicon sidewall spacers
03/02/17Magnetoresistive random access memory cell and fabricating the same
03/02/17Package systems including passive electrical components
03/02/17Method of making a finfet device
02/23/17Semiconductor device and manufacturing method thereof
02/23/17Semiconductive structure and manufacturing method thereof
02/23/17Extreme ultraviolet lithography process and mask with reduced shadow effect and enhanced intensity
Social Network Patent Pack
02/23/17Lithography mask and fabricating the same
02/23/17Damage prevention on euv mask
02/23/17Method to define multiple layer patterns using double exposures
02/23/17Environmental-surrounding-aware opc
02/23/17Method of mask data synthesis and mask making
02/23/17Model-based rule table generation
02/23/17Flowable films and methods of forming flowable films
02/23/17Method and structure for semiconductor device having gate spacer protection layer
02/23/17Etching apparatus
02/23/17Bond chuck, methods of bonding, and tool including bond chuck
02/23/17Method of forming butted contact
02/23/17Thermal dissipation through seal rings in 3dic structure
02/23/17Structure and interconnection
02/23/17Method of forming metal interconnection
02/23/17Interconnection structure and methods of fabrication the same
02/23/17Trench liner for removing impurities in a non-copper trench
02/23/17Protrusion bump pads for bond-on-trace processing
02/23/17Electrostatic discharge protection apparatus and process
02/23/17Package structures and forming the same
02/23/17Finfet with source/drain structure and fabrication thereof
02/23/17Vertical gate-all-around field effect transistors
02/23/17Bi-directional parity bit generator circuit
02/16/17Micro-electro-mechanical system and manufacturing method thereof
02/16/17Etchant and etching process
02/16/17Method to define multiple layer patterns with a single exposure by charged particle beam lithography
02/16/17Apparatus and verification of bonding alignment
02/16/17Methods and package with interposers
02/16/17Invisible dummy features and forming the same
02/16/17Stress tuning for reducing wafer warpage

ARCHIVE: New 2016 2015 2014 2013 2012 2011 2010 2009


This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. is not affiliated or associated with Taiwan Semiconductor Manufacturing Company in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Taiwan Semiconductor Manufacturing Company with additional patents listed. Browse our Agent directory for other possible listings. Page by