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Filing Names

Taiwan Semiconductor Manufacturing Company Ltd
Taiwan Semiconductor Manufacturing Company Limited
Taiwan Semiconductor Manufacturing Company Ltd tsmc
Taiwan Semiconductor Manufacturing Company
Taiwan Semiconductor Manufacturing Company ltd
Taiwan Semiconductor Manufacturing Company Inc
Taiwan Semiconductor Manufacturing Company Limited Limited
Taiwan Semiconductor Manufacturing Company Ltd x201c tsmc x201d
Taiwan Semiconductor Manufacturing Company Ltd tsmc_20131212
Taiwan Semiconductor Manufacturing Company Ltd_20100114
Taiwan Semiconductor Manufacturing Company Tld
Taiwan Semiconductor Manufacturing Company Ltd_20131212
Taiwan Semiconductor Manufacturing Company Ltd_20100128
Taiwan Semiconductor Manufacturing Company Ltd_20100121
Taiwan Semiconductor Manufacturing Company Ltd_20100107

Taiwan Semiconductor Manufacturing Company patents

Recent patent applications related to Taiwan Semiconductor Manufacturing Company. Taiwan Semiconductor Manufacturing Company is listed as an Agent/Assignee. Note: Taiwan Semiconductor Manufacturing Company may have other listings under different names/spellings. We're not affiliated with Taiwan Semiconductor Manufacturing Company, we're just tracking patents.

ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "T" | Taiwan Semiconductor Manufacturing Company-related inventors

Date Taiwan Semiconductor Manufacturing Company patents (updated weekly) - BOOKMARK this page
05/04/17Method for fabricating self-aligned contact in a semiconductor device
04/20/17Apparatus for manufacturing a thin film and a method therefor
03/16/17Semiconductor device including fin fet and manufacturing method thereof
03/02/17Semiconductor device and manufacturing method thereof
02/23/17Semiconductor device and manufacturing method thereof
02/02/17Semiconductor device including fin structures disposed over buffer structures and manufacturing method thereof
01/26/17Finfet with doped isolation insulating layer
01/26/17Semiconductor device and manufacturing method thereof
01/12/17Integrated thermoelectric devices in fin fet technology
10/20/16Finfet semiconductor device having fins with stronger structural strength
09/01/16Reduction of edge effects from aspect ratio trapping
07/28/16Semiconductor device including fin structure with two channel layers and manufacturing method thereof
07/16/15Packaging through pre-formed metal pins
05/29/14High voltage drain-extended mosfet having extra drain-od addition
10/03/13Enhanced euv lithography system
09/19/13Method of fabricating a semiconductor device
03/10/11Method for forming a reduced active area in a phase change memory structure
07/15/10Method to produce 3-d optical gyroscope my mems technology
07/08/10Robust tsv structure
05/27/10Method and cleaning semiconductor device fabrication equipment using supercritical fluids
12/03/09Method of yield management for semiconductor manufacture and apparatus thereof
08/10/17Self-aligned nanowire formation using double patterning
09/04/14Integrated circuit using deep trench through silicon (dts)
02/06/14Method of fabricating a lithography mask
09/05/13Plasma doping to reduce dielectric loss during removal of dummy layers in a gate structure
06/17/10Strained channel transistor
10/24/13Reflective mask and making same
12/14/17 new patent  Semiconductor device
12/14/17 new patent  Fingerprint sensor in info structure and formation method
12/14/17 new patent  Sram arrays and methods of manufacturing same
12/14/17 new patent  Multi-barrier deposition for air gap formation
12/14/17 new patent  Horizontal gate-all-around device having wrapped-around source and drain
12/14/17 new patent  Interconnection structure, fabricating method thereof, and semiconductor device using the same
12/14/17 new patent  Hybrid bonding semiconductor wafers
12/14/17 new patent  Systems and methods for a sequential spacer scheme
12/14/17 new patent  Structure and cooling three-dimensional integrated circuits
12/14/17 new patent  Semiconductor device and fabrication method therefor
12/14/17 new patent  Strained channel field effect transistor
12/07/17Semiconductor method and associated apparatus
12/07/17Semiconductor device and manufacturing method thereof
12/07/17Method for manufacturing semiconductor structure
12/07/17Pellicle assembly and advanced lithography
12/07/17Finfets with strained well regions
12/07/17Double sided nmos/pmos structure and methods of forming the same
12/07/17Connector formation methods and packaged semiconductor devices
12/07/17Method of forming strained structures of semiconductor devices
11/30/17Semiconductor structure and fabricating the same
11/30/17Semiconductor structure and manufacturing method thereof
11/30/17Semiconductor structure and manufacturing the same
11/30/17Semiconductor structure and manufacturing method thereof
11/30/17Circuit with combined cells and manufacturing the same
11/30/17Semiconductor device
11/30/17Transistor structure with field plate for reducing area thereof
11/30/17Retainer ring for semiconductor manufacturing processes
11/30/17Mask with multilayer structure and manufacturing method by using the same
11/30/17Processor power estimation
11/30/17Stacked coil for wireless charging structure on info package
11/30/17Methods for improved critical dimension uniformity in a semiconductor device fabrication process
11/30/17Substrate pad structure
11/30/17Semiconductor packaging structure and process
11/30/17Testing, manufacturing, and packaging methods for semiconductor devices
11/30/173dic packaging with hot spot thermal management features
11/30/17Integrated circuit having slot via and forming the same
11/30/17Electrical fuse structure and formation
11/30/17Seal ring structure and fabrication method therefor
Patent Packs
11/30/17Bump on pad (bop) bonding structure in semiconductor packaged device
11/30/17Contact area design for solder bonding
11/30/17Structure and forming a joint assembly
11/30/17Warpage control of semiconductor die package
11/30/17Integrated circuit structure with active and passive devices in different tiers
11/30/17Package-on-package structure with epoxy flux residue
11/30/17Multi-stack package-on-package structures
11/30/17Metal gate isolation structure and ming same
11/30/17High speed semiconductor device
11/30/17Low noise device and forming the same
11/30/17Semiconductor device and method
11/30/17Low noise amplifier
11/30/17Delay line with short recovery time
11/30/17Voltage detector circuits and methods
11/23/17Chemical mechanical polishing slurry, chemical mechanical polishing and manufacturing semiconductor structure
Patent Packs
11/23/17Method of manufacturing a semiconductor structure
11/23/17Semiconductor device and fabricating method thereof
11/23/17Semiconductor structure and manufacturing method thereof
11/23/17Method for integrated circuit patterning
11/23/17Mosfets with channels on nothing and methods for forming the same
11/23/17Method of forming trenches
11/23/17Methods for hybrid wafer bonding integrated with cmos processing
11/23/17Method of forming interconnect structures by self-aligned approach
11/23/17Packaged semiconductor devices and packaging devices and methods
11/23/17Method for forming semiconductor device structure having conductive structure with twin boundaries
11/23/17Semiconductor device and manufacture
11/23/17Method of fabricating a post-passivation interconnect structure
11/23/17Antennas and waveguides in info structures
11/23/17Advanced info pop and forming thereof
11/23/17Semiconductor devices and methods of manufacture thereof
11/23/17Device and ubm/rdl routing
11/23/17Semiconductor device and manufacture
11/23/17Methods for forming integrated circuit having guard rings
11/23/17High electron mobility transistor structure and making the same
11/23/17Method for silicide formation
11/23/17Methods and structures of novel contact feature
11/23/17Two-step dummy gate formation
11/16/17Method to produce chemical pattern in micro-fluidic structure
11/16/17De-bonding and cleaning process and system
11/16/17Method of fabricating semiconductor device isolation structure
11/16/17Packages with through-vias having tapered ends
11/16/17System and immersion bonding
11/16/17Multi-stack package-on-package structures
11/16/17Structure and sram finfet device having an oxide feature
11/16/17Finfets having dielectric punch-through stoppers
Social Network Patent Pack
11/16/17Semiconductor device and manufacturing method thereof
11/16/17Source/drain junction formation
11/16/17Image sensor device and method
11/16/17Dual-band band-pass filters and use
11/09/17Method for forming interconnect structure
11/09/17Package with tilted interface between device die and encapsulating material
11/09/17Stacked semiconductor structure and method
11/09/17Method of manufacturing semiconductor device
11/09/17Semiconductor film with adhesion layer and forming the same
11/09/17Block layer in the metal gate of mos devices
Patent Packs
11/09/17Integrated circuit structure and method with solid phase diffusion
11/02/17Semiconductor mems structure and manufacturing method thereof
11/02/17Method for manufacturing semiconductor structure
11/02/17Polishing system
11/02/17Method of forming micro electromechanical system sensor
11/02/17Biosensor device and related method
11/02/17Method of generating modified layout and system therefor
11/02/17Memory macro and operating the same
11/02/17Sense amplifier circuits and methods of operation
11/02/17Anti-fuse cell structure including reading and programming devices with different gate dielectric thickness
11/02/17Optical filtering for integrated dielectrics uv curing processes
11/02/17Systems and methods for a tunable electromagnetic field apparatus to improve doping uniformity
11/02/17Global dielectric and barrier layer
11/02/17Finfets and methods of forming finfets
11/02/17Semiconductor device and manufacture
11/02/17Finfet structures and methods of forming the same
11/02/17Thermal dissipation through seal rings in 3dic structure
11/02/17Through-substrate vias with improved connections
11/02/17Dummy features in redistribution layers (rdls) and methods of forming same
11/02/17Structure and formation chip package
11/02/17Solder bump for ball grid array
11/02/17Three-layer package-on-package structure and ming same
11/02/17Integrated circuit, system for and forming an integrated circuit
11/02/17Source/drain regions in fin field effect transistors (finfets) and methods of forming same
11/02/17Method of manufacturing fins and semiconductor device which includes fins
11/02/17Method of forming finfet channel and structures thereof
11/02/17Dual facing bsi image sensors with wafer level stacking
11/02/17Methods of manufacturing semiconductor devices
11/02/17Contact for high-k metal gate device
11/02/17High-k dielectric and manufacture
Patent Packs
11/02/17Method of forming a high electron mobility transistor
11/02/17Finfets with vertical fins and methods for forming the same
11/02/17Thin-sheet finfet device
11/02/17Pll for carrier generator and generating carrier signals
10/26/17Semiconductor structure and manufacturing method thereof
10/26/17Chemical mechanical polishing apparatus and method
10/26/17Method of semiconductor fabrication with height control through active region profile
10/26/17Dummy flip chip bumps for reducing stress
10/26/17Chip on package structure and method
10/26/173dic structure and hybrid bonding semiconductor wafers
10/26/17Finfets and methods of forming finfets
10/26/17Semiconductor device and fabricating the same
10/26/17Semiconductor switching device separated by device isolation
10/26/17Image sensor comprising reflective guide layer and forming the same
10/26/17Semiconductor device and a fabricating the same
10/26/17Apparatus and finfets
10/26/17Lateral mosfet with dielectric isolation trench
10/26/17Circuit and operating circuit
10/19/17Semiconductor structure and manufacturing method thereof
10/19/17Semiconductor structure and manufacturing method thereof
Social Network Patent Pack
10/19/17Wafer carrier assembly
10/19/17Method for manufacturing a semiconductor structure comprising a semiconductor device layer formed on a temporary substrate having a graded sige etch stop layer there between
10/19/17Semiconductor structure and forming the same
10/19/17Method for manufacturing mixed-dimension and void-free mram structure
10/19/17Sram cells with vertical gate-all-round mosfets
10/19/17Thermal sensor
10/19/17Immersion lithography system using a sealed wafer bath
10/19/17Power consumption estimation system on chip (soc), system for implementing the method
10/19/17System and designing cell rows
10/19/17Semiconductor structure
10/19/17Sram structure with reduced capacitance and resistance
10/19/17Semiconductor structure and forming
10/19/17Structure and finfet device
10/19/17Wafer level embedded heat spreader
10/19/17Contact pad for semiconductor device
10/19/17Three-dimensional chip stack and forming the same
10/19/17Method and connecting packages onto printed circuit boards
10/19/17Methods and structures for packaging semiconductor dies
10/19/17Chip packages and methods of manufacture thereof
10/19/173dic formation with dies bonded to formed rdls
Social Network Patent Pack
10/19/17Device arrangement structure assembly and test method
10/19/17Finfet with trench field plate
10/19/17N-work function metal with crystal structure
10/19/17Strained structure of a semiconductor device
10/12/17Image sensing device and manufacturing method thereof
10/12/17Circuit test structure
10/12/17Static random access memory circuits
10/12/17Structure and interconnection
10/12/17Formation of getter layer for memory device
10/12/17Bonding package components through plating
10/12/17Multi-chip fan out package and methods of forming the same
10/05/17Semiconductor package devices integrated with inductor
10/05/17Semiconductor structure, electrode structure and forming the same
10/05/17Interconnect structure having an etch stop layer over conductive lines
10/05/17Monolithic 3d integration inter-tier vias insertion scheme and associated layout structure
10/05/17Alignment mark design for packages
10/05/17Semiconductor device with metal gate
10/05/17Self aligned contact scheme
10/05/17Lateral mosfet
09/28/17Semiconductor memory device and controlling the same
09/28/17Semiconductor structure and fabricating method thereof
09/28/17Bond rings in semiconductor devices and methods of forming same
09/28/17Euv lithography system and method with optimized throughput and stability
09/28/17Memory macro and operating the same
09/28/17Molding wafer chamber
09/28/17Removing polymer through treatment
09/28/17Semiconductor device and fabrication method therefor
09/28/17Semiconductor device with self-aligned contact
09/28/17Semiconductor structures and methods of forming the same
09/28/17Package structures and methods for forming the same
Social Network Patent Pack
09/28/17Interconnect structure for semiconductor devices
09/28/17Method for layout design and structure with inter-layer vias
09/28/17Method of tuning source/drain proximity for input/output device reliability enhancement
09/28/17Bsi image sensor and forming same
09/28/17Deep trench isolation structure and forming same
09/28/17Etching process control in forming mim capacitor
09/28/17Metal gate structure with device gain and yield improvement
09/28/17Fin semiconductor device and manufacture with source/drain regions having opposite conductivities
09/28/17Polysilicon design for replacement gate technology
09/28/17Method and high voltate transistors
09/28/17Finfet with a semiconductor strip as a base
09/28/17Passivated and faceted for fin field effect transistor
09/21/17Image device having multi=layered refractive layer on back surface
09/21/17Semiconductor device and manufacturing the same
09/21/17Semiconductor device, mim capacitor and associated fabricating method
09/21/17Semiconductor device
09/21/17Semiconductor structure and manufacturing method thereof
09/21/17High-electron-mobility transistor (hemt) capable of protecting iii-v compound layer
09/21/17Semiconductor device with localized carrier lifetime reduction and fabrication method thereof
09/21/17Semiconductor device and method
09/21/17Semiconductor device and method
09/21/17Methods of packaging semiconductor devices and structures thereof
09/21/17System and bonding package lid
09/21/17Interconnection structure with confinement layer
09/21/17Interconnect structure and forming same
09/21/17Bonded structures for package and substrate
09/21/17Package on package (pop) bonding structures
09/21/17Hollow metal pillar packaging scheme
09/21/17Structure and finfet sram

ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009


This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. is not affiliated or associated with Taiwan Semiconductor Manufacturing Company in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Taiwan Semiconductor Manufacturing Company with additional patents listed. Browse our Agent directory for other possible listings. Page by