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Filing Names

Taiwan Semiconductor Manufacturing Company Ltd
Taiwan Semiconductor Manufacturing Company Limited
Taiwan Semiconductor Manufacturing Company Ltd tsmc
Taiwan Semiconductor Manufacturing Company
Taiwan Semiconductor Manufacturing Company ltd
Taiwan Semiconductor Manufacturing Company Ltd tsmc_20131212
Taiwan Semiconductor Manufacturing Company Limited Limited
Taiwan Semiconductor Manufacturing Company Inc
Taiwan Semiconductor Manufacturing Company Ltd x201c tsmc x201d
Taiwan Semiconductor Manufacturing Company Ltd_20100114
Taiwan Semiconductor Manufacturing Company Tld
Taiwan Semiconductor Manufacturing Company Ltd_20131212
Taiwan Semiconductor Manufacturing Company Ltd_20100128
Taiwan Semiconductor Manufacturing Company Ltd_20100121
Taiwan Semiconductor Manufacturing Company Ltd_20100107

Taiwan Semiconductor Manufacturing Company patents

Recent patent applications related to Taiwan Semiconductor Manufacturing Company. Taiwan Semiconductor Manufacturing Company is listed as an Agent/Assignee. Note: Taiwan Semiconductor Manufacturing Company may have other listings under different names/spellings. We're not affiliated with Taiwan Semiconductor Manufacturing Company, we're just tracking patents.

ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "T" | Taiwan Semiconductor Manufacturing Company-related inventors

Date Taiwan Semiconductor Manufacturing Company patents (updated weekly) - BOOKMARK this page
05/04/17Method for fabricating self-aligned contact in a semiconductor device
04/20/17Apparatus for manufacturing a thin film and a method therefor
03/16/17Semiconductor device including fin fet and manufacturing method thereof
03/02/17Semiconductor device and manufacturing method thereof
02/23/17Semiconductor device and manufacturing method thereof
02/02/17Semiconductor device including fin structures disposed over buffer structures and manufacturing method thereof
01/26/17Finfet with doped isolation insulating layer
01/26/17Semiconductor device and manufacturing method thereof
01/12/17Integrated thermoelectric devices in fin fet technology
10/20/16Finfet semiconductor device having fins with stronger structural strength
09/01/16Reduction of edge effects from aspect ratio trapping
07/28/16Semiconductor device including fin structure with two channel layers and manufacturing method thereof
07/16/15Packaging through pre-formed metal pins
05/29/14High voltage drain-extended mosfet having extra drain-od addition
10/03/13Enhanced euv lithography system
09/19/13Method of fabricating a semiconductor device
03/10/11Method for forming a reduced active area in a phase change memory structure
07/15/10Method to produce 3-d optical gyroscope my mems technology
07/08/10Robust tsv structure
05/27/10Method and cleaning semiconductor device fabrication equipment using supercritical fluids
12/03/09Method of yield management for semiconductor manufacture and apparatus thereof
09/04/14Integrated circuit using deep trench through silicon (dts)
02/06/14Method of fabricating a lithography mask
09/05/13Plasma doping to reduce dielectric loss during removal of dummy layers in a gate structure
06/17/10Strained channel transistor
10/24/13Reflective mask and making same
06/22/17 new patent  System and method to diagnose integrated circuit
06/22/17 new patent  Semiconductor integrated circuit
06/22/17 new patent  Power mosfets and methods for manufacturing the same
06/22/17 new patent  Semiconductor device and circuit protecting method
06/22/17 new patent  Method of fabricating an integrated circuit with non-printable dummy features
06/22/17 new patent  Pellicle assembly and advanced lithography
06/22/17 new patent  Photoresist and method
06/22/17 new patent  Bandgap reference circuit
06/22/17 new patent  Ion beam generator, ion implantation apparatus including an ion beam generator and using an ion beam generator
06/22/17 new patent  Via corner engineering in trench-first dual damascene process
06/22/17 new patent  Trench liner for removing impurities in a non-copper trench
06/22/17 new patent  Gate device over strained fin structure
06/22/17 new patent  Method of manufacturing semiconductor device and semicondcutor device
06/22/17 new patent  Interposer test structures and methods
06/22/17 new patent  Method of forming trenches
06/22/17 new patent  Contact pad for semiconductor devices
06/22/17 new patent  Method of forming metal pads with openings in integrated circuits including forming a polymer extending into a metal pad
06/22/17 new patent  Semiconductor device structure comprising a plurality of metal oxide fibers and forming the same
06/22/17 new patent  Semiconductor packaging structure and method
06/22/17 new patent  Methods for forming semiconductor device structures
06/22/17 new patent  Mos devices with non-uniform p-type impurity profile
06/22/17 new patent  Finfets with strained well regions
06/22/17 new patent  Finfets with wrap-around silicide and ming the same
06/22/17 new patent  Amplifier and operating same
06/22/17 new patent  Methods of forming metal pad structures over tsvs to reduce shorting of upper metal layers
06/15/17System, method and associated computer readable medium for designing integrated circuit with pre-layout rc information
06/15/17Method of determining galvanic corrosion and interconnect structure in a semiconductor device for prevention of galvanic corrosion
06/15/17Scrambling apparatus and method thereof
06/15/17Semiconductor structure and manufacturing method thereof
06/15/17High voltage ldmos transistor and methods for manufacturing the same
06/15/17Semiconductor structure and forming the same
06/15/17Semiconductor devices with moving members and methods for making the same
06/15/17Material delivery system and method
06/15/17Layout hierachical structure defined in polar coordinate
06/15/17Image mask film scheme and method
06/15/17Memory array and forming the same
06/15/17Finfet doping methods and structures thereof
06/15/17Finfet low resistivity contact formation method
06/15/17Method of semiconductor integrated circuit fabrication
Patent Packs
06/15/17Finfet doping methods and structures thereof
06/15/17Via connection to a partially filled trench
06/15/17Packages with molding structures and methods of forming the same
06/15/17Eliminate sawing-induced peeling through forming trenches
06/15/17Semiconductor device and method
06/15/17Integrated circuit structure and reducing polymer layer delamination
06/15/17Pixel isolation device and fabrication method
06/15/17Integrated circuit structure and method with solid phase diffusion
06/15/17Method of forming self-alignment contact
06/15/17High electron mobility transistor structure
06/15/17Semiconductor device and manufacturing same
06/15/17Source and drain stressors with recessed top surfaces
06/15/17High-mobility multiple-gate transistor with improved on-to-off current ratio
06/15/17Flip flop circuit and operating the same
06/15/17Communication system and data communications
Patent Packs
06/15/17Radio frequency interconnect having a preamble generator
06/15/17Pll with clock and data recovery function for receiver phase synchronization
06/15/17Info coil on metal plate with slot
06/08/17Differential current sensing scheme for magnetic random access memory
06/08/17Semiconductor device and manufacturing the same
06/08/17Semiconductor mixed gate structure
06/08/17Resistive random access memory and manufacturing method thereof
06/08/17Mems device structure with a capping structure
06/08/17Cmp slurry solution for hardened fluid material
06/08/17Method of making a metal grating in a waveguide and device formed
06/08/17Method of designing a semiconductor device, system for implementing the method and standard cell
06/08/17Method and semiconductor planarization
06/08/17Method of spacer patterning to form a target integrated circuit pattern
06/08/17Semiconductor devices and methods of forming same
06/08/17Metal line structure and method
06/08/17Interconnect structure and forming same
06/08/17Antennas and waveguides in info structures
06/08/17Packages with thermal management features for reduced thermal crosstalk and methods of forming same
06/08/17Semiconductor device and manufactures
06/08/17Method for manufacturing static random access memory device
06/08/17Backside structure and methods for bsi image sensors
06/08/17Method of forming the gate electrode of field effect transistor
06/01/17Semiconductor structure and operating the same
06/01/17Mask blank and mask and fabrication method thereof
06/01/17Spacer structure and manufacturing method thereof
06/01/17Method of manufacturing semiconductor device
06/01/17Semiconductor device and manufacturing method thereof
06/01/17Semiconductor device and manufacturing the same
06/01/17Semiconductor device structure and manufacturing method thereof
06/01/17Dislocation smt for finfet device
Social Network Patent Pack
06/01/17Sram structure with reduced capacitance and resistance
06/01/17Anti-fuse cell structure including reading and programming devices with different gate dielectric thickness
06/01/17Semiconductor devices and methods of manufacture thereof
06/01/17Semiconductor device packages, packaging methods, and packaged semiconductor devices
06/01/17Wafer level chip scale package interconnects and methods of manufacture thereof
06/01/17Interconnect structure and methods of making same
06/01/17Fets and methods of forming fets
06/01/17Nano wire structure and fabricating the same
06/01/17Semiconductor device having air gap structures and fabricating thereof
06/01/17Packaged semiconductor devices, methods of packaging semiconductor devices, and pop devices
Patent Packs
06/01/17Methods of forming connector pad structures, interconnect structures, and structures thereof
06/01/17Discrete polymer in fan-out packages
06/01/17Multi-gate device and fabrication thereof
06/01/17Graphene transistor and related methods
06/01/17Channel loss compensation circuits
05/25/17Sram device capable of working in multiple low voltages without loss of performance
05/25/17Device manufacture and packaging method thereof
05/25/17Semiconductor structure and manufacturing the same
05/25/17Semiconductor structure and forming the same
05/25/17Minimizing harmful effects caused by reticle defects by re-arranging ic layout locally
05/25/17Synchronous random access memory (sram) chip and two port sram array
05/25/17Semiconductor devices and methods for manufacturing the same
05/25/17Semiconductor device and process
05/25/17Low-k dielectric layer and porogen
05/25/17Package system for integrated circuits
05/25/17Interconnect structure for semiconductor devices
05/25/17Singulation and bonding methods and structures formed thereby
05/25/173dic packages with heat dissipation structures
05/25/17Integrated circuit packages and methods of forming same
05/25/17Package structures and methods of forming the same
05/25/17Integrated circuit structure and method with solid phase diffusion
05/25/17Method for fabricating a strained structure and structure formed
05/18/17Layout modification method and system
05/18/17Semiconductor structure and manufacturing method thereof
05/18/17Semiconductor package and forming the same
05/18/17Cmp polishing head design for improving removal rate uniformity
05/18/17Acoustic measurement of fabrication equipment clearance
05/18/17Method for repairing a mask
05/18/17Method and system for euv mask cleaning with non-thermal solution
05/18/17Fingerprint sensor device and method
Patent Packs
05/18/17Compact vertical inductors extending in vertical planes
05/18/17Treatment process and system
05/18/17Method of forming ultra-thin nanowires
05/18/17Method for forming stacked nanowire transistors
05/18/17Self-aligned dual-metal silicide and germanide formation
05/18/17Semiconductor device and method
05/18/17Apparatus and wafer level bonding
05/18/17Multi-barrier deposition for air gap formation
05/18/17Horizontal gate-all-around device having wrapped-around source and drain
05/18/17Active atomic reservoir for enhancing electromigration reliability in integrated circuits
05/18/17Methods and structrues of novel contact feature
05/18/17Methods and apparatus of guard rings for wafer-level-packaging
05/18/17Seal rings structures in semiconductor device interconnect layers and methods of forming the same
05/18/17Integrated fan-out structure and forming
05/18/17Package with solder regions aligned to recesses
05/18/17Chip packages and methods of manufacture thereof
05/18/17Conductive external connector structure and forming
05/18/17Post-passivation interconnect structure and forming same
05/18/17Metal bump joint structure and methods of forming
05/18/17Mechanisms for forming hybrid bonding structures with elongated bumps
Social Network Patent Pack
05/18/17Semiconductor device and manufacture
05/18/17Finfet-based esd devices and methods for forming the same
05/18/17Method and structure for semiconductor mid-end-of-line (meol) process
05/18/17Multi-gate device and fabrication thereof
05/18/17Discrete storage element formation for thin-film storage device
05/18/17Method of cutting metal gate
05/18/17Devices including gate spacer with gap or void and methods of forming the same
05/18/17Integrated circuit structure with substrate isolation and un-doped channel
05/18/17Negative capacitance field effect transistor with charged dielectric material
05/18/17Resistive ram structure and fabrication thereof
05/18/17Demodulator, receiver and data communications
05/18/17Pixel unit cell having conversion circuit
05/18/17Network-assisted channel selection and power control for mobile devices
05/11/17Semiconductor structure and manufacturing method thereof
05/11/17Semiconductor device and fabricating the same
05/11/17Semiconductor structure and manufacturing the same
05/11/17Interconnect structure with misaligned metal lines coupled using different interconnect layer
05/11/17Semiconductor device and forming the same
05/11/17High-electron-mobility transistor and manufacturing method thereof
05/11/17Fabrication and structures of crystalline material
Social Network Patent Pack
05/11/17Apparatus and finfets
05/11/17Memory devices and fabricating same
05/11/17Inverters and manufacturing methods thereof
05/11/17Chip-on-wafer process control monitoring for chip-on-wafer-on-substrate packages
05/11/17Conductive structure and forming the same
05/11/17Pad structure design in fan-out package
05/11/17Bump structure for yield improvement
05/11/17Integrated circuit process having alignment marks for underfill
05/11/17Method and structure for finfet devices
05/11/17Integrated circuit having a vertical power mos transistor
05/11/17Semiconductor device and manufacturing method thereof
05/11/17Memory devices and fabricating same
05/11/17Capacitor and making same
05/11/17Circuit structure, transistor and semiconductor device
05/11/17Replacement gate process for finfet
05/11/17Structure and formation semiconductor device structure
05/11/17Source/drain regions for fin field effect transistors and methods of forming same
05/11/17Delay line circuit
05/11/17Sensor having depth sensing pixel and using the same
05/04/17Probe head receiver and probe card assembly having the same
05/04/17Hybrid semiconductor structure on a common substrate
05/04/17Metal gate structure and manufacturing method thereof
05/04/17Method of fabricating semiconductor structure
05/04/17Semiconductor device having a guard ring
05/04/17Semiconductor device
05/04/17Non-volatile memory and manufacturing method thereof
05/04/17High voltage semiconductor device
05/04/17Schottky diode having a well with peripherial cathod regions and center andoe region
05/04/17Semiconductor structure and manufacturing method thereof
05/04/17Semiconductor device with discrete blocks
Social Network Patent Pack
05/04/17Layout optimization of a main pattern and a cut pattern
05/04/17Circuit and generating a sense amplifier enable signal
05/04/17Semiconductor device metallization systems and methods
05/04/17Finfet devices with unique fin shape and the fabrication thereof
05/04/17Moving pyrometer for use with a substrate chamber
05/04/17Polymer-based-semiconductor structure with cavity
05/04/17Self-aligned interconnection structure and method
05/04/17Package structures and methods of making the same
05/04/17Metal pad for laser marking
05/04/17Connector formation methods and packaged semiconductor devices
05/04/17Packages with solder ball revealed through layer
05/04/17Rework process and tool design for semiconductor package
05/04/17System on integrated chips and methods of forming same
05/04/17Stacked integrated circuit structure and forming
05/04/17Elongated semiconductor structure planarization
05/04/17Oxidation and etching post metal gate cmp
05/04/17Devices having a semiconductor material that is semimetal in bulk and methods of forming the same
05/04/17Field-effect transistor with dual vertical gates
05/04/17Channel strain control for nonplanar compound semiconductor devices
05/04/17Input/output circuit
05/04/17Digital code recovery with preamble
04/27/17Characterizing cell using input waveforms with different tail characteristics
04/27/17Network logic synthesis
04/27/17Methods of forming strained-semiconductor-on-insulator device structures
04/27/17Semiconductor devices with bump allocation
04/27/17Interconnection structure and forming same
04/27/17Semiconductor packages and methods of forming the same
04/27/17Contact resistance reduction technique
04/27/17Semiconductor liner of semiconductor device

ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009


This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. is not affiliated or associated with Taiwan Semiconductor Manufacturing Company in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Taiwan Semiconductor Manufacturing Company with additional patents listed. Browse our Agent directory for other possible listings. Page by