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Tela Innovations Inc
Tela Innovations Inc A Delaware Corporation
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Tela Innovations Inc patents

Recent patent applications related to Tela Innovations Inc. Tela Innovations Inc is listed as an Agent/Assignee. Note: Tela Innovations Inc may have other listings under different names/spellings. We're not affiliated with Tela Innovations Inc, we're just tracking patents.

ARCHIVE: New 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "T" | Tela Innovations Inc-related inventors




Date Tela Innovations Inc patents (updated weekly) - BOOKMARK this page
04/13/17Methods for cell boundary encroachment and semiconductor devices implementing the same
04/06/17Enforcement of semiconductor structure regularity for localized transistors and interconnect
02/23/17Semiconductor chip and manufacturing the same
12/29/16Semiconductor chip and manufacturing the same
12/08/16Methods for cell phasing and placement in dynamic array architecture and implementation of the same
12/08/16Oversized contacts and vias in layout defined by linearly constrained topology
10/13/16Methods for multi-wire routing and apparatus implementing same
09/01/16Coarse grid design methods and structures
06/30/16Super-self-aligned contacts and making the same
06/16/16Methods for cell boundary encroachment and semiconductor devices implementing the same
05/12/16Methods, structures, and designs for self-aligning local interconnects used in integrated circuits
05/12/16Methods, structures, and designs for self-aligning local interconnects used in integrated circuits
04/28/16Oversized contacts and vias in layout defined by linearly constrained topology
03/17/16Enforcement of semiconductor structure regularity for localized transistors and interconnect
03/17/16Semiconductor chip including integrated circuit having cross-coupled transistor configuration and manufacturing the same
03/17/16Semiconductor chip including integrated circuit including at least five gate level conductive structures having particular spatial and electrical relationship and manufacturing the same
01/28/16Methods for linewidth modification and apparatus implementing the same
12/17/15Methods for controlling microloading variation in semiconductor wafer layout and fabrication
09/24/15Semiconductor chip including integrated circuit including four transistors of first transistor type and four transistors of second transistor type with electrical connections between various transistors and methods for manufacturing the same
09/03/15Semiconductor chip including region having integrated circuit transistor gate electrodes formed by various conductive structures of specified shape and position and manufacturing the same
07/02/15Semiconductor chip including digital logic circuit including at least six transistors with some transistors forming cross-coupled transistor configuration and associated methods
05/21/15Methods for cell phasing and placement in dynamic array architecture and implementation of the same
04/02/15Super-self-aligned contacts and making the same
12/25/14Scalable meta-data objects
12/18/14Semiconductor chip including digital logic circuit including at least nine linear-shaped conductive structures collectively forming gate electrodes of at least six transistors with some transistors forming cross-coupled transistor configuration and associated methods
09/04/14Semiconductor chip including integrated circuit defined within dynamic array section
08/28/14Semiconductor chip including region having cross-coupled transistor configuration with offset electrical connection areas on gate electrode forming conductive structures and at least two different inner extension distances of gate electrode forming conductive struc
08/28/14Standard cells having transistors annotated for gate-length biasing
08/07/14Gate-length biasing for digital circuit optimization
07/31/14Integrated circuit within semiconductor chip including cross-coupled transistor configuration
07/17/14Enforcement of semiconductor structure regularity for localized transistors and interconnect
06/26/14Integrated circuit cell library for multiple patterning
06/19/14Methods for cell boundary encroachment and layouts implementing the same
06/19/14Coarse grid design methods and structures
06/19/14Methods, structures, and designs for self-aligning local interconnects used in integrated circuits
06/12/14Circuitry and layouts for xor and xnor logic
02/06/14Methods for cell phasing and placement in dynamic array architecture and implementation of the same
01/30/14Super-self-aligned contacts and making the same
10/03/13Optimizing layout of irregular structures in regular layout context
09/26/13Enforcement of semiconductor structure regularity for localized transistors and interconnect
09/26/13Standard cells having transistors annotated for gate-length biasing
08/22/13Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate contact position and offset specifications
05/23/13Coarse grid design methods and structures
01/10/13Standard cells having transistors annotated for gate-length biasing
01/10/13Standard cells having transistors annotated for gate-length biasing
01/10/13Standard cells having transistors annotated for gate-length biasing
12/06/12Integrated circuit including cross-coupled transistors with two transistors of different type having gate electrodes formed by common gate level feature with shared diffusion regions on opposite sides of common gate level feature
11/01/12Methods for cell phasing and placement in dynamic array architecture and implementation of the same
06/07/12Scalable meta-data objects
05/17/12Methods for linewidth modification and apparatus implementing the same
11/17/11Methods, structures, and designs for self-aligning local interconnects used in integrated circuits
08/18/11Methods for multi-wire routing and apparatus implementing same
07/21/11Integrated circuit device including dynamic array section with gate level having linear conductive features on at least three side-by-side lines and uniform line end spacings
06/30/11Methods for consumption of timing margin to reduce power utilization in integrated circuitry and device implementing the same
06/30/11Methods for designing semiconductor device with dynamic array section
05/12/11Semiconductor device with dynamic array sections defined and placed according to manufacturing assurance halos
05/12/11Semiconductor device with dynamic array sections defined and placed according to manufacturing assurance halos
04/14/11Methods for cell boundary encroachment and layouts implementing the same
12/02/10Integrated circuit cell library with cell-level process compensation technique (pct) application and associated methods
11/11/10Cell circuit and layout with linear finfet structures
11/04/10Circuitry and layouts for xor and xnor logic
10/14/10Channelized gate level cross-coupled transistor device with cross-coupled transistor gate electrode connections made using linear first interconnect level above gate electrode level
10/07/10Linear gate level cross-coupled transistor device with contiguous p-type diffusion regions and contiguous n-type diffusion regions
10/07/10Linear gate level cross-coupled transistor device with non-overlapping pmos transistors and non-overlapping nmos transistors relative to direction of gate electrodes
10/07/10Linear gate level cross-coupled transistor device with equal width pmos transistors and equal width nmos transistors
Patent Packs
10/07/10Channelized gate level cross-coupled transistor device with different width pmos transistors and different width nmos transistors
10/07/10Channelized gate level cross-coupled transistor device with cross-coupled transistors defined on three gate electrode tracks with crossing gate electrode connections
10/07/10Methods, structures, and designs for self-aligning local interconnects used in integrated circuits
09/23/10Linear gate level cross-coupled transistor device with cross-coupled transistor gate electrode connections made using linear first interconnect level above gate electrode level
09/23/10Channelized gate level cross-coupled transistor device with contiguous p-type diffusion regions and contiguous n-type diffusion regions
09/23/10Channelized gate level cross-coupled transistor device with non-overlapping pmos transistors and overlapping nmos transistors relative to direction of gate electrodes
09/23/10Channelized gate level cross-coupled transistor device with non-overlapping pmos transistors and non-overlapping nmos transistors relative to direction of gate electrodes
09/23/10Channelized gate level cross-coupled transistor device with equal width pmos transistors and equal width nmos transistors
07/29/10Linear gate level cross-coupled transistor device with direct electrical connection of cross-coupled transistors to common diffusion node
07/29/10Linear gate level cross-coupled transistor device with overlapping pmos transistors and overlapping nmos transistors relative to direction of gate electrodes
07/29/10Linear gate level cross-coupled transistor device with non-overlapping pmos transistors and overlapping nmos transistors relative to direction of gate electrodes
07/29/10Linear gate level cross-coupled transistor device with overlapping pmos transistors and non-overlapping nmos transistors relative to direction of gate electrodes
07/29/10Linear gate level cross-coupled transistor device with different width pmos transistors and different width nmos transistors
07/29/10Linear gate level cross-coupled transistor device with connection between cross-coupled transistor gate electrodes made utilizing interconnect level other than gate electrode level
07/29/10Linear gate level cross-coupled transistor device with constant gate electrode pitch
Patent Packs
07/29/10Linear gate level cross-coupled transistor device with complimentary pairs of cross-coupled transistors defined by physically separate gate electrodes within gate electrode level
07/29/10Linear gate level cross-coupled transistor device with cross-coupled transistors defined on two gate electrode tracks with crossing gate electrode connections
07/29/10Linear gate level cross-coupled transistor device with cross-coupled transistors defined on three gate electrode tracks with crossing gate electrode connections
07/29/10Linear gate level cross-coupled transistor device with cross-coupled transistors defined on four gate electrode tracks with crossing gate electrode connections
07/29/10Channelized gate level cross-coupled transistor device with direct electrical connection of cross-coupled transistors to common diffusion node
07/29/10Channelized gate level cross-coupled transistor device with overlapping pmos transistors and overlapping nmos transistors relative to direction of gate electrodes
07/29/10Channelized gate level cross-coupled transistor device with overlapping pmos transistors and non-overlapping nmos transistors relative to direction of gate electrodes
07/29/10Channelized gate level cross-coupled transistor device with connection between cross-coupled transistor gate electrodes made utilizing interconnect level other than gate electrode level
07/29/10Channelized gate level cross-coupled transistor device with constant gate electrode pitch
07/29/10Channelized gate level cross-coupled transistor device with complimentary pairs of cross-coupled transistors defined by physically separate gate electrodes within gate electrode level
07/29/10Channelized gate level cross-coupled transistor device with cross-coupled transistors defined on two gate electrode tracks with crossing gate electrode connections
07/29/10Channelized gate level cross-coupled transistor device with cross-coupled transistors defined on four gate electrode tracks with crossing gate electrode connections
04/22/10Cell of semiconductor device having gate electrode conductive structures formed from rectangular shaped gate electrode layout features and at least eight transistors
02/11/10Semiconductor device portion having sub-193 nanometers -sized gate electrode conductive structures formed from linear shaped gate electrode layout features defined with minimum end-to-end spacing and having equal number of pmos and nmos transistors
02/11/10Semiconductor device portion having gate electrode conductive structures formed from linear shaped gate electrode layout features defined with minimum end-to-end spacing and having at least eight transistors
02/11/10Semiconductor device portion having sub-wavelength-sized gate electrode conductive structures formed from linear shaped gate electrode layout features defined with minimum end-to-end spacing and having at least eight transistors
02/11/10Cell of semiconductor device having sub-193 nanometers-sized gate electrode conductive structures formed from rectangular shaped gate electrode layout features and equal number of pmos and nmos transistors
02/11/10Semiconductor device portion having sub-193 nanometers -sized gate electrode conductive structures formed from linear shaped gate electrode layout features defined along at least four gate electrode tracks with minimum end-to-end spacing and having corresponding non-symmetric diffusion regions
02/11/10Layout of cell of semiconductor device having linear shaped gate electrode layout features defined with minimum end-to-end spacing and having equal number of pmos and nmos transistors
02/11/10Layout of cell of semiconductor device having linear shaped gate electrode layout features defined with minimum end-to-end spacing and having equal number of pmos and nmos transistors and having corresponding p-type and n-type diffusion regions separated by central inactive region
02/04/10Cell of semiconductor device having gate electrode conductive structures formed from linear shaped gate electrode layout features defined with minimum end-to-end spacing and equal number of pmos and nmos transistors
02/04/10Cell of semiconductor device having sub-wavelength-sized gate electrode conductive structures formed from linear shaped gate electrode layout features defined with minimum end-to-end spacing and at least eight transistors
02/04/10Cell of semiconductor device having sub-193 nanometers-sized gate electrode conductive structures formed from linear shaped gate electrode layout features defined with minimum end-to-end spacing and at least eight transistors
02/04/10Cell of semiconductor device having sub-wavelength-sized gate electrode conductive structures formed from linear shaped gate electrode layout features defined with minimum end-to-end spacing and equal number of pmos and nmos transistors
02/04/10Cell of semiconductor device having sub-193 nanometers-sized gate electrode conductive structures formed from linear shaped gate electrode layout features defined with minimum end-to-end spacing and equal number of pmos and nmos transistors
02/04/10Cell of semiconductor device having gate electrode conductive structures formed from linear shaped gate electrode layout features defined with minimum end-to-end spacing and at least eight transistors
02/04/10Methods for controlling microloading variation in semiconductor wafer layout and fabrication
01/28/10Cell of semiconductor device having gate electrode conductive structures formed from rectangular shaped gate electrode layout features defined along at least four gate electrode tracks
01/28/10Cell of semiconductor device having sub-wavelength-sized gate electrode conductive structures formed from rectangular shaped gate electrode layout features defined along at least four gate electrode tracks
01/28/10Cell of semiconductor device having sub-193 nanometers-sized gate electrode conductive structures formed from rectangular shaped gate electrode layout features defined along at least four gate electrode tracks
Social Network Patent Pack
01/28/10Cell of semiconductor device having sub-wavelength-sized gate electrode conductive structures formed from rectangular shaped gate electrode layout features and equal number of pmos and nmos transistors
01/28/10Cell of semiconductor device having sub-wavelength-sized gate electrode conductive structures formed from rectangular shaped gate electrode layout features and at least eight transistors
01/28/10Cell of semiconductor device having sub-193 nanometers-sized gate electrode conductive structures formed from rectangular shaped gate electrode layout features and at least eight transistors
01/28/10Cell of semiconductor device having gate electrode conductive structures formed from linear shaped gate electrode layout features defined along at least four gate electrode tracks with minimum end-to-end spacing
01/28/10Cell of semiconductor device having sub-193 nanometers-sized gate electrode conductive structures formed from linear shaped gate electrode layout features defined along at least four gate electrode tracks with minimum end-to-end spacing
01/28/10Cell of semiconductor device having sub-wavelength-sized gate electrode conductive structures formed from linear shaped gate electrode layout features defined along at least four gate electrode tracks with minimum end-to-end spacing
01/28/10Layout of cell of semiconductor device having linear shaped gate electrode layout features defined along at least four gate electrode tracks with minimum end-to-end spacing
01/28/10Layout of cell of semiconductor device having linear shaped gate electrode layout features defined along at least four gate electrode tracks with minimum end-to-end spacing and having corresponding p-type and n-type diffusion regions separated by central inactive region
01/28/10Layout of cell of semiconductor device having linear shaped gate electrode layout features defined with minimum end-to-end spacing and having at least eight transistors and having corresponding p-type and n-type diffusion regions separated by central inactive region
01/28/10Layout of cell of semiconductor device having linear shaped gate electrode layout features defined with minimum end-to-end spacing and having at least eight transistors
Patent Packs
01/21/10Semiconductor device portion having gate electrode conductive structures formed from linear shaped gate electrode layout features defined along at least four gate electrode tracks with minimum end-to-end spacing and having corresponding non-symmetric diffusion regions
01/21/10Semiconductor device portion having sub-wavelength-sized gate electrode conductive structures formed from linear shaped gate electrode layout features defined along at least four gate electrode tracks with minimum end-to-end spacing and having corresponding non-symmetric diffusion regions
01/21/10Semiconductor device portion having gate electrode conductive structures formed from linear shaped gate electrode layout features defined with minimum end-to-end spacing and having equal number of pmos and nmos transistors
01/21/10Semiconductor device portion having sub-wavelength-sized gate electrode conductive structures formed from linear shaped gate electrode layout features defined with minimum end-to-end spacing and having equal number of pmos and nmos transistors
01/21/10Semiconductor device portion having sub-193 nanometers -sized gate electrode conductive structures formed from linear shaped gate electrode layout features defined with minimum end-to-end spacing and having at least eight transistors
01/21/10Cell of semiconductor device having gate electrode conductive structures formed from rectangular shaped gate electrode layout features and equal number of pmos and nmos transistors
01/21/10Semiconductor device layout including cell layout having restricted gate electrode level layout with linear shaped gate electrode layout features defined with minimum end-to-end spacing and at least eight transistors
01/21/10Layout of cell of semiconductor device having rectangular shaped gate electrode layout features defined along at least four gate electrode tracks
01/21/10Layout of cell of semiconductor device having rectangular shaped gate electrode layout features defined along at least four gate electrode tracks with corresponding p-type and n-type diffusion regions separated by central inactive region
01/21/10Layout of cell of semiconductor device having rectangular shaped gate electrode layout features and equal number of pmos and nmos transistors
01/21/10Layout of cell of semiconductor device having rectangular shaped gate electrode layout features and equal number of pmos and nmos transistors with corresponding p-type and n-type diffusion regions separated by central inactive region
01/21/10Layout of cell of semiconductor device having rectangular shaped gate electrode layout features and at least eight transistors
01/21/10Layout of cell of semiconductor device having rectangular shaped gate electrode layout features and at least eight transistors with corresponding p-type and n-type diffusion regions separated by central inactive region
01/14/10Semiconductor device layout including cell layout having restricted gate electrode level layout with rectangular shaped gate electrode layout features and at least eight transistors
01/14/10Semiconductor device portion having gate electrode conductive structures formed from rectangular shaped gate electrode layout features and having equal number of pmos and nmos transistors
01/14/10Semiconductor device portion having sub-wavelength-sized gate electrode conductive structures formed from rectangular shaped gate electrode layout features and having equal number of pmos and nmos transistors
01/14/10Semiconductor device portion having gate electrode conductive structures formed from rectangular shaped gate electrode layout features defined along at least four gate electrode tracks and having corresponding non-symmetric diffusion regions
01/14/10Semiconductor device portion having sub-wavelength-sized gate electrode conductive structures formed from rectangular shaped gate electrode layout features defined along at least four gate electrode tracks and having corresponding non-symmetric diffusion regions
01/14/10Semiconductor device portion having sub-193 nanometers-sized gate electrode conductive structures formed from rectangular shaped gate electrode layout features defined along at least four gate electrode tracks and having corresponding non-symmetric diffusion regions
01/14/10Semiconductor device portion having sub-wavelength-sized gate electrode conductive structures formed from rectangular shaped gate electrode layout features and having at least eight transistors
01/14/10Semiconductor device portion having sub-193 nanometers -sized gate electrode conductive structures formed from rectangular shaped gate electrode layout features and having at least eight transistors
01/14/10Semiconductor device portion having gate electrode conductive structures formed from rectangular shaped gate electrode layout features and having at least eight transistors
01/14/10Semiconductor device portion having sub-193 nanometers -sized gate electrode conductive structures formed from rectangular shaped gate electrode layout features and having equal number of pmos and nmos transistors
01/14/10Semiconductor device layout including cell layout having restricted gate electrode level layout with rectangular shaped gate electrode layout features defined along at least four gate electrode tracks with corresponding non-symmetric diffusion regions
01/14/10Semiconductor device layout having restricted layout region including rectangular shaped gate electrode layout features and at least eight transistors
01/14/10Semiconductor device layout including cell layout having restricted gate electrode level layout with linear shaped gate electrode layout features defined with minimum end-to-end spacing and equal number of pmos and nmos transistors
01/14/10Semiconductor device layout including cell layout having restricted gate electrode level layout with rectangular shaped gate electrode layout features and equal number of pmos and nmos transistors
01/14/10Semiconductor device layout having restricted layout region including linear shaped gate electrode layout features defined along at least four gate electrode tracks with minimum end-to-end spacing with corresponding non-symmetric diffusion regions
01/14/10Semiconductor device layout including cell layout having restricted gate electrode level layout with linear shaped gate electrode layout features defined along at least four gate electrode tracks with minimum end-to-end spacing with corresponding non-symmetric diffusion regions
01/14/10Semiconductor device layout having restricted layout region including linear shaped gate electrode layout features defined with minimum end-to-end spacing and equal number of pmos and nmos transistors
Patent Packs
01/14/10Semiconductor device layout having restricted layout region including linear shaped gate electrode layout features defined with minimum end-to-end spacing and at least eight transistors
01/14/10Semiconductor device layout having restricted layout region including rectangular shaped gate electrode layout features and equal number of pmos and nmos transistors
01/07/10Semiconductor device layout having restricted layout region including rectangular shaped gate electrode layout features defined along at least four gate electrode tracks with corresponding non-symmetric diffusion regions
12/03/09Methods for defining and using co-optimized nanopatterns for integrated circuit design and apparatus implementing same
10/29/09Methods for cell phasing and placement in dynamic array architecture and implementation of the same
09/10/09Cross-coupled transistor layouts in restricted gate level layout architecture
09/10/09Methods for multi-wire routing and apparatus implementing same
09/10/09Methods for defining contact grid in dynamic array architecture
09/10/09Enforcement of semiconductor structure regularity for localized transistors and interconnect
06/18/09Super-self-aligned contacts and making the same
05/21/09Diffusion variability control and transistor device sizing using threshold voltage implant
04/30/09Methods, structures and designs for self-aligning local interconnects used in integrated circuits
04/16/09Methods and systems for process compensation technique acceleration
02/05/09Methods for defining dynamic array section with manufacturing assurance halo and apparatus implementing the same
02/05/09Semiconductor device with dynamic array section
02/05/09Methods for designing semiconductor device with dynamic array section
01/28/10Layout of cell of semiconductor device having linear shaped gate electrode layout features defined with minimum end-to-end spacing and having at least eight transistors
01/21/10Layout of cell of semiconductor device having rectangular shaped gate electrode layout features and at least eight transistors with corresponding p-type and n-type diffusion regions separated by central inactive region
01/14/10Semiconductor device layout having restricted layout region including rectangular shaped gate electrode layout features and equal number of pmos and nmos transistors
01/07/10Semiconductor device layout having restricted layout region including rectangular shaped gate electrode layout features defined along at least four gate electrode tracks with corresponding non-symmetric diffusion regions
Social Network Patent Pack
07/01/10Methods for gate-length biasing using annotation data
07/01/10Standard cells having transistors annotated for gate-length biasing







ARCHIVE: New 2016 2015 2014 2013 2012 2011 2010 2009



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