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Tela Innovations Inc
Tela Innovations Inc A Delaware Corporation
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Tela Innovations Inc patents


Recent patent applications related to Tela Innovations Inc. Tela Innovations Inc is listed as an Agent/Assignee. Note: Tela Innovations Inc may have other listings under different names/spellings. We're not affiliated with Tela Innovations Inc, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "T" | Tela Innovations Inc-related inventors


Methods for multi-wire routing and apparatus implementing same

A rectangular interlevel connector array (RICA) is defined in a semiconductor chip. To define the RICA, a virtual grid for interlevel connector placement is defined to include a first set of parallel virtual lines that extend across the layout in a first direction, and a second set of parallel virtual... Tela Innovations Inc

Optimizing layout of irregular structures in regular layout context

A plurality of regular wires are formed within a given chip level, each having a linear-shape with a length extending in a first direction and a width extending in a second direction perpendicular to the first direction. The plurality of regular wires are positioned according to a fixed pitch such... Tela Innovations Inc

Semiconductor chip and manufacturing the same

Gate structures formed from substantially rectangular shaped gate structure layout shapes positioned on a gate horizontal grid having at least seven gate gridlines within a region. A first-metal layer including first-metal structures formed from substantially rectangular shaped first-metal structure layout shapes is formed above top surfaces of the gate structures... Tela Innovations Inc

Semiconductor chip and manufacturing the same

Gate structures are positioned within a region in accordance with a gate horizontal grid that includes at least seven gate gridlines separated from each other by a gate pitch of less than or equal to about 193 nanometers. Each gate structure has a substantially rectangular shape with a width of... Tela Innovations Inc

Semiconductor chip and manufacturing the same

Gate structures are positioned within a region in accordance with a gate horizontal grid that includes at least seven gate gridlines separated from each other by a gate pitch of less than or equal to about 193 nanometers. Each gate structure has a substantially rectangular shape with a width of... Tela Innovations Inc

Oversized contacts and vias in layout defined by linearly constrained topology

A rectangular-shaped interlevel connection layout structure is defined to electrically connect a first layout structure in a first chip level with a second layout structure in a second chip level. The rectangular-shaped interlevel connection layout structure is defined by an as-drawn cross-section having at least one dimension larger than a... Tela Innovations Inc

Methods for linewidth modification and apparatus implementing the same

A linear-shaped core structure of a first material is formed on an underlying material. A layer of a second material is conformally deposited over the linear-shaped core structure and exposed portions of the underlying material. The layer of the second material is etched so as to leave a filament of... Tela Innovations Inc

Circuitry and layouts for xor and xnor logic

An exclusive-or circuit includes a pass gate controlled by a second input node. The pass gate is connected to pass through a version of a logic state present at a first input node to an output node when so controlled. A transmission gate is controlled by the first input node.... Tela Innovations Inc

Integrated circuit cell library for multiple patterning

A method is disclosed for defining a multiple patterned cell layout for use in an integrated circuit design. A layout is defined for a level of a cell in accordance with a dynamic array architecture so as to include a number of layout features. The number of layout features are... Tela Innovations Inc

Semiconductor chip and manufacturing the same

A first transistor has a gate electrode formed by a substantially linear portion of a first conductive structure. A second transistor has a gate electrode formed by a substantially linear portion of a second conductive structure. A third transistor has a gate electrode formed by a substantially linear portion of... Tela Innovations Inc

Semiconductor chip including integrated circuit defined within dynamic array section

A semiconductor chip includes four linear-shaped conductive structures that each form a gate electrode of corresponding transistor of a first transistor type and a gate electrode of a corresponding transistor of a second transistor type. First and second ones of the four linear-shaped conductive structures are positioned to have their... Tela Innovations Inc

Integrated circuit implementing scalable meta-data objects

A method is disclosed for defining an integrated circuit. The method includes generating a digital data file that includes both electrical connection information and physical topology information for a number of circuit components. The method also includes operating a computer to execute a layout generation program. The layout generation program... Tela Innovations Inc

Semiconductor chip including integrated circuit having cross-coupled transistor configuration and manufacturing the same

A first conductive structure forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second conductive structure forms a gate electrode of a second transistor of the first transistor type. A third conductive structure forms a gate electrode... Tela Innovations Inc

Cell circuit and layout with linear finfet structures

A cell circuit and corresponding layout is disclosed to include linear-shaped diffusion fins defined to extend over a substrate in a first direction so as to extend parallel to each other. Each of the linear-shaped diffusion fins is defined to project upward from the substrate along their extent in the... Tela Innovations Inc

Methods for cell boundary encroachment and semiconductor devices implementing the same

A semiconductor device is disclosed to include a plurality of cells. Each of the cells has a respective outer cell boundary defined to circumscribe the cell in an orthogonal manner. Also, each of the cells includes circuitry for performing one or more logic functions. This circuitry includes a plurality of... Tela Innovations Inc

Enforcement of semiconductor structure regularity for localized transistors and interconnect

A global placement grating (GPG) is defined for a chip level to include a set of parallel and evenly spaced virtual lines. At least one virtual line of the GPG is positioned to intersect each contact that interfaces with the chip level. A number of subgratings are defined. Each subgrating... Tela Innovations Inc

Semiconductor chip and manufacturing the same

A first conductive structure forms a gate electrode of a first transistor of a first transistor type. A second conductive structure forms gate electrodes of both a second transistor of the first transistor type and a first transistor of a second transistor type. A third conductive structure forms a gate... Tela Innovations Inc








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