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Tessera Inc
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Tessera Inc patents

Recent patent applications related to Tessera Inc. Tessera Inc is listed as an Agent/Assignee. Note: Tessera Inc may have other listings under different names/spellings. We're not affiliated with Tessera Inc, we're just tracking patents.

ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "T" | Tessera Inc-related inventors




Date Tessera Inc patents (updated weekly) - BOOKMARK this page
07/20/17Packaged microelectronic elements having blind vias for heat dissipation
06/01/17Stackable molded microelectronic packages
04/20/17Systems and methods for producing flat surfaces in interconnect structures
04/06/17Electrical barrier layers
03/16/17Low cost hybrid high density package
03/02/17Flip chip assembly and process with sintering material on metal bumps
01/19/17Robust multi-layer wiring elements and assemblies with embedded microelectronic elements
10/27/16High density three-dimensional integrated capacitors
10/20/16Reliable packaging and interconnect structures
09/29/16Staged via formation from both sides of chip
09/01/16Fan-out wlp with package
08/11/16Substrate and assembly thereof with dielectric removal for increased post height
08/11/16Active chip on carrier or laminated chip having microelectronic element embedded therein
08/04/16Multiple die stacking for two or more die
07/21/16Dram security erase
07/21/16Package-on-package assembly with wire bonds to encapsulation surface
06/30/16Systems and methods for producing flat surfaces in interconnect structures
06/30/16Stacked chip-on-board module with edge connector
06/09/16Stacked microelectronic assembly with tsvs formed in stages and carrier above chip
03/24/16Stackable molded microelectronic packages with area array unit connectors
03/17/16High density three-dimensional integrated capacitors
02/25/16Microelectronic packages and methods therefor
02/04/16Stacked packaging improvements
01/28/16Systems and methods for producing flat surfaces in interconnect structures
01/07/16Semiconductor chip assembly and making same
12/31/15Packaged semiconductor chips with array
12/17/15Stackable molded microelectronic packages
12/10/15Flip chip assembly and process with sintering material on metal bumps
11/26/15Microelectronic packages having cavities for receiving microelectronic elements
11/19/15Off-chip vias in stacked chips
11/19/15Stacked microelectronic assembly with tsvs formed in stages with plural active chips
11/19/15Electrical barrier layers
11/12/15Low-stress vias
11/12/15Method of making a stacked microelectronic package
10/08/15Dram security erase
10/01/15Single exposure in multi-damascene process
09/03/15Microelectronic elements with post-assembly planarization
08/27/15Microelectronic packages with nanoparticle joining
08/27/15Multiple die in a face down package
08/20/15Multi-chip module with stacked face-down connected dies
08/06/15Non-lithographic formation of three-dimensional conductive elements
08/06/15Multiple die face-down stacking for two or more die
07/09/15Methods of making compliant semiconductor chip packages
06/18/15Low cost hybrid high density package
06/04/15Multiple die stacking for two or more die
05/28/15Enhanced stacked microelectronic assemblies with central contacts and improved thermal characteristics
05/21/15Vias in porous substrates
05/14/15Staged via formation from both sides of chip
04/30/15Flip-chip, face-up and face-down centerbond memory wirebond assemblies
04/16/15Stacked packaging improvements
04/02/15Package-on-package assembly with wire bonds to encapsulation surface
03/26/15Stackable molded microelectronic packages
03/19/15Three-dimensional system-in-a-package
02/26/15Flip chip interconnection with double post
02/19/15Stacked microelectronic packages having at least two stacked microelectronic elements adjacent one another
02/12/15Enhanced stacked microelectronic assemblies with central contacts and improved ground or power distribution
02/12/15Fan-out wlp with package
01/29/15Substrate and assembly thereof with dielectric removal for increased post height
01/22/15Multi-function and shielded 3d interconnects
01/15/15Interconnect structure
01/08/15Pin attachment
11/20/14Compliant interconnects in wafers
11/13/14Stacked packages and microelectronic assemblies incorporating the same
11/13/14Power boosting circuit for semiconductor packaging
10/16/14Wearable ultra-thin miniaturized mobile communications
Patent Packs
09/18/14Connection component with posts and pads
09/18/14High density three-dimensional integrated capacitors
09/11/14System and testing fuse blow reliability for integrated circuits
08/28/14Enhanced stacked microelectronic assemblies with central contacts
08/07/14Flow underfill for microelectronic packages
07/31/14Systems and methods for producing flat surfaces in interconnect structures
07/31/14Non-lithographic formation of three-dimensional conductive elements
07/31/14Microelectronic packages and methods therefor
07/24/14Low-stress tsv design using conductive particles
07/24/14Active chip on carrier or laminated chip having microelectronic element embedded therein
07/24/14Stacked microelectronic assembly with tsvs formed in stages and carrier above chip
07/24/14Interposer having molded low cte dielectric
07/03/14Dram security erase
06/26/14Packaged microelectronic elements having blind vias for heat dissipation
06/19/14Microelectronic package with terminals on dielectric mass
Patent Packs
06/12/14Reliable wire structure and method
06/05/14Packaged semiconductor chips with array
05/29/14Fine pitch microcontacts and forming thereof
05/15/14Stacked chip-on-board module with edge connector
05/15/14Chip assembly having via interconnects joined by plating
05/08/14Microelectronic assembly with joined bond elements having lowered inductance
05/01/14Multiple die in a face down package
05/01/14Microelectronic assembly with impedance controlled wirebond and reference wirebond
04/17/14Microelectronic assembly with impedance controlled wirebond and conductive reference element
04/10/14Multi-function and shielded 3d interconnects
04/10/14Electrohydrodynamic (ehd) fluid mover with collector electrode leading surface shaping for spatially selective field reduction
04/10/14Compliant interconnects in wafers
03/27/14Reliable packaging and interconnect structures
03/20/14Microelectronic packages with nanoparticle joining
02/27/14Dual wafer spin coating
02/20/14Stacked microelectronic assembly with tsvs formed in stages with plural active chips
02/13/14Methods of making compliant semiconductor chip packages
02/13/14Flip-chip, face-up and face-down wirebond combination package
02/06/14Enhanced stacked microelectronic assemblies with central contacts and improved thermal characteristics
02/06/14Tsop with impedance control
01/30/14Stack packages using reconstituted wafers
01/23/14Microelectronic packages having cavities for receiving microelectronic elements
01/02/14Electrohydrodynamic (ehd) fluid mover with field blunting structures in flow channel for spatially selective suppression of ion generation
12/26/13Electrohydrodynamic (ehd) air mover configuration with flow path expansion and/or spreading for improved ozone catalysis
12/26/13Simultaneous wafer bonding and interconnect joining
12/26/13Reconstituted wafer stack packaging with after-applied pad extensions
12/26/13Stacked packaging improvements
12/12/13Edge connect wafer level stacking
11/28/13High density three-dimensional integrated capacitors
11/28/13Ultra-thin near-hermetic package based on rainier
Social Network Patent Pack
11/21/13Deskewed multi-die packages
11/14/13Lead structures with vertical offsets
10/03/13Microelectronic package with terminals on dielectric mass
09/26/13Microelectronic package
08/08/13Package-on-package assembly with wire bonds to encapsulation surface
06/06/13Microelectronic assembly with impedance controlled wirebond and reference wirebond
05/23/13Multiple die face-down stacking for two or more die
04/25/13Microelectronic packages with dual or multiple-etched flip-chip connectors
04/25/13Multiple die stacking for two or more die
03/07/13Emitter wire with layered cross-section
Patent Packs
03/07/13Flip-chip, face-up and face-down wirebond combination package
02/28/13Low cost hybrid high density package
02/28/13Through interposer wire bond using low cte interposer with coarse slot apertures
02/28/13Interconnection elements with encased interconnects
02/28/13Dram security erase
02/21/13Multiple die in a face down package
02/21/13Power boosting circuit for semiconductor packaging
02/14/13Area array qfn
02/07/13Packaged microelectronic elements having blind vias for heat dissipation
02/07/13Microelectronic package with terminals on dielectric mass
02/07/13Microelectronic package with stacked microelectronic elements and manufacture thereof
01/31/13System and testing fuse blow reliability for integrated circuits
01/31/13Low stress vias
01/31/13Embedded passive integration
01/24/13System and in-situ conditioning of emitter electrode with silver
01/17/13Electrical barrier layers
01/17/13Connector structures and methods
01/17/13De-skewed multi-die packages
01/10/13Microelectronic elements with post-assembly planarization
01/03/13Flip-chip qfn structure using etched lead frame
12/27/12Reliable wire structure and method
12/27/12Single exposure in multi-damascene process
12/27/12Systems and methods for producing flat surfaces in interconnect structures
12/20/12Reliable packaging and interconnect structures
12/13/12Impedence controlled packages with metal sheet or 2-layer rdl
12/13/12Flip chip assembly and process with sintering material on metal bumps
12/13/12Substrate and assembly thereof with dielectric removal for increased post height
12/13/12Ehd device in-situ airflow
12/13/12Low-stress tsv design using conductive particles
12/06/12Conductive pads defined by embedded traces
Patent Packs
11/08/12Package-on-package assembly with wire bonds to encapsulation surface
10/25/12Stacked chip-on-board module with edge connector
10/25/12Flip-chip, face-up and face-down centerbond memory wirebond assemblies
10/25/12Flip-chip, face-up and face-down wirebond combination package
10/25/12Multiple die face-down stacking for two or more die
10/25/12Electrohydrodynamic (ehd) fluid mover with field shaping feature at leading edge of collector electrodes
09/27/12Substrate for a microelectronic package and fabricating thereof
08/16/12Electronic system adapted for passive convective cooling and staged use of electrohydrodynamic (ehd) and mechanical air movers for quiet forced convection assist
08/02/12Wearable ultra-thin miniaturized mobile communications
06/21/12Enhanced stacked microelectronic assemblies with central contacts and improved ground or power distribution
06/21/12Packaged semiconductor chips with array
06/21/12Enhanced stacked microelectronic assemblies with central contacts and improved ground or power distribution
06/21/12Semiconductor chip assembly and making same
05/31/12Edge connect wafer level stacking
05/24/12Wafer level chip package and a fabricating thereof
05/17/12Microelectronic package with terminals on dielectric mass
05/17/12Electronic system changeable to accommodate an ehd air mover or mechanical air mover
05/17/12Ion protection technique for electronic system with flow between internal air plenum and an ehd device
05/17/12Electronic system with ventilation path through inlet-positioned ehd air mover, over ozone reducing surfaces, and out through outlet-positioned heat exchanger
05/10/12Electronic system with ehd air mover ventilation path isolated from internal air plenum
Social Network Patent Pack
05/03/12Electrohydrodynamic device components employing solid solutions
05/03/12Layered emitter coating structure for crack resistance with pdag coatings
04/26/12Electrode cleaning in an electro-kinetic air mover
04/19/12Microelectronic assemblies having compliancy and methods therefor
04/05/12Off-chip vias in stacked chips
03/08/12Substrate for a microelectronic package and fabricating thereof
02/23/12Electrostatic fluid accelerator for controlling a fluid flow
02/09/12Method of fabricating stacked assembly including plurality of stacked microelectronic elements
01/19/12Stacked microelectronic packages having at least two stacked microelectronic elements adjacent one another
01/05/12Emitter wire cleaning device with wear-tolerant profile
01/05/12Electrostatic precipitator pre-filter for electrohydrodynamic fluid mover
12/22/11Cleaning mechanism with tandem movement over emitter and collector surfaces
12/22/11Granular abrasive cleaning of an emitter wire
12/22/11Electrohydrodynamic device with flow heated ozone reducing material
12/01/11Package stacking through rotation
12/01/11Microelectronic packages having cavities for receiving microelectronic elements
11/24/11Electro-kinetic air mover with upstream focus electrode surfaces
11/03/11Electrode conditioning in an electrohydrodynamic fluid accelerator device
11/03/11Microelectronic assemblies having compliancy
11/03/11Microelectronic packages and methods therefor
Social Network Patent Pack
10/27/11Method of making a connection component with posts and pads
10/13/11Stack packages using reconstituted wafers
09/22/11Stacked packages with bridging traces
08/04/11Edge connect wafer level stacking
07/07/11Microelectronic packages and methods therefor
06/16/11Collector-radiator structure for an electrohydrodynamic cooling system
04/28/11Microelectronic assemblies having compliant layers
03/31/11Flip chip interconnection with double post
03/03/11Off-chip vias in stacked chips
02/24/11Stacked packaging improvements
02/10/11Edge connect wafer level stacking
02/10/11Edge connect wafer level stacking
01/27/11Method of electrically connecting a microelectronic component
01/20/11Packaged semiconductor chips
01/13/11Reconstituted wafer stack packaging with after-applied pad extensions
10/28/10Microelectronic packages fabricated at the wafer level and methods therefor
10/28/10Substrate for a microelectronic package and fabricating thereof
10/14/10Microelectronic packages and methods therefor
09/30/10Compact lens turret assembly
09/16/10Microelectronic assemblies having compliancy and methods therefor
09/16/10Microelectronic packages and methods therefor
09/09/10Chips having rear contacts connected by through vias to front contacts
08/05/10Micro pin grid array with pin motion isolation
08/05/10Microelectronic package with thermal access
07/01/10Electro-kinetic air mover with upstream focus electrode surfaces
06/24/10Collector electrodes and ion collecting surfaces for electrohydrodynamic fluid accelerators
05/13/10Spatially distributed ventilation boundary using electrohydrodynamic fluid accelerators
05/13/10Reversible flow electrohydrodynamic fluid accelerator
05/13/10Electrohydrodynamic fluid accelerator with heat transfer surfaces operable as collector electrode
03/04/10Electrohydrodynamic fluid accelerator device with collector electrode exhibiting curved leading edge profile
Social Network Patent Pack
03/04/10Wafer level compliant packages for rear-face illuminated solid state image sensors
02/11/10Methods of making compliant semiconductor chip packages
01/21/10Stacked packages and microelectronic assemblies incorporating the same
01/14/10Microelectronic interconnect element with decreased conductor spacing
12/31/09Multi-stage electrohydrodynamic fluid accelerator apparatus
09/24/09Method of electrically connecting a microelectronic component
08/27/09Wafer level packages for rear-face illuminated solid state image sensors
08/13/09Method of electrically connecting a microelectronic component
08/13/09Method of electrically connecting a microelectronic component
06/25/09Reconstituted wafer level stacking
06/25/09Method of forming a wafer level package
06/11/09Interconnection element with posts formed by plating
06/11/09Flip chip interconnection with double post
06/11/09Interconnection element with plated posts formed on mandrel
05/28/09Components with posts and pads
05/07/09Robust multi-layer wiring elements and assemblies with embedded microelectronic elements
04/23/09Stacked packaging improvements
03/19/09Formation of circuitry with modification of feature height
03/19/09Multilayer substrate with interconnection vias and manufacturing the same
03/12/09Semiconductor packaging process using through silicon vias
02/19/09Microelectronic package
02/05/09Component and assemblies with ends offset downwardly
12/12/13Edge connect wafer level stacking
01/21/10Stacked packages and microelectronic assemblies incorporating the same
01/14/10Microelectronic interconnect element with decreased conductor spacing







ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009



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This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. Freshpatents.com is not affiliated or associated with Tessera Inc in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Tessera Inc with additional patents listed. Browse our Agent directory for other possible listings. Page by FreshPatents.com

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