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Tessera Inc patents


Recent patent applications related to Tessera Inc. Tessera Inc is listed as an Agent/Assignee. Note: Tessera Inc may have other listings under different names/spellings. We're not affiliated with Tessera Inc, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "T" | Tessera Inc-related inventors


Active chip on carrier or laminated chip having microelectronic element embedded therein

A structure including a first semiconductor chip with front and rear surfaces and a cavity in the rear surface. A second semiconductor chip is mounted within the cavity. ... Tessera Inc

Systems and methods for producing flat surfaces in interconnect structures

In interconnect fabrication (e.g. A damascene process), a barrier layer (possibly conductive) is formed over a substrate with holes, a conductor is formed over the barrier layer, and the conductor and the barrier layer are polished to expose the substrate around the holes and provide interconnect features in the holes. ... Tessera Inc

Flip-chip, face-up and face-down centerbond memory wirebond assemblies

A microelectronic assembly can include a substrate having first and second surfaces and an aperture extending therebetween, the substrate having terminals. The assembly can also include a first microelectronic element having a front surface facing the first surface of the substrate, a second microelectronic element having a front surface facing the first microelectronic element and projecting beyond an edge of the first microelectronic element, first and second leads electrically connecting contacts of the respective first and second microelectronic elements to the terminals, and third leads electrically interconnecting the contacts of the first and second microelectronic elements. ... Tessera Inc

Configurable machine learning assemblies for autonomous operation in personal devices

Configurable machine learning assemblies for autonomous operation in personal devices are provided. Example systems implement machine learning based on neural networks that draw low power for use in smart phones, watches, drones, automobiles, and medical devices. ... Tessera Inc

Systems and methods for producing flat surfaces in interconnect structures

In interconnect fabrication (e.g. A damascene process), a conductive layer is formed over a substrate with holes, and is polished to provide interconnect features in the holes. ... Tessera Inc

Using biometric user-specific attributes

Techniques are provided for determining two or more user-specific parameters that can be measured or obtained using various methods, and using values of the two or more user-specific parameters to uniquely identify or authenticate an individual. Examples of the user-specific parameters may include biometric parameters, textual-based parameters, a combination of biometric parameters and textual-based parameters, and the like.. ... Tessera Inc

Semiconductor chip assembly and method for making same

A microelectronic assembly may include a substrate including a rigid dielectric layer having electrically conductive elements, a microelectronic element having a plurality of contacts exposed at a face thereof, and conductive vias extending through a compliant dielectric layer overlying the rigid dielectric layer. The vias electrically connect the substrate contacts respectively to the conductive elements, and the substrate contacts are joined respectively to the contacts of the microelectronic element. ... Tessera Inc

Reliable packaging and interconnect structures

Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a top surface and portions of the side walls of the interconnect structure covered in a dissimilar material. ... Tessera Inc

Package-on-package assembly with wire bonds to encapsulation surface

Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. ... Tessera Inc

Uniform deceleration unit

An apparatus and method for improving the safety and performance of an automobile in crash events is disclosed. The apparatus includes a front crash pad, rear crash pad, and a connection beam. ... Tessera Inc

Stacked chip-on-board module with edge connector

A module can include a module card and first and second microelectronic elements having front surfaces facing a first surface of the module card. The module card can also have a second surface and a plurality of parallel exposed edge contacts adjacent an edge of at least one of the first and second surfaces for mating with corresponding contacts of a socket when the module is inserted in the socket. ... Tessera Inc

Microelectronic elements with post-assembly planarization

A microelectronic unit can include a carrier structure having a front surface, a rear surface remote from the front surface, and a recess having an opening at the front surface and an inner surface located below the front surface of the carrier structure. The microelectronic unit can also include a microelectronic element having a top surface adjacent the inner surface, a bottom surface remote from the top surface, and a plurality of contacts at the top surface. ... Tessera Inc

Low stress vias

A component can include a substrate having a front surface and a rear surface remote therefrom, an opening extending from the rear surface towards the front surface, and a conductive via extending within the opening. The substrate can have a cte less than 10 ppm/° c. ... Tessera Inc

Control device, storage device, and storage control method

A control device includes: a management information generation unit configured to generate or update logical-physical block address management information with respect to either data to be written to a non-volatile memory or data which has been already written in the non-volatile memory, the logical-physical block address management information indicating association between a logical block address and a physical block address on the non-volatile memory; and an access control unit configured to, during write of the data to the non-volatile memory, control write of the data as well as the logical-physical block address management information to a physical write unit of the non-volatile memory.. . ... Tessera Inc

08/17/17 / #20170231500

Sensor and device for lifetime imaging and detection applications

A method of luminance lifetime imaging includes receiving incident photons at an integrated photodetector from luminescent molecules. The incident photons being received through one or more optical components of a point-of-care device. ... Tessera Inc

08/03/17 / #20170221449

Remote and comparative display of a graphic art with color accuracy simulation in a standard web browser

Embodiments of the present invention define a soft proofing system (sps) that optimizes the usage of standards and common technologies, without relying on proprietary technologies, to enable the use of a pure web browser environment, without the need for any additional software installation to work together with a server-side application to control and verify accuracy of reception and establish mutual communication in the approval process. This may create an opportunity for large scale, cms driven, publishing systems, to provide an accurate, distributed, optimized and highly productive collaborative environment to accomplish fast, up to the minute delivery of digital assets to be output to multiple mediums (print and digital formats).. ... Tessera Inc

07/20/17 / #20170207141

Packaged microelectronic elements having blind vias for heat dissipation

System and method for thermal management in a multi-chip packaged device. A microelectronic unit is disclosed, and includes a semiconductor element having a top surface and a bottom surface remote from the top surface. ... Tessera Inc

06/15/17 / #20170170131

Electronic device, assembly and methods of manufacturing an electronic device including a vertical trench capacitor and a vertical interconnect

A semiconductor substrate comprises both vertical interconnects and vertical capacitors with a common dielectric layer. The substrate can be suitably combined with further devices to form an assembly. ... Tessera Inc

06/01/17 / #20170154874

Stackable molded microelectronic packages

A microelectronic package has a microelectronic element overlying or mounted to a first surface of a substrate and substantially rigid conductive posts projecting above the first surface or projecting above a second surface of the substrate remote therefrom. Conductive elements exposed at a surface of the substrate opposite the surface above which the conductive posts project are electrically interconnected with the microelectronic element. ... Tessera Inc

04/20/17 / #20170110370

Systems and methods for producing flat surfaces in interconnect structures

In interconnect fabrication (e.g. A damascene process), a conductive layer is formed over a substrate with holes, and is polished to provide interconnect features in the holes. ... Tessera Inc

04/06/17 / #20170098621

Electrical barrier layers

An electrical connection structure includes a variable-composition nickel alloy layer with a minor constituent selected from a group consisting of boron, carbon, and tungsten, wherein at least over a portion of a conductive substrate, the concentration of the minor constituent varies throughout the variable-composition nickel alloy layer in a direction from the bottom surface of the variable-composition nickel alloy layer to the top surface of the variable-composition nickel alloy layer.. . ... Tessera Inc

03/16/17 / #20170077018

Low cost hybrid high density package

A microelectronic assembly includes a substrate, a first and second microelectronic elements, a lead finger, electrical connections extending between contacts of the second microelectronic element and the lead fingers, and an encapsulant overlying at least portions of the first and second microelectronic elements, lead finger and electrical connections. The substrate has contacts at a first surface and terminals at an opposed second surface that are electrically connected with the substrate contacts. ... Tessera Inc

03/02/17 / #20170062318

Flip chip assembly and process with sintering material on metal bumps

A method is disclosed of fabricating a microelectronic package comprising a substrate overlying the front face of a microelectronic element. A plurality of metal bumps project from conductive elements of the substrate towards the microelectronic element, the metal bumps having first ends extending from the conductive elements, second ends remote from the conductive elements, and lateral surfaces extending between the first and second ends. ... Tessera Inc

01/19/17 / #20170018440

Robust multi-layer wiring elements and assemblies with embedded microelectronic elements

An interconnect element 130 can include a dielectric layer 116 having a top face 116b and a bottom face 116a remote from the top face, a first metal layer defining a plane extending along the bottom face and a second metal layer extending along the top face. One of the first or second metal layers, or both, can include a plurality of conductive traces 132, 134. ... Tessera Inc

01/12/17 / #20170013089

Information delivery system for generating a data stream with a server system based on a content file received from a client device

An information delivery system, an information delivery method, an information processing apparatus, and an information processing method is used advantageously to deliver content stream data easily, reliably and inexpensively to the general users. A personal computer prepares a content file and an order form file using software provided by a center system, and transmits the prepared files to the center system over the internet. ... Tessera Inc








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