FreshPatents.com Logo

new TOP 200 Companies filing patents this week

new Companies with the Most Patent Filings (2010+)


Similar
Filing Names

Texas Instruments Incorporated
Texas Instruments Incorporated A Delaware Corporation
Texas Instruments Incorporated_20100114
Texas Instruments Incorporated_20100107
Texas Instruments Incorporated_20100121
Texas Instruments Incorporated_20131212
Texas Instruments Incorporated_20100128

Popular
Companies


Web
Adobe patents
Akamai patents
Amazon patents
Apple patents
Ebay patents
Facebook patents
Google patents
IBM patents
Linkedin patents
Microsoft patents
Oracle patents
Red Hat patents
Yahoo patents

Food/Health
Adidas
Nike patents
Pfizer patents
Monsanto patents
Medtronic patents
Kraft patents

Transportation
Boeing patents
Tesla Motors patents

Telecom
Qualcomm patents
Motorola patents
Nokia patents
RIMM patents

Industrial/Electronics
AMD
Applied Materials
Seagate patents
General Electric
Caterpillar patents
Samsung
Wal-mart patents

Ticker Symbols

Texas Instruments, Inc.orporated patents


      
Recent patent applications related to Texas Instruments, Inc.orporated. Texas Instruments, Inc.orporated is listed as an Agent/Assignee. Note: Texas Instruments, Inc.orporated may have other listings under different names/spellings. We're not affiliated with Texas Instruments, Inc.orporated, we're just tracking patents.

ARCHIVE: New 2014 2013 2012 2011 2010 2009 | Company Directory "T" | Texas Instruments, Inc.orporated-related inventors



Texas Instruments

Negative edge reset flip-flop with dual-port slave latch

Texas Instruments

Voltage conversion and charging from low bipolar input voltage

Texas Instruments

Positive edge preset flip-flop with dual-port slave latch

Search recent Press Releases: Texas Instruments, Inc.orporated-related press releases
Count Application # Date Texas Instruments, Inc.orporated patents (updated weekly) - BOOKMARK this page
12014023235908/21/14 new patent  Resonance-based single inductor output-driven dc-dc converter and method
22014023242208/21/14 new patent  Built-in self-test methods, circuits and apparatus for concurrent test of rf modules with a dynamically configurable test structure
32014023243908/21/14 new patent  Negative edge preset reset flip-flop with dual-port slave latch
42014023244008/21/14 new patent  Positive edge reset flip-flop with dual-port slave latch
52014023244108/21/14 new patent  Positive edge preset flip-flop with dual-port slave latch
62014023244208/21/14 new patent  Negative edge reset flip-flop with dual-port slave latch
72014023244308/21/14 new patent  Negative edge preset flip-flop with dual-port slave latch
82014023293808/21/14 new patent  Systems and methods for video processing
92014023327008/21/14 new patent  Voltage conversion and charging from low bipolar input voltage
102014023349808/21/14 new patent  Multiple cqi feedback for cellular networks
112014023350708/21/14 new patent  Uplink synchronization management in wireless networks
122014023358608/21/14 new patent  Carrier sense multiple access (csma) protocols for power line communications (plc)
132014023360908/21/14 new patent  Ultra wideband modulation for body area networks
142014023647508/21/14 new patent  Methods and systems for navigation in indoor environments
152014023647908/21/14 new patent  Attitude estimation for pedestrian navigation using low cost mems accelerometer in mobile applications, and processing methods, apparatus and systems
162014023730908/21/14 new patent  Interconnections for plural and hierarchical p1500 test wrappers
172014023731108/21/14 new patent  System and method for sharing a communications link between multiple communications protocols
182014022511008/14/14Default trim code technique
192014022511208/14/14Die testing using top surface test pads
202014022522608/14/14Multi-step deposition of ferroelectric dielectric material
212014022587408/14/14Touch panel apparatus and methods
222014022651808/14/14Cqi feedback structure
232014022670508/14/14Adaptive real-time control of de-emphasis level in a usb 3.0 signal conditioner based on incoming signal frequency range
242014022673908/14/14Pre-coder selection based on resource block grouping
252014022766908/14/14Guided tool tips for expression calculation
262014022780508/14/14Adhesion of ferroelectric material to underlying conductive capacitor plate
272014022785908/14/14Diffusion resistor with reduced voltage coefficient of resistance and increased breakdown voltage using cmos wells
282014022787708/14/14Method of forming a metal contact opening with a width that is smaller than the minimum feature size of a photolithographically-defined opening
292014022789108/14/14Interdigitated chip capacitor assembly
302014022974808/14/14Apparatus and method for optimizing use of nvdc chargers
312014022978008/14/14Ieee 1149.1 and p1500 test interfaces combined circuits and processes
322014022978108/14/14Hierarchical access of test access ports in embedded core integrated circuits
332014021651708/07/14Vertical thermoelectric structures
342014021749708/07/14Mosfet with curved trench feature coupling termination trench to active trench
352014021756808/07/14Semiconductor package with cantilever leads
362014021794408/07/14Permanent magnet motor with sinusoidal back-emf waveform and related motor controller for position sensorless drives
372014021801808/07/14Apparatus and method for in situ current measurement in a conductor
382014021807508/07/14Adaptive slope generator
392014021809008/07/14Negative edge flip-flop with dual-port slave latch
402014021809108/07/14Positive edge flip-flop with dual-port slave latch
412014021811208/07/14Compensation circuitry and method for amplifiers driving large capacitive loads
422014021917308/07/14Uplink synchronization management in wireless networks
432014021921808/07/14Downlink 8 tx codebook sub-sampling for csi feedback
442014021921908/07/14Downlink 8 tx codebook sub-sampling for csi feedback
452014021927708/07/14Conditional instructions for packet processing
462014021929408/07/14Rotate-mask-merge and deposit-field instructions for packet processing
472014022076108/07/14Reduction of polysilicon residue in a trench for polysilicon trench filling processes
482014022305208/07/14System and method for slave-based memory protection
492014022312708/07/14System and method for virtual hardware memory protection
502014021005307/31/14Bi-directional esd protection circuit
512014021006207/31/14Leadframe-based semiconductor package having terminals on top and bottom surfaces
522014021006407/31/14Wire bonding method and structure
532014021051107/31/14Error detection in nonvolatile logic arrays using parity
542014021053307/31/14Edge rate control gate drive circuit and system for high and low side devices with large driver fet
552014021053507/31/14Signal level conversion in nonvolatile bitcell array
562014021076507/31/14Capacitive single layer multi-touch panel having improved response characteristics
572014021134707/31/14Bi-directional esd protection circuit
582014021143907/31/14Circuit assembly
592014021153207/31/14Four capacitor nonvolatile bit cell
602014021153307/31/14Two capacitor self-referencing nonvolatile bitcell
612014021157207/31/14Nonvolatile logic array with built-in test result signal
622014021157607/31/14Nonvolatile logic array with built-in test drivers
632014021175507/31/14Radio bearer dependent forwarding for handover
642014021188207/31/14Dynamic determination of volterra kernels for digital pre-distortion
652014021386307/31/14Low-complexity sensor displacement tolerant pulse oximetry based heart rate measurement
662014021528207/31/141149.1 tap linking modules
672014021528307/31/14Integrated circuit with jtag port, tap linking module, and off-chip tap interface port
682014021542507/31/14Adjustable dummy fill
692014020338807/24/14Optical sensor with integrated pinhole
702014020378007/24/14System and method for active charge and discharge current balancing in multiple parallel-connected battery packs
712014020418207/24/14Multi-sensor video frame synchronization apparatus and methods
722014020482507/24/14Methods for energy-efficient unicast and multicast transmission in a wireless communication system
732014020629607/24/14Transceiver with asymmetric matching network
742014020798407/24/14Signal conitioner
752014020813407/24/14Host controller interface for universal serial bus (usb) power delivery
762014020817607/24/14Scan chain in an integrated circuit
772014020817707/24/14Circuits and methods for dynamic allocation of scan test resources
782014019748607/17/14Power integrated circuit including series-connected source substrate and drain substrate power mosfets
792014019753407/17/14Substrate with bond fingers
802014019787507/17/14Circuits and methods for signal interference mitigation
812014019789507/17/14Variability and aging sensor for integrated circuits
822014019841507/17/14Electrostatic discharge protection apparatus
832014019855007/17/14Frequency multiplier
842014019897707/17/14Enhancement of stereo depth maps
852014020150307/17/14Processor micro-architecture for compute, save or restore multiple registers, devices, systems, methods and processes of manufacture
862014019137807/10/14Integrated circuit package
872014019138007/10/14Integrated circuit package and method of making
882014019138107/10/14Integrated circuit module with dual leadframe
892014019173007/10/14Converter and method for extracting maximum power from piezo vibration harvester
902014019174307/10/14Current mode control arrangement and method thereof
912014019194707/10/14Using natural movements of a hand-held device to manipulate digital content
922014019239707/10/14Mems device with sloped support
932014019274007/10/14Methods and apparatus for dual connectivity operation in a wireless communication network
942014019586907/10/14Serial i/o using jtag tck and tms signals
952014019588007/10/14Rate matching and scrambling techniques for control signaling
962014019615407/10/14Systems and methods for controlling access to secure debugging and profiling features of a computer system
972014018365507/03/14High performance isolated vertical bipolar junction transistor and method for forming in a cmos integrated circuit
982014018365707/03/14Embedded polysilicon resistor in integrated circuits formed by a replacement gate process
992014018365807/03/14Poly resistor for metal gate integrated circuits
1002014018366307/03/14Raised source/drain mos transistor and method of forming the transistor with an implant spacer and an epitaxial spacer
1012014018371907/03/14Electronic assembly includes a composite carrier
1022014018374407/03/14Package substrate with bondable traces having different lead finishes
1032014018425907/03/14Method and device for testing wafers
1042014018431007/03/14Switch architecture at low supply voltages
1052014018433007/03/14Time gain compensation
1062014018435007/03/14Two layer differential pair layout, and method of making thereof, for reduced crosstalk
1072014018438107/03/14Single photomask high precision thin film resistor
1082014018485007/03/14System and method for generating 360 degree video recording using mvc
1092014018547207/03/14Method for incorporating invisible access points for rssi-based indoor positioning applications
1102014018551807/03/14System and method for wifi positioning
1112014018555607/03/14Channel quality report processes, circuits and systems
1122014018568107/03/14Hierarchical inter-layer prediction in multi-loop scalable video coding
1132014018569107/03/14Signaling decoded picture buffer size in multi-loop scalable video coding
1142014018962807/03/14System and method of crossover determination in differential pair and bondwire pairs to minimize crosstalk
1152014017559706/26/14Trench with reduced silicon loss
1162014017559906/26/14Integrated circuit package with printed circuit layer
1172014017562606/26/14Integrated circuit package and method of manufacture
1182014017730306/26/14Volt-second integration cable compensation circuit
1192014017774006/26/14Hexagonal constellations and decoding same in digital communication systems
1202014017906406/26/14Method for fabricating a package-in-package for high heat dissipation
1212014018116506/26/14Three-term predictive adder and/or subtracter
1222014018160606/26/14Direct scan access jtag
1232014018160706/26/14Lock state machine operations upon stp data captures and shifts
1242014018160806/26/14Tap and linking module for scan access of multiple cores with ieee 1149.1 test access ports
1252014018160906/26/14Semiconductor test system and method
1262014016718206/19/14Ztcr poly resistor in replacement gate flow
1272014016729506/19/14Coatings for relatively movable surfaces
1282014016779206/19/14Scan testing system, method and apparatus
1292014016779506/19/14Active feedback silicon failure analysis die temperature control system
1302014016836106/19/14Systems and methods for memory-bandwidth efficient display composition
1312014016903806/19/14Digital isolator
1322014016948506/19/14Asymmetric channels in power line communications
1332014016949606/19/14Crest factor reduction for multi-band system
1342014017096706/19/14Wireless powered ic card for sensor data acquisition, processing and radio frequency transmission
1352014017110806/19/14Dynamic access point based positioning
1362014017314106/19/14Robust cable-type detection for usb power delivery
1372014017316206/19/14Command queue for communications bus
1382014017354806/19/14Tool for automation of functional safety metric calculation and prototyping of functional safety systems
1392014015914206/12/14Recessed channel insulated-gate field effect transistor with self-aligned gate and increased channel length
1402014015920106/12/14Single pattern high precision capacitor
1412014015924706/12/143d semiconductor interposer for heterogeneous integration of standard memory and split-architecture processor
1422014015981406/12/14Differential receiver
1432014015985406/12/14Planar inductor floating shield for q enhancement
1442014015995006/12/14Method, system, and apparatus for reducing inaccuracy in global navigation satellite system position and velocity solution
1452014016034106/12/14Maintaining distortion-free projection from a mobile device
1462014016060006/12/14Reverse voltage condition protection in a power supply system
1472014016120206/12/14Method, system and apparatus for reducing the peak-to-average ratio of a signal
1482014016125206/12/14One-way key fob and vehicle pairing verification, retention, and revocation
1492014016483806/12/14At-speed test access port operations
1502014016484406/12/14Pbist engine with distributed data logging
1512014016485406/12/14Pbist architecture with multiple asynchronous sub chips operating in differring voltage domains
1522014016485506/12/14Pbist read only memory image compression
1532014016485606/12/14Pbist engine with reduced sram testing bus width
1542014015155906/05/14On-chip calibration system and method for infrared sensor
1552014015189506/05/14Die having through-substrate vias with deformation protected tips
1562014015268606/05/14Local tone mapping for high dynamic range images
1572014015269406/05/14Merging multiple exposures to generate a high dynamic range image
1582014015297406/05/14Method for time of flight modulation frequency detection and illumination modulation frequency adjustment
1592014015297506/05/14Method for dynamically adjusting the operating parameters of a tof camera according to vehicle speed
1602014015308206/05/14Method and system for generating a display
1612014015346806/05/14Access and power management for centralized networks
1622014015488006/05/14Post-polymer revealing of through-substrate via tips
1632014015695106/05/14Multicore, multibank, fully concurrent coherence controller
1642014015703906/05/14Using data watchpoints to detect unitialized memory reads
1652014015707006/05/14Selectively accessing test access ports in a multiple test access port environment
1662014015707106/05/14Low power scan & delay test method and apparatus
1672014014401305/29/14Microelectromechanical system having movable element integrated into substrate-based package
1682014014563405/29/14Circuit and method for generating a reference voltage for a power converter
1692014014576205/29/14Power supply sensing circuits in integrated circuits
1702014014576705/29/14Pulse generation circuits in integrated circuits
1712014014603605/29/14Electrophoretic display and method of operating
1722014014680805/29/14Power efficient tunneled direct link setup apparatus, systems and methods
1732014014689305/29/14Method and apparatus for predictive reference data transfer scheme for motion estimation
1742014014690005/29/14Building, transmitting, and receiving frame structures in power line communications
1752014014696305/29/14Detecting double talk in acoustic echo cancellation using zero-crossing rate
1762014014705705/29/14Content adaptive edge and detail enhancement for image and video processing
1772014014794005/29/14Process-compatible sputtering target for forming ferroelectric memory capacitor plates
1782014014893505/29/14Pressurized gas stopper for leadframe transporting apparatus
1792014014969005/29/14Multi-processor, multi-domain, multi-protocol cache coherent speculation aware shared memory controller and interconnect
1802014013880505/22/14System for no-lead integrated circuit packages without tape frame
1812014013882205/22/14Integrated circuit package and method of manufacture
1822014013929705/22/14Balun with integrated decoupling as ground shield
1832014013994105/22/14Preamplifier output current control
1842014014010905/22/14Flyback power supply regulation apparatus and methods
1852014014014105/22/14Read margin measurement in a read-only memory
1862014014038005/22/14Initialization sequence for bi-directional communications in a carrier-based system
1872014014039505/22/14Adaptive coding unit (cu) partitioning based on image statistics
1882014014045205/22/14Crest factor reduction for signals with dynamic power and frequency distribution
1892014014348605/22/14Flexible arbitration scheme for multi endpoint atomic accesses in multicore systems
1902014014362205/22/14Jtag bus communication method and apparatus
1912014014363205/22/14Method to extend data retention for flash based storage in a real time device processed on generic semiconductor technology
1922014014384905/22/14Secure master and secure guest endpoint security firewall
1932014013880505/22/14System for no-lead integrated circuit packages without tape frame
1942014013882205/22/14Integrated circuit package and method of manufacture
1952014013929705/22/14Balun with integrated decoupling as ground shield
1962014013994105/22/14Preamplifier output current control
1972014014010905/22/14Flyback power supply regulation apparatus and methods
1982014014014105/22/14Read margin measurement in a read-only memory
1992014014038005/22/14Initialization sequence for bi-directional communications in a carrier-based system
2002014014039505/22/14Adaptive coding unit (cu) partitioning based on image statistics
2012014014045205/22/14Crest factor reduction for signals with dynamic power and frequency distribution
2022014014348605/22/14Flexible arbitration scheme for multi endpoint atomic accesses in multicore systems
2032014014362205/22/14Jtag bus communication method and apparatus
2042014014363205/22/14Method to extend data retention for flash based storage in a real time device processed on generic semiconductor technology
2052014014384905/22/14Secure master and secure guest endpoint security firewall
2062014013157705/15/14Infrared sensor structure and method
2072014013178105/15/14Low resistance stacked annular contact
2082014013233105/15/14Wide common mode range transmission gate
2092014013340405/15/14Mac extensions for smart antenna support
2102014013360205/15/14Digital pre-distortion of non-linear systems with reduced bandwidth feedback
2112014013361305/15/14Apparatus and methods for clock alignment for high speed interfaces
2122014013506805/15/14Systems, processes and integrated circuits for rate and/or diversity adaptation for packet communications
2132014013691305/15/14Dual mode test access port method and apparatus
2142014013613805/15/14On-chip spectral analysis using enhanced recursive discrete fourier transforms
2152014013157705/15/14Infrared sensor structure and method
2162014013178105/15/14Low resistance stacked annular contact
2172014013233105/15/14Wide common mode range transmission gate
2182014013340405/15/14Mac extensions for smart antenna support
2192014013360205/15/14Digital pre-distortion of non-linear systems with reduced bandwidth feedback
2202014013361305/15/14Apparatus and methods for clock alignment for high speed interfaces
2212014013506805/15/14Systems, processes and integrated circuits for rate and/or diversity adaptation for packet communications
2222014013691305/15/14Dual mode test access port method and apparatus
2232014013613805/15/14On-chip spectral analysis using enhanced recursive discrete fourier transforms
2242014012482805/08/14Esd protection circuit with isolated scr for negative voltage operation
2252014012487405/08/14Metal-gate mos transistor and method of forming the transistor with reduced gate-to-source and gate-to-drain overlap capacitance
2262014012487605/08/14Metal gate structure for midgap semiconductor device and method of making same
2272014012489505/08/14Radiation induced diode structure
2282014012490005/08/14Through-silicon via (tsv) die and method to control warpage
2292014012493905/08/14Discrete device mounted on substrate
2302014012519805/08/14Integrated piezoelectric resonator and additional active circuit
2312014012523905/08/14Circuits and methods for reducing flicker in an led light source
2322014012529905/08/14Switched mode assisted linear regulator with decoupled output impedance and signal path bandwidth
2332014012538805/08/14Optimizing pre-driver control for digital integrated circuits
2342014012538905/08/14Edge rate control gate drive circuit and system for low side devices with capacitor
2352014012565205/08/14Look-ahead convergence for optimizing display rendering of sterioscopic videos and images
2362014012649105/08/14Efficient allocation of uplink harq-ack resources for lte enhanced control channel
2372014012652505/08/14Mapping between logical and physical uplink control resource blocks in wireless networks
2382014012652605/08/14Apparatus for dimensioning the control channel for transmission efficiency in communications systems
2392014012665505/08/14Compatible communication between devices using different communication protocols
2402014012785605/08/14Electronic assembly with three dimensional inkjet printed traces
2412014012916605/08/14On-time based peak current density rule and design method
2422014012988605/08/14Boundary scan path method and system with functional and non-functional scan cell memories
2432014012990805/08/14Viterbi butterfly operations
2442014012482805/08/14Esd protection circuit with isolated scr for negative voltage operation
2452014012487405/08/14Metal-gate mos transistor and method of forming the transistor with reduced gate-to-source and gate-to-drain overlap capacitance
2462014012487605/08/14Metal gate structure for midgap semiconductor device and method of making same
2472014012489505/08/14Radiation induced diode structure
2482014012490005/08/14Through-silicon via (tsv) die and method to control warpage
2492014012493905/08/14Discrete device mounted on substrate


ARCHIVE: New 2014 2013 2012 2011 2010 2009



###

This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. Freshpatents.com is not affiliated or associated with Texas Instruments, Inc.orporated in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Texas Instruments, Inc.orporated with additional patents listed. Browse our Agent directory for other possible listings. Page by FreshPatents.com

###

     SHARE
  
         


FreshNews promo