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Texas Instruments, Inc.orporated patents

Recent patent applications related to Texas Instruments, Inc.orporated. Texas Instruments, Inc.orporated is listed as an Agent/Assignee. Note: Texas Instruments, Inc.orporated may have other listings under different names/spellings. We're not affiliated with Texas Instruments, Inc.orporated, we're just tracking patents.

ARCHIVE: New 2014 2013 2012 2011 2010 2009 | Company Directory "T" | Texas Instruments, Inc.orporated-related inventors

Texas Instruments

Battery charger

Texas Instruments

Low-cost cmos structure with dual gate dielectrics and method of forming the cmos structure

Texas Instruments

Mems device and method of manufacture

Search recent Press Releases: Texas Instruments, Inc.orporated-related press releases
Count Application # Date Texas Instruments, Inc.orporated patents (updated weekly) - BOOKMARK this page
12014025176009/11/14 new patent  Die eject assembly for die bonder
22014025236709/11/14 new patent  Driver for normally on iii-nitride transistors to get normally-off functionality
32014025241909/11/14 new patent  Mems device and method of manufacture
42014025245709/11/14 new patent  Multi-landing contact etching
52014025248509/11/14 new patent  Low-cost cmos structure with dual gate dielectrics and method of forming the cmos structure
62014025303909/11/14 new patent  Battery charger
72014025309609/11/14 new patent  Electronic device and method for tracking energy consumption
82014025314109/11/14 new patent  Detecting power supply sag in an integrated circuit
92014025368809/11/14 new patent  Time of flight sensor binning
102014025375809/11/14 new patent  Method and apparatus for a time-of-flight sensor with charge storage
112014025423509/11/14 new patent  Power supply brownout protection circuit and method for embedded fram
122014025480909/11/14 new patent  Audio accessory circuitry and method compatible with both msft mode and digital communication mode
132014025493209/11/14 new patent  Content adaptive edge and detail enhancement for image and video processing
142014025704909/11/14 new patent  Wearable heart monitoring apparatus
152014025879909/11/14 new patent  Ip core design supporting user-added scan register option
162014025882009/11/14 new patent  Providing information during different stages of a design cycle
172014024559809/04/14Fabricating a power supply converter with load inductor structured as heat sink
182014024649309/04/14Novel nfc receiver architecture with improved power sensitivity
192014024704009/04/14Position detecting system
202014024707109/04/14Architecture for vbus pulsing in udsm processes
212014024708409/04/14Specifications support enablement
222014024717509/04/14Asynchronous to synchronous sampling using an augmented least squares solver
232014024756209/04/14Dc-dc converter vertically integrated with load inductor structured as heat sink
242014024764109/04/14Power reduction circuit and method
252014024764209/04/14Single sided bit line restore for power reduction
262014024874609/04/14Making a flip-chip assembly with bond fingers
272014025034209/04/14Automatable scan partitioning for low power using external control
282014023940908/28/14Non-volatile anti-fuse with consistent rupture
292014023947308/28/14Wire bonding assembly and method
302014023950008/28/14Integrated circuit (ic) having electrically conductive corrosion protecting cap over bond pads
312014023976808/28/14Capacitive micromachined ultrasonic transducer (cmut) with through-substrate via (tsv) substrate plug
322014023976908/28/14Capacitive micromachined ultrasonic transducer (cmut) device with through-substrate via (tsv)
332014023992208/28/14Apparatus and methods to control peak current mode controlled power converters using selective noise blanking
342014023992408/28/14Emulated current ramp for dc-dc converter
352014023993508/28/14Apparatus and method for selective and adaptive slope compensation in peak current mode controlled power converters
362014023997708/28/14Capacitive sensing
372014023997908/28/14Capacitive mems sensor devices
382014023998308/28/14Capacitive sensing
392014024006208/28/14Dielectric waveguide with deformable interface surface
402014024015308/28/14Advanced overload protection in sigma delta modulators
412014024046108/28/143d camera using flash with structured light
422014024057308/28/14Shared-field projection and imaging system
432014024098408/28/14Light emitting diode light bulb and incandescent lamp conversion apparatus
442014024106608/28/14Dual-function read/write cache for programmable non-volatile memory
452014024108308/28/14Read assist circuit for an sram technical field
462014024108908/28/14Read assist circuit for an sram technical field
472014024135808/28/14Packet processing match and action unit with a vliw action engine
482014024135908/28/14Packet processing vliw action unit with or-multi-ported instruction memory
492014024136108/28/14Packet processing match and action unit with configurable memory allocation
502014024136208/28/14Packet processing match and action unit with configurable bit allocation
512014024154908/28/14Robust estimation of sound source localization
522014024162008/28/14Illumination estimation using natural scene statistics
532014024184608/28/14Pick up tip assembly
542014024275508/28/14Making an integtated circuit module with dual leadframes
552014024422308/28/14Method for simulating circuitry by dynamically modifying device models that are problematic for out-of-range voltages
562014024496608/28/14Packet processing match and action unit with stateful actions
572014024509008/28/14Parallel scan distributors and collectors and process of testing integrated circuits
582014024530808/28/14System and method for scheduling jobs in a multi-core processor
592014023235908/21/14Resonance-based single inductor output-driven dc-dc converter and method
602014023242208/21/14Built-in self-test methods, circuits and apparatus for concurrent test of rf modules with a dynamically configurable test structure
612014023243908/21/14Negative edge preset reset flip-flop with dual-port slave latch
622014023244008/21/14Positive edge reset flip-flop with dual-port slave latch
632014023244108/21/14Positive edge preset flip-flop with dual-port slave latch
642014023244208/21/14Negative edge reset flip-flop with dual-port slave latch
652014023244308/21/14Negative edge preset flip-flop with dual-port slave latch
662014023293808/21/14Systems and methods for video processing
672014023327008/21/14Voltage conversion and charging from low bipolar input voltage
682014023349808/21/14Multiple cqi feedback for cellular networks
692014023350708/21/14Uplink synchronization management in wireless networks
702014023358608/21/14Carrier sense multiple access (csma) protocols for power line communications (plc)
712014023360908/21/14Ultra wideband modulation for body area networks
722014023647508/21/14Methods and systems for navigation in indoor environments
732014023647908/21/14Attitude estimation for pedestrian navigation using low cost mems accelerometer in mobile applications, and processing methods, apparatus and systems
742014023730908/21/14Interconnections for plural and hierarchical p1500 test wrappers
752014023731108/21/14System and method for sharing a communications link between multiple communications protocols
762014022511008/14/14Default trim code technique
772014022511208/14/14Die testing using top surface test pads
782014022522608/14/14Multi-step deposition of ferroelectric dielectric material
792014022587408/14/14Touch panel apparatus and methods
802014022651808/14/14Cqi feedback structure
812014022670508/14/14Adaptive real-time control of de-emphasis level in a usb 3.0 signal conditioner based on incoming signal frequency range
822014022673908/14/14Pre-coder selection based on resource block grouping
832014022766908/14/14Guided tool tips for expression calculation
842014022780508/14/14Adhesion of ferroelectric material to underlying conductive capacitor plate
852014022785908/14/14Diffusion resistor with reduced voltage coefficient of resistance and increased breakdown voltage using cmos wells
862014022787708/14/14Method of forming a metal contact opening with a width that is smaller than the minimum feature size of a photolithographically-defined opening
872014022789108/14/14Interdigitated chip capacitor assembly
882014022974808/14/14Apparatus and method for optimizing use of nvdc chargers
892014022978008/14/14Ieee 1149.1 and p1500 test interfaces combined circuits and processes
902014022978108/14/14Hierarchical access of test access ports in embedded core integrated circuits
912014021651708/07/14Vertical thermoelectric structures
922014021749708/07/14Mosfet with curved trench feature coupling termination trench to active trench
932014021756808/07/14Semiconductor package with cantilever leads
942014021794408/07/14Permanent magnet motor with sinusoidal back-emf waveform and related motor controller for position sensorless drives
952014021801808/07/14Apparatus and method for in situ current measurement in a conductor
962014021807508/07/14Adaptive slope generator
972014021809008/07/14Negative edge flip-flop with dual-port slave latch
982014021809108/07/14Positive edge flip-flop with dual-port slave latch
992014021811208/07/14Compensation circuitry and method for amplifiers driving large capacitive loads
1002014021917308/07/14Uplink synchronization management in wireless networks
1012014021921808/07/14Downlink 8 tx codebook sub-sampling for csi feedback
1022014021921908/07/14Downlink 8 tx codebook sub-sampling for csi feedback
1032014021927708/07/14Conditional instructions for packet processing
1042014021929408/07/14Rotate-mask-merge and deposit-field instructions for packet processing
1052014022076108/07/14Reduction of polysilicon residue in a trench for polysilicon trench filling processes
1062014022305208/07/14System and method for slave-based memory protection
1072014022312708/07/14System and method for virtual hardware memory protection
1082014021005307/31/14Bi-directional esd protection circuit
1092014021006207/31/14Leadframe-based semiconductor package having terminals on top and bottom surfaces
1102014021006407/31/14Wire bonding method and structure
1112014021051107/31/14Error detection in nonvolatile logic arrays using parity
1122014021053307/31/14Edge rate control gate drive circuit and system for high and low side devices with large driver fet
1132014021053507/31/14Signal level conversion in nonvolatile bitcell array
1142014021076507/31/14Capacitive single layer multi-touch panel having improved response characteristics
1152014021134707/31/14Bi-directional esd protection circuit
1162014021143907/31/14Circuit assembly
1172014021153207/31/14Four capacitor nonvolatile bit cell
1182014021153307/31/14Two capacitor self-referencing nonvolatile bitcell
1192014021157207/31/14Nonvolatile logic array with built-in test result signal
1202014021157607/31/14Nonvolatile logic array with built-in test drivers
1212014021175507/31/14Radio bearer dependent forwarding for handover
1222014021188207/31/14Dynamic determination of volterra kernels for digital pre-distortion
1232014021386307/31/14Low-complexity sensor displacement tolerant pulse oximetry based heart rate measurement
1242014021528207/31/141149.1 tap linking modules
1252014021528307/31/14Integrated circuit with jtag port, tap linking module, and off-chip tap interface port
1262014021542507/31/14Adjustable dummy fill
1272014020338807/24/14Optical sensor with integrated pinhole
1282014020378007/24/14System and method for active charge and discharge current balancing in multiple parallel-connected battery packs
1292014020418207/24/14Multi-sensor video frame synchronization apparatus and methods
1302014020482507/24/14Methods for energy-efficient unicast and multicast transmission in a wireless communication system
1312014020629607/24/14Transceiver with asymmetric matching network
1322014020798407/24/14Signal conitioner
1332014020813407/24/14Host controller interface for universal serial bus (usb) power delivery
1342014020817607/24/14Scan chain in an integrated circuit
1352014020817707/24/14Circuits and methods for dynamic allocation of scan test resources
1362014019748607/17/14Power integrated circuit including series-connected source substrate and drain substrate power mosfets
1372014019753407/17/14Substrate with bond fingers
1382014019787507/17/14Circuits and methods for signal interference mitigation
1392014019789507/17/14Variability and aging sensor for integrated circuits
1402014019841507/17/14Electrostatic discharge protection apparatus
1412014019855007/17/14Frequency multiplier
1422014019897707/17/14Enhancement of stereo depth maps
1432014020150307/17/14Processor micro-architecture for compute, save or restore multiple registers, devices, systems, methods and processes of manufacture
1442014019137807/10/14Integrated circuit package
1452014019138007/10/14Integrated circuit package and method of making
1462014019138107/10/14Integrated circuit module with dual leadframe
1472014019173007/10/14Converter and method for extracting maximum power from piezo vibration harvester
1482014019174307/10/14Current mode control arrangement and method thereof
1492014019194707/10/14Using natural movements of a hand-held device to manipulate digital content
1502014019239707/10/14Mems device with sloped support
1512014019274007/10/14Methods and apparatus for dual connectivity operation in a wireless communication network
1522014019586907/10/14Serial i/o using jtag tck and tms signals
1532014019588007/10/14Rate matching and scrambling techniques for control signaling
1542014019615407/10/14Systems and methods for controlling access to secure debugging and profiling features of a computer system
1552014018365507/03/14High performance isolated vertical bipolar junction transistor and method for forming in a cmos integrated circuit
1562014018365707/03/14Embedded polysilicon resistor in integrated circuits formed by a replacement gate process
1572014018365807/03/14Poly resistor for metal gate integrated circuits
1582014018366307/03/14Raised source/drain mos transistor and method of forming the transistor with an implant spacer and an epitaxial spacer
1592014018371907/03/14Electronic assembly includes a composite carrier
1602014018374407/03/14Package substrate with bondable traces having different lead finishes
1612014018425907/03/14Method and device for testing wafers
1622014018431007/03/14Switch architecture at low supply voltages
1632014018433007/03/14Time gain compensation
1642014018435007/03/14Two layer differential pair layout, and method of making thereof, for reduced crosstalk
1652014018438107/03/14Single photomask high precision thin film resistor
1662014018485007/03/14System and method for generating 360 degree video recording using mvc
1672014018547207/03/14Method for incorporating invisible access points for rssi-based indoor positioning applications
1682014018551807/03/14System and method for wifi positioning
1692014018555607/03/14Channel quality report processes, circuits and systems
1702014018568107/03/14Hierarchical inter-layer prediction in multi-loop scalable video coding
1712014018569107/03/14Signaling decoded picture buffer size in multi-loop scalable video coding
1722014018962807/03/14System and method of crossover determination in differential pair and bondwire pairs to minimize crosstalk
1732014017559706/26/14Trench with reduced silicon loss
1742014017559906/26/14Integrated circuit package with printed circuit layer
1752014017562606/26/14Integrated circuit package and method of manufacture
1762014017730306/26/14Volt-second integration cable compensation circuit
1772014017774006/26/14Hexagonal constellations and decoding same in digital communication systems
1782014017906406/26/14Method for fabricating a package-in-package for high heat dissipation
1792014018116506/26/14Three-term predictive adder and/or subtracter
1802014018160606/26/14Direct scan access jtag
1812014018160706/26/14Lock state machine operations upon stp data captures and shifts
1822014018160806/26/14Tap and linking module for scan access of multiple cores with ieee 1149.1 test access ports
1832014018160906/26/14Semiconductor test system and method
1842014016718206/19/14Ztcr poly resistor in replacement gate flow
1852014016729506/19/14Coatings for relatively movable surfaces
1862014016779206/19/14Scan testing system, method and apparatus
1872014016779506/19/14Active feedback silicon failure analysis die temperature control system
1882014016836106/19/14Systems and methods for memory-bandwidth efficient display composition
1892014016903806/19/14Digital isolator
1902014016948506/19/14Asymmetric channels in power line communications
1912014016949606/19/14Crest factor reduction for multi-band system
1922014017096706/19/14Wireless powered ic card for sensor data acquisition, processing and radio frequency transmission
1932014017110806/19/14Dynamic access point based positioning
1942014017314106/19/14Robust cable-type detection for usb power delivery
1952014017316206/19/14Command queue for communications bus
1962014017354806/19/14Tool for automation of functional safety metric calculation and prototyping of functional safety systems
1972014015914206/12/14Recessed channel insulated-gate field effect transistor with self-aligned gate and increased channel length
1982014015920106/12/14Single pattern high precision capacitor
1992014015924706/12/143d semiconductor interposer for heterogeneous integration of standard memory and split-architecture processor
2002014015981406/12/14Differential receiver
2012014015985406/12/14Planar inductor floating shield for q enhancement
2022014015995006/12/14Method, system, and apparatus for reducing inaccuracy in global navigation satellite system position and velocity solution
2032014016034106/12/14Maintaining distortion-free projection from a mobile device
2042014016060006/12/14Reverse voltage condition protection in a power supply system
2052014016120206/12/14Method, system and apparatus for reducing the peak-to-average ratio of a signal
2062014016125206/12/14One-way key fob and vehicle pairing verification, retention, and revocation
2072014016483806/12/14At-speed test access port operations
2082014016484406/12/14Pbist engine with distributed data logging
2092014016485406/12/14Pbist architecture with multiple asynchronous sub chips operating in differring voltage domains
2102014016485506/12/14Pbist read only memory image compression
2112014016485606/12/14Pbist engine with reduced sram testing bus width
2122014015155906/05/14On-chip calibration system and method for infrared sensor
2132014015189506/05/14Die having through-substrate vias with deformation protected tips
2142014015268606/05/14Local tone mapping for high dynamic range images
2152014015269406/05/14Merging multiple exposures to generate a high dynamic range image
2162014015297406/05/14Method for time of flight modulation frequency detection and illumination modulation frequency adjustment
2172014015297506/05/14Method for dynamically adjusting the operating parameters of a tof camera according to vehicle speed
2182014015308206/05/14Method and system for generating a display
2192014015346806/05/14Access and power management for centralized networks
2202014015488006/05/14Post-polymer revealing of through-substrate via tips
2212014015695106/05/14Multicore, multibank, fully concurrent coherence controller
2222014015703906/05/14Using data watchpoints to detect unitialized memory reads
2232014015707006/05/14Selectively accessing test access ports in a multiple test access port environment
2242014015707106/05/14Low power scan & delay test method and apparatus
2252014014401305/29/14Microelectromechanical system having movable element integrated into substrate-based package
2262014014563405/29/14Circuit and method for generating a reference voltage for a power converter
2272014014576205/29/14Power supply sensing circuits in integrated circuits
2282014014576705/29/14Pulse generation circuits in integrated circuits
2292014014603605/29/14Electrophoretic display and method of operating
2302014014680805/29/14Power efficient tunneled direct link setup apparatus, systems and methods
2312014014689305/29/14Method and apparatus for predictive reference data transfer scheme for motion estimation
2322014014690005/29/14Building, transmitting, and receiving frame structures in power line communications
2332014014696305/29/14Detecting double talk in acoustic echo cancellation using zero-crossing rate
2342014014705705/29/14Content adaptive edge and detail enhancement for image and video processing
2352014014794005/29/14Process-compatible sputtering target for forming ferroelectric memory capacitor plates
2362014014893505/29/14Pressurized gas stopper for leadframe transporting apparatus
2372014014969005/29/14Multi-processor, multi-domain, multi-protocol cache coherent speculation aware shared memory controller and interconnect
2382014013880505/22/14System for no-lead integrated circuit packages without tape frame
2392014013882205/22/14Integrated circuit package and method of manufacture
2402014013929705/22/14Balun with integrated decoupling as ground shield
2412014013994105/22/14Preamplifier output current control
2422014014010905/22/14Flyback power supply regulation apparatus and methods
2432014014014105/22/14Read margin measurement in a read-only memory
2442014014038005/22/14Initialization sequence for bi-directional communications in a carrier-based system
2452014014039505/22/14Adaptive coding unit (cu) partitioning based on image statistics
2462014014045205/22/14Crest factor reduction for signals with dynamic power and frequency distribution
2472014014348605/22/14Flexible arbitration scheme for multi endpoint atomic accesses in multicore systems
2482014014362205/22/14Jtag bus communication method and apparatus
2492014014363205/22/14Method to extend data retention for flash based storage in a real time device processed on generic semiconductor technology

ARCHIVE: New 2014 2013 2012 2011 2010 2009


This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. is not affiliated or associated with Texas Instruments, Inc.orporated in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Texas Instruments, Inc.orporated with additional patents listed. Browse our Agent directory for other possible listings. Page by



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