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Texas Instruments Incorporated
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Texas Instruments, Inc.orporated patents

Recent patent applications related to Texas Instruments, Inc.orporated. Texas Instruments, Inc.orporated is listed as an Agent/Assignee. Note: Texas Instruments, Inc.orporated may have other listings under different names/spellings. We're not affiliated with Texas Instruments, Inc.orporated, we're just tracking patents.

ARCHIVE: New 2014 2013 2012 2011 2010 2009 | Company Directory "T" | Texas Instruments, Inc.orporated-related inventors

Texas Instruments

Wire bonding assembly and method

Texas Instruments

Packet processing vliw action unit with or-multi-ported instruction memory

Texas Instruments

Light emitting diode light bulb and incandescent lamp conversion apparatus

Search recent Press Releases: Texas Instruments, Inc.orporated-related press releases
Count Application # Date Texas Instruments, Inc.orporated patents (updated weekly) - BOOKMARK this page
12014023940908/28/14 new patent  Non-volatile anti-fuse with consistent rupture
22014023947308/28/14 new patent  Wire bonding assembly and method
32014023950008/28/14 new patent  Integrated circuit (ic) having electrically conductive corrosion protecting cap over bond pads
42014023976808/28/14 new patent  Capacitive micromachined ultrasonic transducer (cmut) with through-substrate via (tsv) substrate plug
52014023976908/28/14 new patent  Capacitive micromachined ultrasonic transducer (cmut) device with through-substrate via (tsv)
62014023992208/28/14 new patent  Apparatus and methods to control peak current mode controlled power converters using selective noise blanking
72014023992408/28/14 new patent  Emulated current ramp for dc-dc converter
82014023993508/28/14 new patent  Apparatus and method for selective and adaptive slope compensation in peak current mode controlled power converters
92014023997708/28/14 new patent  Capacitive sensing
102014023997908/28/14 new patent  Capacitive mems sensor devices
112014023998308/28/14 new patent  Capacitive sensing
122014024006208/28/14 new patent  Dielectric waveguide with deformable interface surface
132014024015308/28/14 new patent  Advanced overload protection in sigma delta modulators
142014024046108/28/14 new patent  3d camera using flash with structured light
152014024057308/28/14 new patent  Shared-field projection and imaging system
162014024098408/28/14 new patent  Light emitting diode light bulb and incandescent lamp conversion apparatus
172014024106608/28/14 new patent  Dual-function read/write cache for programmable non-volatile memory
182014024108308/28/14 new patent  Read assist circuit for an sram technical field
192014024108908/28/14 new patent  Read assist circuit for an sram technical field
202014024135808/28/14 new patent  Packet processing match and action unit with a vliw action engine
212014024135908/28/14 new patent  Packet processing vliw action unit with or-multi-ported instruction memory
222014024136108/28/14 new patent  Packet processing match and action unit with configurable memory allocation
232014024136208/28/14 new patent  Packet processing match and action unit with configurable bit allocation
242014024154908/28/14 new patent  Robust estimation of sound source localization
252014024162008/28/14 new patent  Illumination estimation using natural scene statistics
262014024184608/28/14 new patent  Pick up tip assembly
272014024275508/28/14 new patent  Making an integtated circuit module with dual leadframes
282014024422308/28/14 new patent  Method for simulating circuitry by dynamically modifying device models that are problematic for out-of-range voltages
292014024496608/28/14 new patent  Packet processing match and action unit with stateful actions
302014024509008/28/14 new patent  Parallel scan distributors and collectors and process of testing integrated circuits
312014024530808/28/14 new patent  System and method for scheduling jobs in a multi-core processor
322014023235908/21/14Resonance-based single inductor output-driven dc-dc converter and method
332014023242208/21/14Built-in self-test methods, circuits and apparatus for concurrent test of rf modules with a dynamically configurable test structure
342014023243908/21/14Negative edge preset reset flip-flop with dual-port slave latch
352014023244008/21/14Positive edge reset flip-flop with dual-port slave latch
362014023244108/21/14Positive edge preset flip-flop with dual-port slave latch
372014023244208/21/14Negative edge reset flip-flop with dual-port slave latch
382014023244308/21/14Negative edge preset flip-flop with dual-port slave latch
392014023293808/21/14Systems and methods for video processing
402014023327008/21/14Voltage conversion and charging from low bipolar input voltage
412014023349808/21/14Multiple cqi feedback for cellular networks
422014023350708/21/14Uplink synchronization management in wireless networks
432014023358608/21/14Carrier sense multiple access (csma) protocols for power line communications (plc)
442014023360908/21/14Ultra wideband modulation for body area networks
452014023647508/21/14Methods and systems for navigation in indoor environments
462014023647908/21/14Attitude estimation for pedestrian navigation using low cost mems accelerometer in mobile applications, and processing methods, apparatus and systems
472014023730908/21/14Interconnections for plural and hierarchical p1500 test wrappers
482014023731108/21/14System and method for sharing a communications link between multiple communications protocols
492014022511008/14/14Default trim code technique
502014022511208/14/14Die testing using top surface test pads
512014022522608/14/14Multi-step deposition of ferroelectric dielectric material
522014022587408/14/14Touch panel apparatus and methods
532014022651808/14/14Cqi feedback structure
542014022670508/14/14Adaptive real-time control of de-emphasis level in a usb 3.0 signal conditioner based on incoming signal frequency range
552014022673908/14/14Pre-coder selection based on resource block grouping
562014022766908/14/14Guided tool tips for expression calculation
572014022780508/14/14Adhesion of ferroelectric material to underlying conductive capacitor plate
582014022785908/14/14Diffusion resistor with reduced voltage coefficient of resistance and increased breakdown voltage using cmos wells
592014022787708/14/14Method of forming a metal contact opening with a width that is smaller than the minimum feature size of a photolithographically-defined opening
602014022789108/14/14Interdigitated chip capacitor assembly
612014022974808/14/14Apparatus and method for optimizing use of nvdc chargers
622014022978008/14/14Ieee 1149.1 and p1500 test interfaces combined circuits and processes
632014022978108/14/14Hierarchical access of test access ports in embedded core integrated circuits
642014021651708/07/14Vertical thermoelectric structures
652014021749708/07/14Mosfet with curved trench feature coupling termination trench to active trench
662014021756808/07/14Semiconductor package with cantilever leads
672014021794408/07/14Permanent magnet motor with sinusoidal back-emf waveform and related motor controller for position sensorless drives
682014021801808/07/14Apparatus and method for in situ current measurement in a conductor
692014021807508/07/14Adaptive slope generator
702014021809008/07/14Negative edge flip-flop with dual-port slave latch
712014021809108/07/14Positive edge flip-flop with dual-port slave latch
722014021811208/07/14Compensation circuitry and method for amplifiers driving large capacitive loads
732014021917308/07/14Uplink synchronization management in wireless networks
742014021921808/07/14Downlink 8 tx codebook sub-sampling for csi feedback
752014021921908/07/14Downlink 8 tx codebook sub-sampling for csi feedback
762014021927708/07/14Conditional instructions for packet processing
772014021929408/07/14Rotate-mask-merge and deposit-field instructions for packet processing
782014022076108/07/14Reduction of polysilicon residue in a trench for polysilicon trench filling processes
792014022305208/07/14System and method for slave-based memory protection
802014022312708/07/14System and method for virtual hardware memory protection
812014021005307/31/14Bi-directional esd protection circuit
822014021006207/31/14Leadframe-based semiconductor package having terminals on top and bottom surfaces
832014021006407/31/14Wire bonding method and structure
842014021051107/31/14Error detection in nonvolatile logic arrays using parity
852014021053307/31/14Edge rate control gate drive circuit and system for high and low side devices with large driver fet
862014021053507/31/14Signal level conversion in nonvolatile bitcell array
872014021076507/31/14Capacitive single layer multi-touch panel having improved response characteristics
882014021134707/31/14Bi-directional esd protection circuit
892014021143907/31/14Circuit assembly
902014021153207/31/14Four capacitor nonvolatile bit cell
912014021153307/31/14Two capacitor self-referencing nonvolatile bitcell
922014021157207/31/14Nonvolatile logic array with built-in test result signal
932014021157607/31/14Nonvolatile logic array with built-in test drivers
942014021175507/31/14Radio bearer dependent forwarding for handover
952014021188207/31/14Dynamic determination of volterra kernels for digital pre-distortion
962014021386307/31/14Low-complexity sensor displacement tolerant pulse oximetry based heart rate measurement
972014021528207/31/141149.1 tap linking modules
982014021528307/31/14Integrated circuit with jtag port, tap linking module, and off-chip tap interface port
992014021542507/31/14Adjustable dummy fill
1002014020338807/24/14Optical sensor with integrated pinhole
1012014020378007/24/14System and method for active charge and discharge current balancing in multiple parallel-connected battery packs
1022014020418207/24/14Multi-sensor video frame synchronization apparatus and methods
1032014020482507/24/14Methods for energy-efficient unicast and multicast transmission in a wireless communication system
1042014020629607/24/14Transceiver with asymmetric matching network
1052014020798407/24/14Signal conitioner
1062014020813407/24/14Host controller interface for universal serial bus (usb) power delivery
1072014020817607/24/14Scan chain in an integrated circuit
1082014020817707/24/14Circuits and methods for dynamic allocation of scan test resources
1092014019748607/17/14Power integrated circuit including series-connected source substrate and drain substrate power mosfets
1102014019753407/17/14Substrate with bond fingers
1112014019787507/17/14Circuits and methods for signal interference mitigation
1122014019789507/17/14Variability and aging sensor for integrated circuits
1132014019841507/17/14Electrostatic discharge protection apparatus
1142014019855007/17/14Frequency multiplier
1152014019897707/17/14Enhancement of stereo depth maps
1162014020150307/17/14Processor micro-architecture for compute, save or restore multiple registers, devices, systems, methods and processes of manufacture
1172014019137807/10/14Integrated circuit package
1182014019138007/10/14Integrated circuit package and method of making
1192014019138107/10/14Integrated circuit module with dual leadframe
1202014019173007/10/14Converter and method for extracting maximum power from piezo vibration harvester
1212014019174307/10/14Current mode control arrangement and method thereof
1222014019194707/10/14Using natural movements of a hand-held device to manipulate digital content
1232014019239707/10/14Mems device with sloped support
1242014019274007/10/14Methods and apparatus for dual connectivity operation in a wireless communication network
1252014019586907/10/14Serial i/o using jtag tck and tms signals
1262014019588007/10/14Rate matching and scrambling techniques for control signaling
1272014019615407/10/14Systems and methods for controlling access to secure debugging and profiling features of a computer system
1282014018365507/03/14High performance isolated vertical bipolar junction transistor and method for forming in a cmos integrated circuit
1292014018365707/03/14Embedded polysilicon resistor in integrated circuits formed by a replacement gate process
1302014018365807/03/14Poly resistor for metal gate integrated circuits
1312014018366307/03/14Raised source/drain mos transistor and method of forming the transistor with an implant spacer and an epitaxial spacer
1322014018371907/03/14Electronic assembly includes a composite carrier
1332014018374407/03/14Package substrate with bondable traces having different lead finishes
1342014018425907/03/14Method and device for testing wafers
1352014018431007/03/14Switch architecture at low supply voltages
1362014018433007/03/14Time gain compensation
1372014018435007/03/14Two layer differential pair layout, and method of making thereof, for reduced crosstalk
1382014018438107/03/14Single photomask high precision thin film resistor
1392014018485007/03/14System and method for generating 360 degree video recording using mvc
1402014018547207/03/14Method for incorporating invisible access points for rssi-based indoor positioning applications
1412014018551807/03/14System and method for wifi positioning
1422014018555607/03/14Channel quality report processes, circuits and systems
1432014018568107/03/14Hierarchical inter-layer prediction in multi-loop scalable video coding
1442014018569107/03/14Signaling decoded picture buffer size in multi-loop scalable video coding
1452014018962807/03/14System and method of crossover determination in differential pair and bondwire pairs to minimize crosstalk
1462014017559706/26/14Trench with reduced silicon loss
1472014017559906/26/14Integrated circuit package with printed circuit layer
1482014017562606/26/14Integrated circuit package and method of manufacture
1492014017730306/26/14Volt-second integration cable compensation circuit
1502014017774006/26/14Hexagonal constellations and decoding same in digital communication systems
1512014017906406/26/14Method for fabricating a package-in-package for high heat dissipation
1522014018116506/26/14Three-term predictive adder and/or subtracter
1532014018160606/26/14Direct scan access jtag
1542014018160706/26/14Lock state machine operations upon stp data captures and shifts
1552014018160806/26/14Tap and linking module for scan access of multiple cores with ieee 1149.1 test access ports
1562014018160906/26/14Semiconductor test system and method
1572014016718206/19/14Ztcr poly resistor in replacement gate flow
1582014016729506/19/14Coatings for relatively movable surfaces
1592014016779206/19/14Scan testing system, method and apparatus
1602014016779506/19/14Active feedback silicon failure analysis die temperature control system
1612014016836106/19/14Systems and methods for memory-bandwidth efficient display composition
1622014016903806/19/14Digital isolator
1632014016948506/19/14Asymmetric channels in power line communications
1642014016949606/19/14Crest factor reduction for multi-band system
1652014017096706/19/14Wireless powered ic card for sensor data acquisition, processing and radio frequency transmission
1662014017110806/19/14Dynamic access point based positioning
1672014017314106/19/14Robust cable-type detection for usb power delivery
1682014017316206/19/14Command queue for communications bus
1692014017354806/19/14Tool for automation of functional safety metric calculation and prototyping of functional safety systems
1702014015914206/12/14Recessed channel insulated-gate field effect transistor with self-aligned gate and increased channel length
1712014015920106/12/14Single pattern high precision capacitor
1722014015924706/12/143d semiconductor interposer for heterogeneous integration of standard memory and split-architecture processor
1732014015981406/12/14Differential receiver
1742014015985406/12/14Planar inductor floating shield for q enhancement
1752014015995006/12/14Method, system, and apparatus for reducing inaccuracy in global navigation satellite system position and velocity solution
1762014016034106/12/14Maintaining distortion-free projection from a mobile device
1772014016060006/12/14Reverse voltage condition protection in a power supply system
1782014016120206/12/14Method, system and apparatus for reducing the peak-to-average ratio of a signal
1792014016125206/12/14One-way key fob and vehicle pairing verification, retention, and revocation
1802014016483806/12/14At-speed test access port operations
1812014016484406/12/14Pbist engine with distributed data logging
1822014016485406/12/14Pbist architecture with multiple asynchronous sub chips operating in differring voltage domains
1832014016485506/12/14Pbist read only memory image compression
1842014016485606/12/14Pbist engine with reduced sram testing bus width
1852014015155906/05/14On-chip calibration system and method for infrared sensor
1862014015189506/05/14Die having through-substrate vias with deformation protected tips
1872014015268606/05/14Local tone mapping for high dynamic range images
1882014015269406/05/14Merging multiple exposures to generate a high dynamic range image
1892014015297406/05/14Method for time of flight modulation frequency detection and illumination modulation frequency adjustment
1902014015297506/05/14Method for dynamically adjusting the operating parameters of a tof camera according to vehicle speed
1912014015308206/05/14Method and system for generating a display
1922014015346806/05/14Access and power management for centralized networks
1932014015488006/05/14Post-polymer revealing of through-substrate via tips
1942014015695106/05/14Multicore, multibank, fully concurrent coherence controller
1952014015703906/05/14Using data watchpoints to detect unitialized memory reads
1962014015707006/05/14Selectively accessing test access ports in a multiple test access port environment
1972014015707106/05/14Low power scan & delay test method and apparatus
1982014014401305/29/14Microelectromechanical system having movable element integrated into substrate-based package
1992014014563405/29/14Circuit and method for generating a reference voltage for a power converter
2002014014576205/29/14Power supply sensing circuits in integrated circuits
2012014014576705/29/14Pulse generation circuits in integrated circuits
2022014014603605/29/14Electrophoretic display and method of operating
2032014014680805/29/14Power efficient tunneled direct link setup apparatus, systems and methods
2042014014689305/29/14Method and apparatus for predictive reference data transfer scheme for motion estimation
2052014014690005/29/14Building, transmitting, and receiving frame structures in power line communications
2062014014696305/29/14Detecting double talk in acoustic echo cancellation using zero-crossing rate
2072014014705705/29/14Content adaptive edge and detail enhancement for image and video processing
2082014014794005/29/14Process-compatible sputtering target for forming ferroelectric memory capacitor plates
2092014014893505/29/14Pressurized gas stopper for leadframe transporting apparatus
2102014014969005/29/14Multi-processor, multi-domain, multi-protocol cache coherent speculation aware shared memory controller and interconnect
2112014013880505/22/14System for no-lead integrated circuit packages without tape frame
2122014013882205/22/14Integrated circuit package and method of manufacture
2132014013929705/22/14Balun with integrated decoupling as ground shield
2142014013994105/22/14Preamplifier output current control
2152014014010905/22/14Flyback power supply regulation apparatus and methods
2162014014014105/22/14Read margin measurement in a read-only memory
2172014014038005/22/14Initialization sequence for bi-directional communications in a carrier-based system
2182014014039505/22/14Adaptive coding unit (cu) partitioning based on image statistics
2192014014045205/22/14Crest factor reduction for signals with dynamic power and frequency distribution
2202014014348605/22/14Flexible arbitration scheme for multi endpoint atomic accesses in multicore systems
2212014014362205/22/14Jtag bus communication method and apparatus
2222014014363205/22/14Method to extend data retention for flash based storage in a real time device processed on generic semiconductor technology
2232014014384905/22/14Secure master and secure guest endpoint security firewall
2242014013880505/22/14System for no-lead integrated circuit packages without tape frame
2252014013882205/22/14Integrated circuit package and method of manufacture
2262014013929705/22/14Balun with integrated decoupling as ground shield
2272014013994105/22/14Preamplifier output current control
2282014014010905/22/14Flyback power supply regulation apparatus and methods
2292014014014105/22/14Read margin measurement in a read-only memory
2302014014038005/22/14Initialization sequence for bi-directional communications in a carrier-based system
2312014014039505/22/14Adaptive coding unit (cu) partitioning based on image statistics
2322014014045205/22/14Crest factor reduction for signals with dynamic power and frequency distribution
2332014014348605/22/14Flexible arbitration scheme for multi endpoint atomic accesses in multicore systems
2342014014362205/22/14Jtag bus communication method and apparatus
2352014014363205/22/14Method to extend data retention for flash based storage in a real time device processed on generic semiconductor technology
2362014014384905/22/14Secure master and secure guest endpoint security firewall
2372014013157705/15/14Infrared sensor structure and method
2382014013178105/15/14Low resistance stacked annular contact
2392014013233105/15/14Wide common mode range transmission gate
2402014013340405/15/14Mac extensions for smart antenna support
2412014013360205/15/14Digital pre-distortion of non-linear systems with reduced bandwidth feedback
2422014013361305/15/14Apparatus and methods for clock alignment for high speed interfaces
2432014013506805/15/14Systems, processes and integrated circuits for rate and/or diversity adaptation for packet communications
2442014013691305/15/14Dual mode test access port method and apparatus
2452014013613805/15/14On-chip spectral analysis using enhanced recursive discrete fourier transforms
2462014013157705/15/14Infrared sensor structure and method
2472014013178105/15/14Low resistance stacked annular contact
2482014013233105/15/14Wide common mode range transmission gate
2492014013340405/15/14Mac extensions for smart antenna support

ARCHIVE: New 2014 2013 2012 2011 2010 2009


This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. is not affiliated or associated with Texas Instruments, Inc.orporated in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Texas Instruments, Inc.orporated with additional patents listed. Browse our Agent directory for other possible listings. Page by



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