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Texas Instruments Incorporated
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Texas Instruments Incorporated patents

Recent patent applications related to Texas Instruments Incorporated. Texas Instruments Incorporated is listed as an Agent/Assignee. Note: Texas Instruments Incorporated may have other listings under different names/spellings. We're not affiliated with Texas Instruments Incorporated, we're just tracking patents.

ARCHIVE: New 2015 2014 2013 2012 2011 2010 2009 | Company Directory "T" | Texas Instruments Incorporated-related inventors

Count Application # Date Texas Instruments Incorporated patents (updated weekly) - BOOKMARK this page
12015024147708/27/15 Effective and efficient solution for pin to pad contactor on wide range of smd package tolerances using a reverse funnel design anvil handler mechanism
22015024151308/27/15 Core circuit test architecture
32015024349408/27/15 Mechanically robust silicon substrate having group iiia-n epitaxial layer thereon
42015024363908/27/15 Integrated passive flip chip package
52015024364108/27/15 Integrated circuit package
62015024364808/27/15 Quantum well-modulated bipolar junction transistor
72015024374208/27/15 Method to form stepped dielectric for field plate formation
82015024375708/27/15 Bi-directional esd diode structure with ultra-low capacitance that consumes a small amount of silicon real estate
92015024426908/27/15 Switching mode power supply with adaptively randomized spread spectrum
102015024435508/27/15 Low-power offset-stored latch
112015024437208/27/15 Single supply level shifter with improved rise time and reduced leakage
122015024438608/27/15 Background dac calibration for pipeline adc
132015024454108/27/15 Enhanced carrier sense multiple access (csma) protocols
142015024497508/27/15 Power supply architectures for powered devices
152015024502608/27/15 Signaling signed band offset values for sample adaptive offset (sao) filtering in video coding
162015024503808/27/15 Methods and reduced bandwidth pulse width modulation
172015023369508/20/15 Inductive position-sensing
182015023400008/20/15 Real time semiconductor process excursion monitor
192015023400908/20/15 Test compression in a jtag daisy-chain environment
202015023440408/20/15 Low dropout voltage regulator circuits
212015023451908/20/15 Touchscreen controller and charger noise reduction through noise shaping
222015023599908/20/15 Converter having partially thinned leadframe with stacked chips and interposer, free of wires and clips
232015023667008/20/15 Output range for interpolation architectures employing a cascaded integrator-comb (cic) filter with a multiplier
242015023673008/20/15 Subtracting linear impairments for non-linear impairment digital pre-distortion error signal
252015023675308/20/15 Coexistence method by requesting access to the channel
262015023675908/20/15 Loop powered transmitter with a single tap data isolation transformer and unipolar voltage converters
272015023688208/20/15 Sounding reference signal processing for lte
282015023737008/20/15 Parallel motion estimation in video coding
292015023738008/20/15 Systems and methods for reducing blocking artifacts
302015022461508/13/15 Turntable
312015022661808/13/15 Piezoelectric thin-film sensor and use thereof
322015022679808/13/15 Boundary scan path method and system with functional and non-functional scan cell memories
332015022679908/13/15 Removable and replaceable tap domain selection circuitry
342015022714708/13/15 Load dependent biasing cell for low dropout regulator
352015022742108/13/15 Package on package memory interface and configuration with error code correction
362015022748508/13/15 Usb switch with multi-role ports
372015022748808/13/15 System and improving ecc enabled memory timing
382015022764008/13/15 File systems, processes, circuits, devices and electronic systems
392015022856308/13/15 Lead frame with abutment surface
402015022856608/13/15 High pin count, small packages having heat-dissipating pad
412015022858108/13/15 Integrated circuit package fabrication
422015022910208/13/15 Method and disabling a laser
432015022912408/13/15 Dynamic current pull-down for voltage regulator
442015022919908/13/15 Constant on-time control for power converter
452015022921508/13/15 Buck-boost converter with smooth transition circuits and methods
462015022924108/13/15 Mems electrostatic actuator
472015022925408/13/15 Angular frequency extractor for controlling a brushed dc motor
482015022927808/13/15 Chopped operational-amplifier (op-amp) system
492015022928008/13/15 Nonlinear class ab input stage
502015022945808/13/15 Electric vehicle and service equipment on a pilot wire
512015022961308/13/15 Methods and apparatus to provide extended object notation data
522015023031308/13/15 Led control system
532015023034508/13/15 Interdigitated chip capacitor assembly
542015021969008/06/15 Current sensor
552015021975408/06/15 Programmable wavelet tree
562015021976808/06/15 Cross coupled positioning engine (pe) architecture for sensor integration in global navigation satellite system (gnss)
572015022006508/06/15 Circuit for detecting and correcting timing errors
582015022151608/06/15 Process-compatible sputtering target for forming ferroelectric memory capacitor plates
592015022152408/06/15 Sloped photoresist edges for defect reduction for metal dry etch processes
602015022152608/06/15 Selective planishing making a semiconductor device
612015022158408/06/15 Stacked synchronous buck converter having chip embedded in outside recess of leadframe
622015022162208/06/15 Dc-dc converter having terminals of semiconductor chips directly attachable to circuit board
632015022174708/06/15 Avalanche energy handling capable iii-nitride transistors
642015022200408/06/15 Terminationless power splitter/combiner
652015022221708/06/15 Travelling wave motor pre-driver using high resolution pwm generators
662015022223708/06/15 Amplifier with reduced idle power loss using single-ended loops
672015022228208/06/15 Timing compensation using the system clock
682015022232708/06/15 Scaled power line based network
692015022232808/06/15 Scaled power line based network
702015022246308/06/15 Transmitter and transmitting
712015022262108/06/15 Auto-provisioning for internet-of-things devices
722015022265808/06/15 Relay attack countermeasure system
732015022290308/06/15 Method and sub-picture based raster scanning coding order
742015022290408/06/15 Parsing friendly and error resilient merge flag coding in video coding
752015021189507/30/15 Inductive sensing including inductance multiplication with series connected coils
762015021211607/30/15 Magnetically coupled dc current sensor
772015021214307/30/15 Kill die subroutine at probe for reducing parametric failing devices at package test
782015021215007/30/15 Dft approach to enable faster scan chain diagnosis
792015021215207/30/15 Testing of integrated circuits during at-speed mode of operation
802015021215307/30/15 System and sharing a communications link between multiple communications protocols
812015021292107/30/15 Debug trace stream timestamping using downstream correlation
822015021295507/30/15 Programmable interrupt routing in multiprocessor devices
832015021388307/30/15 Testing signal development on a bit line in an sram
842015021406907/30/15 Piezoelectric thin film process
852015021409607/30/15 Sinker with a reduced width
862015021413607/30/15 Semiconductor device having leadframe with pressure-absorbing pad straps
872015021419807/30/15 Stacked semiconductor system having interposer of half-etched and molded sheet metal
882015021422207/30/15 Monolithically integrated transistors for a buck converter using source down mosfet
892015021484607/30/15 Bi-modal voltage converter
902015021490707/30/15 System, for power amplification of a signal in an integrated circuit
912015021493407/30/15 Relaxation oscillator with low drift and native offset cancellation
922015021498807/30/15 Dual loop digital predistortion for power amplifiers
932015021501507/30/15 Multi-rank precoding matrix indicator (pmi) feedback in a multiple-input multiple-output (mimo) system
942015021591607/30/15 Physical downlink control channel and physical hybrid automatic repeat request indicator channel enhancements
952015021596807/30/15 Random access channel false alarm control
962015020492507/23/15 Method and lra real time impedance tracking and bemf extraction
972015020509807/23/15 Low cost window production for hermetically sealed optical packages
982015020740007/23/15 Control thermal balancing in multiphase dc-dc converters
992015020740507/23/15 Input offset control
1002015020752107/23/15 Usb power delivery multiple drop using cyclic redundancy check
1012015020754007/23/15 Systems and methods for implementing application profiles and device classes in power line communication (plc) environments
1022015020797407/23/15 Methods and apparatus to generate wide dynamic range images
1032015020845107/23/15 Access point discoverability in multi-role multi-channel devices
1042015019621307/16/15 Heart monitors and processes with accelerometer motion artifact cancellation, and other electronic systems
1052015019866407/16/15 Integrated circuit
1062015019869407/16/15 Positioning server
1072015019869507/16/15 Wireless device for indoor positioning
1082015019872107/16/15 System for crowd-sourced fingerprinting
1092015020077107/16/15 Methods and systems for clock drift compensation interpolation
1102015019491407/09/15 Automated motor control
1112015019500307/09/15 Enhanced cross correlation detection or mitigation circuits, processes, devices, receivers and systems
1122015018499307/02/15 Resonant inductive sensing with active resonator target
1132015018528307/02/15 Handling slower scan outputs at optimal frequency
1142015018529407/02/15 Resonant impedance sensing with a negative impedance control loop implemented with synchronized class d and output comparators
1152015018531607/02/15 Techniques for angle resolution in radar
1162015018658807/02/15 Multilevel via placement with improved yield in dual damascene interconnection
1172015018668207/02/15 Less-secure processors, integrated circuits, wireless communications apparatus, methods and processes of making
1182015018748807/02/15 Integrated circuit with micro inductor and micro transformer with magnetic core
1192015018757007/02/15 Process for forming pzt or plzt thinfilms with low defectivity
1202015018758307/02/15 Dilution doped integrated circuit resistors
1212015018758507/02/15 Dummy gate placement methodology to enhance integrated circuit performance
1222015018759707/02/15 Method to improve slip resistance of silicon wafers
1232015018759807/02/15 High precision capacitor dielectric
1242015018763207/02/15 Metal thin film resistor and process
1252015018763507/02/15 Method to reduce particles during sti fill and reduce cmp scratches
1262015018765307/02/15 High-k / metal gate cmos transistors with tin gates
1272015018765507/02/15 Method to improve transistor matching
1282015018765607/02/15 Laser anneals for reduced diode leakage
1292015018765807/02/15 Implant profiling with resist
1302015018765907/02/15 High quality dielectric for hi-k last replacement gate transistors
1312015018766107/02/15 Dual layer hardmask for embedded epi growth
1322015018767707/02/15 Lid for integrated circuit package
1332015018771107/02/15 Opening in a multilayer polymeric dielectric layer without delamination
1342015018772907/02/15 Wire stitch bond having strengthened heel
1352015018775207/02/15 Bi-directional esd protection device
1362015018775507/02/15 Npn heterojunction bipolar transistor in cmos flow
1372015018775807/02/15 Schottky diodes for replacement metal gate integrated circuits
1382015018775907/02/15 High sheet resistor in cmos flow
1392015018776007/02/15 Deep collector vertical bipolar transistor with enhanced gain
1402015018776807/02/15 Poly gate extension design methodology to improve cmos performance in dual stress liner process flow
1412015018777007/02/15 High mobility transistors
1422015018777107/02/15 Hybrid high-k first and high-k last replacement gate process
1432015018777207/02/15 Optimized layout for relaxed and strained liner in single stress liner technology
1442015018777307/02/15 High mobility transistors
1452015018790307/02/15 Fringe capacitance reduction for replacement gate cmos
1462015018793407/02/15 High voltage multiple channel ldmos
1472015018793707/02/15 Ldmos chc reliability
1482015018793807/02/15 Low cost demos transistor with improved chc immunity
1492015018795707/02/15 Transistor with improved radiation hardness
1502015018841307/02/15 Multiple output integrated power factor correction
1512015018843207/02/15 Switched mode assisted linear regulator with seamless transition between power tracking configurations
1522015018851907/02/15 Dual edge-triggered retention flip-flop
1532015018852207/02/15 Resonant impedance sensing with drive current pulse shaping to reduce noise folding
1542015018853307/02/15 Bootstrapped sampling switch circuits and systems
1552015018856107/02/15 Novel technique to combine a coarse adc and a sar adc
1562015018862607/02/15 Optical fiber defect detection
1572015018883807/02/15 Disabling network connectivity on student devices
1582015017732306/25/15 Scan test method and apparatus
1592015017732406/25/15 Scan topology discovery in target systems
1602015017732506/25/15 Semiconductor test system and method
1612015017732606/25/15 Waveform calibration using built in self test mechanism
1622015017822106/25/15 Level one data cache line lock and enhanced snoop protocol during cache victims and writebacks to maintain level one data cache and level two cache coherence
1632015017851306/25/15 Method and system of verifying proper execution of a secure mode entry sequence
1642015017857306/25/15 Ground plane detection
1652015017945206/25/15 High voltage depletion mode n-channel jfet
1662015017959206/25/15 Self-aligned under bump metal
1672015017965406/25/15 Epitaxial source/drain differential spacers
1682015017978306/25/15 Metal-gate mos transistor and forming the transistor with reduced gate-to-source and gate-to-drain overlap capacitance
1692015017979206/25/15 Scheme to align ldmos drain extension to moat
1702015017979306/25/15 Lateral mosfet with buried drain extension layer
1712015018033006/25/15 Apparatus and zero voltage switching in bridgeless totem pole power factor correction converter
1722015018053906/25/15 Enabling co-existence among power line communication (plc) technologies
1732015018059406/25/15 Self-calibrating shared-component dual synthesizer
1742015018068006/25/15 Overlapping priority contention windows power line communications networks
1752015018069206/25/15 Circuits and methods for transmitting signals
1762015018162106/25/15 Multiple nfc card applications in multiple execution environments
1772015018170606/25/15 High voltage polymer dielectric capacitor isolation device
1782015016832806/18/15 Capacitive sensing for paper tray
1792015016849206/18/15 Test access port with address and command capability
1802015016849306/18/15 Testing interposer method and apparatus
1812015016849406/18/15 Synchronizing a device that has been power cycled to an already operational system
1822015016981406/18/15 Harmonic distortion macro model correction using a memory table
1832015016981506/18/15 Harmonic distortion vs. output loading macro-modeling
1842015017096206/18/15 Metal on elongated contacts
1852015017097106/18/15 Methodology of forming cmos gates on the secondary axis using double-patterning technique
1862015017097206/18/15 Method to form silicide and contact at embedded epitaxial facet
1872015017097506/18/15 Elongated contacts using litho-freeze-litho-etch process
1882015017098306/18/15 Probe pad design to reduce saw defects
1892015017099806/18/15 Use of dielectric slots for reducing via resistance in dual damascene process
1902015017099906/18/15 Multiple depth vias in an integrated circuit
1912015017104606/18/15 Self-adhesive die
1922015017107706/18/15 Poly resistor for metal gate integrated circuits
1932015017109106/18/15 Self aligned active trench contact
1942015017115806/18/15 Low temperature coefficient resistor in cmos flow
1952015017121106/18/15 Reduced area power devices using deep trench isolation
1962015017121206/18/15 High voltage lateral dmos transistor with optimized source-side blocking capability
1972015017121306/18/15 High voltage lateral extended drain mos transistor with improved drift layer contact
1982015017121706/18/15 Design and integration of finfet device
1992015017163406/18/15 Data extraction threshold circuit and method
2002015017192206/18/15 Channel selection in power line communications
2012015017193206/18/15 Circuit and architecture for a demodulator for a wireless power transfer system and method therefor
2022015017193506/18/15 Circuit and architecture for a demodulator for a wireless power transfer system and method therefor
2032015017207306/18/15 Transmission of segmented frames in power line communication
2042015017271806/18/15 Low complexity large transform
2052015016922306/18/15 Dynamic processor-memory revectoring architecture
2062015016028506/11/15 Apparatus and methods for qualifying hemt fet devices
2072015016029406/11/15 Parallel and serial access to test compression architectures
2082015016029506/11/15 Method and device access port selection
2092015016035006/11/15 Antenna selection for gnss receivers
2102015016045406/11/15 Multiple illumination sources for dmd lighting apparatus and methods
2112015016231706/11/15 Fabricating a proximity sensor having light-blocking structure in leadframe
2122015016283006/11/15 Power converter soft start circuit
2132015016313406/11/15 Routing protocols for power line communications (plc)
2142015016320706/11/15 Pairwise temporal key creation for secure networks
2152015015341106/04/15 Ieee 1149.1 interposer method and apparatus
2162015015341206/04/15 Dual mode test access port method and apparatus
2172015015402406/04/15 Vector simd vliw data path architecture
2182015015578306/04/15 Switched mode assisted linear regulator with dynamic buck turn-off using zcd-controlled tub switching
2192015015649006/04/15 Virtual boundary processing simplification for adaptive loop filtering (alf) in video coding
2202015014369005/28/15 Forming integrated inductors and transformers with embedded magnetic cores
2212015014438905/28/15 Method of minimizing mold flash during dambar cut
2222015014503605/28/15 Power integrated circuit including series-connected source substrate and drain substrate power mosfets
2232015014504005/28/15 Metal oxide semiconductor and making
2242015014505805/28/15 Transistor with deep nwell implanted through the gate
2252015014509705/28/15 Photodiode with a dark current suppression junction
2262015014512505/28/15 Passivation process to prevent tiw corrosion
2272015014543005/28/15 Combined digital modulation and current dimming control for light emitting diodes
2282015014549705/28/15 Low-loss step-up and step-down voltage converter
2292015014617405/28/15 Projector with optical conversion media pumped by low etendue source
2302015014633005/28/15 Esd robust mos device
2312015014667605/28/15 Downlink multiple input multiple output enhancements for single-cell with remote radio heads
2322015014682305/28/15 Wireless network receiver
2332015014703405/28/15 Optical connector
2342015014784505/28/15 Dual sided embedded die and fabrication of same background
2352015014788105/28/15 Passivation ash/oxidation of bare copper
2362015014933105/28/15 Taking device inventory using dynamically generated symbols
2372015014983305/28/15 Embedding stall and event trace profiling data in the timing stream - extended timing trace circuits, processes, and systems
2382015014984405/28/15 Double data rate test interface and architecture
2392015014984505/28/15 Device testing architecture, method, and system
2402015013761905/21/15 Method and circuitry for controlling a depletion-mode transistor
2412015013770005/21/15 Systems and methods of driving multiple outputs
2422015013771305/21/15 Adaptive linear resonance actuator controller
2432015013800405/21/15 Method for calibrating a pipelined continuous-time sigma delta modulator
2442015013831205/21/15 Method and a surround view camera system photometric alignment
2452015013844605/21/15 Compact optical projection apparatus
2462015013899505/21/15 Method, system and phase noise cancellation
2472015013956805/21/15 Method and a optimal seam for surround view synthesis
2482015014076905/21/15 Raised source/drain mos transistor and forming the transistor with an implant spacer and an epitaxial spacer
2492015014237905/21/15 Method and forcing the measurements of the angles of a triangle

ARCHIVE: New 2015 2014 2013 2012 2011 2010 2009


This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. is not affiliated or associated with Texas Instruments Incorporated in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Texas Instruments Incorporated with additional patents listed. Browse our Agent directory for other possible listings. Page by