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Texas Instruments Incorporated patents


      
Recent patent applications related to Texas Instruments Incorporated. Texas Instruments Incorporated is listed as an Agent/Assignee. Note: Texas Instruments Incorporated may have other listings under different names/spellings. We're not affiliated with Texas Instruments Incorporated, we're just tracking patents.

ARCHIVE: New 2015 2014 2013 2012 2011 2010 2009 | Company Directory "T" | Texas Instruments Incorporated-related inventors


Low cost window production for hermetically sealed optical packages

Texas Instruments

Low cost window production for hermetically sealed optical packages

Usb power delivery multiple drop using cyclic redundancy check

Texas Instruments

Usb power delivery multiple drop using cyclic redundancy check



Count Application # Date Texas Instruments Incorporated patents (updated weekly) - BOOKMARK this page
12015020492507/23/15  new patent  Method and lra real time impedance tracking and bemf extraction
22015020509807/23/15  new patent  Low cost window production for hermetically sealed optical packages
32015020740007/23/15  new patent  Control thermal balancing in multiphase dc-dc converters
42015020740507/23/15  new patent  Input offset control
52015020752107/23/15  new patent  Usb power delivery multiple drop using cyclic redundancy check
62015020754007/23/15  new patent  Systems and methods for implementing application profiles and device classes in power line communication (plc) environments
72015020797407/23/15  new patent  Methods and apparatus to generate wide dynamic range images
82015020845107/23/15  new patent  Access point discoverability in multi-role multi-channel devices
92015019621307/16/15 Heart monitors and processes with accelerometer motion artifact cancellation, and other electronic systems
102015019866407/16/15 Integrated circuit
112015019869407/16/15 Positioning server
122015019869507/16/15 Wireless device for indoor positioning
132015019872107/16/15 System for crowd-sourced fingerprinting
142015020077107/16/15 Methods and systems for clock drift compensation interpolation
152015019491407/09/15 Automated motor control
162015019500307/09/15 Enhanced cross correlation detection or mitigation circuits, processes, devices, receivers and systems
172015018499307/02/15 Resonant inductive sensing with active resonator target
182015018528307/02/15 Handling slower scan outputs at optimal frequency
192015018529407/02/15 Resonant impedance sensing with a negative impedance control loop implemented with synchronized class d and output comparators
202015018531607/02/15 Techniques for angle resolution in radar
212015018658807/02/15 Multilevel via placement with improved yield in dual damascene interconnection
222015018668207/02/15 Less-secure processors, integrated circuits, wireless communications apparatus, methods and processes of making
232015018748807/02/15 Integrated circuit with micro inductor and micro transformer with magnetic core
242015018757007/02/15 Process for forming pzt or plzt thinfilms with low defectivity
252015018758307/02/15 Dilution doped integrated circuit resistors
262015018758507/02/15 Dummy gate placement methodology to enhance integrated circuit performance
272015018759707/02/15 Method to improve slip resistance of silicon wafers
282015018759807/02/15 High precision capacitor dielectric
292015018763207/02/15 Metal thin film resistor and process
302015018763507/02/15 Method to reduce particles during sti fill and reduce cmp scratches
312015018765307/02/15 High-k / metal gate cmos transistors with tin gates
322015018765507/02/15 Method to improve transistor matching
332015018765607/02/15 Laser anneals for reduced diode leakage
342015018765807/02/15 Implant profiling with resist
352015018765907/02/15 High quality dielectric for hi-k last replacement gate transistors
362015018766107/02/15 Dual layer hardmask for embedded epi growth
372015018767707/02/15 Lid for integrated circuit package
382015018771107/02/15 Opening in a multilayer polymeric dielectric layer without delamination
392015018772907/02/15 Wire stitch bond having strengthened heel
402015018775207/02/15 Bi-directional esd protection device
412015018775507/02/15 Npn heterojunction bipolar transistor in cmos flow
422015018775807/02/15 Schottky diodes for replacement metal gate integrated circuits
432015018775907/02/15 High sheet resistor in cmos flow
442015018776007/02/15 Deep collector vertical bipolar transistor with enhanced gain
452015018776807/02/15 Poly gate extension design methodology to improve cmos performance in dual stress liner process flow
462015018777007/02/15 High mobility transistors
472015018777107/02/15 Hybrid high-k first and high-k last replacement gate process
482015018777207/02/15 Optimized layout for relaxed and strained liner in single stress liner technology
492015018777307/02/15 High mobility transistors
502015018790307/02/15 Fringe capacitance reduction for replacement gate cmos
512015018793407/02/15 High voltage multiple channel ldmos
522015018793707/02/15 Ldmos chc reliability
532015018793807/02/15 Low cost demos transistor with improved chc immunity
542015018795707/02/15 Transistor with improved radiation hardness
552015018841307/02/15 Multiple output integrated power factor correction
562015018843207/02/15 Switched mode assisted linear regulator with seamless transition between power tracking configurations
572015018851907/02/15 Dual edge-triggered retention flip-flop
582015018852207/02/15 Resonant impedance sensing with drive current pulse shaping to reduce noise folding
592015018853307/02/15 Bootstrapped sampling switch circuits and systems
602015018856107/02/15 Novel technique to combine a coarse adc and a sar adc
612015018862607/02/15 Optical fiber defect detection
622015018883807/02/15 Disabling network connectivity on student devices
632015017732306/25/15 Scan test method and apparatus
642015017732406/25/15 Scan topology discovery in target systems
652015017732506/25/15 Semiconductor test system and method
662015017732606/25/15 Waveform calibration using built in self test mechanism
672015017822106/25/15 Level one data cache line lock and enhanced snoop protocol during cache victims and writebacks to maintain level one data cache and level two cache coherence
682015017851306/25/15 Method and system of verifying proper execution of a secure mode entry sequence
692015017857306/25/15 Ground plane detection
702015017945206/25/15 High voltage depletion mode n-channel jfet
712015017959206/25/15 Self-aligned under bump metal
722015017965406/25/15 Epitaxial source/drain differential spacers
732015017978306/25/15 Metal-gate mos transistor and forming the transistor with reduced gate-to-source and gate-to-drain overlap capacitance
742015017979206/25/15 Scheme to align ldmos drain extension to moat
752015017979306/25/15 Lateral mosfet with buried drain extension layer
762015018033006/25/15 Apparatus and zero voltage switching in bridgeless totem pole power factor correction converter
772015018053906/25/15 Enabling co-existence among power line communication (plc) technologies
782015018059406/25/15 Self-calibrating shared-component dual synthesizer
792015018068006/25/15 Overlapping priority contention windows power line communications networks
802015018069206/25/15 Circuits and methods for transmitting signals
812015018162106/25/15 Multiple nfc card applications in multiple execution environments
822015018170606/25/15 High voltage polymer dielectric capacitor isolation device
832015016832806/18/15 Capacitive sensing for paper tray
842015016849206/18/15 Test access port with address and command capability
852015016849306/18/15 Testing interposer method and apparatus
862015016849406/18/15 Synchronizing a device that has been power cycled to an already operational system
872015016981406/18/15 Harmonic distortion macro model correction using a memory table
882015016981506/18/15 Harmonic distortion vs. output loading macro-modeling
892015017096206/18/15 Metal on elongated contacts
902015017097106/18/15 Methodology of forming cmos gates on the secondary axis using double-patterning technique
912015017097206/18/15 Method to form silicide and contact at embedded epitaxial facet
922015017097506/18/15 Elongated contacts using litho-freeze-litho-etch process
932015017098306/18/15 Probe pad design to reduce saw defects
942015017099806/18/15 Use of dielectric slots for reducing via resistance in dual damascene process
952015017099906/18/15 Multiple depth vias in an integrated circuit
962015017104606/18/15 Self-adhesive die
972015017107706/18/15 Poly resistor for metal gate integrated circuits
982015017109106/18/15 Self aligned active trench contact
992015017115806/18/15 Low temperature coefficient resistor in cmos flow
1002015017121106/18/15 Reduced area power devices using deep trench isolation
1012015017121206/18/15 High voltage lateral dmos transistor with optimized source-side blocking capability
1022015017121306/18/15 High voltage lateral extended drain mos transistor with improved drift layer contact
1032015017121706/18/15 Design and integration of finfet device
1042015017163406/18/15 Data extraction threshold circuit and method
1052015017192206/18/15 Channel selection in power line communications
1062015017193206/18/15 Circuit and architecture for a demodulator for a wireless power transfer system and method therefor
1072015017193506/18/15 Circuit and architecture for a demodulator for a wireless power transfer system and method therefor
1082015017207306/18/15 Transmission of segmented frames in power line communication
1092015017271806/18/15 Low complexity large transform
1102015016922306/18/15 Dynamic processor-memory revectoring architecture
1112015016028506/11/15 Apparatus and methods for qualifying hemt fet devices
1122015016029406/11/15 Parallel and serial access to test compression architectures
1132015016029506/11/15 Method and device access port selection
1142015016035006/11/15 Antenna selection for gnss receivers
1152015016045406/11/15 Multiple illumination sources for dmd lighting apparatus and methods
1162015016231706/11/15 Fabricating a proximity sensor having light-blocking structure in leadframe
1172015016283006/11/15 Power converter soft start circuit
1182015016313406/11/15 Routing protocols for power line communications (plc)
1192015016320706/11/15 Pairwise temporal key creation for secure networks
1202015015341106/04/15 Ieee 1149.1 interposer method and apparatus
1212015015341206/04/15 Dual mode test access port method and apparatus
1222015015402406/04/15 Vector simd vliw data path architecture
1232015015578306/04/15 Switched mode assisted linear regulator with dynamic buck turn-off using zcd-controlled tub switching
1242015015649006/04/15 Virtual boundary processing simplification for adaptive loop filtering (alf) in video coding
1252015014369005/28/15 Forming integrated inductors and transformers with embedded magnetic cores
1262015014438905/28/15 Method of minimizing mold flash during dambar cut
1272015014503605/28/15 Power integrated circuit including series-connected source substrate and drain substrate power mosfets
1282015014504005/28/15 Metal oxide semiconductor and making
1292015014505805/28/15 Transistor with deep nwell implanted through the gate
1302015014509705/28/15 Photodiode with a dark current suppression junction
1312015014512505/28/15 Passivation process to prevent tiw corrosion
1322015014543005/28/15 Combined digital modulation and current dimming control for light emitting diodes
1332015014549705/28/15 Low-loss step-up and step-down voltage converter
1342015014617405/28/15 Projector with optical conversion media pumped by low etendue source
1352015014633005/28/15 Esd robust mos device
1362015014667605/28/15 Downlink multiple input multiple output enhancements for single-cell with remote radio heads
1372015014682305/28/15 Wireless network receiver
1382015014703405/28/15 Optical connector
1392015014784505/28/15 Dual sided embedded die and fabrication of same background
1402015014788105/28/15 Passivation ash/oxidation of bare copper
1412015014933105/28/15 Taking device inventory using dynamically generated symbols
1422015014983305/28/15 Embedding stall and event trace profiling data in the timing stream - extended timing trace circuits, processes, and systems
1432015014984405/28/15 Double data rate test interface and architecture
1442015014984505/28/15 Device testing architecture, method, and system
1452015013761905/21/15 Method and circuitry for controlling a depletion-mode transistor
1462015013770005/21/15 Systems and methods of driving multiple outputs
1472015013771305/21/15 Adaptive linear resonance actuator controller
1482015013800405/21/15 Method for calibrating a pipelined continuous-time sigma delta modulator
1492015013831205/21/15 Method and a surround view camera system photometric alignment
1502015013844605/21/15 Compact optical projection apparatus
1512015013899505/21/15 Method, system and phase noise cancellation
1522015013956805/21/15 Method and a optimal seam for surround view synthesis
1532015014076905/21/15 Raised source/drain mos transistor and forming the transistor with an implant spacer and an epitaxial spacer
1542015014237905/21/15 Method and forcing the measurements of the angles of a triangle
1552015014299405/21/15 Robust cable-type detection for usb power delivery
1562015014318105/21/15 Dual endianess and other configuration safety in lock step dual-core system, and other circuits, processes and systems
1572015014319105/21/15 Shadow access port method and apparatus
1582015014351405/21/15 Methods, apparatus, and systems for securing sim (subscriber identity module) personalization and other data on a first processor and secure communication of the sim data to a second processor
1592015013043405/14/15 Fast current limiting circuit in multi loop ldos
1602015013044505/14/15 Remote sensing system
1612015013048505/14/15 Modulated test messaging from dedicated test circuitry to power terminal
1622015013049505/14/15 Assembly for testing semiconductor devices
1632015013049605/14/15 Method for testing semiconductor devices
1642015013051105/14/15 Scheme to improve the performance and reliability in high voltage io circuits designed using low voltage devices
1652015013052705/14/15 Low power scheme to protect the low voltage capacitors in high voltage io circuits
1662015013075505/14/15 Integrated receiver and adc for capacitive touch sensing apparatus and methods
1672015013318005/14/15 Selective power reduction to mitigate band interference
1682015013422405/14/15 Automotive cruise controls, circuits, systems and processes
1692015013471105/14/15 File access method and system thereof
1702015013502905/14/15 Tap and linking module for scan access of multiple cores with ieee 1149.1 test access ports
1712015013515205/14/15 Clock tree design
1722015012362705/07/15 Power converters and compensation circuits thereof
1732015012364805/07/15 Devices and methods for detecting usb devices attached to a usb charging port
1742015012371005/07/15 Cross-conduction detector for switching regulator
1752015012371105/07/15 Optimized peak detector for the agc loop in a digital radio receiver
1762015012466305/07/15 Method and configuraton, measurement and reporting of channel state information for lte tdd with dynamic ul/dl configuration
1772015012474205/07/15 Near-optimal qos-based resource allocation for hybrid-medium communication networks
1782015012769505/07/15 Processor trigonometric computation
1792015012799205/07/15 Using an in-system component as an embedded trace receiver
1802015012799305/07/15 Trace data export to remote memory using memory mapped write transactions
1812015012799405/07/15 Trace data export to remote memory using remotely generated reads
1822015012799705/07/15 Minimizing the amount of time stamp information reported with instrumentation data
1832015012800205/07/15 Jtag bus communication method and apparatus
1842015012810205/07/15 Circuit design synthesis tool with export to a computer-aided design format
1852015011542104/30/15 Method an stopping resin bleed and mold flash on integrated circit lead finishes
1862015011592904/30/15 Method and generating piece-wise linear regulated supply
1872015011599004/30/15 Die stack test architecture and method
1882015011669504/30/15 Light radar signal processing apparatus, systems and methods
1892015011741704/30/15 Enabling coordinated multi-point reception
1902015011757504/30/15 Method, system and carrier frequency offset correction and channel estimation
1912015011886104/30/15 Czochralski substrates having reduced oxygen donors
1922015012002604/30/15 Analog-to-digital converter
1932015012072604/30/15 Using audio cues to improve object retrieval in video
1942015012104304/30/15 Computer and methods for solving math functions
1952015012111904/30/15 Plural circuit selection using role reversing control inputs
1962015011602704/30/15 Unified bandgap voltage curvature correction circuit
1972015010803804/23/15 Tape and reel cover tape to improve die sticking issues
1982015010858804/23/15 Radiation hardened mos devices and methods of fabrication
1992015010862604/23/15 Multilevel leadframe
2002015010896904/23/15 On-chip linear variable differential transformer
2012015010907004/23/15 Dielectric waveguide signal divider
2022015011013004/23/15 Dynamic medium switching for hybrid networks
2032015011016304/23/15 Phy payload over multiple tone masks using single tone mask phy header information
2042015011131804/23/15 Heterogeneous integration of memory and split-architecture processor
2052015011134404/23/15 Method of fabricating a circuit
2062015011250204/23/15 Low drop-out voltage regulator modeling systems and methods
2072015011303004/23/15 Novel approach for significant improvement of fft performance in microcontrollers
2082015011333604/23/15 Method for generating descriptive trace gaps
2092015011334704/23/15 Commanded jtag test access port operations
2102015011364204/23/15 Method and system for preventing unauthorized processor mode switches
2112015010279404/16/15 Dc-dc converter using internal ripple with the dcm function
2122015010284104/16/15 Circuit for current sensing in high-voltage transistor
2132015010285804/16/15 Distributed pole-zero compensation for an amplifier
2142015010339104/16/15 Mems device with improved via support planarization
2152015010345104/16/15 Bi-directional esd protection circuit
2162015010356304/16/15 Automatic timing adjustment for synchronous rectifier circuit
2172015010356604/16/15 Systems and methods of ccm primary-side regulation
2182015010368704/16/15 Method and device for dynamic optimization of network parameters for optimal performance
2192015010369604/16/15 Reliable configuration for network access
2202015010386804/16/15 Small highly accurate battery temperature monitoring circuit
2212015010389204/16/15 Quantization matrix compression in video coding
2222015010390804/16/15 Method and a low complexity transform unit partitioning structure for hevc
2232015010391004/16/15 Intra block copy (intrabc) cost estimation
2242015010477704/16/15 Context-sensitive and location-aware adaptive learning to improve test effectiveness
2252015010563004/16/15 Heart pulse monitor including a fluxgate sensor
2262015010651904/16/15 Selective multiple-media access control
2272015009718604/09/15 Die testing using top surface test pads
2282015009722504/09/15 Trench gate trench field plate semi-vertical semi-lateral mosfet
2292015009723004/09/15 Trench gate trench field plate vertical mosfet
2302015009723104/09/15 Vertical trench mosfet device in integrated power technologies
2312015009750004/09/15 Stator resistance estimation for electric motors
2322015009753904/09/15 Systems and methods for real-time inductor current simulation for a switching converter
2332015009754504/09/15 Adaptive power adjustment for current output circuit
2342015009757704/09/15 Capacitance detection circuit that detects minute changes in capacitance
2352015009759304/09/15 Parallel scan distributors and collectors and process of testing integrated circuits
2362015009760004/09/15 Pwm controller with drive signal on current sensing pin
2372015009760804/09/15 System and controlling circuit input-output timing
2382015009772904/09/15 Method and gnss signal tracking
2392015009851504/09/15 Automatic gain control for power line communication
2402015009856904/09/15 Power line communication (plc) network nodes using cipher then segment security
2412015009932904/09/15 Packaged semiconductor device having multilevel leadframes configured as modules
2422015010060804/09/15 Reconfiguring an asic at runtime
2432015010081204/09/15 Serial bus voltage compensation
2442015010085604/09/15 Packet header protection for utility networks
2452015009230804/02/15 Scheme to reduce stress of input/ output (io) driver
2462015009138504/02/15 Power harvest architecture for near field communication devices
2472015009150204/02/15 Shared antenna solution for wireless charging and near field communication
2482015009153504/02/15 Directly amplified ripple tracking control scheme for multiphase dc-dc converter
2492015009153804/02/15 Method and system for converting a dc voltage



ARCHIVE: New 2015 2014 2013 2012 2011 2010 2009



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