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Texas Instruments Incorporated patents


      
Recent patent applications related to Texas Instruments Incorporated. Texas Instruments Incorporated is listed as an Agent/Assignee. Note: Texas Instruments Incorporated may have other listings under different names/spellings. We're not affiliated with Texas Instruments Incorporated, we're just tracking patents.

ARCHIVE: New 2015 2014 2013 2012 2011 2010 2009 | Company Directory "T" | Texas Instruments Incorporated-related inventors


Systems and methods of driving multiple outputs

Texas Instruments

Systems and methods of driving multiple outputs

Robust cable-type detection for usb power delivery

Texas Instruments

Robust cable-type detection for usb power delivery

Methods, apparatus, and systems for securing sim (subscriber identity module) personalization and other data on a first…

Texas Instruments

Methods, apparatus, and systems for securing sim (subscriber identity module) personalization and other data on a first…

Search recent Press Releases: Texas Instruments Incorporated-related press releases
Count Application # Date Texas Instruments Incorporated patents (updated weekly) - BOOKMARK this page
12015013761905/21/15 new patent  Method and circuitry for controlling a depletion-mode transistor
22015013770005/21/15 new patent  Systems and methods of driving multiple outputs
32015013771305/21/15 new patent  Adaptive linear resonance actuator controller
42015013800405/21/15 new patent  Method for calibrating a pipelined continuous-time sigma delta modulator
52015013831205/21/15 new patent  Method and a surround view camera system photometric alignment
62015013844605/21/15 new patent  Compact optical projection apparatus
72015013899505/21/15 new patent  Method, system and phase noise cancellation
82015013956805/21/15 new patent  Method and a optimal seam for surround view synthesis
92015014076905/21/15 new patent  Raised source/drain mos transistor and forming the transistor with an implant spacer and an epitaxial spacer
102015014237905/21/15 new patent  Method and forcing the measurements of the angles of a triangle
112015014299405/21/15 new patent  Robust cable-type detection for usb power delivery
122015014318105/21/15 new patent  Dual endianess and other configuration safety in lock step dual-core system, and other circuits, processes and systems
132015014319105/21/15 new patent  Shadow access port method and apparatus
142015014351405/21/15 new patent  Methods, apparatus, and systems for securing sim (subscriber identity module) personalization and other data on a first processor and secure communication of the sim data to a second processor
152015013043405/14/15Fast current limiting circuit in multi loop ldos
162015013044505/14/15Remote sensing system
172015013048505/14/15Modulated test messaging from dedicated test circuitry to power terminal
182015013049505/14/15Assembly for testing semiconductor devices
192015013049605/14/15Method for testing semiconductor devices
202015013051105/14/15Scheme to improve the performance and reliability in high voltage io circuits designed using low voltage devices
212015013052705/14/15Low power scheme to protect the low voltage capacitors in high voltage io circuits
222015013075505/14/15Integrated receiver and adc for capacitive touch sensing apparatus and methods
232015013318005/14/15Selective power reduction to mitigate band interference
242015013422405/14/15Automotive cruise controls, circuits, systems and processes
252015013471105/14/15File access method and system thereof
262015013502905/14/15Tap and linking module for scan access of multiple cores with ieee 1149.1 test access ports
272015013515205/14/15Clock tree design
282015012362705/07/15Power converters and compensation circuits thereof
292015012364805/07/15Devices and methods for detecting usb devices attached to a usb charging port
302015012371005/07/15Cross-conduction detector for switching regulator
312015012371105/07/15Optimized peak detector for the agc loop in a digital radio receiver
322015012466305/07/15Method and configuraton, measurement and reporting of channel state information for lte tdd with dynamic ul/dl configuration
332015012474205/07/15Near-optimal qos-based resource allocation for hybrid-medium communication networks
342015012769505/07/15Processor trigonometric computation
352015012799205/07/15Using an in-system component as an embedded trace receiver
362015012799305/07/15Trace data export to remote memory using memory mapped write transactions
372015012799405/07/15Trace data export to remote memory using remotely generated reads
382015012799705/07/15Minimizing the amount of time stamp information reported with instrumentation data
392015012800205/07/15Jtag bus communication method and apparatus
402015012810205/07/15Circuit design synthesis tool with export to a computer-aided design format
412015011542104/30/15Method an stopping resin bleed and mold flash on integrated circit lead finishes
422015011592904/30/15Method and generating piece-wise linear regulated supply
432015011599004/30/15Die stack test architecture and method
442015011669504/30/15Light radar signal processing apparatus, systems and methods
452015011741704/30/15Enabling coordinated multi-point reception
462015011757504/30/15Method, system and carrier frequency offset correction and channel estimation
472015011886104/30/15Czochralski substrates having reduced oxygen donors
482015012002604/30/15Analog-to-digital converter
492015012072604/30/15Using audio cues to improve object retrieval in video
502015012104304/30/15Computer and methods for solving math functions
512015012111904/30/15Plural circuit selection using role reversing control inputs
522015011602704/30/15Unified bandgap voltage curvature correction circuit
532015010803804/23/15Tape and reel cover tape to improve die sticking issues
542015010858804/23/15Radiation hardened mos devices and methods of fabrication
552015010862604/23/15Multilevel leadframe
562015010896904/23/15On-chip linear variable differential transformer
572015010907004/23/15Dielectric waveguide signal divider
582015011013004/23/15Dynamic medium switching for hybrid networks
592015011016304/23/15Phy payload over multiple tone masks using single tone mask phy header information
602015011131804/23/15Heterogeneous integration of memory and split-architecture processor
612015011134404/23/15Method of fabricating a circuit
622015011250204/23/15Low drop-out voltage regulator modeling systems and methods
632015011303004/23/15Novel approach for significant improvement of fft performance in microcontrollers
642015011333604/23/15Method for generating descriptive trace gaps
652015011334704/23/15Commanded jtag test access port operations
662015011364204/23/15Method and system for preventing unauthorized processor mode switches
672015010279404/16/15Dc-dc converter using internal ripple with the dcm function
682015010284104/16/15Circuit for current sensing in high-voltage transistor
692015010285804/16/15Distributed pole-zero compensation for an amplifier
702015010339104/16/15Mems device with improved via support planarization
712015010345104/16/15Bi-directional esd protection circuit
722015010356304/16/15Automatic timing adjustment for synchronous rectifier circuit
732015010356604/16/15Systems and methods of ccm primary-side regulation
742015010368704/16/15Method and device for dynamic optimization of network parameters for optimal performance
752015010369604/16/15Reliable configuration for network access
762015010386804/16/15Small highly accurate battery temperature monitoring circuit
772015010389204/16/15Quantization matrix compression in video coding
782015010390804/16/15Method and a low complexity transform unit partitioning structure for hevc
792015010391004/16/15Intra block copy (intrabc) cost estimation
802015010477704/16/15Context-sensitive and location-aware adaptive learning to improve test effectiveness
812015010563004/16/15Heart pulse monitor including a fluxgate sensor
822015010651904/16/15Selective multiple-media access control
832015009718604/09/15Die testing using top surface test pads
842015009722504/09/15Trench gate trench field plate semi-vertical semi-lateral mosfet
852015009723004/09/15Trench gate trench field plate vertical mosfet
862015009723104/09/15Vertical trench mosfet device in integrated power technologies
872015009750004/09/15Stator resistance estimation for electric motors
882015009753904/09/15Systems and methods for real-time inductor current simulation for a switching converter
892015009754504/09/15Adaptive power adjustment for current output circuit
902015009757704/09/15Capacitance detection circuit that detects minute changes in capacitance
912015009759304/09/15Parallel scan distributors and collectors and process of testing integrated circuits
922015009760004/09/15Pwm controller with drive signal on current sensing pin
932015009760804/09/15System and controlling circuit input-output timing
942015009772904/09/15Method and gnss signal tracking
952015009851504/09/15Automatic gain control for power line communication
962015009856904/09/15Power line communication (plc) network nodes using cipher then segment security
972015009932904/09/15Packaged semiconductor device having multilevel leadframes configured as modules
982015010060804/09/15Reconfiguring an asic at runtime
992015010081204/09/15Serial bus voltage compensation
1002015010085604/09/15Packet header protection for utility networks
1012015009230804/02/15Scheme to reduce stress of input/ output (io) driver
1022015009138504/02/15Power harvest architecture for near field communication devices
1032015009150204/02/15Shared antenna solution for wireless charging and near field communication
1042015009153504/02/15Directly amplified ripple tracking control scheme for multiphase dc-dc converter
1052015009153804/02/15Method and system for converting a dc voltage
1062015009161604/02/15Technique to realize high voltage io driver in a low voltage bicmos process
1072015009164204/02/15Method and circuitry for multi-stage amplification
1082015009164704/02/15Reducing a settling time after a slew condition in an amplifier
1092015009174204/02/15Apparatus and multilevel coding (mlc) with binary alphabet polar codes
1102015009245404/02/15Interleaved forward converter with wide input and output dynamic range
1112015009247504/02/15Pseudo retention till access mode enabled memory
1122015009273204/02/15Frame structure for medium access in body area networks (ban)
1132015009276504/02/15Implant access in the medical implant communications service band
1142015009286504/02/15Method and frame coding in vertical raster scan order for hevc
1152015009287904/02/15Apparatus and multilevel coding in communication systems
1162015009288604/02/15Apparatus and supporting polar code designs
1172015009459204/02/15Method and low complexity ultrasound based heart rate detection
1182015009570604/02/15Offline at start up of a powered on device
1192015009573004/02/15Blocking the effects of scan chain testing upon a change in scan chain topology
1202015009573104/02/15Reduced signaling interface method & apparatus
1212015008364103/26/15Selective heat seal wafer cover tape (has tape)
1222015008457503/26/15Angle/frequency selector in an electric motor controller architecture
1232015008457603/26/15Low speed and high speed controller architecture for electric motors
1242015008479703/26/15Low power excess loop delay compensation technique for delta-sigma modulators
1252015008515103/26/15Method and fusing images from an array of cameras
1262015008540903/26/15Active esd protection circuit with blocking diode
1272015008572503/26/15Power efficient wi-fi home automation
1282015008574803/26/15System and controlling peak to average power ratio
1292015008588103/26/15Data frame for plc having destination address in the phy header
1302015008588303/26/15Hybrid communication networks
1312015008590103/26/15Circuits, devices, and processes for improved positioning satellite reception and other spread spectrum reception
1322015008610703/26/15Use of three-dimensional top-down views for business analytics
1332015008612503/26/15Adaptive weighted-local-difference order statistics filters
1342015008712703/26/15Mosfet with source side only stress
1352015008713503/26/15Method of forming a trench isolation structure using a sion layer
1362015008841903/26/15Method, system and vehicular navigation using inertial sensors
1372015008929303/26/15Non-volatile logic based processing device
1382015008930103/26/15Recording processor instruction execution cycle and non-cycle count trace events
1392015008931303/26/15Hierarchical access of test access ports in embedded core integrated circuitsgb
1402015008931403/26/15Position independent testing of circuits
1412015008928903/26/15Programmable interface-based validation and debug
1422015007657703/19/15Three dimensional three semiconductor high-voltage capacitors
1432015007707003/19/15Feedforward cancellation of power supply noise in a voltage regulator
1442015007709403/19/15Inductive position sensing with single channel interface to multiple resonant sensors
1452015007758203/19/15Method and system for adapting a device for enhancement of images
1462015007800103/19/15Laser speckle reduction for uniform illumination
1472015007819803/19/15Simple mesh network for wireless transceivers
1482015007969803/19/15Thermal treatment for reducing transistor performance variation in ferroelectric memories
1492015007988603/19/15Permeated grooving in cmp polishing pads
1502015008200403/19/15Faster and more efficient different precision sum of absolute differences for dynamically configurable block searches for motion estimation
1512015008210503/19/15Error prediction in logic and memory devices
1522015008211003/19/153d stacked die test architecture
1532015008226403/19/15Minimizing the use of chip routing resources when using timestamped instrumentation data
1542015006801303/12/15Current, temperature or electromagnetic field actuated fasteners
1552015006951603/12/15Inner l-spacer for replacement gate flow
1562015006957203/12/15Multilayer high voltage isolation barrier in an integrated circuit
1572015006960003/12/15Embedded silver nanomaterials into die backside to enhance package performance and reliability
1582015006994203/12/15Tri-stating brushless dc motor phase for direct detection of back emf zero cross
1592015006999203/12/15Reference generator circuit with dynamically tracking threshold
1602015007004503/12/15Ultra fast transistor threshold voltage extraction
1612015007006103/12/15Dual-port negative level sensitive reset preset data retention latch
1622015007006303/12/15Low power clock gated flip-flops
1632015007008803/12/15Circuits and methods for cancelling nonlinear distortions in pulse width modulated sequences
1642015007011103/12/15System for transmitting information between circuits
1652015007074903/12/15Micromirror apparatus and methods
1662015007085003/12/15Three-dimensional power supply module with passive stacked over cavity
1672015007094903/12/15Device for transfering power from a first circuit to a second circuit
1682015007107703/12/15Flow control for powerline communications
1692015007130603/12/15Time and frequency diversity modulation system and method
1702015007136403/12/15Power line communication using padding to overcome interleaver failings
1712015007138003/12/15Method and circuitry for transmitting data
1722015007244303/12/15Method of etching ferroelectric capacitor stack
1732015007379503/12/15User programmable voice command recognition based on sparse features
1742015007430603/12/15Single wire communications interface and protocol
1752015007431803/12/15Methods and systems for multimedia data processing
1762015007447903/12/15Method and test connectivity, communication, and control
1772015006012303/05/15Locking dual leadframe for flip chip on leadframe packages
1782015006094903/05/15Fet dielectric reliability enhancement
1792015006103403/05/15Devices having inhomogeneous silicide schottky barrier contacts
1802015006108103/05/15Crack deflector structure for improving semiconductor device robustness against saw-induced damage
1812015006110303/05/15Embedded die package
1822015006152103/05/15Method and calculating an average value of an inaccessible current from an acessible current
1832015006152203/05/15Method and calculating an average value of an inaccessible current from an acessible current
1842015006161403/05/15Method and calculating an average value of an inaccessible current from an acessible current
1852015006163603/05/15Automatic calibration active and reactive power measurement
1862015006173903/05/15Dual-port negative level sensitive data retention latch
1872015006176703/05/15Telescopic amplifier with improved common mode settling
1882015006190703/05/15Technique for excess loop delay compensation in delta-sigma modulators
1892015006197603/05/15Multi-focus heads-up display using single picture generator unit
1902015006198803/05/15Adaptive power savings on a device display
1912015006230603/05/15System and methods for depth imaging using conventional ccd image sensors
1922015006235403/05/15Method and system for capturing images with a front-facing camera
1932015006254203/05/15Automatic keystone correction in a projection system
1942015006255803/05/15Time-of-flight (tof) assisted structured light imaging
1952015006328503/05/15Non-beacon network communications using frequency subbands
1962015006357503/05/15Acoustic sound signature detection based on sparse features
1972015006358303/05/15Method and system for active noise cancellation
1982015006649503/05/15Robust feature extraction using differential zero-crossing countes
1992015006649703/05/15Cloud based adaptive learning for distributed sensors
2002015006649803/05/15Analog to information sound signature detection
2012015006700803/05/15Determining median value of an array on vector simd architectures
2022015006711903/05/15Dynamic programming and control of networked sensors and microcontrollers
2032015006742603/05/15Packet based integrated circuit testing
2042015006742703/05/15Gating tap register control bus and auxiliary/wrapper test bus
2052015005358602/26/15Carrier tape
2062015005408402/26/15Silicide formation due to improved sige faceting
2072015005414502/26/15Integrated circuit package with die attach paddle having at least one recessed portion
2082015005452802/26/15Embedded sar based active gain capacitance measurement system and method
2092015005454402/26/15Dual-port positive level sensitive preset data retention latch
2102015005454502/26/15Dual-port positive level sensitive reset preset data retention latch
2112015005455602/26/15Dual-port negative level sensitive reset data retention latch
2122015005455702/26/15Dual-port negative level sensitive preset data retention latch
2132015005456002/26/15Dc offset correction with low frequency signal support circuits and methods
2142015005477202/26/15Low noise capacitive sensor with integrated bandpass filter
2152015005562402/26/15Mapping schemes for secondary synchronization signal scrambling
2162015005572402/26/15Transmission modes and signaling for uplink mimo support or single tb dual-layer transmission in lte uplink
2172015005693402/26/15Multi-mode crystal oscillators
2182015005868802/26/15System and sharing a communications link between multiple communications protocols
2192015005868902/26/15High speed double data rate jtag interface
2202015004886602/19/15Cascoded h-bridge pre-driver
2212015004887202/19/15Dual-port positive level sensitive reset data retention latch
2222015004980502/19/15Coding unit quantization parameters in video coding
2232015005146802/19/15Blood pulse measurement based on capacitive sensing
2242015005241202/19/15Selectable jtag or trace access with data store and output
2252015004067102/12/15Structural health monitoring system and method
2262015004119002/12/15High voltage polymer dielectric capacitor isolation device
2272015004190702/12/15Ic with floating buried layer ring for isolation of embedded islands
2282015004199402/12/15Semiconductor package having recessed solder terminals
2292015004224302/12/15Power-over-ethernet (poe) control system
2302015004230202/12/15Power management apparatus with rapid short response and full load recovery
2312015004230802/12/15Fast high-side power fet gate sense circuit for high voltage applications
2322015004239002/12/15Dual-port positive level sensitive data retention latch
2332015004339602/12/15Dynamic signaling of the downlink and uplink subframe allocation for a tdd wireless communication system
2342015004359602/12/15Frequency diversity modulation system and method
2352015004362802/12/15Serdes communications with retiming receiver supporting link training
2362015004369902/12/15Digital phase locked loop
2372015004483002/12/15Hard mask for source/drain epitaxy control
2382015004484802/12/15High voltage hybrid polymeric-ceramic dielectric capacitor
2392015004565002/12/15Blood flow measurement system based on inductive sensing
2402015004670302/12/15Target directed joining algorithm for multi-pan networks
2412015004670402/12/15Target directed joining algorithm for multi-pan networks
2422015003513002/05/15Integrated circuit with stress isolation
2432015003536502/05/15System and controlling power delivered to a powered device through a communication cable
2442015003547702/05/15Method and apparatus of fast battery charging with universal high power input source
2452015003551102/05/15Low power switching mode regulator having automatic pfm and pwm operation
2462015003671902/05/15Thermometer device and making
2472015003673802/05/15Method and real-time sao parameter estimation
2482015003699902/05/15Viewer attention controlled video playback
2492015003793802/05/15Packaging a semiconductor device having wires with polymerized insulator skin



ARCHIVE: New 2015 2014 2013 2012 2011 2010 2009



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