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Toshiba Memory Corporation patents


Recent patent applications related to Toshiba Memory Corporation. Toshiba Memory Corporation is listed as an Agent/Assignee. Note: Toshiba Memory Corporation may have other listings under different names/spellings. We're not affiliated with Toshiba Memory Corporation, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "T" | Toshiba Memory Corporation-related inventors


 new patent  Uniformization of parasitic capacitance around wiring of a circuit substrate

A circuit substrate includes an insulating body, a wiring enclosed by the insulating body, a conductive layer formed within the insulating body on a same plane as the wiring, and electrically insulated from the wiring by the insulating body, and one or more conductive vias extending through an edge portion of the conductive layer in a thickness direction intersecting the plane. A first width of the insulating body between the wiring and the conductive layer at a first position in the plane direction that does not correspond to any of said one or more conductive vias is smaller than a second width of the insulating body between the wiring and the conductive layer at a second position in the plane direction that corresponds to one of said one or more conductive vias.. ... Toshiba Memory Corporation

 new patent  Variable resistance element and memory device

According to one embodiment, a variable resistance element includes first and second conductive layers and a first layer. The first conductive layer includes at least one of silver, copper, zinc, titanium, vanadium, chrome, manganese, iron, cobalt, nickel, tellurium, or bismuth. ... Toshiba Memory Corporation

 new patent  Dry etching method and method for manufacturing semiconductor device

A dry etching method includes a process of, while continuously applying bias power using an ion species to a material to be processed including a first conductive member, a first insulating film provided on the first conductive member, a second conductive member provided on the first insulating film, and a second insulating film provided on the second conductive member, dry etching the second insulating film to expose the second conductive member. A time for which the bias power is continuously applied is set to 50 microseconds or less and a duty ratio of the bias power is set to 50% or less.. ... Toshiba Memory Corporation

 new patent  Memory device that executes an erase operation for a nonvolatile memory

According to one embodiment, a memory device includes a controller, and a nonvolatile memory in which an erase operation is controlled by the controller, the nonvolatile memory including blocks, the erase operation executing every block, the nonvolatile memory transferring a first reply showing a completion of the erase operation and a fail bit count showing a number of memory cells in which a data erase is uncompleted after the completion of the erase operation to the controller. The controller selects a target block as a target of the erase operation based on the fail bit count.. ... Toshiba Memory Corporation

 new patent  Semiconductor memory device and writing operation mathod thereof

A memory system includes a semiconductor memory device having memory cells arranged in rows and columns, and a controller configured to issue a write command with or without a partial page program command to the semiconductor memory device. The semiconductor memory device, in response to the write command issued without the partial page command, executes a first program operation on a page of memory cells and then a first verify operation on the memory cells of the page using a first verify voltage for all of the memory cells of the page, and in response to the write command issued with the partial page command, executes a second program operation on a subset of the memory cells of the page and then a second verify operation on the memory cells of the subset using one of several different second verify voltages corresponding to the subset.. ... Toshiba Memory Corporation

 new patent  Magnetic memory and memory system

According to one embodiment, a magnetic memory includes: a first magnetoresistive effect element having a first resistance state or a second resistance state; and a read circuit. A read circuit is configured to apply the first read voltage to the first magnetoresistive effect element, hold a first charging potential caused by the first read voltage, apply a second read voltage higher than the first read voltage to the first magnetoresistive effect element, hold a second charging potential caused by the second read voltage, and determine whether the first magnetoresistive effect element is in the first resistance state or the second resistance state based on a comparison result between the first charging potential and the second charging potential.. ... Toshiba Memory Corporation

 new patent  Storage system

A storage system includes non-volatile storage devices and a control device. Each of the storage devices is divided into blocks, and data is erased in units of the blocks. ... Toshiba Memory Corporation

 new patent  Reconstruct drive for dynamic resizing

A solid-state drive (ssd) is configured for dynamic resizing. When the ssd approaches the end of its useful life because the over-provisioning amount is nearing the minimum threshold as a result of an increasing number of bad blocks, the ssd is reformatted with a reduced logical capacity so that the over-provisioning amount may be maintained above the minimum threshold.. ... Toshiba Memory Corporation

Memory controller

According to one embodiment, a memory controller includes an encoder, a randomizing circuit, and an interface. The encoder subjects first data received from an external device to error correction coding. ... Toshiba Memory Corporation

Data transmission device

According to one embodiment, a buffer circuit sets a level of transmission data to high or low, a power supply line supplies a power supply voltage to the buffer circuit, a buffer control circuit controls a switching operation of the buffer circuit, a current circuit feeds a dummy current to the power supply line, and a current control circuit controls the dummy current based on the level set in the transmission data.. . ... Toshiba Memory Corporation

Magnetoresistive effect element and magnetic memory

According to one embodiment, a magnetoresistive effect element includes: a first magnetic layer; a nonmagnetic layer provided on the first magnetic layer; a second magnetic layer provided on the nonmagnetic layer; a first insulating layer provided at least on a side surface of the second magnetic layer; a second insulating layer covering at least a part of the first insulating layer; a conductive layer provided between the first insulating layer and the second insulating layer; and a first electrode including a first portion on the second magnetic layer and a second portion on a side surface of the second insulating layer. A height of a lower surface of the second portion is equal to or less than a height of an upper surface of the conductive layer.. ... Toshiba Memory Corporation

Semiconductor device having a memory cell array provided inside a stacked body

According to one embodiment, a semiconductor device includes a stacked body, a memory cell array, and a columnar portion. The stacked body is provided on a major surface of a substrate. ... Toshiba Memory Corporation

Semiconductor memory device

A semiconductor memory device includes a plurality of electrode layers stacked in a first direction; a semiconductor layer of a columnar shape extending through the electrode layers in the first direction; and a plurality of floating gates provided between the electrode layers and the semiconductor layer respectively. The floating gates surround the semiconductor layer. ... Toshiba Memory Corporation

Pattern formation method

According to one embodiment, a pattern formation method includes forming a structure body on a first surface of a patterning member, the structure body having protrusions and a recess. The protrusions are arranged at a first pitch along a first direction. ... Toshiba Memory Corporation

05/17/18 / #20180137926

Semiconductor storage device

According to one embodiment, a semiconductor storage device includes: a nand string with a first set of memory cells including a first memory cell; and a second set of memory cells including a second memory cell disposed above the first memory cell. The number of memory cells included in the first set is different from that of memory cells included in the second set. ... Toshiba Memory Corporation

05/17/18 / #20180137285

Information processing apparatus and computer program product

According to one embodiment, an information processing apparatus includes a first memory, a signal generation unit, an integrity check unit, and an access-right update unit. Firmware is stored in the first memory. ... Toshiba Memory Corporation

05/17/18 / #20180137020

Electronic circuit board

According to an embodiment, an electronic circuit board includes a nonvolatile memory, a reading circuit to read data stored in the nonvolatile memory, a switch, and a communication circuit. When power is supplied from a first power source, the switch performs switching to a first state in which the nonvolatile memory and a host device configured to read and write data from and in the nonvolatile memory are connected. ... Toshiba Memory Corporation

05/17/18 / #20180136849

Memory controller, information processing apparatus, and processor

According to one embodiment, a memory controller includes a nonvolatile cache memory and a controller. The nonvolatile cache memory is configured to store a piece of data stored in a nonvolatile main memory connected to the memory controller. ... Toshiba Memory Corporation

05/17/18 / #20180136272

Fault detection apparatus

A fault detection apparatus is provided, including a measurement unit that measures a first time period taken until a reflection signal reflected on a fault of a test apparatus is received after a first signal is transmitted to the test apparatus; a memory unit that includes a cad data unit having cad data of the test apparatus and a model data unit to store model data indicating a relation between the first time period and a predicted conduction distance of the first signal; a control unit that calculates a range of a test object selected in the test apparatus, calculates the predicted conduction distance from the first time period based on the model data, and specifies a position of the fault which is separated by the predicted conduction distance from the measurement unit in said range; and a display unit that displays the position of the fault.. . ... Toshiba Memory Corporation

05/10/18 / #20180130820

Semiconductor memory device

A semiconductor memory device includes a first electrode layer extending in a first direction, a second electrode layer above the first electrode layer and extending in the first direction, a third electrode layer above the first electrode layer and extending in the first direction, an insulating member between the second and third electrode layers and extending in the first direction, first semiconductor members extending in the second direction through the first and second electrodes, second semiconductor members extending in the second direction through the first and third electrode layers, and third semiconductor members extending in the second direction, each having a first portion between the second and third electrode layers and in contact with the insulating member, and a second portion extending through the first electrode layer. In the first direction, an arrangement density of the third semiconductor members is lower than that of the first or second semiconductor member.. ... Toshiba Memory Corporation

05/10/18 / #20180130810

Semiconductor memory device and method for manufacturing the same

A semiconductor memory device according to an embodiment includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. ... Toshiba Memory Corporation

05/10/18 / #20180130529

Semiconductor memory device

According to embodiments, a semiconductor memory device includes a first electrode, a second electrode, a memory cell, and a control circuit. The memory cell is provided between the first electrode and the second electrode and includes a metal film and a resistance change film. ... Toshiba Memory Corporation

05/10/18 / #20180129600

Memory system and control method

A memory system includes a nonvolatile memory having memory dies controlled in parallel and each including a plurality of physical blocks, and a controller. The controller manages a plurality of logical areas for storing data portions received from the host and parities calculated from the data portions, the logical areas including first and second logical areas for storing first and second parity groups, respectively. ... Toshiba Memory Corporation

05/10/18 / #20180129420

Memory system with selective access to first and second memories

A memory system includes a nonvolatile memory having a plurality of nonvolatile memory chips incorporated therein, a control circuit that controls the nonvolatile memory, an mpu that controls the control circuit, and an interface circuit that communicates with a host, all of which are mounted on a board of the memory system, and the memory system further includes a bus switch that switches connection of a signal line between the control circuit and the nonvolatile memory chips.. . ... Toshiba Memory Corporation

05/10/18 / #20180129415

Memory system and method

According to one embodiment, a memory system includes a nonvolatile first memory, a second memory which has a buffer, and a memory controller. The memory controller manages a plurality of pieces of translation information. ... Toshiba Memory Corporation

05/03/18 / #20180122488

Semiconductor memory device for storing multivalued data

Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of 5 first memory cells selected simultaneously by a word line. ... Toshiba Memory Corporation

05/03/18 / #20180121592

Non-transitory computer readable storage medium, mask evaluation method and inspection apparatus

A non-transitory computer readable storage medium according to an embodiment stores a mask evaluation program evaluating a mask used to manufacture an integrated circuit device. The program causes a computer to realize a convolutional neural network. ... Toshiba Memory Corporation

05/03/18 / #20180121354

Memory system

A memory system includes a non-volatile memory, a buffer memory, and a controller. The controller is configured to write data corresponding to a write command received from a host in the buffer memory, and based on an indication from the host, do not write the data stored in the buffer memory into the non-volatile memory unless a non-volatilization event occurs, the non-volatilization event being one of a flush request from the host and a detection of a power shutdown.. ... Toshiba Memory Corporation

05/03/18 / #20180121136

Memory system

A memory system capable of being connected to a host, includes a non-volatile memory that includes a plurality of non-volatile memory dies, and a controller that is electrically connected to the non-volatile memory. The controller is configured to manage the plurality of non-volatile memory dies as a plurality of die sets, each die set including two or more of the non-volatile memory dies to which priorities are assigned respectively, select one die set from the plurality of die sets based on an identifier received from the host, and select, based on the assigned priorities, a non-volatile memory die from the selected die set as a writing destination die of write data received from the host.. ... Toshiba Memory Corporation

05/03/18 / #20180119288

Template and method of manufacturing semiconductor device

According to one embodiment, a template forming method is provided. In the template forming method, a template pattern is formed on a first surface of a substrate. ... Toshiba Memory Corporation

05/03/18 / #20180117796

Imprint template manufacturing apparatus and imprint template manufacturing method

According to one embodiment, an imprint template manufacturing apparatus includes: a stage that support a template having a convex portion where a concavo-convex pattern is formed; a supply head that supplies a liquid-repellent material in liquid form to the template on the stage; a moving mechanism that moves the stage and the supply head relatively in a direction along the stage; and a controller that controls the supply head and the moving mechanism such that the supply head applies the liquid-repellent material to at least a side surface of the convex portion so as to avoid the concavo-convex pattern. The liquid-repellent material contains a liquid-repellent component and a non-liquid-repellent component that react with the surface of the template, a volatile solvent that dissolves the liquid-repellent component, and a fluorine-based volatile solvent that dissolves the non-liquid-repellent component.. ... Toshiba Memory Corporation

05/03/18 / #20180117795

Imprint template manufacturing apparatus and imprint template manufacturing method

According to one embodiment, an imprint template manufacturing apparatus includes: a supply head that supplies a liquid-repellent material in liquid form to a template having a convex portion where a concavo-convex pattern is formed on a stage; a moving mechanism that moves the stage and the supply head relatively in a direction along the stage; a controller that controls the supply head and the moving mechanism such that the supply head applies the liquid-repellent material to at least a side surface of the convex portion so as to avoid the concavo-convex pattern; and a cleaning unit that supplies a liquid to the template coated with the liquid-repellent material. The liquid-repellent material contains a liquid-repellent component and a non-liquid-repellent component that react with the surface of the template, and a volatile solvent that dissolves the liquid-repellent component. ... Toshiba Memory Corporation

04/19/18 / #20180108418

Semiconductor memory device

A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.. ... Toshiba Memory Corporation

04/19/18 / #20180107592

Reconstruction of address mapping in a host of a storage system

A storage device includes a nonvolatile memory including a plurality of physical blocks, a communication interface connectable to a host, and a controller. The controller is configured to generate metadata of host data, which include user data and metadata of the user data, and write, in a physical block of the nonvolatile memory, the metadata of the host data, the metadata of the user data, and the user data continuously in this order, when the host data are received through the communication interface in association with a write command.. ... Toshiba Memory Corporation

04/19/18 / #20180107536

Memory system

According to one embodiment, a memory system includes a non-volatile first memory, a second memory, a battery, a first processor, and a second processor. The first processor is configured to execute fault diagnosis on the battery by discharging energy stored in the battery. ... Toshiba Memory Corporation

04/19/18 / #20180107432

Storage device and control method

According to one embodiment, a storage device includes a processor which executes first processing, second processing and third processing. The second processing includes processing for relaying a command issued by a host device, and an execution result of the first processing corresponding to the command, between the host device and the first processing. ... Toshiba Memory Corporation

04/19/18 / #20180107413

Reading of start-up information from different memory regions of a memory system

A memory system includes a nonvolatile semiconductor memory including a first memory region for storing start-up information and a second memory region for storing a copy of the start-up information, a volatile semiconductor memory, and a controller. The controller is configured to determine whether or not an address of the second memory region is stored in the volatile semiconductor memory, issue a first start-up read command, which designates no read address, to the nonvolatile semiconductor memory to read the start-up information from the first memory region if the address of the second memory region is not stored in the volatile semiconductor memory, and issue a second start-up read command, which designates the address of the second memory region as a read address, to read the start-up information from the second memory region if the address of the second memory region is stored in the volatile semiconductor memory.. ... Toshiba Memory Corporation

04/19/18 / #20180107391

Storage system having a host that manages physical data locations of storage device

A storage device includes a nonvolatile memory, a communication interface connectable to a host, and a controller. The controller is configured to carry out writing of data that is received through the communication interface at a physical location of the nonvolatile memory when a write command associated with the data is received through the communication interface, control the communication interface to return a first notification upon determining that the writing of data at the physical location of the nonvolatile memory has completed, and control the communication interface to return a second notification a predetermined period of time after the first notification has been returned.. ... Toshiba Memory Corporation

04/19/18 / #20180107389

Memory system

According to one embodiment, a memory system includes a memory and a memory controller. The memory includes a first buffer and a memory cell array. ... Toshiba Memory Corporation

04/19/18 / #20180105936

Semiconductor manufacturing apparatus and manufacturing method of semiconductor device

According to some embodiments, a semiconductor manufacturing apparatus includes a first boat and a second boat, each of the first boat and the second boat having two support rings respectively provided at a top end and a bottom end thereof and a plurality of pillars provided between the top support ring and bottom support ring and spaced apart from one another. The pillar is provided with support protrusions on which a semiconductor substrate can be placed, and vertical positions of upper surfaces of the support protrusions of the second boat are lower than positions of upper surfaces of the support protrusions of the first boat. ... Toshiba Memory Corporation

04/05/18 / #20180097623

Authenticator, authenticatee and authentication method

According to one embodiment, an authenticator which authenticates an authenticatee, which stores first key information (nkey) that is hidden, includes a memory configured to store second key information (hkey) which is hidden, a random number generation module configured to generate random number information, and a data generation module configured to generate a session key (skey) by using the second key information (hkey) and the random number information. The authenticator is configured such that the second key information (hkey) is generated from the first key information (nkey) but the first key information (nkey) is not generated from the second key information (hkey).. ... Toshiba Memory Corporation

04/05/18 / #20180097011

Semiconductor memory device and method for manufacturing same

A semiconductor memory device according to one embodiment, includes a first electrode film, a plurality of semiconductor members, and a charge storage member. The first electrode film includes three or more first portions and a second portion connecting the first portions to each other. ... Toshiba Memory Corporation

04/05/18 / #20180096729

Semiconductor integrated circuit adapted to output pass/fail results of internal operations

In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.. . ... Toshiba Memory Corporation

04/05/18 / #20180096725

Semiconductor storage device and control method of semiconductor storage device with detecting levels of a multi-ary signal

According to one embodiment, there is provided a semiconductor storage device including n word lines, m bit lines, multiple memory cells, and a read circuit. N is an integer of four or greater. ... Toshiba Memory Corporation

04/05/18 / #20180096723

Semiconductor memory device which stores plural data in a cell

A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. ... Toshiba Memory Corporation

04/05/18 / #20180095663

Information processing device including host device and semiconductor memory device having a block rearrangement to secure free blocks

A device includes a host including a main memory, and semiconductor memory including a nonvolatile semiconductor memory, memory unit, and controller. The nonvolatile semiconductor memory stores first address information. ... Toshiba Memory Corporation

04/05/18 / #20180095523

Card and host apparatus

A host apparatus, into which a card having a nonvolatile semiconductor memory is inserted, issues a check command to the card. The check command instructs to send information on whether the card supports a termination process in which the card shifts into a state ready for a stop of power supply from the host apparatus.. ... Toshiba Memory Corporation

03/29/18 / #20180091170

Memory system including a memory device that can determine optimum read voltage applied to a word line

A memory system includes a nonvolatile memory including a word line and a plurality of memory cells connected to the word line, and a controller configured to transmit to the nonvolatile memory, a command that causes the nonvolatile memory to search for an optimum read voltage for the plurality of memory cells connected to the word line.. . ... Toshiba Memory Corporation

03/29/18 / #20180090511

Integrated circuit device and method for manufacturing same

An integrated circuit device includes an insulating film, a contact extending in a first direction and being provided inside the insulating film, and an insulating member. A composition of the insulating member is different from a composition of the insulating film. ... Toshiba Memory Corporation

03/29/18 / #20180090510

Semiconductor memory device and method for manufacturing the same

According to one embodiment, a semiconductor memory device includes first to third conductive layers extending along a first direction, and a memory portion. A portion of the second conductive layer is provided between the third conductive layer and a portion of the first conductive layer. ... Toshiba Memory Corporation

03/29/18 / #20180090507

Semiconductor device and method for manufacturing same

A semiconductor device includes a stacked body and an insulating portion. The stacked body includes first to fourth electrode layers. ... Toshiba Memory Corporation

03/29/18 / #20180090450

Semiconductor device and method for manufacturing same

According to one embodiment, the recess has a side surface and a bottom surface. The side surface is continuous with the major surface. ... Toshiba Memory Corporation

03/29/18 / #20180090438

Semiconductor device and manufacturing method thereof

According to some embodiments, a semiconductor device includes a substrate and an insulating film that is provided on the substrate. The device further includes a contact plug which includes a barrier metal layer provided in the insulating film, and a plug material layer provided in the insulating film, the barrier metal layer disposed between the plug material layer and the insulating film. ... Toshiba Memory Corporation

03/29/18 / #20180090369

Semiconductor device manufacturing method

A semiconductor device manufacturing method includes forming a first hole in a first processed layer. A first sacrificial film is formed in the first hole. ... Toshiba Memory Corporation

03/29/18 / #20180090220

Semiconductor memory device

A semiconductor memory device includes memory cells, a word line connected to gates of the memory cells, and a control circuit configured to execute a write operation on the memory cells. The write operation includes a first program operation during which a first program voltage is applied to the word line, a first verify operation during which a first verification voltage is applied to the word line to determine whether or not the first program operation passed, a second program operation during which a second program voltage is applied to the word line, and a second verify operation during which a second verification voltage is applied to the word line to determine whether or not the second program operation passed. ... Toshiba Memory Corporation

03/29/18 / #20180090218

Memory system that carries out temperature-based access to a memory chip

A memory system is connectable to a host and comprises a memory chip including a nonvolatile semiconductor memory cell array, a memory controller, a first temperature sensor positioned to measure a first temperature, which is representative of a temperature of the memory controller, and a second temperature sensor positioned to measure a second temperature, which is representative of a temperature of the memory chip. The memory controller is configured to compare the first temperature against a first threshold temperature and a second temperature against a second threshold temperature and carry out access to the memory chip when either the first temperature is greater than the first threshold temperature or the second temperature is greater than the second threshold temperature.. ... Toshiba Memory Corporation

03/29/18 / #20180090212

Semiconductor memory device and memory system

A semiconductor memory device includes first, second, and third memory cells, and first, second, and third word lines that are respectively connected to gates of the first, second, and third memory cells. A control circuit executes first, second, and third read operations in response to first, second, and third command sets, respectively. ... Toshiba Memory Corporation

03/29/18 / #20180090210

Semiconductor memory device and method for driving same

A semiconductor memory device includes first to fourth electrodes; first and second semiconductor members; a first charge storage member provided between the first semiconductor member and the first electrode; a first interconnect connected to the second electrode side of the first semiconductor member and to the fourth electrode side of the second semiconductor member; and a control circuit. The control circuit sets the first interconnect to a floating state, causes a potential of the third electrode side of the second semiconductor member to increase to a first potential, causes the potential of the third electrode to increase to a second potential lower than the first potential, causes the potential of the second electrode to increase to a third potential lower than the first potential, applies a fourth potential lower than the second and the third potentials to the first electrode, and sets the fourth electrode to a floating state.. ... Toshiba Memory Corporation

03/29/18 / #20180090182

Semiconductor device having a slit for aligning a connector and a hole for determining positional accuracy of the slit

A semiconductor device includes a substrate, a nonvolatile semiconductor memory disposed on a surface of the substrate, and a controller disposed on a surface of the controller. The substrate has a slit on an edge on which interface connection terminals are formed, a ground pattern, first and second wiring patterns that are electrically connected to the ground pattern and extend in a direction in which the slit extends, and a through hole that is formed between the first and second wiring patterns and is large enough along a dimension between the first and second wiring patterns to span substantially all of the spacing between the first and second wiring patterns.. ... Toshiba Memory Corporation

03/29/18 / #20180089078

Storage device that restores data lost during a subsequent data write

A storage device that can be connected to a host device includes a plurality of nonvolatile memories. Each nonvolatile memory includes first memory cells connected to a first word line and second memory cells connected to a second word line. ... Toshiba Memory Corporation

03/29/18 / #20180089021

Storage device that restores data lost during a subsequent data write

A storage device includes a plurality of nonvolatile memories each of which includes first memory cells connected to a first word line and second memory cells connected to a second word line that is adjacent to the first word line, and a controller. The controller is configured to maintain parity data for data written in the first memory cells of the nonvolatile memories, and when carrying out data writing in the second memory cells connected to the second word line in a targeted nonvolatile memory, which is one of the plurality of nonvolatile memories, upon detecting a failure in the data writing therein, carrying out restoration of data that were written in the first memory cells of the targeted nonvolatile memory using the parity data.. ... Toshiba Memory Corporation

03/29/18 / #20180088828

Memory system with garbage collection

According to one embodiment, a memory system includes a nonvolatile memory, and a controller configured to control the nonvolatile memory. The controller includes an access controller configured to control access to the nonvolatile memory, based on a first request which is issued from a host, and a processor configured to execute a background process for the nonvolatile memory, based on a second request which is issued from the host before the first request is issued.. ... Toshiba Memory Corporation

03/29/18 / #20180088811

Storage device that compresses data received from a host before writing therein

A storage device includes a nonvolatile storage and a controller. The controller is configured to compress data received from a host in association with a write command designating a first data length as a length of the data and a starting logical address of the data, into compressed data of a second data length shorter than the first data length, write the compressed data in the nonvolatile storage. ... Toshiba Memory Corporation

03/29/18 / #20180088805

Storage device that writes data from a host during garbage collection

A memory system includes a controller, a buffer, and a nonvolatile memory including a plurality of blocks, wherein each of the blocks includes a plurality of pages and each of the pages includes a plurality of unit data portions. The controller is configured to carry out garbage collection by reading data from one or more pages of a target block of the garbage collection and selectively copying valid unit data portions included in the read data to another block, count a number of invalid unit data portions included in the read data, and accept, in the buffer, unit data portions from a host as write data, up to a number determined based on the counted number, during the garbage collection.. ... Toshiba Memory Corporation

03/29/18 / #20180088100

Analysis device

An analysis device includes a vapor phase decomposition unit, a heating unit, an evacuation unit, a recovery unit and an analysis unit. The vapor phase decomposition unit performs vapor phase decomposition of a first film on a substrate. ... Toshiba Memory Corporation

03/29/18 / #20180085799

Exhaust system, semiconductor manufacturing equipment, and method for operating the exhaust system

According to one embodiment, an exhaust system includes a first pump unit, a second pump unit, a shaft, and a motor. The first pump unit includes a first exhaust chamber, a first intake port, a first exhaust port, and a first rotor. ... Toshiba Memory Corporation

03/22/18 / #20180083185

Magnetic memory device

According to one embodiment, a magnetic memory device includes a stacked structure including a first layer having a variable magnetization direction, a second layer having a fixed magnetization direction, a third layer between the first and second layers, adjacent to the first main surface of the first layer and the first main surface of the second layer, and functioning as a tunnel barrier, and a conductive fourth layer including a first main surface adjacent to the second main surface of the first layer, wherein a first resistance between the second main surface of the first layer and the second main surface of the second layer and a second resistance between the first main surface of the first layer and the second main surface of the fourth layer change based on the magnetization direction of the first layer.. . ... Toshiba Memory Corporation

03/22/18 / #20180083102

Semiconductor memory device

A semiconductor memory device includes a conductive layer; a plurality of electrode layers stacked on the conductive layer; a semiconductor pillar extending through the electrode layers in a stacking direction and electrically connected to the conductive layer; and an insulating layer positioned between the semiconductor pillar and the electrode layers and extending along the semiconductor pillar. The semiconductor pillar has a channel portion extending through the electrode layers and a high impurity concentration portion positioned at a bottom end on a side of the conductive layer. ... Toshiba Memory Corporation

03/22/18 / #20180083068

Memory device

A memory device includes a first interconnect extending in a first direction, a first and a second semiconductor members extending in a second direction, a first and a second gate lines extending in a third direction, a second and a third interconnects extending in the second direction. The first and the second semiconductor members are arranged along the first direction, with first ends in the second direction connected to the first interconnect. ... Toshiba Memory Corporation

03/22/18 / #20180083065

Magnetoresistive element and magnetic memory

A magnetoresistive element according to an embodiment includes: a first layer; a first magnetic layer; a second magnetic layer disposed between the first layer and the first magnetic layer; a nonmagnetic layer disposed between the first magnetic layer and the second magnetic layer; and an insulating layer disposed at least on side surfaces of the nonmagnetic layer, the first layer including: at least one element selected from a first group consisting of hf, zr, al, cr, and mg; and at least one element selected from a second group consisting of ta, w, mo, nb, si, ge, be, li, sn, sb, and p, and the insulating layer including at least one element selected from the first group.. . ... Toshiba Memory Corporation

03/22/18 / #20180083034

Semiconductor memory device and method of manufacturing the same

According to an embodiment, a semiconductor memory device comprises: a stacked body that includes a plurality of control gate electrodes stacked above a substrate; a memory columnar body that extends in a first direction above the substrate and configures a memory string along with the stacked body; and a source contact that extends in the first direction and is electrically connected to one end of the memory string. Moreover, this source contact is adjacent to the stacked body via a spacer insulating layer. ... Toshiba Memory Corporation

03/22/18 / #20180083033

Semiconductor memory device and method of manufacturing the same

A semiconductor memory device according to an embodiment comprises: a semiconductor substrate; a stacked body having a plurality of first insulating layers and conductive layers stacked alternately on the semiconductor substrate; a columnar semiconductor layer contacting the semiconductor substrate in the stacked body being provided extending in a stacking direction of the stacked body and including a first portion and a second portion which is provided above the first portion; a memory layer provided on a side surface of the columnar semiconductor layer facing the stacked conductive layers and extending along the columnar semiconductor layer; and a second insulating layer provided between one of the first insulating layer and the conductive layers of the stacked body. The columnar semiconductor layer has a boundary of the first portion and the second portion, the boundary being close to the second insulating layer; and an average value of an outer diameter of the memory layer facing a side surface of the second insulating layer is larger than that of the memory layer facing a side surface of a lowermost layer of the first insulating layers in the second portion.. ... Toshiba Memory Corporation

03/22/18 / #20180083032

Semiconductor memory device with first and second semicondutor films in first and second columnar bodies

A semiconductor memory device according to an embodiment comprises: conductive layers stacked in a vertical direction on a semiconductor substrate; and first and columnar bodies that extend in the vertical direction, the first and second columnar bodies each comprising: a first film; a second film disposed on the first film; and a semiconductor film, and the first film of the second columnar body having an upper end positioned higher than a first position lower than a first conductive layer and lower than a second position higher than the first conductive layer and a lower end positioned at or lower than the first position, and the second film of the second columnar body having an upper end positioned higher than the second position and a lower end positioned lower than the first position.. . ... Toshiba Memory Corporation

03/22/18 / #20180083031

Semiconductor memory device and method for manufacturing same

A semiconductor memory device includes a conductive layer; electrode layers stacked on the conductive layer; an insulating body extending through the electrode layers; and a semiconductor layer positioned between the insulating body and the electrode layers. The plurality of electrode layers include a first electrode layer, a second electrode layer provided between the conductive layer and the first electrode layer, and a third electrode layer provided between the conductive layer and the second electrode layer, and the semiconductor layer has a first layer thickness between the insulating body and the first electrode layer, a second layer thickness between the insulating body and the second electrode layer and a third layer thickness between the insulating body and the third electrode layer. ... Toshiba Memory Corporation

03/22/18 / #20180083029

Semiconductor memory device

A semiconductor memory device includes a memory plane including a plurality of electrode layers stacked on a substrate and a semiconductor layer extending through the plurality of electrode layers in a stacking direction thereof, a circuit provided on the substrate around the memory plane, a first insulating layer covering the circuit, and a second insulating layer including a first portion and a second portion between the substrate and the first insulating layer. The first portion is provided along an outer edge of the memory plane, and the second portion is spaced from the first portion and is provided on the circuit side. ... Toshiba Memory Corporation

03/22/18 / #20180083028

Semiconductor device and method for manufacturing semiconductor device

According to one embodiment, a semiconductor device includes a foundation layer, a stacked body provided on the foundation layer, the stacked body including a plurality of electrode layers stacked with an insulator interposed, a semiconductor body extending through the stacked body in a stacking direction of the stacked body, and a charge storage portion provided between the semiconductor body and the electrode layers. The semiconductor body includes a first semiconductor film, and a second semiconductor film provided between the first semiconductor film and the charge storage portion. ... Toshiba Memory Corporation

03/22/18 / #20180083027

Semiconductor memory device and method for manufacturing same

A semiconductor memory device includes a conductive layer; a first electrode layer provided above the conductive layer; a second electrode layer provided between the conductive layer and the first electrode layer; a first semiconductor channel body extending through the first electrode layer in a first direction from the conductive layer to the first electrode layer; a second semiconductor channel body provided between the conductive layer and the first semiconductor channel body, the second semiconductor channel body extending through the second electrode layer; and an insulating layer provided between the second semiconductor channel body and the second electrode layer. The second semiconductor channel body includes a first recessed portion in a lateral surface facing the second electrode layer, and the second electrode layer includes a second recessed portion in a surface facing the second semiconductor channel body.. ... Toshiba Memory Corporation

03/22/18 / #20180083026

Semiconductor device, manufacturing method and controlling method of semiconductor device

A semiconductor device includes a substrate, a semiconductor layer, first electrodes, data storage regions, first conductive regions, contacts and second conductive regions. The first electrodes are formed in the semiconductor layer arrayed in a first direction and a second direction and penetrating the insulator films and the semiconductor films in a third direction. ... Toshiba Memory Corporation

03/22/18 / #20180083025

Semiconductor memory device and method of manufacturing the same

A semiconductor memory device includes a gate insulating film on a semiconductor substrate, a memory cell array in a memory cell region, a first transistor in a peripheral circuit region which surrounds the memory cell region, a second transistor in a scribe region which surrounds the peripheral circuit region, a first stepped structure in the memory cell region, a second stepped structure in the peripheral circuit region facing the first stepped structure, and an interlayer insulating film between the first and second stepped structures. Each of the first and second stepped structures includes a plurality of insulating layers and conductive layers that are alternately stacked on the semiconductor substrate, and an upper surface of an uppermost layer of the first stepped structure, an upper surface of an uppermost layer of the second stepped structure, and an upper surface of the interlayer insulating film are formed on the same plane.. ... Toshiba Memory Corporation

03/22/18 / #20180083022

Stacked type semiconductor memory device and method for manufacturing the same

According to one embodiment, a semiconductor memory device includes a substrate, semiconductor pillars, first electrode films, a second electrode film, a first insulating film, a second insulating film, and a contact. The semiconductor pillars are provided on the substrate, extend in a first direction crossing an upper surface of the substrate, and are arranged along second and third directions being parallel to the upper surface and crossing each other. ... Toshiba Memory Corporation

03/22/18 / #20180083021

Semiconductor device and method for manufacturing same

A semiconductor device includes a stacked body 100, first insulating layers 45, a second insulating layer 46 and columnar portions cl. The stacked body 100 includes electrode layers 41 stacked with an insulating body interposed along a z-direction. ... Toshiba Memory Corporation

03/22/18 / #20180083020

Semiconductor memory device

A semiconductor memory device includes first wires extending in a first direction; second wires provided in a first interconnect layer including the first wires, the second wires extending in the first direction along extension lines of the first wires respectively; third wires provided in a second interconnect layer different from the first interconnect layer; and transistors on/off controlling electrical connections between the first wires and the second wires through the third wires. The first and second wires are arranged respectively in a second direction crossing the first direction. ... Toshiba Memory Corporation

03/22/18 / #20180083018

Semiconductor memory device and method of manufacturing the same

A semiconductor memory device includes a semiconductor substrate, a stepped structure including a stepped part in which a plurality of first insulating layers and conductive layers are alternately stacked on a main surface of the semiconductor substrate, the conductive layers including first, second, and third conductive layers, a second insulating layer which covers the stepped structure, a first contact interconnection which penetrates the second insulating layer and the first conductive layer in a thickness direction of the semiconductor substrate and is electrically connected to the second conductive layer, and a second contact interconnection which penetrates the second insulating layer and the second conductive layer in the thickness direction of the semiconductor substrate and is electrically connected to the third conductive layer.. . ... Toshiba Memory Corporation

03/22/18 / #20180082943

Manufacturing method of a semiconductor device and method for creating a layout thereof

A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity.. . ... Toshiba Memory Corporation

03/22/18 / #20180082893

Semiconductor device manufacturing method

According to some embodiments, a semiconductor device manufacturing method includes forming a sacrificial film on a material film. The method includes processing the sacrificial film, and forming a first groove in the sacrificial film having a first width and a second groove in the sacrificial film having a second width larger than the first width, the material film defining a base of the first groove and a base of the second groove. ... Toshiba Memory Corporation

03/22/18 / #20180082880

Substrate holding apparatus

A substrate holding apparatus includes a placing portion, a first depressurization unit, a second depressurization unit, a storage unit and a control unit. The placing portion includes a plurality of convex portions supporting a substrate, and includes a first region which faces a center portion of the substrate and second regions which face outer peripheral portions of the substrate. ... Toshiba Memory Corporation

03/22/18 / #20180082869

Substrate processing device and method of manufacturing semiconductor device

A substrate processing device capable of stabilizing an etching amount of a metal film provided on a substrate is provided. The substrate processing device includes a first container, a second container and a control unit. ... Toshiba Memory Corporation

03/22/18 / #20180082862

Substrate processing device and method of manufacturing semiconductor device

A substrate processing device includes a bath configured to accommodate a plurality of substrates and configured to store a liquid for etching the plurality of substrates, a plurality of bubble generators configured to generate bubbles in the liquid, the bubble generators provided so as to correspond to each of the plurality of substrates, a measurement device configured to measure the generation state of the bubbles of at least one of the plurality of bubble generators, and a control device configured to individually control at least one of the plurality of bubble generators based on the measurement result of the measurement device.. . ... Toshiba Memory Corporation

03/22/18 / #20180082843

Manufacturing method of a semiconductor device

In a manufacturing method of a semiconductor device according to an embodiment, an oxide film is formed on a semiconductor layer containing an impurity. A heat treatment is performed on the semiconductor layer to diffuse part of the impurity into the oxide film with hydrogen plasma treatment on the oxide film or with ultraviolet irradiation on the oxide film. ... Toshiba Memory Corporation

03/22/18 / #20180082832

Apparatus and method of treating surface of semiconductor substrate

In one embodiment, an apparatus of treating a surface of a semiconductor substrate comprises a substrate holding and rotating unit, first to fourth supplying units, and a removing unit. A substrate holding and rotating unit holds a semiconductor substrate, having a convex pattern formed on its surface, and rotates the semiconductor substrate. ... Toshiba Memory Corporation

03/22/18 / #20180082753

Memory device to executed read operation using read target voltage

A memory device includes a first string including first and second memory cells, first and second select transistors, and a third select transistor between the first and second select transistors, a second string including third and fourth memory cells, fourth and fifth select transistors, and a sixth select transistor between the fourth and fifth select transistors, and a controller. During a first read phase, a first voltage is applied to first, second, and third select transistors, and one of fourth and fifth select transistor, and a second voltage lower than the first voltage is applied to sixth select transistor and other of fourth and fifth select transistors. ... Toshiba Memory Corporation

03/22/18 / #20180082751

Semiconductor device

A semiconductor device includes first and second memory cells, a first word line, and a first and second bit lines, and a row control circuit. The first memory cell has a first gate electrode and a first channel having one end and another end. ... Toshiba Memory Corporation

03/22/18 / #20180082750

Non-volatile semiconductor memory device

According to one embodiment, a non-volatile semiconductor memory device is disclosed. The device includes a semiconductor substrate, and a memory cell array provided on the semiconductor substrate. ... Toshiba Memory Corporation

03/22/18 / #20180082743

Semiconductor memory device

A semiconductor memory device comprises a memory string that includes a plurality of memory cells electrically connected in series, the memory cells including first to fourth memory cells, first to fourth word lines that are electrically connected to gates of the first to fourth memory cells, respectively, a voltage generation circuit configured to generate a first voltage, a first circuit configured to output the first voltage to one of first and second wires, a second circuit configured to connect the first and second wires to the first and second word lines, respectively, and a third circuit configured to connect the first and second wires to the third and fourth word lines, respectively.. . ... Toshiba Memory Corporation

03/22/18 / #20180082742

Memory device and method for driving same

A memory device includes a first interconnect extending in a first direction, a second interconnect extending in a second direction crossing the first direction, a third interconnect extending in a third direction crossing a plane including the first direction and the second direction, a fourth interconnect extending in the third direction, a semiconductor member, a first resistance change film, and a second resistance change film. The semiconductor member is connected between a first end of the second interconnect and the first interconnect. ... Toshiba Memory Corporation

03/22/18 / #20180082733

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes a memory cell, a sense amplifier, a first transfer transistor, a second transfer transistor, and a controller. The memory cell can store a first value and a second value. ... Toshiba Memory Corporation

03/22/18 / #20180081820

Memory system and processor system

A memory system has a first memory to be accessed per first data size, a second memory to be accessed per second data size smaller than the first data size, the second memory being accessible at a higher speed than the first memory; and a third memory to store address conversion information that converts an address for accessing the second memory into an address for accessing the first memory, the first and third memories are non-volatile memories.. . ... Toshiba Memory Corporation

03/22/18 / #20180081801

Memory system and processing system

According to one embodiment, a memory system includes a first memory, a second memory, a third memory, and a controller. The controller executes a second access to the second memory in a first case, where the first case is a case in which a command for executing the first access to a first address is issued and data corresponding to the first address is stored in the second memory executes a third access to a second address in a second case, where the second case is a case in which the command is issued and the data corresponding to the first address is stored in the second address of the third memory, and executes a fourth access to a third address in a third case, where the third case is a case in which the command is issued, the command indicates a write operation to the first address.. ... Toshiba Memory Corporation

03/22/18 / #20180081799

Memory device and non-transitory computer readable recording medium

According to one embodiment, a memory device includes a nonvolatile memory, address translation unit, generation unit, and reception unit. The nonvolatile memory includes erase unit areas. ... Toshiba Memory Corporation

03/22/18 / #20180081593

Memory system and processor system

A memory system has a non-volatile memory, a storage accessible at higher speed than the non-volatile memory, to store access information to the non-volatile memory before accessing the non-volatile memory, and a memory controller to control a write pulse width to the non-volatile memory based on a free space of the storage or based on the access information stored in the storage.. . ... Toshiba Memory Corporation

03/22/18 / #20180081575

Memory system

A memory system includes: a semiconductor memory device; and a controller. When receiving the first read instruction, the semiconductor memory device issues a strobe signal at a first timing to read data from the first memory cell and the second memory cell. ... Toshiba Memory Corporation

03/22/18 / #20180081574

Memory system

According to one embodiment, a memory system includes a first memory including a message queue having first to nth addresses (n≧2, n is natural number), a first pointer showing one of the first to nth addresses, and a second pointer showing one of the first to nth addresses, a monitor unit which detects whether the first and second pointers show the first address, and a processing unit which changes an address shown by the first pointer from the first address to an ith address (n≧i≧2, i is natural number) when the first and second pointers show the first address. An address shown by the second pointer is incremented from the first address to a (j+1)th address (j≧1, j is natural number) when first to jth messages are queued in the first to jth addresses.. ... Toshiba Memory Corporation

03/22/18 / #20180081555

Memory control circuitry, memory system and processor system

A memory control circuitry has a write destination selector to select either a volatile memory or a non-volatile memory in a first storage as a write destination, for an address area in the first storage written by a processor, a write controller to write data in the write destination selected by the write destination selector, and an access information register to register information selecting the volatile memory or the non-volatile memory as the write destination, and number-of-times information indicating how many times a page of successive addresses for the address area is switched, as both information being associated with each other. When there is a write request from the processor, the write destination selector selects the write destination based on the information registered in the access information register.. ... Toshiba Memory Corporation

03/22/18 / #20180081542

Memory system

A memory system includes: a semiconductor memory device; and a controller capable of issuing a first read instruction and a second read instruction different from the first read instruction. When receiving the first read instruction, the semiconductor memory device reads first data and second data from a memory cell array, holds the first data and the second data in the latch circuit, and outputs the first data to the controller. ... Toshiba Memory Corporation

03/22/18 / #20180081414

Memory system and control method

A memory system includes a nonvolatile memory a controller that controls the nonvolatile memory, and a backup power supply. In response to a detection that power from an external source to the memory system is interrupted, at which time power to the memory system starts to be supplied from the backup power supply, the controller transmits a first command to the nonvolatile memory to change a parameter for a write operation and then transmits a second command to the nonvolatile memory to carry out a write operation, such that the nonvolatile memory carries out the write operation using the changed parameter.. ... Toshiba Memory Corporation

03/22/18 / #20180079547

Magnetic shield tray, magnetic shield wrapper and magnetic memory product shielded from external magnetic field

According to an embodiment, a magnetic shield tray includes a main body with a plate form including a magnetic material, and mount portions as holes disposed in the main body. The magnetic material is exposed on an inner surface of the holes.. ... Toshiba Memory Corporation

03/22/18 / #20180079096

Semiconductor memory device and method for manufacturing same

According to one embodiment, the stacked body includes a plurality of stacked units and a first intermediate layer. Each of the stacked units includes a plurality of electrode layers and a plurality of insulating layers. ... Toshiba Memory Corporation

03/15/18 / #20180077236

Storage system including a plurality of nodes

A storage system includes a plurality of nodes, each of the nodes including one or more node modules each of which includes a nonvolatile storage, and a connection unit directly connectable to at least one of the nodes. The connection unit is configured to transmit an access request or an inquiry directed to a target node module, determine a length of an interval before re-transmitting the access request or the inquiry, based on a response indicating an operation status of the target node module, which is returned by the target node module in response to the access request or the inquiry, and re-transmits the access request or the inquiry after the interval of the determined length has passed.. ... Toshiba Memory Corporation

03/15/18 / #20180076983

Semiconductor device and memory system

A semiconductor device includes a first chip and a second chip. The first chip includes a first circuit having a first output terminal. ... Toshiba Memory Corporation

03/15/18 / #20180076833

Information processing device and host device

According to one embodiment, in a case where a first command is received from a host, a storage device starts a first process. The storage device transmits a first response to the host in a case where a first condition is satisfied and transmits a second response and an interrupt signal to the host in a case where the first process is completed. ... Toshiba Memory Corporation

03/15/18 / #20180076832

Memory system that carries out soft bit decoding

A memory system includes a nonvolatile semiconductor memory and a controller. The controller is configured to maintain a plurality of log likelihood ratio (llr) tables for predicting a value of data read from the nonvolatile semiconductor memory, count a number of times that each of write operations, erase operations, and read operations have been carried out with respect to each unit storage region of the nonvolatile semiconductor memory, determine an order in which the llr tables are referred to, based on the counted number of the read operations and one of the counted number of the write operations and the counted number of the erase operations, which correspond to a target unit storage region of a read operation, and carry out decoding of data read from the target unit storage region of the read operation, using one of the llr tables selected according to the determined order.. ... Toshiba Memory Corporation

03/15/18 / #20180076829

Memory system and method

A memory system includes a memory that includes a plurality of memory cells, and a controller. During a write operation to write data to the memory cells, the controller encodes first data to be written at a first code rate. ... Toshiba Memory Corporation

03/15/18 / #20180076828

Storgae device that inverts bits of data written into a nonvolatile memory thereof

A storage device includes a nonvolatile memory and a controller. The controller is configured to generate coded data based on write data and an error correction code generated from the write data, determine whether or not to invert each bit of the coded data, based on a logical page position of the nonvolatile memory in which the write data are to be written and a value “0” or “1” of bits that are more populated in the coded data than bits having the other value of “1” and “0”, invert each bit of the coded data upon determining to invert, and write the non-inverted or inverted coded data into the logical page position of the nonvolatile memory. ... Toshiba Memory Corporation

03/15/18 / #20180076776

Semiconductor circuit

A semiconductor circuit includes a differential amplifier having a first positive terminal, a second positive terminal, a first negative terminal, a second negative terminal, and an output terminal. The output voltage is at a level that corresponds to a voltage level obtained by subtracting a voltage of the first negative terminal and the second negative terminal from a voltage sum of the first positive terminal and the second positive terminal. ... Toshiba Memory Corporation

03/15/18 / #20180076383

Magnetic memory device

According to one embodiment, a magnetic memory device includes a first magnetic layer having a variable magnetization direction, a second magnetic layer having a fixed magnetization direction, and a nonmagnetic layer between the first and second magnetic layers. The second magnetic layer includes a first main surface on the nonmagnetic layer side and a second main surface opposite to the first main surface, and includes a first region on the first main surface side and a second region on the second main surface side, and an intermediate region between the first and second regions and containing a predetermined nonmagnetic element. ... Toshiba Memory Corporation

03/15/18 / #20180076293

Semiconductor memory device and method for manufacturing the same

According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a semiconductor portion, and an insulating portion. The insulating portion is provided in the stacked body and extends in a stacking direction and a first direction along a surface of the substrate, the first direction crossing the stacking direction. ... Toshiba Memory Corporation

03/15/18 / #20180076266

Semiconductor device and semiconductor memory device

A semiconductor device according to the embodiment includes a plurality of semiconductor layers arranged along a first direction and a second direction, wherein each of the semiconductor layers includes a first semiconductor layer and second semiconductor layers positioned at both upper and lower sides of the first semiconductor layer, and a gate electrode which faces the first semiconductor layer. A row of the semiconductor layer in the first direction is oblique to a row of the semiconductor layer in the second direction. ... Toshiba Memory Corporation

03/15/18 / #20180076264

Semiconductor memory device

A semiconductor memory device according to an embodiment includes: a first wiring line extending in a first direction; a second wiring line extending in a second direction, the second direction intersecting the first direction; a variable resistance film disposed at an intersection of the first wiring line and the second wiring line; a channel body disposed at a first end of the first wiring line; a third wiring line electrically connected to the first wiring line via the channel body; and a gate wiring line extending in the first direction and facing the channel body from the second direction.. . ... Toshiba Memory Corporation

03/15/18 / #20180076263

Magnetic memory device

According to one embodiment, a magnetic memory device includes a first insulating film provided on a semiconductor region, and having a portion located in a memory cell array area and thicker than a portion located in a peripheral circuit area, a plurality of conductive plugs located in the memory cell array area and provided in the first insulating film, stacked structures located in the memory cell array area, provided on the conductive plugs, and each having layers including a magnetic layer, and transistors located in the peripheral circuit area, and each including a gate electrode provided on the semiconductor region and covered with the first insulating film, wherein a thickness t0 from a main surface of the semiconductor region to a lower surface of each stacked structure is greater than a predetermined value.. . ... Toshiba Memory Corporation

03/15/18 / #20180076262

Semiconductor device having rare earth oxide layer and method of manufacturing the same

According to one embodiment, a semiconductor device includes a first rare earth oxide layer, a first magnetic layer being adjacent to the first rare earth oxide layer, and a nonmagnetic layer, the first magnetic layer being disposed between the first rare earth oxide layer and the nonmagnetic layer and being oriented in a crystal surface which is the same as a crystal surface of the nonmagnetic layer.. . ... Toshiba Memory Corporation

03/15/18 / #20180076261

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes a magnetoresistive element and an insulating layer. The magnetoresistive element includes a first magnetic layer, a nonmagnetic layer, and a second magnetic layer and. ... Toshiba Memory Corporation

03/15/18 / #20180076216

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a columnar member, and an insulating film. The stacked body is provided on the substrate, and includes a plurality of electrode layers separately stacked each other. ... Toshiba Memory Corporation

03/15/18 / #20180076215

Semiconductor memory device and method for manufacturing the same

According to one embodiment, a semiconductor memory device includes a substrate, interconnect portions, a conductive layer, a stacked body, and columnar portions. At least one portion of the interconnect portions is provided inside the substrate, each of the interconnect portions extends in a first direction along a surface of the substrate, and the interconnect portions are arranged along a second direction crossing the first direction. ... Toshiba Memory Corporation

03/15/18 / #20180076213

Semiconductor device and method for manufacturing the same

A method for manufacturing a semiconductor device includes forming a first semiconductor layer, forming a stacked body including alternately formed first and second layers on the first semiconductor layer, forming a hole from an upper surface of the stacked body to the first semiconductor layer to expose the first semiconductor layer therein. A first insulating layer is formed on the inner wall of the hole, and a second semiconductor layer is formed on the first insulating layer within the hole, wherein the second semiconductor layer is electrically connected to the first semiconductor layer. ... Toshiba Memory Corporation

03/15/18 / #20180076211

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes a first conductive layer, a first semiconductor body, a second semiconductor body, a first memory layer, and a second memory layer. The first conductive layer includes first to fourth extension regions, and a first connection region. ... Toshiba Memory Corporation

03/15/18 / #20180076210

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes a base semiconductor layer, first and second conductive layers, a semiconductor body, a memory layer, first and second semiconductor regions, and an insulating portion. The first conductive layer is separated from the base semiconductor layer in a first direction. ... Toshiba Memory Corporation

03/15/18 / #20180076208

Semiconductor device

The semiconductor device according to the embodiments comprises: a plurality of first conductive layers arranged in a first direction above a substrate, the first direction intersecting an upper surface of the substrate; a semiconductor layer that faces a side surface of the plurality of first conductive layers and extends in the first direction as a longitudinal direction thereof; a wiring portion configured by causing end portions of the first conductive layers to be at different positions, respectively; and a transistor located above the wiring portion. The transistor comprises: a channel portion arranged at a same height as a second conductive layer, the second conductive layer being one of the plurality of the first conductive layers; a gate insulating film arranged on an upper surface of the channel portion; and a gate electrode layer arranged on an upper surface of the gate insulating film.. ... Toshiba Memory Corporation

03/15/18 / #20180076187

Semiconductor device manufacturing method

A semiconductor device manufacturing method includes stacking a second semiconductor chip on a first surface of a first semiconductor chip such that the at bump electrode overlies the position of a first through silicon via in the first semiconductor chip, stacking a third semiconductor chip on the second semiconductor chip such that a second bump electrode on the second semiconductor chip overlies the position of a second through silicon via in the third semiconductor chip to form a chip stacked body, connecting the first and second bump electrodes of the chip stacked body to the first and the second through silicon vias by reflowing the bump material, placing the chip stacked body on the first substrate such that the first surface of the first semiconductor chip faces the second surface, and sealing the second surface and the first, second, and third semiconductor chips with a filling resin.. . ... Toshiba Memory Corporation

03/15/18 / #20180076186

Semiconductor memory system

According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. ... Toshiba Memory Corporation

03/15/18 / #20180076180

Semiconductor device having stacked chips

A semiconductor device includes a first chip having a first via and a second via through the first chip; and a second chip provided on the first chip and having a third via and a fourth via through the second chip. The first chip includes: a first logical operation circuit configured to perform a first logical operation (not) on a first address input signal to output a first address output signal to the second chip through the first via; a second logical operation circuit connected to the first logical operation circuit, the second logical operation circuit being configured to perform a second logical operation (xor) on a second address input signal and the first address output signal to output a second address output signal to the second chip through the second via; and a first activation circuit connected to the second logical operation circuit, the first activation circuit being configured to activate the first chip based on at least the second address output signal.. ... Toshiba Memory Corporation

03/15/18 / #20180076146

Semiconductor device and method of manufacturing the same

In one embodiment, a semiconductor device includes a substrate, and a first shield member provided on or in the substrate. The device further includes a semiconductor chip provided on the first shield member, and a first wire electrically connected to the semiconductor chip and the substrate. ... Toshiba Memory Corporation

03/15/18 / #20180076130

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a plurality of columnar portions, and an interconnect portion. The interconnect portion is provided in the stacked body and extends in a stacking direction of a plurality of electrode layers and a first direction crossing the stacking direction. ... Toshiba Memory Corporation

03/15/18 / #20180076085

Semiconductor device and method for manufacturing same

According to one embodiment, a semiconductor device includes a foundation layer, a stacked body, and an insulating layer. The stacked body provides on the foundation layer, the stacked body includes a plurality of electrode layers stacked with an insulator interposed. ... Toshiba Memory Corporation

03/15/18 / #20180076019

Pattern forming method, self-organization material, and method of manufacturing semiconductor apparatus

According to one embodiment, a pattern forming method includes supplying, onto an under layer, a self-organization material including a block copolymer which includes a first polymer and a second polymer, and a third polymer having a molecular structure with oxygen attached to a cyclic structure, wherein the third polymer is bonded to the first polymer, and phase-separating the block copolymer to form a phase-separation pattern on the under layer.. . ... Toshiba Memory Corporation

03/15/18 / #20180075917

Semiconductor memory device and memory system

A semiconductor memory device includes memory cells, a sense amplifier unit including a first latch circuit, and a control unit configured to execute read and write operations on the memory cells. The control unit, while executing the write operation on the memory cells, responsive to a write suspend command followed by a read command, performs a data saving operation, the read operation, and a data restoring operation prior to resuming the write operation. ... Toshiba Memory Corporation

03/15/18 / #20180075912

Semiconductor memory device

A semiconductor memory device includes first and second memory cell arrays, and first and second control circuits configured to execute an operation on the first and second memory cell arrays. The first control circuit executes an operation on the first memory cell array responsive to a first command set that is received by the semiconductor memory device. ... Toshiba Memory Corporation

03/15/18 / #20180075908

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes a stacked body including a first stacked region, and a first structure body. The first stacked region includes first and second selection gate electrodes, first electrodes arranged in a first direction and provided between the first and second selection gate electrodes, second electrodes arranged in the first direction and provided between the second selection gate electrode and the first electrodes, and third electrodes arranged in the first direction and provided between the first electrodes and the second electrodes. ... Toshiba Memory Corporation

03/15/18 / #20180075903

Semiconductor memory device including variable resistance element

According to one embodiment, a variable resistance memory includes first to third insulating layers, first and second variable resistance layers, first and second semiconductor layers, and first and second electric conductors. The first insulating layer extends in a first direction. ... Toshiba Memory Corporation

03/15/18 / #20180075902

Semiconductor storage device and memory system

According to one embodiment, a semiconductor storage device includes a first memory cell capable of storing n-bit data (n is a natural number not less than 4). When receiving first data, including first and second bits of the n-bit data, from a controller, the semiconductor storage device writes the received first data to the first memory cell. ... Toshiba Memory Corporation

03/15/18 / #20180075897

Memory device

A memory device includes: a memory cell array including memory cells; a correction circuit which encodes write data and generates an error correction signal, in a first period; a write circuit which writes the write data to a memory cell in a second period following the first period; a first circuit which receives a first signal generated based on a write command, generates a first clock signal having a first cycle from the first signal, and sets the first period with the first clock signal; and a second circuit which receives the first clock signal, generates a second clock signal having a second cycle from the first clock signal, and sets the second period with the second clock signal.. . ... Toshiba Memory Corporation

03/15/18 / #20180075895

Memory device

According to one embodiment, a memory device includes: a magnetoresistive element including first and second magnetic layers and a non-magnetic layer provided between the first and second magnetic layers; and a write circuit which controls a first writing setting magnetization of the first and second magnetic layers in a parallel state and a second writing setting the magnetization of the first and second magnetic layers in an antiparallel state, and applies a current pulse to the magnetoresistive element. A first pulse pattern used in the first writing is different from a second pulse pattern used in the second writing.. ... Toshiba Memory Corporation

03/15/18 / #20180075894

Semiconductor memory device

According to one embodiment, a semiconductor memory device comprises a memory cell including a variable resistance element; and a first circuit configured to control writing to the memory cell. The first circuit is configured to generate a first pulse of a second signal based on a first signal from outside, generate a second pulse of a third signal obtained by delaying the first pulse, and generate a third pulse of a fourth signal obtained by delaying the second pulse. ... Toshiba Memory Corporation

03/15/18 / #20180075893

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes a first memory cell capable of storing one of first and second data, first and second lines coupled to the first memory cell, a first controller capable of simultaneously outputting first and second signals, and a first driver configured to apply a first voltage to the first line and apply a second voltage to the second line according to the first data and an asserted first signal in the first data writing, and apply a third voltage to the first line and apply a fourth voltage to the second line according to the second data and an asserted second signal in the second data writing.. . ... Toshiba Memory Corporation

03/15/18 / #20180075892

Semiconductor memory device

According to one embodiment, a semiconductor memory device comprises: first to fourth memory cells, each of which is configured to have a first resistance state or a second resistance state; and a first circuit configured to output first data based on a first signal representing a resistance state of the first memory cell and a second signal representing a resistance state of the second memory cell, output second data based on the second signal and a third signal representing a resistance state of the third memory cell, and output third data based on the third signal and a fourth signal representing a resistance state of the fourth memory cell.. . ... Toshiba Memory Corporation

03/15/18 / #20180075890

Magnetic storage device

According to an embodiment, a magnetic storage device includes a memory cell including a magnetoresistive effect element including a storage layer and a reference layer; first and second line electrically coupled to the magnetoresistive effect element; and a write driver. The write driver supplies a first voltage to the first line in a first write operation in which a first resistance value of the magnetoresistive effect element is changed to a second resistance value smaller than the first resistance value, and supplies a second voltage different from the first voltage to the second line in a second write operation in which the second resistance value of the magnetoresistive effect element is changed to the first resistance value.. ... Toshiba Memory Corporation

03/15/18 / #20180075334

Receiving system and memory card

According to one embodiment, a receiving system includes a first receiving circuit and a second receiving circuit each receiving a differential signal with a positive phase signal and a negative phase signal, and a controller controlling the first and second receiving circuits. The first receiving circuit comprises a first differential amplifier outputting a first signal in a first time frame in which a polarity of the differential signal does not change dependent on a passage of time. ... Toshiba Memory Corporation

03/15/18 / #20180074971

Ddr storage adapter

A method of accessing a persistent memory over a memory interface is disclosed. In one embodiment, the method includes allocating a virtual address range comprising virtual memory pages to be associated with physical pages of a memory buffer and marking each page table entry associated with the virtual address range as not having a corresponding one of the physical pages of the memory buffer. ... Toshiba Memory Corporation

03/15/18 / #20180074896

Memory system

According to one embodiment, a system includes a memory device including a memory cell, the memory cell storing a piece of data among first to third data, each the first to third data including first and second bits, the first data having the first and second bits of a first value, the second data having the first bit of a second value and the second bit of the first value, and the third data having the first bit of the first value and the second bit of the second value. When the threshold voltage of the memory cell into which the first data is programmed is higher than a level between a first voltage corresponding to the first data and the second voltage corresponding to the second data, the device programs the third data to the memory cell.. ... Toshiba Memory Corporation

03/15/18 / #20180074894

Memory system

According to one embodiment, a memory system includes a decoder configured to correct an error of the data stored in a memory based on result of the first read and the second read, and output a first signal of a first value indicating corrected data and a second signal of a second value indicating corrected data; a generator configured to count the first and second signals for first data items based on the result of the first and second read for generating count numbers of the first and second signals for each of the first data items; and a controller configured to compare a magnitude relation of the count numbers in order of read levels, determine the first data item when the magnitude relation changes.. . ... Toshiba Memory Corporation

03/15/18 / #20180074791

Randomization of data using a plurality of types of pseudorandom number generators

A randomizer includes a first pseudorandom number generator, a second pseudorandom number generator, and a first logic circuit configured to output a pseudorandom sequence by carrying out an operation on a pseudorandom sequence generated by the first pseudorandom number generator and a pseudorandom sequence generated by the second pseudorandom number generator, and a second logic circuit configured to randomize a data string input to the randomizer based on the pseudorandom sequence output by the first logic circuit.. . ... Toshiba Memory Corporation








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