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United Microelectronics Corp patents


Recent patent applications related to United Microelectronics Corp. United Microelectronics Corp is listed as an Agent/Assignee. Note: United Microelectronics Corp may have other listings under different names/spellings. We're not affiliated with United Microelectronics Corp, we're just tracking patents.

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Device with reinforced metal gate spacer and fabricating

A semiconductor device with reinforced gate spacers and a method of fabricating the same. The semiconductor device includes low-k dielectric gate spacers adjacent to a gate structure. A high-k dielectric material is disposed over an upper surface of the low-k dielectric gate spacers to prevent unnecessary contact between the gate... United Microelectronics Corp

Field-effect transistor and making the same

A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. A vertically extending portion of the epitaxial structure extends vertically above a top surface of the semiconductor substrate in an area adjacent the gate structure.... United Microelectronics Corp

Method for fabricating a fin field effect transistor (finfet)

The invention provides a method for fabricating a fin field effect transistor (FinFET), comprising: providing a substrate having a logic region and a large region; forming a plurality of fin structures in the logic region by removing a portion of the substrate in the logic region; forming an oxide layer... United Microelectronics Corp

Method of epitaxial structure formation in a semiconductor

The invention provides a method of epitaxial structure formation in a semiconductor, comprising: providing a substrate; performing a dry etch to form a first recess; after performing the dry etch, performing a SPM cleaning process on the substrate by using a nozzle spraying SPM solution with an angle greater than... United Microelectronics Corp

Method for manufacturing a high-voltage finfet device having ldmos structure

A high-voltage FinFET device having LDMOS structure and a method for manufacturing the same are provided. The method includes: providing a substrate with a fin structure to define a first and a second type well regions; forming a trench in the first-type well region to separate the fin structure into... United Microelectronics Corp

Device with reinforced metal gate spacer and fabricating

A semiconductor device with reinforced gate spacers and a method of fabricating the same. The semiconductor device includes low-k dielectric gate spacers adjacent to a gate structure. A high-k dielectric material is disposed over an upper surface of the low-k dielectric gate spacers to prevent unnecessary contact between the gate... United Microelectronics Corp

Fin-shaped field effect transistor

The present invention provides a fin-shaped field effect transistor (FinFET), comprises: a substrate having a fin structure; a plurality trenches formed on the fin structure with an alloy grown in the trenches; a gate structure on the fin structure perpendicular to an extending direction of the fin structure in-between the... United Microelectronics Corp

Semiconductor device and forming the same

A method of forming a semiconductor device is provided including the following steps. A substrate having a first voltage area and a second voltage area is provided. A first oxide layer is formed in the first voltage area. The first oxide layer is removed to form a recess in the... United Microelectronics Corp

Semiconductor device with single-crystal nanowire finfet

A semiconductor device and a method of forming the same, the semiconductor device includes a single crystal substrate, a source/drain structure and a nanowire structure. The source/drain structure is disposed on and contacts with the substrate. The nanowire structure is connected to the source/drain structure.... United Microelectronics Corp

Vertical channel oxide semiconductor field effect transistor and fabricating the same

A semiconductor device includes: a channel layer surrounded by a source layer; a first dielectric layer around the source layer; a gate layer around the channel layer and on the source layer; a first oxide semiconductor layer between the gate layer and the channel layer; a second oxide semiconductor layer... United Microelectronics Corp

Finfet structure and fabricating gate structure

A method of forming a gate structure on a fin structure includes the steps of providing a fin structure covered by a first silicon oxide layer, a silicon nitride layer, a gate material and a cap material in sequence, wherein the silicon nitride layer contacts the first silicon oxide layer.... United Microelectronics Corp

Method for fabricating finfet

The present invention provides a method of fabricating a FinFET, comprising the following steps: first, a substrate having a plurality of fin structures disposed thereon is provided, an STI disposed between adjacent fin structures and a gate structure crossing the fin structures. Next, the fin structures not covered by the... United Microelectronics Corp

High-voltage metal-oxide-semiconductor transistor and fabrication method thereof

A high-voltage MOS transistor includes a semiconductor substrate, a gate oxide layer on the semiconductor substrate, a gate on the gate oxide layer, a spacer covering a sidewall of the gate, a source on one side of the gate, and a drain on the other side of the gate. The... United Microelectronics Corp

Semiconductor device

The present invention provides a semiconductor device, including a substrate, two gate structures disposed on a channel region of the substrate, an epitaxial layer disposed in the substrate between two gate structures, a first dislocation disposed in the epitaxial layer, wherein the profile of the first dislocation has at least... United Microelectronics Corp

Method for manufacturing a semiconductor structure

A method for manufacturing a semiconductor structure comprises the following steps. First, a recess is formed in a substrate. At least one wet cleaning process is performed to the recess and the substrate. Then, a baking process is performed to the recess and the substrate in an atmosphere containing H2... United Microelectronics Corp

Electric fuse structure

An electric fuse structure is disclosed. The electric fuse preferably includes a substrate and a stacked capacitor on the substrate. Preferably, the stacked capacitor further includes: two or more bottom electrodes on the substrate; a capacitor dielectric layer on the two or more bottom electrodes; and a top electrode on... United Microelectronics Corp

Semiconductor device

A semiconductor device includes a substrate, an electrode layer disposed on the substrate, and a tri-layered gate-control stack sandwiched between the substrate and the electrode layer. The tri-layered gate-control stack includes a ferroelectric layer disposed on the substrate, a mid-gap metal layer sandwiched between the ferroelectric layer and the substrate,... United Microelectronics Corp

Semiconductor integrated circuit structure and forming the same

A semiconductor IC structure includes a substrate including at least a memory cell region and a peripheral region defined thereon, a plurality of memory cells formed in the memory cell region, at least an active device formed in the peripheral region, a plurality of contact plugs formed in the memory... United Microelectronics Corp

Mask rom and process for fabricating the same

A Mask ROM is shown, including first resistors as a first part of memory cells, second resistors as a second part of memory cells, and contact plugs. Each first resistor includes: an undoped first poly-Si layer including a convex portion and a step structure with a step height adjacent to... United Microelectronics Corp

Semiconductor device and fabricating the same

A semiconductor device includes: a gate structure extending along a first direction on a substrate, in which the gate structure includes a first edge and a second edge extending along the first direction; a first doped region adjacent to one side of the gate structure, in which the first doped... United Microelectronics Corp

Microstrip line structure and fabricating the same

A method for fabricating microstrip line structure is disclosed. First, a substrate is provided, ground patterns are formed on the substrate, an interlayer dielectric (ILD) layer is formed on the ground patterns, contact plugs are formed in the ILD layer, a ground plate is formed on the ILD layer, and... United Microelectronics Corp

Color filter device and forming method thereof

A color filter device includes a dielectric layer, a passivation layer, a plurality of color filters and an inorganic film. The dielectric layer is disposed on a substrate, wherein the substrate has a light sensing area and a periphery area, and the periphery area is beside the light sensing area.... United Microelectronics Corp

Semiconductor device and fabricating the same

A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a first gate structure is formed on the substrate, a first spacer is formed around the first gate structure, and an interlayer dielectric (ILD) layer is formed around the first spacer. Next, a first etching process is... United Microelectronics Corp

Bipolar junction transistor

A bipolar junction transistor (BJT) includes a semiconductor substrate and a first isolation structure. The semiconductor substrate includes a first fin structure disposed in an emitter region, a second fin structure disposed in a base region, and a third fin structure disposed in a collector region. The first, the second,... United Microelectronics Corp

Method of forming semiconductor structure

A method of forming a semiconductor structure is disclosed. A substrate having a first area and a second area is provided, wherein a first surface of the first area is lower than a second surface of the second area. A first insulating layer, a first gate, a first dielectric layer... United Microelectronics Corp

Semiconductor sensor and manufacturing the same

A semiconductor sensor, comprising a gas-sensing device and an integrated circuit electrically connected to the gas-sensing device, is provided. The gas-sensing device includes a substrate having a sensing area and an interconnection area in the vicinity of the sensing area, an inter-metal dielectric (IMD) layer formed above the substrate in... United Microelectronics Corp

Method for forming semiconductor structure

A method for forming a semiconductor structure includes following steps. A substrate is provided, and a semiconductor layer is formed on the substrate. Next, a SiN-rich pre-oxide layer is formed on the semiconductor layer. After forming the SiN-rich pre-oxide layer, an anneal treatment is performed to partially transfer the SiN-rich... United Microelectronics Corp

Semiconductor device and fabricating the same

A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a capacitor is formed on the substrate and a hard mask on the capacitor, in which the capacitor includes a bottom electrode, a capacitor dielectric layer, and a top electrode. Next, a protective layer is formed... United Microelectronics Corp

Transistor device with threshold voltage adjusted by body effect

A transistor device including a substrate, a gate structure, a first doped region, a second doped region and a body region is provided. The gate structure is disposed on the substrate. The first doped region and the second doped region are respectively disposed in the substrate at one side and... United Microelectronics Corp

Fabricating semiconductor structure

A fabricating method of a semiconductor structure includes the following steps. A gate material layer is formed on a semiconductor substrate. A patterned mask layer is formed on the gate material layer. The pattern mask layer includes at least one opening exposing a part of the gate material layer. An... United Microelectronics Corp

Alignment mark structure with dummy pattern

An alignment mark structure including a substrate, an alignment mark and at least one dummy pattern is provided. The alignment mark is disposed on the substrate. The at least one dummy pattern is disposed on the substrate and located adjacent to the alignment mark, wherein a size of the at... United Microelectronics Corp

Semiconductor device and manufacturing method thereof

A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate including at least one fin structure is provided. A gate material layer is formed on the semiconductor substrate, and the fin structure is covered by the gate material layer. A trench is formed partly in the... United Microelectronics Corp

Semiconductor structure and fabricating the same

A method for fabricating a semiconductor structure is shown. A first gate of a first device and a second gate of a second device are formed over a semiconductor substrate. First LDD regions are formed in the substrate beside the first gate using the first gate as a mask. A... United Microelectronics Corp

Semiconductor device and fabricating the same

A semiconductor device comprises a semiconductor substrate and a semiconductor fin. The semiconductor substrate has an upper surface and a recess extending downwards into the semiconductor substrate from the upper surface. The semiconductor fin is disposed in the recess and extends upwards beyond the upper surface, wherein the semiconductor fin... United Microelectronics Corp

Semiconductor device and manufacturing method thereof

A semiconductor device includes a semiconductor substrate, an isolation structure, and a spacer. The semiconductor substrate includes at least one fin structure. The isolation structure is partly disposed in the fin structure and partly disposed above the fin structure. The fin structure includes a first fin and a second fin... United Microelectronics Corp

02/15/18 / #20180047809

Bipolar junction transistor device and fabricating the same

A bipolar junction transistor (BJT) device includes a semiconductor substrate, a first doping region with a first conductivity, a second doping region with a second conductivity, a third doping region with the first conductivity, at least one stacked block and a conductive contact. The first doping region is formed in... United Microelectronics Corp

02/15/18 / #20180047810

Semiconductor device and fabricating the same

A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a gate structure is formed on the substrate, a recess is formed adjacent to the gate structure, a buffer layer is formed in the recess, and an epitaxial layer is formed on the buffer layer. Preferably, the... United Microelectronics Corp

02/15/18 / #20180047842

Semiconductor structure and forming the same

A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a substrate, at least a first cell, and at least a second cell. The substrate has a first region and a second region. The first and second cells are in the first and second... United Microelectronics Corp

02/15/18 / #20180047848

Method of fabricating semiconductor device

A semiconductor device and a method of fabricating the same, the semiconductor device includes a plurality of fin shaped structures, a trench, a spacing layer and a dummy gate structure. The fin shaped structures are disposed on a substrate. The trench is disposed between the fin shaped structures. The spacing... United Microelectronics Corp

02/08/18 / #20180040558

Semiconductor device and fabricating the same

A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a substrate, a plurality of gates and a plurality of plugs. The gates are disposed on the substrate and extend in a first direction. The gates include a first gate and a second gate.... United Microelectronics Corp

02/08/18 / #20180040693

Method for fabricating shallow trench isolation between fin-shaped structures

A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a plurality of fin-shaped structures and a first shallow trench isolation (STI) around the fin-shaped structures on the first region and the second region; forming a patterned hard... United Microelectronics Corp

02/08/18 / #20180040694

Semiconductor structure and forming the same

A semiconductor structure and method of forming the same. The semiconductor structure includes a fin structure formed on a substrate and an isolation structure formed therein. The isolation structure includes a trench with a concave upper sidewall, a straight lower sidewall and a rounded top corner. A first dielectric layer... United Microelectronics Corp

02/01/18 / #20180033633

Method for planarizing material layer

A method for planarizing a silicon layer includes providing a silicon layer having at least one recess therein. Next, a photoresist layer is formed to cover the silicon layer and fill up the recess. Then, the photoresist layer is hardened. After that, part of the photoresist layer is removed by... United Microelectronics Corp

02/01/18 / #20180033636

Method of fabricating a semiconductor structure

A method of fabricating a semiconductor structure is provided. A substrate surface is provided and a first layer is disposed on the substrate surface. A second layer covering the first layer is formed wherein the materials of the first layer and the second layer are different. A first polishing operation... United Microelectronics Corp

02/01/18 / #20180033874

Method of fabricating a semiconductor device

A method of fabricating a semiconductor device is disclosed. A substrate is provided. A dummy gate stack is formed on the substrate. The dummy gate stack includes a gate dielectric layer and an amorphous silicon dummy gate on the gate dielectric layer. The amorphous silicon dummy gate is transformed into... United Microelectronics Corp

02/01/18 / #20180033891

Oxide semiconductor device

An oxide semiconductor device includes an oxide semiconductor transistor and a protection wall. The protection wall extends in a vertical direction and surrounds the oxide semiconductor transistor. The oxide semiconductor transistor includes a first oxide semiconductor layer, and a bottom surface of the protection wall is lower than the first... United Microelectronics Corp

02/01/18 / #20180033961

Semiconductor device and manufacturing method thereof

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a bottom metal layer, a resistive random access memory (ReRAM) cell structure, and an upper metal layer. The bottom metal layer is located above the substrate. The ReRAM cell structure is formed on the... United Microelectronics Corp

01/25/18 / #20180027337

Piezoresistive microphone and fabricating the same

A piezoresistive microphone includes a substrate, an insulating layer, and a polysilicon layer. A first pattern is disposed within the polysilicon layer. The first pattern includes numerous first opening. A second pattern is disposed within the polysilicon layer. The second pattern includes numerous second openings. The first pattern surrounds the... United Microelectronics Corp

01/18/18 / #20180019205

Semiconductor device and fabricating the same

A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a first dielectric layer is formed on the substrate, in which a first conductor is embedded within the first dielectric layer. Next, a second dielectric layer is formed on the first dielectric layer, part of the... United Microelectronics Corp

01/18/18 / #20180019206

Electric fuse structure and fabricating the same

A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and first fuse branches and second fuse branches are formed in the substrate, in which the first fuse branches and the second fuse branches are separated by a shallow trench isolation (STI) and the second fuse branches... United Microelectronics Corp

01/18/18 / #20180019324

Semiconductor device having silicon-germanium layer on fin and manufacturing the same

A semiconductor device is provided, including a substrate with an isolation layer formed thereon, wherein the substrate has a fin protruding up through the isolation layer to form a top surface and a pair of lateral sidewalls of the fin above the isolation layer; a silicon-germanium (SiGe) layer epitaxially grown... United Microelectronics Corp

01/18/18 / #20180019341

Tunneling transistor and fabricating the same

A tunneling transistor and a method of fabricating the same, the tunneling transistor includes a fin shaped structure, a source structure and a drain structure, and a gate structure. The fin shaped structure is disposed in a substrate, and the source structure and the drain structure are disposed the fin... United Microelectronics Corp

01/11/18 / #20180012771

Method of planarizing substrate surface

A method of planarizing a substrate surface is disclosed. A substrate having a major surface of a material layer is provided. The major surface of the material layer comprises a first region with relatively low removal rate and a second region of relatively high removal rate. A photoresist pattern is... United Microelectronics Corp

01/11/18 / #20180012772

Method of planarizing substrate surface

A method of planarizing a substrate surface is disclosed. A substrate having a major surface of a material layer is provided. The major surface of the material layer comprises a first region with relatively low removal rate and a second region of relatively high removal rate. A photoresist pattern is... United Microelectronics Corp

01/11/18 / #20180012793

Method for fabricating a semiconductor device

A method for fabricating semiconductor device includes the steps of: forming a dielectric layer on a substrate; forming a stop layer between the dielectric layer and the substrate, wherein the stop layer contacts the substrate directly and the dielectric layer covers the top surface of the stop layer; forming an... United Microelectronics Corp

01/11/18 / #20180012808

Semiconductor device and fabrication method thereof

A method for fabricating a semiconductor device is provided. A substrate having a dummy gate thereon is prepared. A spacer is disposed on a sidewall of the dummy gate. A source/drain region is disposed adjacent to the dummy gate. A sacrificial layer is then formed on the source/drain region. A... United Microelectronics Corp

01/11/18 / #20180012882

Semiconductor structure for electrostatic discharge protection

A semiconductor structure for electrostatic discharge (ESD) protection is provided. The semiconductor structure includes a substrate, a first doped well, a source doped region, a drain doped region, and a gate structure. The first doped well is disposed in the substrate and has a first conductive type. The source doped... United Microelectronics Corp

01/11/18 / #20180012899

Integrated circuit and manufacturing thereof

A method for manufacturing an integrated circuit includes following steps. A substrate including a memory region and a core region is provided. At least two semiconductor word lines, two memory cells in between the two semiconductor word lines, and a semiconductor gate in between the two memory cells are formed... United Microelectronics Corp

01/11/18 / #20180012971

Planar field effect transistor

A fin-shaped field effect transistor includes a substrate and a gate. The substrate includes an active area, where the active area includes a fin structure having at least an extension part protruding from the fin structure. The gate is disposed over the fin structure and directly on the extension part.... United Microelectronics Corp

01/11/18 / #20180012975

Method of fabricating semiconductor device

A semiconductor device and a method of forming the same, the semiconductor device includes a fin shaped structure, agate structure, an epitaxial layer, an interlayer dielectric layer, a first plug and a protection layer. The fin shaped structure is disposed on a substrate, and the gate structure is across the... United Microelectronics Corp

01/11/18 / #20180012976

Semiconductor structure

A method for making a semiconductor device. A substrate having a fin structure is provided. A continuous dummy gate line is formed on the substrate. The dummy gate line strides across the fin structure. A source/drain structure is formed on the fin structure on both sides of the dummy gate... United Microelectronics Corp

01/11/18 / #20180012992

Semiconductor device and forming the same

A semiconductor device and a forming method thereof, the semiconductor device includes a first and a second wells, a source region, a drain region, two gate structures and at least one doping region. The first well with a first conductive type is disposed in a substrate, and the source region... United Microelectronics Corp

01/04/18 / #20180005835

Memory device

Provided is a memory device including a first gate, a second gate and an inter-gate dielectric layer. The first gate is buried in a substrate. The second gate includes metal and is disposed on the substrate. The inter-gate dielectric layer is disposed between the first and second gates. The inter-gate... United Microelectronics Corp

01/04/18 / #20180006038

Layout pattern for static random access memory

A layout pattern of a static random access memory includes a pull-up device, a first pull-down device, a second pull-up device, a second pull-down device, a first pass gate device, a second pass gate device, a third pass gate device and a fourth pass gate device disposed on a substrate.... United Microelectronics Corp

01/04/18 / #20180006040

Static random-access memory (sram) cell array and forming method thereof

A static random-access memory (SRAM) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein the fin structures include a plurality of active fins and a plurality of dummy fins, each PG (pass-gate) FinFET shares at least one of the active... United Microelectronics Corp

Patent Packs
01/04/18 / #20180006129

Transistor and manufacturing method thereof

A transistor includes a semiconductor channel layer, a gate structure, a gate insulation layer, an internal electrode, and a ferroelectric material layer. The gate structure is disposed on the semiconductor channel layer. The gate insulation layer is disposed between the gate structure and the semiconductor channel layer. The internal electrode... United Microelectronics Corp

12/28/17 / #20170373073

Static random-access memory (sram) cell array

A static random-access memory (SRAM) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein the fin structures include a plurality of active fins and a plurality of dummy fins, each PG (pass-gate) FinFET shares at least one of the active... United Microelectronics Corp

12/28/17 / #20170373191

Semiconductor device and fabricating the same

A method for fabricating semiconductor device is disclosed. First, a fin-shaped structure is formed on a substrate, a first liner is formed on the substrate and the fin-shaped structure, a second liner is formed on the first liner, part of the second liner and part of the first liner are... United Microelectronics Corp

12/21/17 / #20170362081

Mems structure and fabricating the same

A method of fabricating a MEMS structure includes providing a substrate comprising a logic element region and a MEMS region. Next, a logic element is formed within the logic element region. A nitrogen-containing material layer is formed to cover the logic element region and the MEMS region conformally. Then, part... United Microelectronics Corp

12/21/17 / #20170365510

Method of forming opening pattern

A method of forming an opening pattern including the following steps is provided. An ultra low dielectric constant layer, a dielectric hard mask layer and a patterned metal hard mask layer are sequentially formed on a substrate. A portion of the dielectric hard mask layer is removed to form a... United Microelectronics Corp

12/21/17 / #20170365675

Dummy pattern arrangement and arranging dummy patterns

A dummy pattern arrangement and a method of arranging dummy patterns are provided in the present invention. The dummy pattern arrangement includes a substrate with a dummy region, a plurality of first base dummy cells arranged spaced apart from each other along a first direction in the dummy region, and... United Microelectronics Corp

12/14/17 / #20170358455

Method of forming fin-shaped structure

A fin-shaped structure includes a substrate having a first fin-shaped structure located in a first area and a second fin-shaped structure located in a second area, wherein the second fin-shaped structure includes a ladder-shaped cross-sectional profile part. The present invention also provides two methods of forming this fin-shaped structure. In... United Microelectronics Corp

12/14/17 / #20170358491

Semiconductor transistor device and fabrication method thereof

A semiconductor transistor device includes a substrate having an active area and a trench isolation region surrounding the active area, a gate oxide layer, a gate, a spacer on a sidewall of the gate, a doping region on one side of the gate, an insulating cap layer covering the gate,... United Microelectronics Corp

12/14/17 / #20170358582

Semiconductor memory device and semiconductor memory array comprising the same

A semiconductor array, the semiconductor memory array includes bit lines, word lines and memory cells. The bit lines are arranged in parallel in a first direction, and the word lines are arranged in parallel in a second direction which is different from the first direction. The memory cells are arranged... United Microelectronics Corp

12/14/17 / #20170358684

Semiconductor device

A semiconductor device includes a substrate, an electrode layer disposed on the substrate, and a tri-layered gate-control stack sandwiched between the substrate and the electrode layer. The tri-layered gate-control stack includes a ferroelectric layer disposed on the substrate, a mid-gap metal layer sandwiched between the ferroelectric layer and the substrate,... United Microelectronics Corp

12/07/17 / #20170352736

Semiconductor process

A fin-shaped field effect transistor includes a substrate and a gate. The substrate includes an active area, where the active area includes a fin structure having at least an extension part protruding from the fin structure. The gate is disposed over the fin structure and directly on the extension part.... United Microelectronics Corp

11/30/17 / #20170345720

Method and controlling voltage of doped well in substrate

A method for controlling voltage of a doped well in a substrate is provided. The substrate and the doped well are in different conductive type. The method includes applying a substrate voltage to the substrate while a well power for applying a well voltage to the doped well is turned... United Microelectronics Corp

11/30/17 / #20170345819

Semiconductor device having gate structure with reduced threshold voltage and manufacturing the same

A semiconductor device is provided, including: a substrate having a first area and a second area; several first gate structures formed at the first area, and at least one of the first gate structures including a first hardmask on a first gate, and the first gate structure having a first... United Microelectronics Corp

11/30/17 / #20170345926

High-voltage metal-oxide-semiconductor transistor and fabrication method thereof

A high-voltage MOS transistor includes a semiconductor substrate, a gate oxide layer on the semiconductor substrate, a gate on the gate oxide layer, a spacer covering a sidewall of the gate, a source on one side of the gate, and a drain on the other side of the gate. The... United Microelectronics Corp

11/30/17 / #20170345937

Method for forming semiconductor structure

A method for manufacturing a semiconductor structure includes the following steps. First, a semiconductor substrate including a first semiconductor material is provided. The semiconductor substrate includes a dielectric structure formed thereon, and the dielectric structure includes at least a recess formed therein. A first epitaxial layer is then formed in... United Microelectronics Corp

Patent Packs
11/30/17 / #20170345938

Bottom-up epitaxy growth on air-gap buffer

A fin structure for a semiconductor device, such as a FinFET structure, has first and second semiconductor layers and an air gap between the layers. The second semiconductor layer includes a recessed portion, the air gap is located in the recessed portion, and the recessed portion has an upwardly-opening acute... United Microelectronics Corp

11/23/17 / #20170338227

Semiconductor device with metal gates

A semiconductor device includes at least a substrate, fin-shaped structures, a protection layer, epitaxial layers, and a gate electrode. The fin-shaped structures are disposed in a first region and a second region of the substrate. The protection layer conformally covers the surface of the substrate and the sidewalls of fin-shaped... United Microelectronics Corp

11/23/17 / #20170338239

Semiconductor structure and manufacturing the same

A semiconductor structure includes a substrate and a plurality of memory cells disposed on the substrate. Each memory cell includes a gate structure. The gate structures are spaced from each other by a spacing S. Each gate structure includes a dielectric layer and a gate electrode. The dielectric layer has... United Microelectronics Corp

11/23/17 / #20170338327

Semiconductor device and manufacturing method thereof

A semiconductor device and a manufacturing method thereof, the semiconductor device includes two gate structures and an epitaxial structure. The two gate structures are disposed on a substrate. The epitaxial structure is disposed in the substrate between the gate structures, wherein a protruding portion of the substrate extends into the... United Microelectronics Corp

11/23/17 / #20170338351

Semiconductor device

A semiconductor device is provided in the present invention, which includes a substrate, an oxide-semiconductor layer, source/drain regions, a dielectric layer, a first gate electrode, a second gate electrode and a charge storage structure. The oxide-semiconductor layer is disposed on the first gate electrode on the substrate. The source/drain regions... United Microelectronics Corp

11/16/17 / #20170328949

Semiconductor structure and testing method using the same

A semiconductor structure includes at least two via chains. Each via chain includes at least one first conductive component, at least one second conductive component and at least one via. The first conductive component has an axis along an extending direction of the first conductive component. The via connects the... United Microelectronics Corp

11/16/17 / #20170330742

Method of forming semiconductor device

A semiconductor device and a method of forming the same, the semiconductor device includes fin shaped structures and a recessed insulating layer. The fin shaped structures are disposed on a substrate. The recessed insulating layer covers a bottom portion of each of the fin shaped structures to expose a top... United Microelectronics Corp

11/16/17 / #20170330820

Method for fabrication semiconductor device

A method for is used for forming a semiconductor device. The method includes forming an ILD layer on a substrate and a buffer layer on the ILD layer, wherein at least one contact is formed in the ILD layer; forming an opening through the buffer layer, the ILD layer, and... United Microelectronics Corp

11/16/17 / #20170330937

Manufacturing semiconductor device

A semiconductor device includes a substrate including a plurality of transistor devices formed thereon, at least an epitaxial structure formed in between the transistor devices, and a tri-layered structure formed on the epitaxial structure. The epitaxial structure includes a first semiconductor material and a second semiconductor material, and a lattice... United Microelectronics Corp

11/16/17 / #20170330947

Metal-oxide-semiconductor transistor and forming gate layout

A metal-oxide semiconductor transistor includes a substrate, a gate insulating layer disposed on a surface of the substrate, and a metal gate disposed on the gate insulating layer, wherein at least one of the length or the width of the metal gate is greater than or equal to approximately 320... United Microelectronics Corp

11/16/17 / #20170330948

Metal-oxide-semiconductor transistor and forming gate layout

A method of forming a gate layout includes providing a gate layout design diagram comprising at least one gate pattern, disposing at least one insulating plug pattern in the gate pattern for producing a modified gate layout in a case where any one of a length and a width of... United Microelectronics Corp

11/16/17 / #20170330952

Semiconductor device and forming the same

A semiconductor device and a method of forming the same, the semiconductor device include a substrate, and a first gate structure and a second gate structure disposed on the substrate. The first gate structure includes a barrier layer, a first work function layer, a second work function layer and a... United Microelectronics Corp

11/16/17 / #20170330954

Semiconductor device and fabricating the same

A semiconductor device includes an interfacial layer on a substrate and agate structure on the interfacial layer. Preferably, the gate structure includes a patterned high-k dielectric layer, the patterned high-k dielectric layer comprises a metal oxide layer, and a horizontal direction width of the patterned high-k dielectric layer and a... United Microelectronics Corp

11/16/17 / #20170330956

Method for fabricating semiconductor device

A method for fabricating semiconductor device includes the steps of: providing a substrate, wherein the substrate comprises a first region and a second region; forming a high-k dielectric layer on the first region and the second region; forming a first bottom barrier metal (BBM) layer on the high-k dielectric layer... United Microelectronics Corp

11/09/17 / #20170320727

Microelectromechanical system structure and fabricating the same

A microelectromechanical system structure and a method for fabricating the same are provided. A method for fabricating a MEMS structure includes the following steps. A first substrate is provided, wherein a transistor, a first dielectric layer and an interconnection structure are formed thereon. A second substrate is provided, wherein a... United Microelectronics Corp

11/09/17 / #20170323824

Semiconductor device and fabricating the same

A semiconductor device includes: a substrate, a gate structure on the substrate, and a spacer adjacent to the gate structure, in which the spacer extends to a top surface of the gate structure, a top surface of the spacer includes a planar surface, the spacer encloses an air gap, and... United Microelectronics Corp

11/09/17 / #20170323852

Semiconductor device and fabricating the same

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; forming an epitaxial layer adjacent to the gate structure; forming an interlayer dielectric (ILD) layer on the gate structure; forming a first contact hole in the... United Microelectronics Corp

11/09/17 / #20170323854

Feeding overlay data of one layer to next layer for manufacturing integrated circuit

A method of manufacturing an integrated circuit includes the following steps. A substrate including a plurality of exposure fields is provided, and each of the exposure fields includes a target portion and a set of overlay marks. The substrate is exposed to form a first layer lithography pattern on the... United Microelectronics Corp

11/09/17 / #20170323880

Semiconductor device for electrostatic discharge protection

A semiconductor device for electrostatic discharge (ESD) protection includes a doped well, a drain region, a source region, a first doped region and a guard ring. The doped well is disposed in a substrate and has a first conductive type. The drain region is disposed in the doped well and... United Microelectronics Corp

11/09/17 / #20170323894

Layout pattern for static random access memory

A layout pattern of a static random access memory includes a pull-up device, a first pull-down device, a second pull-up device, a second pull-down device, a first pass gate device and a second pass gate device disposed on a substrate. A plurality of fin structures are disposed on the substrate,... United Microelectronics Corp

11/09/17 / #20170323950

Semiconductor process

A semiconductor process is described. A silicon-phosphorus (SiP) epitaxial layer is formed serving as a source/drain (S/D) region. A crystalline metal silicide layer is formed directly on the SiP epitaxial layer and thus prevents oxidation of the SiP epitaxial layer. A contact plug is formed over the crystalline metal silicide... United Microelectronics Corp








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