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United Microelectronics Corp patents


Recent patent applications related to United Microelectronics Corp. United Microelectronics Corp is listed as an Agent/Assignee. Note: United Microelectronics Corp may have other listings under different names/spellings. We're not affiliated with United Microelectronics Corp, we're just tracking patents.

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Device with reinforced metal gate spacer and fabricating

A semiconductor device with reinforced gate spacers and a method of fabricating the same. The semiconductor device includes low-k dielectric gate spacers adjacent to a gate structure. A high-k dielectric material is disposed over an upper surface of the low-k dielectric gate spacers to prevent unnecessary contact between the gate... United Microelectronics Corp

Field-effect transistor and making the same

A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. A vertically extending portion of the epitaxial structure extends vertically above a top surface of the semiconductor substrate in an area adjacent the gate structure.... United Microelectronics Corp

Method for fabricating a fin field effect transistor (finfet)

The invention provides a method for fabricating a fin field effect transistor (FinFET), comprising: providing a substrate having a logic region and a large region; forming a plurality of fin structures in the logic region by removing a portion of the substrate in the logic region; forming an oxide layer... United Microelectronics Corp

Method of epitaxial structure formation in a semiconductor

The invention provides a method of epitaxial structure formation in a semiconductor, comprising: providing a substrate; performing a dry etch to form a first recess; after performing the dry etch, performing a SPM cleaning process on the substrate by using a nozzle spraying SPM solution with an angle greater than... United Microelectronics Corp

Method for manufacturing a high-voltage finfet device having ldmos structure

A high-voltage FinFET device having LDMOS structure and a method for manufacturing the same are provided. The method includes: providing a substrate with a fin structure to define a first and a second type well regions; forming a trench in the first-type well region to separate the fin structure into... United Microelectronics Corp

Device with reinforced metal gate spacer and fabricating

A semiconductor device with reinforced gate spacers and a method of fabricating the same. The semiconductor device includes low-k dielectric gate spacers adjacent to a gate structure. A high-k dielectric material is disposed over an upper surface of the low-k dielectric gate spacers to prevent unnecessary contact between the gate... United Microelectronics Corp

Fin-shaped field effect transistor

The present invention provides a fin-shaped field effect transistor (FinFET), comprises: a substrate having a fin structure; a plurality trenches formed on the fin structure with an alloy grown in the trenches; a gate structure on the fin structure perpendicular to an extending direction of the fin structure in-between the... United Microelectronics Corp

 new patent  Semiconductor device and fabricating the same

A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a first dielectric layer is formed on the substrate, in which a first conductor is embedded within the first dielectric layer. Next, a second dielectric layer is formed on the first dielectric layer, part of the... United Microelectronics Corp

 new patent  Electric fuse structure and fabricating the same

A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and first fuse branches and second fuse branches are formed in the substrate, in which the first fuse branches and the second fuse branches are separated by a shallow trench isolation (STI) and the second fuse branches... United Microelectronics Corp

 new patent  Semiconductor device having silicon-germanium layer on fin and manufacturing the same

A semiconductor device is provided, including a substrate with an isolation layer formed thereon, wherein the substrate has a fin protruding up through the isolation layer to form a top surface and a pair of lateral sidewalls of the fin above the isolation layer; a silicon-germanium (SiGe) layer epitaxially grown... United Microelectronics Corp

 new patent  Tunneling transistor and fabricating the same

A tunneling transistor and a method of fabricating the same, the tunneling transistor includes a fin shaped structure, a source structure and a drain structure, and a gate structure. The fin shaped structure is disposed in a substrate, and the source structure and the drain structure are disposed the fin... United Microelectronics Corp

Method of planarizing substrate surface

A method of planarizing a substrate surface is disclosed. A substrate having a major surface of a material layer is provided. The major surface of the material layer comprises a first region with relatively low removal rate and a second region of relatively high removal rate. A photoresist pattern is... United Microelectronics Corp

Method of planarizing substrate surface

A method of planarizing a substrate surface is disclosed. A substrate having a major surface of a material layer is provided. The major surface of the material layer comprises a first region with relatively low removal rate and a second region of relatively high removal rate. A photoresist pattern is... United Microelectronics Corp

Method for fabricating a semiconductor device

A method for fabricating semiconductor device includes the steps of: forming a dielectric layer on a substrate; forming a stop layer between the dielectric layer and the substrate, wherein the stop layer contacts the substrate directly and the dielectric layer covers the top surface of the stop layer; forming an... United Microelectronics Corp

Semiconductor device and fabrication method thereof

A method for fabricating a semiconductor device is provided. A substrate having a dummy gate thereon is prepared. A spacer is disposed on a sidewall of the dummy gate. A source/drain region is disposed adjacent to the dummy gate. A sacrificial layer is then formed on the source/drain region. A... United Microelectronics Corp

Semiconductor structure for electrostatic discharge protection

A semiconductor structure for electrostatic discharge (ESD) protection is provided. The semiconductor structure includes a substrate, a first doped well, a source doped region, a drain doped region, and a gate structure. The first doped well is disposed in the substrate and has a first conductive type. The source doped... United Microelectronics Corp

Integrated circuit and manufacturing thereof

A method for manufacturing an integrated circuit includes following steps. A substrate including a memory region and a core region is provided. At least two semiconductor word lines, two memory cells in between the two semiconductor word lines, and a semiconductor gate in between the two memory cells are formed... United Microelectronics Corp

Planar field effect transistor

A fin-shaped field effect transistor includes a substrate and a gate. The substrate includes an active area, where the active area includes a fin structure having at least an extension part protruding from the fin structure. The gate is disposed over the fin structure and directly on the extension part.... United Microelectronics Corp

Method of fabricating semiconductor device

A semiconductor device and a method of forming the same, the semiconductor device includes a fin shaped structure, agate structure, an epitaxial layer, an interlayer dielectric layer, a first plug and a protection layer. The fin shaped structure is disposed on a substrate, and the gate structure is across the... United Microelectronics Corp

Semiconductor structure

A method for making a semiconductor device. A substrate having a fin structure is provided. A continuous dummy gate line is formed on the substrate. The dummy gate line strides across the fin structure. A source/drain structure is formed on the fin structure on both sides of the dummy gate... United Microelectronics Corp

Semiconductor device and forming the same

A semiconductor device and a forming method thereof, the semiconductor device includes a first and a second wells, a source region, a drain region, two gate structures and at least one doping region. The first well with a first conductive type is disposed in a substrate, and the source region... United Microelectronics Corp

Memory device

Provided is a memory device including a first gate, a second gate and an inter-gate dielectric layer. The first gate is buried in a substrate. The second gate includes metal and is disposed on the substrate. The inter-gate dielectric layer is disposed between the first and second gates. The inter-gate... United Microelectronics Corp

Layout pattern for static random access memory

A layout pattern of a static random access memory includes a pull-up device, a first pull-down device, a second pull-up device, a second pull-down device, a first pass gate device, a second pass gate device, a third pass gate device and a fourth pass gate device disposed on a substrate.... United Microelectronics Corp

Static random-access memory (sram) cell array and forming method thereof

A static random-access memory (SRAM) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein the fin structures include a plurality of active fins and a plurality of dummy fins, each PG (pass-gate) FinFET shares at least one of the active... United Microelectronics Corp

Transistor and manufacturing method thereof

A transistor includes a semiconductor channel layer, a gate structure, a gate insulation layer, an internal electrode, and a ferroelectric material layer. The gate structure is disposed on the semiconductor channel layer. The gate insulation layer is disposed between the gate structure and the semiconductor channel layer. The internal electrode... United Microelectronics Corp

Static random-access memory (sram) cell array

A static random-access memory (SRAM) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein the fin structures include a plurality of active fins and a plurality of dummy fins, each PG (pass-gate) FinFET shares at least one of the active... United Microelectronics Corp

Semiconductor device and fabricating the same

A method for fabricating semiconductor device is disclosed. First, a fin-shaped structure is formed on a substrate, a first liner is formed on the substrate and the fin-shaped structure, a second liner is formed on the first liner, part of the second liner and part of the first liner are... United Microelectronics Corp

Mems structure and fabricating the same

A method of fabricating a MEMS structure includes providing a substrate comprising a logic element region and a MEMS region. Next, a logic element is formed within the logic element region. A nitrogen-containing material layer is formed to cover the logic element region and the MEMS region conformally. Then, part... United Microelectronics Corp

Method of forming opening pattern

A method of forming an opening pattern including the following steps is provided. An ultra low dielectric constant layer, a dielectric hard mask layer and a patterned metal hard mask layer are sequentially formed on a substrate. A portion of the dielectric hard mask layer is removed to form a... United Microelectronics Corp

Dummy pattern arrangement and arranging dummy patterns

A dummy pattern arrangement and a method of arranging dummy patterns are provided in the present invention. The dummy pattern arrangement includes a substrate with a dummy region, a plurality of first base dummy cells arranged spaced apart from each other along a first direction in the dummy region, and... United Microelectronics Corp

Method of forming fin-shaped structure

A fin-shaped structure includes a substrate having a first fin-shaped structure located in a first area and a second fin-shaped structure located in a second area, wherein the second fin-shaped structure includes a ladder-shaped cross-sectional profile part. The present invention also provides two methods of forming this fin-shaped structure. In... United Microelectronics Corp

Semiconductor transistor device and fabrication method thereof

A semiconductor transistor device includes a substrate having an active area and a trench isolation region surrounding the active area, a gate oxide layer, a gate, a spacer on a sidewall of the gate, a doping region on one side of the gate, an insulating cap layer covering the gate,... United Microelectronics Corp

Semiconductor memory device and semiconductor memory array comprising the same

A semiconductor array, the semiconductor memory array includes bit lines, word lines and memory cells. The bit lines are arranged in parallel in a first direction, and the word lines are arranged in parallel in a second direction which is different from the first direction. The memory cells are arranged... United Microelectronics Corp

Semiconductor device

A semiconductor device includes a substrate, an electrode layer disposed on the substrate, and a tri-layered gate-control stack sandwiched between the substrate and the electrode layer. The tri-layered gate-control stack includes a ferroelectric layer disposed on the substrate, a mid-gap metal layer sandwiched between the ferroelectric layer and the substrate,... United Microelectronics Corp

Semiconductor process

A fin-shaped field effect transistor includes a substrate and a gate. The substrate includes an active area, where the active area includes a fin structure having at least an extension part protruding from the fin structure. The gate is disposed over the fin structure and directly on the extension part.... United Microelectronics Corp

11/30/17 / #20170345720

Method and controlling voltage of doped well in substrate

A method for controlling voltage of a doped well in a substrate is provided. The substrate and the doped well are in different conductive type. The method includes applying a substrate voltage to the substrate while a well power for applying a well voltage to the doped well is turned... United Microelectronics Corp

11/30/17 / #20170345819

Semiconductor device having gate structure with reduced threshold voltage and manufacturing the same

A semiconductor device is provided, including: a substrate having a first area and a second area; several first gate structures formed at the first area, and at least one of the first gate structures including a first hardmask on a first gate, and the first gate structure having a first... United Microelectronics Corp

11/30/17 / #20170345926

High-voltage metal-oxide-semiconductor transistor and fabrication method thereof

A high-voltage MOS transistor includes a semiconductor substrate, a gate oxide layer on the semiconductor substrate, a gate on the gate oxide layer, a spacer covering a sidewall of the gate, a source on one side of the gate, and a drain on the other side of the gate. The... United Microelectronics Corp

11/30/17 / #20170345937

Method for forming semiconductor structure

A method for manufacturing a semiconductor structure includes the following steps. First, a semiconductor substrate including a first semiconductor material is provided. The semiconductor substrate includes a dielectric structure formed thereon, and the dielectric structure includes at least a recess formed therein. A first epitaxial layer is then formed in... United Microelectronics Corp

11/30/17 / #20170345938

Bottom-up epitaxy growth on air-gap buffer

A fin structure for a semiconductor device, such as a FinFET structure, has first and second semiconductor layers and an air gap between the layers. The second semiconductor layer includes a recessed portion, the air gap is located in the recessed portion, and the recessed portion has an upwardly-opening acute... United Microelectronics Corp

11/23/17 / #20170338227

Semiconductor device with metal gates

A semiconductor device includes at least a substrate, fin-shaped structures, a protection layer, epitaxial layers, and a gate electrode. The fin-shaped structures are disposed in a first region and a second region of the substrate. The protection layer conformally covers the surface of the substrate and the sidewalls of fin-shaped... United Microelectronics Corp

11/23/17 / #20170338239

Semiconductor structure and manufacturing the same

A semiconductor structure includes a substrate and a plurality of memory cells disposed on the substrate. Each memory cell includes a gate structure. The gate structures are spaced from each other by a spacing S. Each gate structure includes a dielectric layer and a gate electrode. The dielectric layer has... United Microelectronics Corp

11/23/17 / #20170338327

Semiconductor device and manufacturing method thereof

A semiconductor device and a manufacturing method thereof, the semiconductor device includes two gate structures and an epitaxial structure. The two gate structures are disposed on a substrate. The epitaxial structure is disposed in the substrate between the gate structures, wherein a protruding portion of the substrate extends into the... United Microelectronics Corp

11/23/17 / #20170338351

Semiconductor device

A semiconductor device is provided in the present invention, which includes a substrate, an oxide-semiconductor layer, source/drain regions, a dielectric layer, a first gate electrode, a second gate electrode and a charge storage structure. The oxide-semiconductor layer is disposed on the first gate electrode on the substrate. The source/drain regions... United Microelectronics Corp

11/16/17 / #20170328949

Semiconductor structure and testing method using the same

A semiconductor structure includes at least two via chains. Each via chain includes at least one first conductive component, at least one second conductive component and at least one via. The first conductive component has an axis along an extending direction of the first conductive component. The via connects the... United Microelectronics Corp

11/16/17 / #20170330742

Method of forming semiconductor device

A semiconductor device and a method of forming the same, the semiconductor device includes fin shaped structures and a recessed insulating layer. The fin shaped structures are disposed on a substrate. The recessed insulating layer covers a bottom portion of each of the fin shaped structures to expose a top... United Microelectronics Corp

11/16/17 / #20170330820

Method for fabrication semiconductor device

A method for is used for forming a semiconductor device. The method includes forming an ILD layer on a substrate and a buffer layer on the ILD layer, wherein at least one contact is formed in the ILD layer; forming an opening through the buffer layer, the ILD layer, and... United Microelectronics Corp

11/16/17 / #20170330937

Manufacturing semiconductor device

A semiconductor device includes a substrate including a plurality of transistor devices formed thereon, at least an epitaxial structure formed in between the transistor devices, and a tri-layered structure formed on the epitaxial structure. The epitaxial structure includes a first semiconductor material and a second semiconductor material, and a lattice... United Microelectronics Corp

11/16/17 / #20170330947

Metal-oxide-semiconductor transistor and forming gate layout

A metal-oxide semiconductor transistor includes a substrate, a gate insulating layer disposed on a surface of the substrate, and a metal gate disposed on the gate insulating layer, wherein at least one of the length or the width of the metal gate is greater than or equal to approximately 320... United Microelectronics Corp

11/16/17 / #20170330948

Metal-oxide-semiconductor transistor and forming gate layout

A method of forming a gate layout includes providing a gate layout design diagram comprising at least one gate pattern, disposing at least one insulating plug pattern in the gate pattern for producing a modified gate layout in a case where any one of a length and a width of... United Microelectronics Corp

11/16/17 / #20170330952

Semiconductor device and forming the same

A semiconductor device and a method of forming the same, the semiconductor device include a substrate, and a first gate structure and a second gate structure disposed on the substrate. The first gate structure includes a barrier layer, a first work function layer, a second work function layer and a... United Microelectronics Corp

11/16/17 / #20170330954

Semiconductor device and fabricating the same

A semiconductor device includes an interfacial layer on a substrate and agate structure on the interfacial layer. Preferably, the gate structure includes a patterned high-k dielectric layer, the patterned high-k dielectric layer comprises a metal oxide layer, and a horizontal direction width of the patterned high-k dielectric layer and a... United Microelectronics Corp

11/16/17 / #20170330956

Method for fabricating semiconductor device

A method for fabricating semiconductor device includes the steps of: providing a substrate, wherein the substrate comprises a first region and a second region; forming a high-k dielectric layer on the first region and the second region; forming a first bottom barrier metal (BBM) layer on the high-k dielectric layer... United Microelectronics Corp

11/09/17 / #20170320727

Microelectromechanical system structure and fabricating the same

A microelectromechanical system structure and a method for fabricating the same are provided. A method for fabricating a MEMS structure includes the following steps. A first substrate is provided, wherein a transistor, a first dielectric layer and an interconnection structure are formed thereon. A second substrate is provided, wherein a... United Microelectronics Corp

11/09/17 / #20170323824

Semiconductor device and fabricating the same

A semiconductor device includes: a substrate, a gate structure on the substrate, and a spacer adjacent to the gate structure, in which the spacer extends to a top surface of the gate structure, a top surface of the spacer includes a planar surface, the spacer encloses an air gap, and... United Microelectronics Corp

11/09/17 / #20170323852

Semiconductor device and fabricating the same

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; forming an epitaxial layer adjacent to the gate structure; forming an interlayer dielectric (ILD) layer on the gate structure; forming a first contact hole in the... United Microelectronics Corp

11/09/17 / #20170323854

Feeding overlay data of one layer to next layer for manufacturing integrated circuit

A method of manufacturing an integrated circuit includes the following steps. A substrate including a plurality of exposure fields is provided, and each of the exposure fields includes a target portion and a set of overlay marks. The substrate is exposed to form a first layer lithography pattern on the... United Microelectronics Corp

11/09/17 / #20170323880

Semiconductor device for electrostatic discharge protection

A semiconductor device for electrostatic discharge (ESD) protection includes a doped well, a drain region, a source region, a first doped region and a guard ring. The doped well is disposed in a substrate and has a first conductive type. The drain region is disposed in the doped well and... United Microelectronics Corp

11/09/17 / #20170323894

Layout pattern for static random access memory

A layout pattern of a static random access memory includes a pull-up device, a first pull-down device, a second pull-up device, a second pull-down device, a first pass gate device and a second pass gate device disposed on a substrate. A plurality of fin structures are disposed on the substrate,... United Microelectronics Corp

11/09/17 / #20170323950

Semiconductor process

A semiconductor process is described. A silicon-phosphorus (SiP) epitaxial layer is formed serving as a source/drain (S/D) region. A crystalline metal silicide layer is formed directly on the SiP epitaxial layer and thus prevents oxidation of the SiP epitaxial layer. A contact plug is formed over the crystalline metal silicide... United Microelectronics Corp

11/02/17 / #20170315892

Memory system capable of generating notification signals

A memory system includes a memory device, a switch device, and a built-in self-test circuit. The memory device is for storing data and toggling a notification signal whenever a read operation or a write operation is completed. The switch device has a first input terminal for receiving an external clock... United Microelectronics Corp

11/02/17 / #20170316830

Light-erasable embedded memory device and manufacturing the same

A light-erasable embedded memory device and a method for manufacturing the same are provided in the present invention. The light-erasable embedded memory device includes a substrate with a memory region and a core circuit region, a floating gate on the memory region of the substrate, at least two light-absorbing films... United Microelectronics Corp

11/02/17 / #20170317090

Method of forming static random-access memory (sram) cell array

A static random-access memory (SRAM) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein the fin structures include a plurality of active fins and a plurality of dummy fins, each PG (pass-gate) FinFET shares at least one of the active... United Microelectronics Corp

11/02/17 / #20170317091

Static random-access memory (sram) cell array

A static random-access memory (SRAM) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein the fin structures include a plurality of active fins and a plurality of dummy fins, each PG (pass-gate) FinFET shares at least one of the active... United Microelectronics Corp

11/02/17 / #20170317092

Structure of memory cell with asymmetric cell structure and fabricating the same

A memory cell disposed on a substrate has a first gate structure and a second gate structure. The memory cell includes a first heavily doped region adjacent to an outer side of the first gate structure. Further, a first lightly doped drain (LDD) region with a first type dopant is... United Microelectronics Corp

Patent Packs
11/02/17 / #20170317197

Bipolar junction transistor layout structure

A bipolar junction transistor layout structure includes a first emitter including a pair of first sides and a pair of second sides, a pair of collectors disposed at the first sides of the first emitter, and a pair of bases disposed at the second sides of the first emitter. The... United Microelectronics Corp

10/26/17 / #20170309485

Apparatus for semiconductor wafer treatment and semiconductor wafer treatment

An apparatus for semiconductor wafer treatment includes a wafer holding unit configured to receive a single wafer, at least a solution supply unit configured to apply a solution onto the wafer and an irradiation unit configured to emit irradiation to the wafer. The irradiation unit further includes at least a... United Microelectronics Corp

10/26/17 / #20170309520

Semiconductor device and fabricating the same

A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a first metal gate and a second metal gate are formed on the substrate, in which the first metal gate includes a first work function metal layer, the second metal gate includes a second work function... United Microelectronics Corp

10/26/17 / #20170309613

Electrostatic discharge protection semiconductor device and layout structure of esd protection semiconductor device

A layout structure of an ESD protection semiconductor device includes a substrate, a first doped region, a pair of second doped regions, a pair of third doped regions, at least a first gate structure formed within the first doped region, and a drain region and a first source region formed... United Microelectronics Corp

10/26/17 / #20170309621

Semiconductor device having gate structure with reduced threshold voltage and manufacturing the same

A semiconductor device is provided, including: a substrate having a first area and a second area; several first gate structures formed at the first area, and at least one of the first gate structures including a first hardmask on a first gate, and the first gate structure having a first... United Microelectronics Corp

10/26/17 / #20170309708

Field effect transistor

A field effect transistor is provided in the present invention with an active area including a source region, a drain region, and a channel region. The width of the channel region is larger than the width of the source/drain regions, and at least one of the source region and the... United Microelectronics Corp

10/26/17 / #20170309722

Semiconductor device having metal gate structure

A metal gate transistor includes a substrate, a metal gate on the substrate, and a source/drain region in the substrate adjacent to the metal gate. The metal gate includes a high-k dielectric layer, a bottom barrier metal (BBM) layer comprising TiSiN on the high-k dielectric layer, a TiN layer on... United Microelectronics Corp

10/26/17 / #20170309727

Manufacturing patterned structure of semiconductor

A method of fabricating a patterned structure of a semiconductor device includes the following steps: providing a substrate having a target layer thereon; forming a patterned sacrificial layer on the target layer, wherein the patterned sacrificial layer consists of a plurality of sacrificial features; forming spacers respectively on sidewalls of... United Microelectronics Corp

10/19/17 / #20170301536

Method for fabricating semiconductor device

A method for forming an epitaxial layer on a substrate is disclosed. The method includes the steps of: providing a substrate into a chamber; injecting a precursor and a carrier gas to form the epitaxial layer on the substrate at a starting pressure; and pumping down the starting pressure to... United Microelectronics Corp

10/19/17 / #20170301670

Semiconductor device and fabricating the same

A method for fabricating semiconductor device includes the steps of: providing a substrate having a gate structure thereon; forming a silicon layer on the substrate to cover the gate structure entirely; planarizing the silicon layer; and performing a replacement metal gate (RMG) process to transform the gate structure into a... United Microelectronics Corp

10/19/17 / #20170301683

Semiconductor device with split gate flash memory cell structure and manufacturing the same

A semiconductor device with split gate flash memory cell structure includes a substrate having a first area and a second area, at least a first cell formed in the first area and at least a second cell formed in the second area. The first cell includes a first dielectric layer... United Microelectronics Corp

10/12/17 / #20170292976

Test circuit for testing a device-under-test by using a voltage-setting unit to pull an end of the device-under-test to a predetermined voltage

A test circuit includes a pull-up device, a pull-down device, a switch circuit and a voltage-setting unit. The pull-up device is used to receive a first control signal and coupled to a first end of the device-under-test. The pull-down device is used to receive a second control signal and coupled... United Microelectronics Corp

10/12/17 / #20170294429

Semiconductor layout structure

A semiconductor layout structure includes a substrate comprising a cell edge region and a dummy region abutting thereto, a plurality of dummy contact patterns disposed in the dummy region and arranged along a first direction, and a plurality of dummy gate patterns disposed in the dummy region and arranged along... United Microelectronics Corp

10/12/17 / #20170294508

Semiconductor device and fabricating the same

A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a gate structure is formed on the substrate. Next, a recess is formed adjacent to two sides of the gate structure, and an epitaxial layer is formed in the recess, in which a top surface of... United Microelectronics Corp

10/12/17 / #20170294523

Method for fabricating semiconductor device

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first organic layer on the substrate; patterning the first organic layer to form an opening; forming a second organic layer in the opening; and removing the first organic layer to form... United Microelectronics Corp

Patent Packs
10/12/17 / #20170294539

Semiconductor device and fabricating semiconductor device

The present invention provides a semiconductor device, including a substrate, two gate structures disposed on a channel region of the substrate, an epitaxial layer disposed in the substrate between two gate structures, a first dislocation disposed in the epitaxial layer, wherein the profile of the first dislocation has at least... United Microelectronics Corp

10/12/17 / #20170294540

Semiconductor structure and manufacturing the same

A semiconductor structure and a method for manufacturing the same are provided. The semiconductor includes a substrate, two source/drain regions, a gate structure and two salicide layers. The two source/drain regions are partially disposed in the substrate each with a substantially flat top surface higher than a top surface of... United Microelectronics Corp

10/05/17 / #20170287723

Semiconductor device and fabricating the same

A method for fabricating semiconductor device includes the steps of: providing a substrate; forming a fin-shaped structure on the substrate; performing a first etching process to remove part of the fin-shaped structure for forming a trench; and performing a second etching process to extend the depth of the trench and... United Microelectronics Corp

10/05/17 / #20170287843

Semiconductor device having contact plugs with different interfacial layers

According to a preferred embodiment of the present invention, a semiconductor device is disclosed. The semiconductor device includes: a substrate having a first region and a second region; a first contact plug on the first region, and a second contact plug on the second region. Preferably, the first contact plug... United Microelectronics Corp

10/05/17 / #20170287858

Semiconductor device with modified pad spacing structure

A semiconductor device is provided, including a substrate, an interconnection structure formed on the substrate, a first top conductive layer formed on the interconnection structure, bars formed on the interconnection structure, and a second top conductive layer formed above the first top conductive layer. The first top conductive layer includes... United Microelectronics Corp

10/05/17 / #20170288018

Nanowire transistor and fabricating the same

A method for fabricating a nanowire transistor is disclosed. First, a substrate is provided, and a stack structure is formed on the substrate, in which the stack structure includes a first semiconductor layer and a second semiconductor layer and the first semiconductor layer and the second semiconductor layer are made... United Microelectronics Corp

09/28/17 / #20170278845

Method for fabricating fin-shaped structure and bump made of different material

A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a first fin-shaped structure and a bump are formed on the substrate, and an insulating layer is formed on the bump and around the first fin-shaped structure. Next, a part of the first fin-shaped structure is removed,... United Microelectronics Corp

09/28/17 / #20170278928

Semiconductor device and forming the same

The present invention provides a semiconductor device, including a substrate, a first semiconductor layer, a plurality of first sub recess, a plurality of insulation structures and a first top semiconductor layer. The substrate has a first region disposed within an STI. The first semiconductor layer is disposed in the first... United Microelectronics Corp

09/28/17 / #20170278947

Semiconductor fin structure and forming the same

A method of forming a semiconductor fin structure is provided. A substrate is provided, which has at least two sub regions and a dummy region disposed therebetween. A recess is disposed in each sub region. A semiconductor layer is formed to fill the recesses. A patterned mask layer is formed... United Microelectronics Corp

09/21/17 / #20170271197

Semiconductor device and fabricating the same

A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region, a second region, and a third region; forming a plurality of spacers on the first region, the second region, and the third region; forming a first patterned mask to cover the spacers on... United Microelectronics Corp

09/21/17 / #20170271504

Semiconductor structure and manufacturing the same

A semiconductor structure and a manufacturing method for the same are disclosed. The semiconductor structure includes a first gate structure, a second gate structure and a second dielectric spacer. Each of the first gate structure and the second gate structure adjacent to each other includes a first dielectric spacer. The... United Microelectronics Corp

09/21/17 / #20170271529

Avalanche photo detector device and manufacturing method thereof

An avalanche photodetector device includes a substrate having a front side and a back side, an avalanche photo detector structure disposed on the front side of the substrate, a plurality of heat sinks disposed on the back side of the substrate, and a plurality of reflecting islands disposed on the... United Microelectronics Corp

09/14/17 / #20170263294

Semiconductor memory device capable of performing read operation and write operation simultaneously

A semiconductor memory device includes a charge storage element, a read transistor, and a write transistor. The charge storage element is for preserving a first data voltage. The read transistor has a first terminal coupled to the charge storage element, a second terminal coupled to a read bit line, and... United Microelectronics Corp

09/14/17 / #20170263454

Method for forming fin structures for non-planar semiconductor device

A method for forming fin structure includes following steps. A substrate is provided. A first mandrel and a plurality of second mandrels are formed on the substrate simultaneously. A plurality of spacers are respectively formed on sidewalls of the first mandrel and the second mandrels and followed by removing the... United Microelectronics Corp

09/14/17 / #20170263504

Method for fabricating semiconductor device

A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a plurality of fin shaped structures and an insulating layer. The substrate has a fin field-effect transistor (finFET) region, a first region, a second region and a third region. The first region, the second... United Microelectronics Corp

09/14/17 / #20170263597

Novel dummy gate technology to avoid shorting circuit

Semiconductor devices and method of manufacturing such semiconductor devices are provided for improved FinFET memory cells to avoid electric short often happened between metal contacts of a bit cell, where the meal contacts are positioned next to a dummy gate of a neighboring dummy edge cell. In one embodiment, during... United Microelectronics Corp

09/14/17 / #20170263608

Semiconductor device and forming the same

The present invention provides a semiconductor device and a method of forming the same. The semiconductor device includes a substrate, a first transistor and a second transistor. The first transistor and the second transistor are disposed on the substrate. The first transistor includes a first channel and a first work... United Microelectronics Corp

09/14/17 / #20170263730

Semiconductor process

A semiconductor process including the following steps is provided. An epitaxial layer is formed on a substrate. An oxide layer is formed on the epitaxial layer, wherein the oxide layer includes a chemical oxide layer, a high-temperature oxide (HTO) layer or a surface modification oxide layer. An ion implant process... United Microelectronics Corp

09/14/17 / #20170263732

Semiconductor device and fabricating the same

A semiconductor device preferably includes a substrate, a fin-shaped structure on the substrate, a buffer layer on the fin-shaped structure, and an epitaxial layer on the buffer layer. Preferably, the buffer layer is made of silicon germanium and including three or more than three elements. The buffer layer also includes... United Microelectronics Corp

09/14/17 / #20170263744

Method for fabricating a semiconductor device having gate structure with doped hard mask

A method for fabricating semiconductor device includes the steps of: providing a substrate having at least a gate structure thereon and an interlayer dielectric (ILD) layer surrounding the gate structure, wherein the gate structure comprises a hard mask thereon; forming a dielectric layer on the gate structure and the ILD... United Microelectronics Corp

09/07/17 / #20170256459

Method of fabricating semiconductor structure with self-aligned spacers

A method of fabricating a semiconductor with self-aligned spacer includes providing a substrate. At least two gate structures are disposed on the substrate. The substrate between two gate structures is exposed. A silicon oxide layer is formed to cover the exposed substrate. A nitride-containing material layer covers each gate structure... United Microelectronics Corp

09/07/17 / #20170256652

Oxide semiconductor device and manufacturing the same

An oxide semiconductor device and a method for manufacturing the same are provided in the present invention. The oxide semiconductor device includes a back gate, an oxide semiconductor film, a pair of source and drain electrodes, agate insulating film, a gate electrode on the oxide semiconductor film with the gate... United Microelectronics Corp








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