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United Microelectronics Corporation patents


Recent patent applications related to United Microelectronics Corporation. United Microelectronics Corporation is listed as an Agent/Assignee. Note: United Microelectronics Corporation may have other listings under different names/spellings. We're not affiliated with United Microelectronics Corporation, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "U" | United Microelectronics Corporation-related inventors


 new patent  Finfet with epitaxial layer having octagonal cross-section

A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first epitaxial layer adjacent to two sides of the gate structure; forming a patterned mask on the epitaxial layer; and using the patterned mask to remove part of the first epitaxial layer for forming a second epitaxial layer.. . ... United Microelectronics Corporation

 new patent  Method for forming recess within epitaxial layer

A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first recess adjacent to two sides of the gate structure; forming an epitaxial layer in the first recess; removing part of the epitaxial layer to forma second recess; and forming an interlayer dielectric (ild) layer on the gate structure and into the second recess.. . ... United Microelectronics Corporation

 new patent  Method for fabricating cap layer on an epitaxial layer

A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a gate structure is formed on the substrate. ... United Microelectronics Corporation

 new patent  Integrated circuit and method for manufacturing thereof

A method for manufacturing an integrated circuit includes following steps. A substrate including a memory region and a core region is provided. ... United Microelectronics Corporation

 new patent  Method of forming fin shape structure

A fin shaped structure and a method of forming the same. The method includes providing a substrate having a first fin structure and a second fin structure. ... United Microelectronics Corporation

 new patent  Semiconductor device and fabrication method thereof

A method for fabricating semiconductor device is disclosed. A substrate having a first transistor on a first region, a second transistor on a second region, a trench isolation region, a resistor-forming region is provided. ... United Microelectronics Corporation

 new patent  Method for filling patterns

A method for filling patterns includes the steps of: providing a substrate having a cell region defined thereon; forming main patterns on the substrate and within the cell region; and filling first dummy patterns adjacent to the main patterns. Preferably, each of the first dummy patterns comprises a first length along x-direction between 2 μm to 5 μm and a second length along y-direction between 3 μm to 5 μm.. ... United Microelectronics Corporation

 new patent  Semiconductor device and fabrication method thereof

A semiconductor device includes a semiconductor substrate comprising a mos transistor. A mems device is integrally constructed above the mos transistor. ... United Microelectronics Corporation

Field-effect transistor

A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. The gate structure includes a gate dielectric layer formed over the semiconductor substrate, a gate electrode formed over the gate dielectric layer, and a spacer formed on side surfaces of the gate dielectric layer and the gate electrode. ... United Microelectronics Corporation

Method of fabricating sti trench and sti structure

A method of fabricating an sti trench has a sidewall with two different slopes. The fabricating steps include providing a substrate with a patterned mask thereon. ... United Microelectronics Corporation

Semiconductor device

A semiconductor device comprises a fin shaped structure, a shallow trench isolation, a diffusion break structure and a gate electrode. The fin shaped structure is disposed on a substrate. ... United Microelectronics Corporation

Semiconductor device structure

A method for fabricating a semiconductor device structure is shown. A gate dielectric layer is formed on a substrate. ... United Microelectronics Corporation

Test key structure and method of measuring resistance of vias

The present invention provides a test key structure for measuring or simulating a target via array. The structure includes a substrate with a test region, a plurality of first conductive lines in the test region; a plurality of second conductive lines in the test region and on the first conductive lines, wherein the first conductive lines and the second conductive lines overlaps vertically in a plurality of target regions, and a plurality of vias disposed between the first conductive lines and the second conductive lines, wherein at least two vias vertically contact one of the first conductive lines and one of the second conductive lines. ... United Microelectronics Corporation

Method of forming semiconductor device

A method of forming a semiconductor device includes the following steps. A substrate is provided, and the substrate has a first region. ... United Microelectronics Corporation

05/31/18 / #20180151666

Method of fabricating metal-insulator-metal capacitor

A method of fabricating a metal-insulator-metal capacitor includes providing a dielectric layer. The dielectric layer is etched to form a first hole including a first convex profile bulging into the dielectric layer. ... United Microelectronics Corporation

05/31/18 / #20180151571

Layout of semiconductor transistor device

The present invention provides a layout of a semiconductor transistor device including a first and a second active area, a first and a second gate, and a metal line. The first active and the second active area are extended along a first direction. ... United Microelectronics Corporation

05/31/18 / #20180151555

Intra-metal capacitor and method of forming the same

An intra-metal capacitor is provided. The intra-metal capacitor is formed in a dielectric layer and comprising a first electrode and a second electrode, wherein the first electrode penetrate through the whole thickness of the dielectric layer, and the second electrode does not penetrate through the whole thickness of the dielectric layer.. ... United Microelectronics Corporation

05/31/18 / #20180151428

Conductive structure and method for manufacturing conductive structure

A conductive structure includes a substrate including a first dielectric layer formed thereon, at least a first opening formed in the first dielectric layer, a low resistive layer formed in the opening, and a first metal bulk formed on the lower resistive layer in the opening. The first metal bulk directly contacts a surface of the first low resistive layer. ... United Microelectronics Corporation

05/31/18 / #20180151371

Semiconductor device and fabrication method thereof

A semiconductor device includes first fin-shaped structures and second fin-shaped structures, which are separately disposed on a semiconductor substrate. Each of the first and second fin-shaped structures includes a base portion and a top portion protruding from the top portion. ... United Microelectronics Corporation

05/31/18 / #20180149978

Method for forming patterned structure

A method for forming a patterned structure includes following steps. First lines elongated in a first direction and second lines elongated in a second direction in a layout pattern are decomposed into two masks. ... United Microelectronics Corporation

05/24/18 / #20180145081

Static random access memory unit cell

The present invention provides a sram unit cell which includes a semiconductor substrate, six transistors, a first well, two first doped regions and two second doped regions. The transistors are disposed on the semiconductor substrate, and include a first gate line and a second gate line. ... United Microelectronics Corporation

05/24/18 / #20180144988

Semiconductor device and manufacturing method thereof

A semiconductor device includes a semiconductor substrate, a shallow trench isolation structure, gate electrodes, and a gate isolation structure. The semiconductor substrate includes fin structures, and each of the fin structures is elongated in a first direction. ... United Microelectronics Corporation

05/24/18 / #20180143529

Method of forming photomask

A method of forming a photomask is provided. A first layout pattern is first provided to a computer system and followed by generating an assist feature pattern by the computer system based on the first layout pattern and adding the assist feature pattern into the first layout pattern to form a second layout pattern. ... United Microelectronics Corporation

05/17/18 / #20180138316

Semiconductor device

A semiconductor device is provided in the present invention, which includes a substrate, an oxide-semiconductor layer, source/drain regions, a first dielectric layer covering on the oxide-semiconductor layer and the source/drain regions, a second gate between the two source/drain regions and partially covering the oxide-semiconductor layer, and a charge storage structure between the first gate electrode and the oxide-semiconductor layer.. . ... United Microelectronics Corporation

05/17/18 / #20180138263

Semiconductor structure and method for forming the same

A semiconductor structure includes a capacitor. The capacitor includes a bottom electrode, a first high-k dielectric layer, a second high-k dielectric layer and a top electrode. ... United Microelectronics Corporation

05/17/18 / #20180138180

Semiconductor device and method for fabricating the same

A semiconductor device includes a semiconductor substrate having a first region and a second region, a plurality of first semiconductor fins in the first region, a plurality of second semiconductor fins in the second region, a first solid-state dopant source layer within the first region on the semiconductor substrate, a first insulating buffer layer on the first solid-state dopant source layer, a second solid-state dopant source layer within the second region on the semiconductor substrate, a second insulating buffer layer on the second solid-state dopant source layer and on the first insulating buffer layer, a first fin bump in the first region, and a second fin bump in the second region. The first fin bump includes a first sidewall spacer and the second fin bump comprises a second sidewall spacer. ... United Microelectronics Corporation

05/17/18 / #20180138178

Semiconductor device including barrier layer and manufacturing method thereof

A manufacturing method of a semiconductor device includes the following steps. A barrier layer is formed in a first region and a second region of a semiconductor substrate. ... United Microelectronics Corporation

05/17/18 / #20180138167

Electrostatic discharge (esd) protection device and method fabricating the esd protection device

An electrostatic discharge (esd) device includes a gate structure, disposed on a substrate. A drain doped region of a first conductive type is in the substrate, adjacent to a first side of the gate structure, wherein the drain doped region has a first impurity concentration. ... United Microelectronics Corporation

05/17/18 / #20180138166

Semiconductor device for electrostatic discharge protection

A semiconductor device for esd protection, includes a drain region, a first doped region, a second doped region and a source region. The drain region is disposed in a substrate at a first side of a gate and the drain region has a first conductivity type. ... United Microelectronics Corporation

05/17/18 / #20180138125

Conductive structure, layout structure including conductive structure, and method for manufacturing conductive structure

A layout structure including a conductive structure is provided. The layout structure includes a dielectric layer formed on a substrate and a conductive structure formed in the dielectric layer. ... United Microelectronics Corporation

05/17/18 / #20180138088

Method of forming semiconductor device

A semiconductor device and method of forming the same, the semiconductor device includes a first and second fin shaped structures, a first and second gate structures and a first and second plugs. The first and second fin shaped structures are disposed on a first region and a second region of a substrate and the first and second gate structure are disposed across the first and second fin shaped structures, respectively. ... United Microelectronics Corporation

05/10/18 / #20180130871

Capacitor structure and manufacturing method thereof

The present invention provides a capacitor structure, including a bottom plate and a top plate, wherein the top plate has a first sidewall, and wherein an area of the top plate is less than an area of the bottom plate. The capacitor structure further includes a dielectric layer in between the bottom plate and the top plate, the dielectric layer having a second sidewall, wherein the first sidewall is aligned with the second sidewall, and at least one sidewall spacer placed against the first sidewall of the top plate and the second sidewall of the dielectric layer, and overlaying a portion of the bottom plate.. ... United Microelectronics Corporation

05/10/18 / #20180130753

Semiconductor device

A semiconductor device includes a substrate including a plurality of chip areas and a scribe line defined thereon, and a mark pattern disposed in the scribe line. The mark pattern includes a plurality of unit cells immediately adjacent to each other, and each unit cell includes a first active region, a second active region isolated from the first active region, a plurality of first gate structures extending along a first direction and arranged along a second direction perpendicular to the first direction, and a plurality of first conductive structures. ... United Microelectronics Corporation

05/10/18 / #20180130742

Method for fabricating semiconductor device having a patterned metal layer embedded in an interlayer dielectric layer

A method for fabricating semiconductor device first includes providing a substrate and a shallow trench isolation (sti) in the substrate, in which the substrate includes a first metal gate and a second metal gate thereon, a first hard mask on the first metal gate and a second hard mask on the second metal gate, and a first interlayer dielectric (ild) layer around the first metal gate and the second metal gate. Next, the first hard mask and the second hard mask as mask are utilized to remove part of the first ild layer for forming a recess, and a patterned metal layer is formed in the recess and on the sti.. ... United Microelectronics Corporation

05/03/18 / #20180122897

Semiconductor device and method for fabricating the same

A method for fabricating semiconductor device includes the steps of first providing a substrate, forming a gate structure on the substrate, forming a hard mask on the substrate and the gate structure, patterning the hard mask to form trenches exposing part of the substrate, and forming raised epitaxial layers in the trenches. Preferably, the gate structure is extended along a first direction on the substrate and the raised epitaxial layers are elongated along a second direction adjacent to two sides of the gate structure.. ... United Microelectronics Corporation

05/03/18 / #20180122707

Method for forming semiconductor device

The present invention provides a method for forming a semiconductor device, comprising the following steps: firstly, a substrate is provided, having a nmos region and a pmos region defined thereon, next, a gate structure is formed on the substrate within the nmos region, and a disposal spacer is formed on two sides of the gate structure, afterwards, a mask layer is formed on the pmos region to expose the nmos region, next, a recess is formed on two sides of the gate structure spaced from the gate structure by the disposal spacer within the nmos region, the disposal spacer is then removed after the recess is formed, and an epitaxial layer is formed into the recess.. . ... United Microelectronics Corporation

05/03/18 / #20180122705

Method for fabricating semiconductor device

First, a substrate having a first region and a second region is provided, a first gate structure is formed on the first region and a second gate structure is formed on the second region, an interlayer dielectric (ild) layer is formed around the first gate structure and the second gate structure, and the first gate structure and the second gate structure are removed to expose the substrate on the first region and the second region. Next, part of the substrate on the first region is removed to form a first recess and part of the substrate on the second region is removed to form a second recess, in which the depths of the first recess and the second recess are different. ... United Microelectronics Corporation

05/03/18 / #20180122693

Method for forming semiconductor structure

A method for forming a semiconductor structure is provided, including the following steps. A first dielectric layer is formed on a substrate. ... United Microelectronics Corporation

05/03/18 / #20180120693

Method for correcting layout pattern

A method of correcting a layout pattern is provided in the present invention. The method includes the following steps. ... United Microelectronics Corporation

04/19/18 / #20180108837

Semiconductor device having memory cell structure and method of manufacturing the same

A semiconductor device is provided, including a lower conducting layer formed above a substrate, an upper conducting layer, and a memory cell structure formed on the lower conducting layer (such as formed between the lower and upper conducting layers). The memory cell structure includes a bottom electrode formed on the lower conducting layer and electrically connected to the lower conducting layer, a transitional metal oxide (tmo) layer formed on the bottom electrode, a tmo sidewall oxides formed at sidewalls of the tmo layer, a top electrode formed on the tmo layer, and spacers formed on the bottom electrode. ... United Microelectronics Corporation

04/19/18 / #20180108744

Method of manufacturing semiconductor memory device

A method of manufacturing a semiconductor memory device and a semiconductor memory cell thereof are provided. The semiconductor memory device formed from the manufacturing method includes a plurality of semiconductor memory cells and an electric isolating structure. ... United Microelectronics Corporation

04/19/18 / #20180108656

Asymmetrical fin structure and method of fabricating the same

An asymmetrical fin structure includes a substrate. The substrate includes a top surface. ... United Microelectronics Corporation

04/19/18 / #20180108570

Method for manufacturing fins

A method for manufacturing fins includes following steps. A substrate including a plurality of fins formed thereon is provided. ... United Microelectronics Corporation

04/19/18 / #20180108528

Gate oxide structure and method for fabricating the same

A method for forming a gate oxide layer on a substrate is provided, in which a region of the substrate is defined out by a shallow trench isolation (sti) structure. An oxide layer covers over the substrate and a mask layer with an opening to expose oxide layer corresponding to the region with an interface edge of the sti structure. ... United Microelectronics Corporation

04/12/18 / #20180102434

Vertical channel oxide semiconductor field effect transistor and method for fabricating the same

A semiconductor device includes: a channel layer surrounded by a source layer; a first dielectric layer around the source layer; a gate layer around the channel layer and on the source layer; a first oxide semiconductor layer between the gate layer and the channel layer; a second oxide semiconductor layer between the gate layer and the drain layer; a second gate dielectric layer between the second oxide semiconductor layer and the drain layer; a drain layer on the gate layer and around the channel layer; and a second dielectric layer around the drain layer.. . ... United Microelectronics Corporation

04/12/18 / #20180102411

Semiconductor device with single-crystal nanowire finfet

A semiconductor device and a method of forming the same, the semiconductor device includes a single crystal substrate, a source/drain structure and a nanowire structure. The source/drain structure is disposed on and contacts with the substrate. ... United Microelectronics Corporation

04/12/18 / #20180102408

Semiconductor device and method of forming the same

A method of forming a semiconductor device is provided including the following steps. A substrate having a first voltage area and a second voltage area is provided. ... United Microelectronics Corporation

04/05/18 / #20180097110

Method for manufacturing a semiconductor structure

A method for manufacturing a semiconductor structure comprises the following steps. First, a recess is formed in a substrate. ... United Microelectronics Corporation

04/05/18 / #20180097109

Semiconductor device

The present invention provides a semiconductor device, including a substrate, two gate structures disposed on a channel region of the substrate, an epitaxial layer disposed in the substrate between two gate structures, a first dislocation disposed in the epitaxial layer, wherein the profile of the first dislocation has at least two non-parallel slanting lines, and a second dislocation disposed adjacent to a top surface of the epitaxial layer, and the profile of the second dislocation has at least two non-parallel slanting lines.. . ... United Microelectronics Corporation

04/05/18 / #20180097104

High-voltage metal-oxide-semiconductor transistor and fabrication method thereof

A high-voltage mos transistor includes a semiconductor substrate, a gate oxide layer on the semiconductor substrate, a gate on the gate oxide layer, a spacer covering a sidewall of the gate, a source on one side of the gate, and a drain on the other side of the gate. The gate includes at least a first discrete segment and a second discrete segment. ... United Microelectronics Corporation

04/05/18 / #20180097098

Method for fabricating finfet

The present invention provides a method of fabricating a finfet, comprising the following steps: first, a substrate having a plurality of fin structures disposed thereon is provided, an sti disposed between adjacent fin structures and a gate structure crossing the fin structures. Next, the fin structures not covered by the gate structure and the sti not covered by the gate structure are etched, until the sti is removed entirely and a first recessed and protruding profile is formed on the substrate, wherein the first recessed and protruding profile includes a first recess and a plurality of second recesses, and the position of the second recesses corresponds to the position of the fin structures, and an epitaxial layer is formed on the first recessed and protruding profile.. ... United Microelectronics Corporation

04/05/18 / #20180096995

Finfet structure and fabricating method of gate structure

A method of forming a gate structure on a fin structure includes the steps of providing a fin structure covered by a first silicon oxide layer, a silicon nitride layer, a gate material and a cap material in sequence, wherein the silicon nitride layer contacts the first silicon oxide layer. Later, the cap material is patterned to form a first cap layer and the gate material is patterned to form a first gate electrode by taking the silicon nitride layer as an etching stop layer. ... United Microelectronics Corporation

03/22/18 / #20180083141

Semiconductor device

A semiconductor device includes a substrate, an electrode layer disposed on the substrate, and a tri-layered gate-control stack sandwiched between the substrate and the electrode layer. The tri-layered gate-control stack includes a ferroelectric layer disposed on the substrate, a mid-gap metal layer sandwiched between the ferroelectric layer and the substrate, and an anti-ferroelectric layer. ... United Microelectronics Corporation

03/15/18 / #20180076500

Microstrip line structure and method for fabricating the same

A method for fabricating microstrip line structure is disclosed. First, a substrate is provided, ground patterns are formed on the substrate, an interlayer dielectric (ild) layer is formed on the ground patterns, contact plugs are formed in the ild layer, a ground plate is formed on the ild layer, and a signal line is formed on the ground plate. ... United Microelectronics Corporation

03/15/18 / #20180076327

Semiconductor device and method for fabricating the same

A semiconductor device includes: a gate structure extending along a first direction on a substrate, in which the gate structure includes a first edge and a second edge extending along the first direction; a first doped region adjacent to one side of the gate structure, in which the first doped region includes a third edge and a fourth edge extending along the first direction; a second doped region adjacent to another side of the gate structure, in which the second doped region comprises a fifth edge and a sixth edge extending along the first direction; a first fin-shaped structure extending from the second edge of the gate structure toward the third edge of the first doped region; and a second fin-shaped structure extending from the first edge of the gate structure toward the sixth edge of the second doped region.. . ... United Microelectronics Corporation

03/15/18 / #20180076207

Mask rom and process for fabricating the same

A mask rom is shown, including first resistors as a first part of memory cells, second resistors as a second part of memory cells, and contact plugs. Each first resistor includes: an undoped first poly-si layer including a convex portion and a step structure with a step height adjacent to the convex portion, a spacer on the sidewall of the step structure, and a first silicide layer on the first poly-si layer and being divided apart by the spacer. ... United Microelectronics Corporation

03/08/18 / #20180069089

Method of forming semiconductor structure

A method of forming a semiconductor structure is disclosed. A substrate having a first area and a second area is provided, wherein a first surface of the first area is lower than a second surface of the second area. ... United Microelectronics Corporation

03/08/18 / #20180068998

Bipolar junction transistor

A bipolar junction transistor (bjt) includes a semiconductor substrate and a first isolation structure. The semiconductor substrate includes a first fin structure disposed in an emitter region, a second fin structure disposed in a base region, and a third fin structure disposed in a collector region. ... United Microelectronics Corporation

03/08/18 / #20180068951

Semiconductor device and method for fabricating the same

A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a first gate structure is formed on the substrate, a first spacer is formed around the first gate structure, and an interlayer dielectric (ild) layer is formed around the first spacer. ... United Microelectronics Corporation

03/08/18 / #20180067241

Color filter device and forming method thereof

A color filter device includes a dielectric layer, a passivation layer, a plurality of color filters and an inorganic film. The dielectric layer is disposed on a substrate, wherein the substrate has a light sensing area and a periphery area, and the periphery area is beside the light sensing area. ... United Microelectronics Corporation

03/01/18 / #20180061963

Fabricating method of semiconductor structure

A fabricating method of a semiconductor structure includes the following steps. A gate material layer is formed on a semiconductor substrate. ... United Microelectronics Corporation

03/01/18 / #20180061950

Transistor device with threshold voltage adjusted by body effect

A transistor device including a substrate, a gate structure, a first doped region, a second doped region and a body region is provided. The gate structure is disposed on the substrate. ... United Microelectronics Corporation

03/01/18 / #20180061752

Semiconductor device and method for fabricating the same

A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a capacitor is formed on the substrate and a hard mask on the capacitor, in which the capacitor includes a bottom electrode, a capacitor dielectric layer, and a top electrode. ... United Microelectronics Corporation

03/01/18 / #20180061656

Method for forming semiconductor structure

A method for forming a semiconductor structure includes following steps. A substrate is provided, and a semiconductor layer is formed on the substrate. ... United Microelectronics Corporation

03/01/18 / #20180057354

Semiconductor sensor and method of manufacturing the same

A semiconductor sensor, comprising a gas-sensing device and an integrated circuit electrically connected to the gas-sensing device, is provided. The gas-sensing device includes a substrate having a sensing area and an interconnection area in the vicinity of the sensing area, an inter-metal dielectric (imd) layer formed above the substrate in the sensing area and in the interconnection area, and an interconnect structure formed in the interconnection area. ... United Microelectronics Corporation

02/22/18 / #20180053826

Semiconductor device and method for fabricating the same

A semiconductor device comprises a semiconductor substrate and a semiconductor fin. The semiconductor substrate has an upper surface and a recess extending downwards into the semiconductor substrate from the upper surface. ... United Microelectronics Corporation

02/22/18 / #20180053771

Semiconductor structure and method for fabricating the same

A method for fabricating a semiconductor structure is shown. A first gate of a first device and a second gate of a second device are formed over a semiconductor substrate. ... United Microelectronics Corporation

02/22/18 / #20180053761

Semiconductor device and manufacturing method thereof

A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate including at least one fin structure is provided. ... United Microelectronics Corporation

02/22/18 / #20180053729

Alignment mark structure with dummy pattern

An alignment mark structure including a substrate, an alignment mark and at least one dummy pattern is provided. The alignment mark is disposed on the substrate. ... United Microelectronics Corporation

02/15/18 / #20180047848

Method of fabricating semiconductor device

A semiconductor device and a method of fabricating the same, the semiconductor device includes a plurality of fin shaped structures, a trench, a spacing layer and a dummy gate structure. The fin shaped structures are disposed on a substrate. ... United Microelectronics Corporation

02/15/18 / #20180047842

Semiconductor structure and method for forming the same

A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a substrate, at least a first cell, and at least a second cell. ... United Microelectronics Corporation

02/15/18 / #20180047810

Semiconductor device and method for fabricating the same

A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a gate structure is formed on the substrate, a recess is formed adjacent to the gate structure, a buffer layer is formed in the recess, and an epitaxial layer is formed on the buffer layer. ... United Microelectronics Corporation

02/15/18 / #20180047809

Bipolar junction transistor device and method for fabricating the same

A bipolar junction transistor (bjt) device includes a semiconductor substrate, a first doping region with a first conductivity, a second doping region with a second conductivity, a third doping region with the first conductivity, at least one stacked block and a conductive contact. The first doping region is formed in the semiconductor substrate. ... United Microelectronics Corporation

02/15/18 / #20180047635

Semiconductor device and manufacturing method thereof

A semiconductor device includes a semiconductor substrate, an isolation structure, and a spacer. The semiconductor substrate includes at least one fin structure. ... United Microelectronics Corporation

02/08/18 / #20180040694

Semiconductor structure and method of forming the same

A semiconductor structure and method of forming the same. The semiconductor structure includes a fin structure formed on a substrate and an isolation structure formed therein. ... United Microelectronics Corporation

02/08/18 / #20180040693

Method for fabricating shallow trench isolation between fin-shaped structures

A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a plurality of fin-shaped structures and a first shallow trench isolation (sti) around the fin-shaped structures on the first region and the second region; forming a patterned hard mask on the second region; removing the fin-shaped structures and the first sti from the first region; forming a second sti on the first region; removing the patterned hard mask; and forming a gate structure on the second sti.. . ... United Microelectronics Corporation

02/08/18 / #20180040558

Semiconductor device and method of fabricating the same

A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a substrate, a plurality of gates and a plurality of plugs. ... United Microelectronics Corporation

02/01/18 / #20180033961

Semiconductor device and manufacturing method thereof

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a bottom metal layer, a resistive random access memory (reram) cell structure, and an upper metal layer. ... United Microelectronics Corporation

02/01/18 / #20180033891

Oxide semiconductor device

An oxide semiconductor device includes an oxide semiconductor transistor and a protection wall. The protection wall extends in a vertical direction and surrounds the oxide semiconductor transistor. ... United Microelectronics Corporation

02/01/18 / #20180033874

Method of fabricating a semiconductor device

A method of fabricating a semiconductor device is disclosed. A substrate is provided. ... United Microelectronics Corporation

02/01/18 / #20180033636

Method of fabricating a semiconductor structure

A method of fabricating a semiconductor structure is provided. A substrate surface is provided and a first layer is disposed on the substrate surface. ... United Microelectronics Corporation

02/01/18 / #20180033633

Method for planarizing material layer

A method for planarizing a silicon layer includes providing a silicon layer having at least one recess therein. Next, a photoresist layer is formed to cover the silicon layer and fill up the recess. ... United Microelectronics Corporation

01/25/18 / #20180027337

Piezoresistive microphone and method of fabricating the same

A piezoresistive microphone includes a substrate, an insulating layer, and a polysilicon layer. A first pattern is disposed within the polysilicon layer. ... United Microelectronics Corporation

01/18/18 / #20180019341

Tunneling transistor and method of fabricating the same

A tunneling transistor and a method of fabricating the same, the tunneling transistor includes a fin shaped structure, a source structure and a drain structure, and a gate structure. The fin shaped structure is disposed in a substrate, and the source structure and the drain structure are disposed the fin shaped structure, wherein an entirety of the source structure and an entirety of the drain structure being of complementary conductivity types with respect to one another and having different materials. ... United Microelectronics Corporation

01/18/18 / #20180019324

Semiconductor device having silicon-germanium layer on fin and method for manufacturing the same

A semiconductor device is provided, including a substrate with an isolation layer formed thereon, wherein the substrate has a fin protruding up through the isolation layer to form a top surface and a pair of lateral sidewalls of the fin above the isolation layer; a silicon-germanium (sige) layer epitaxially grown on the top surface and the lateral sidewalls of the fin; and a gate stack formed on the isolation layer and across the fin, wherein the fin and the gate stack respectively extend along a first direction and a second direction. The sige layer formed on the top surface has a first thickness, the sige layer formed on said lateral sidewall has a second thickness, and a ratio of the first thickness to the second thickness is in a range of 1:10 to 1:30.. ... United Microelectronics Corporation

01/18/18 / #20180019205

Semiconductor device and method for fabricating the same

A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a first dielectric layer is formed on the substrate, in which a first conductor is embedded within the first dielectric layer. ... United Microelectronics Corporation

01/11/18 / #20180012992

Semiconductor device and method of forming the same

A semiconductor device and a forming method thereof, the semiconductor device includes a first and a second wells, a source region, a drain region, two gate structures and at least one doping region. The first well with a first conductive type is disposed in a substrate, and the source region is disposed in the first well. ... United Microelectronics Corporation

01/11/18 / #20180012976

Semiconductor structure

A method for making a semiconductor device. A substrate having a fin structure is provided. ... United Microelectronics Corporation

01/11/18 / #20180012975

Method of fabricating semiconductor device

A semiconductor device and a method of forming the same, the semiconductor device includes a fin shaped structure, agate structure, an epitaxial layer, an interlayer dielectric layer, a first plug and a protection layer. The fin shaped structure is disposed on a substrate, and the gate structure is across the fin shaped structure. ... United Microelectronics Corporation

01/11/18 / #20180012971

Planar field effect transistor

A fin-shaped field effect transistor includes a substrate and a gate. The substrate includes an active area, where the active area includes a fin structure having at least an extension part protruding from the fin structure. ... United Microelectronics Corporation

01/11/18 / #20180012899

Integrated circuit and method for manufacturing thereof

A method for manufacturing an integrated circuit includes following steps. A substrate including a memory region and a core region is provided. ... United Microelectronics Corporation

01/11/18 / #20180012882

Semiconductor structure for electrostatic discharge protection

A semiconductor structure for electrostatic discharge (esd) protection is provided. The semiconductor structure includes a substrate, a first doped well, a source doped region, a drain doped region, and a gate structure. ... United Microelectronics Corporation

01/11/18 / #20180012808

Semiconductor device and fabrication method thereof

A method for fabricating a semiconductor device is provided. A substrate having a dummy gate thereon is prepared. ... United Microelectronics Corporation

01/11/18 / #20180012793

Method for fabricating a semiconductor device

A method for fabricating semiconductor device includes the steps of: forming a dielectric layer on a substrate; forming a stop layer between the dielectric layer and the substrate, wherein the stop layer contacts the substrate directly and the dielectric layer covers the top surface of the stop layer; forming an opening in the dielectric layer, wherein the dielectric layer comprises a damaged layer adjacent to the opening; forming a dielectric protective layer in the opening; forming a metal layer in the opening; removing the damaged layer and the dielectric protective layer to form a void, wherein the void exposes a top surface of the substrate; and forming a cap layer on and covering the dielectric layer, the void, and the metal layer.. . ... United Microelectronics Corporation

01/11/18 / #20180012772

Method of planarizing substrate surface

A method of planarizing a substrate surface is disclosed. A substrate having a major surface of a material layer is provided. ... United Microelectronics Corporation

01/11/18 / #20180012771

Method of planarizing substrate surface

A method of planarizing a substrate surface is disclosed. A substrate having a major surface of a material layer is provided. ... United Microelectronics Corporation

01/04/18 / #20180006133

Device with reinforced metal gate spacer and method of fabricating

A semiconductor device with reinforced gate spacers and a method of fabricating the same. The semiconductor device includes low-k dielectric gate spacers adjacent to a gate structure. ... United Microelectronics Corporation

01/04/18 / #20180006129

Transistor and manufacturing method thereof

A transistor includes a semiconductor channel layer, a gate structure, a gate insulation layer, an internal electrode, and a ferroelectric material layer. The gate structure is disposed on the semiconductor channel layer. ... United Microelectronics Corporation

01/04/18 / #20180006040

Static random-access memory (sram) cell array and forming method thereof

A static random-access memory (sram) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein the fin structures include a plurality of active fins and a plurality of dummy fins, each pg (pass-gate) finfet shares at least one of the active fins with a pd (pull-down) finfet, and at least one dummy fin is disposed between the two active fins having two adjacent pu (pull-up) finfets thereover in a static random-access memory cell. ... United Microelectronics Corporation

01/04/18 / #20180006038

Layout pattern for static random access memory

A layout pattern of a static random access memory includes a pull-up device, a first pull-down device, a second pull-up device, a second pull-down device, a first pass gate device, a second pass gate device, a third pass gate device and a fourth pass gate device disposed on a substrate. A plurality of fin structures is disposed on the substrate, the fin structures including at least one first fin structure and at least one second fin structure. ... United Microelectronics Corporation

01/04/18 / #20180005835

Memory device

Provided is a memory device including a first gate, a second gate and an inter-gate dielectric layer. The first gate is buried in a substrate. ... United Microelectronics Corporation

12/28/17 / #20170373191

Semiconductor device and method for fabricating the same

A method for fabricating semiconductor device is disclosed. First, a fin-shaped structure is formed on a substrate, a first liner is formed on the substrate and the fin-shaped structure, a second liner is formed on the first liner, part of the second liner and part of the first liner are removed to expose a top surface of the fin-shaped structure, part of the first liner between the fin-shaped structure and the second liner is removed to form a recess, and an epitaxial layer is formed in the recess.. ... United Microelectronics Corporation

12/28/17 / #20170373073

Static random-access memory (sram) cell array

A static random-access memory (sram) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein the fin structures include a plurality of active fins and a plurality of dummy fins, each pg (pass-gate) finfet shares at least one of the active fins with a pd (pull-down) finfet, and at least one dummy fin is disposed between the two active fins having two adjacent pull-up finfets thereover in a static random-access memory cell. ... United Microelectronics Corporation

12/21/17 / #20170365703

Field-effect transistor and method of making the same

A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. A vertically extending portion of the epitaxial structure extends vertically above a top surface of the semiconductor substrate in an area adjacent the gate structure. ... United Microelectronics Corporation

12/21/17 / #20170365675

Dummy pattern arrangement and method of arranging dummy patterns

A dummy pattern arrangement and a method of arranging dummy patterns are provided in the present invention. The dummy pattern arrangement includes a substrate with a dummy region, a plurality of first base dummy cells arranged spaced apart from each other along a first direction in the dummy region, and two first edge dummy cells arranged respectively at two opposite sides of the first base dummy cells along the first direction in the dummy region.. ... United Microelectronics Corporation

12/21/17 / #20170365510

Method of forming opening pattern

A method of forming an opening pattern including the following steps is provided. An ultra low dielectric constant layer, a dielectric hard mask layer and a patterned metal hard mask layer are sequentially formed on a substrate. ... United Microelectronics Corporation

12/21/17 / #20170362081

Mems structure and method of fabricating the same

A method of fabricating a mems structure includes providing a substrate comprising a logic element region and a mems region. Next, a logic element is formed within the logic element region. ... United Microelectronics Corporation

12/14/17 / #20170358684

Semiconductor device

A semiconductor device includes a substrate, an electrode layer disposed on the substrate, and a tri-layered gate-control stack sandwiched between the substrate and the electrode layer. The tri-layered gate-control stack includes a ferroelectric layer disposed on the substrate, a mid-gap metal layer sandwiched between the ferroelectric layer and the substrate, and an anti-ferroelectric layer. ... United Microelectronics Corporation

12/14/17 / #20170358582

Semiconductor memory device and semiconductor memory array comprising the same

A semiconductor array, the semiconductor memory array includes bit lines, word lines and memory cells. The bit lines are arranged in parallel in a first direction, and the word lines are arranged in parallel in a second direction which is different from the first direction. ... United Microelectronics Corporation

12/14/17 / #20170358491

Semiconductor transistor device and fabrication method thereof

A semiconductor transistor device includes a substrate having an active area and a trench isolation region surrounding the active area, a gate oxide layer, a gate, a spacer on a sidewall of the gate, a doping region on one side of the gate, an insulating cap layer covering the gate, the spacer and the doping region, and a redistributed contact layer (rcl) on the insulating cap layer. The rcl extends from the active area to the trench isolation region. ... United Microelectronics Corporation

12/14/17 / #20170358455

Method of forming fin-shaped structure

A fin-shaped structure includes a substrate having a first fin-shaped structure located in a first area and a second fin-shaped structure located in a second area, wherein the second fin-shaped structure includes a ladder-shaped cross-sectional profile part. The present invention also provides two methods of forming this fin-shaped structure. ... United Microelectronics Corporation

12/07/17 / #20170352736

Semiconductor process

A fin-shaped field effect transistor includes a substrate and a gate. The substrate includes an active area, where the active area includes a fin structure having at least an extension part protruding from the fin structure. ... United Microelectronics Corporation

12/07/17 / #20170352541

Method for fabricating a fin field effect transistor (finfet)

The invention provides a method for fabricating a fin field effect transistor (finfet), comprising: providing a substrate having a logic region and a large region; forming a plurality of fin structures in the logic region by removing a portion of the substrate in the logic region; forming an oxide layer on the substrate filling in-between the fin structures in the logic region; forming an first epitaxial structure in the large region by removing a portion of the substrate in the large region; exposing a portion of the fin structures and a portion of the epitaxial structure by removing a portion of the oxide layer; and forming a gate electrode on portions of the fin structures.. . ... United Microelectronics Corporation

11/30/17 / #20170345938

Bottom-up epitaxy growth on air-gap buffer

A fin structure for a semiconductor device, such as a finfet structure, has first and second semiconductor layers and an air gap between the layers. The second semiconductor layer includes a recessed portion, the air gap is located in the recessed portion, and the recessed portion has an upwardly-opening acute angle in the range from about 10° to about 55°. ... United Microelectronics Corporation

11/30/17 / #20170345937

Method for forming semiconductor structure

A method for manufacturing a semiconductor structure includes the following steps. First, a semiconductor substrate including a first semiconductor material is provided. ... United Microelectronics Corporation

11/30/17 / #20170345926

High-voltage metal-oxide-semiconductor transistor and fabrication method thereof

A high-voltage mos transistor includes a semiconductor substrate, a gate oxide layer on the semiconductor substrate, a gate on the gate oxide layer, a spacer covering a sidewall of the gate, a source on one side of the gate, and a drain on the other side of the gate. The gate includes at least a first discrete segment and a second discrete segment. ... United Microelectronics Corporation

11/30/17 / #20170345819

Semiconductor device having gate structure with reduced threshold voltage and method for manufacturing the same

A semiconductor device is provided, including: a substrate having a first area and a second area; several first gate structures formed at the first area, and at least one of the first gate structures including a first hardmask on a first gate, and the first gate structure having a first gate length; several second gate structures formed at the second area, and at least one of the second gate structures including a second hardmask on a second gate, and the second gate structure having a second gate length. The first gate length is smaller than the second gate length, and the first hardmask contains at least a portion of nitrogen (n2)-based silicon nitride (sin) which is free of oh concentration.. ... United Microelectronics Corporation

11/30/17 / #20170345720

Method and apparatus for controlling voltage of doped well in substrate

A method for controlling voltage of a doped well in a substrate is provided. The substrate and the doped well are in different conductive type. ... United Microelectronics Corporation

11/23/17 / #20170338351

Semiconductor device

A semiconductor device is provided in the present invention, which includes a substrate, an oxide-semiconductor layer, source/drain regions, a dielectric layer, a first gate electrode, a second gate electrode and a charge storage structure. The oxide-semiconductor layer is disposed on the first gate electrode on the substrate. ... United Microelectronics Corporation

11/23/17 / #20170338327

Semiconductor device and manufacturing method thereof

A semiconductor device and a manufacturing method thereof, the semiconductor device includes two gate structures and an epitaxial structure. The two gate structures are disposed on a substrate. ... United Microelectronics Corporation

11/23/17 / #20170338239

Semiconductor structure and method for manufacturing the same

A semiconductor structure includes a substrate and a plurality of memory cells disposed on the substrate. Each memory cell includes a gate structure. ... United Microelectronics Corporation

11/23/17 / #20170338227

Semiconductor device with metal gates

A semiconductor device includes at least a substrate, fin-shaped structures, a protection layer, epitaxial layers, and a gate electrode. The fin-shaped structures are disposed in a first region and a second region of the substrate. ... United Microelectronics Corporation

11/16/17 / #20170330956

Method for fabricating semiconductor device

A method for fabricating semiconductor device includes the steps of: providing a substrate, wherein the substrate comprises a first region and a second region; forming a high-k dielectric layer on the first region and the second region; forming a first bottom barrier metal (bbm) layer on the high-k dielectric layer of the first region and the second region; forming a stop layer on the first region and the second region; removing the stop layer on the second region; and forming a second bbm layer on the first region and the second region.. . ... United Microelectronics Corporation

11/16/17 / #20170330954

Semiconductor device and method for fabricating the same

A semiconductor device includes an interfacial layer on a substrate and agate structure on the interfacial layer. Preferably, the gate structure includes a patterned high-k dielectric layer, the patterned high-k dielectric layer comprises a metal oxide layer, and a horizontal direction width of the patterned high-k dielectric layer and a horizontal direction width of the interfacial layer are different. ... United Microelectronics Corporation

11/16/17 / #20170330952

Semiconductor device and method of forming the same

A semiconductor device and a method of forming the same, the semiconductor device include a substrate, and a first gate structure and a second gate structure disposed on the substrate. The first gate structure includes a barrier layer, a first work function layer, a second work function layer and a conductive layer stacked one over another on the substrate. ... United Microelectronics Corporation

11/16/17 / #20170330948

Metal-oxide-semiconductor transistor and method of forming gate layout

A method of forming a gate layout includes providing a gate layout design diagram comprising at least one gate pattern, disposing at least one insulating plug pattern in the gate pattern for producing a modified gate layout in a case where any one of a length and a width of the gate pattern is greater than or equal to a predetermined size, and outputting and manufacturing the modified gate layout onto a photomask. The predetermined size is determined by a process ability limit, and the process ability limit is a smallest gate size causing gate dishing when a chemical mechanical polishing process is performed to a gate.. ... United Microelectronics Corporation

11/16/17 / #20170330947

Metal-oxide-semiconductor transistor and method of forming gate layout

A metal-oxide semiconductor transistor includes a substrate, a gate insulating layer disposed on a surface of the substrate, and a metal gate disposed on the gate insulating layer, wherein at least one of the length or the width of the metal gate is greater than or equal to approximately 320 nanometers, and the metal gate has at least one plug hole. The metal-oxide semiconductor transistor further includes at least one insulating plug disposed in the plug hole and two diffusion regions disposed respectively at two sides of the metal gate in the substrate.. ... United Microelectronics Corporation

11/16/17 / #20170330937

Manufacturing method of semiconductor device

A semiconductor device includes a substrate including a plurality of transistor devices formed thereon, at least an epitaxial structure formed in between the transistor devices, and a tri-layered structure formed on the epitaxial structure. The epitaxial structure includes a first semiconductor material and a second semiconductor material, and a lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. ... United Microelectronics Corporation

11/16/17 / #20170330820

Method for fabrication semiconductor device

A method for is used for forming a semiconductor device. The method includes forming an ild layer on a substrate and a buffer layer on the ild layer, wherein at least one contact is formed in the ild layer; forming an opening through the buffer layer, the ild layer, and the substrate; forming a liner structure layer over the substrate, wherein an exposed surface of the opening is covered by the liner structure layer; depositing a conductive material over the substrate to fill the opening; performing a polishing process, to polish over the substrate and stop at the buffer layer, wherein the liner structure layer and the conductive material remaining in the opening form a conductive via; performing an etching back process, to remove the buffer layer and expose the ild layer, wherein a top portion of the conductive via is also exposed and higher than the ild layer.. ... United Microelectronics Corporation

11/16/17 / #20170330742

Method of forming semiconductor device

A semiconductor device and a method of forming the same, the semiconductor device includes fin shaped structures and a recessed insulating layer. The fin shaped structures are disposed on a substrate. ... United Microelectronics Corporation

11/16/17 / #20170328949

Semiconductor structure and testing method using the same

A semiconductor structure includes at least two via chains. Each via chain includes at least one first conductive component, at least one second conductive component and at least one via. ... United Microelectronics Corporation

11/09/17 / #20170323950

Semiconductor process

A semiconductor process is described. A silicon-phosphorus (sip) epitaxial layer is formed serving as a source/drain (s/d) region. ... United Microelectronics Corporation

11/09/17 / #20170323894

Layout pattern for static random access memory

A layout pattern of a static random access memory includes a pull-up device, a first pull-down device, a second pull-up device, a second pull-down device, a first pass gate device and a second pass gate device disposed on a substrate. A plurality of fin structures are disposed on the substrate, and the fin structures include at least one first fin structure and at least one second fin structure. ... United Microelectronics Corporation

11/09/17 / #20170323880

Semiconductor device for electrostatic discharge protection

A semiconductor device for electrostatic discharge (esd) protection includes a doped well, a drain region, a source region, a first doped region and a guard ring. The doped well is disposed in a substrate and has a first conductive type. ... United Microelectronics Corporation

11/09/17 / #20170323854

Feeding overlay data of one layer to next layer for manufacturing integrated circuit

A method of manufacturing an integrated circuit includes the following steps. A substrate including a plurality of exposure fields is provided, and each of the exposure fields includes a target portion and a set of overlay marks. ... United Microelectronics Corporation

11/09/17 / #20170323852

Semiconductor device and method for fabricating the same

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; forming an epitaxial layer adjacent to the gate structure; forming an interlayer dielectric (ild) layer on the gate structure; forming a first contact hole in the ild layer adjacent to the gate structure; and forming a cap layer in the recess, in which a top surface of the cap layer is even with or lower than a top surface of the substrate.. ... United Microelectronics Corporation

11/09/17 / #20170323824

Semiconductor device and method for fabricating the same

A semiconductor device includes: a substrate, a gate structure on the substrate, and a spacer adjacent to the gate structure, in which the spacer extends to a top surface of the gate structure, a top surface of the spacer includes a planar surface, the spacer encloses an air gap, and the spacer is composed of a single material. The gate structure includes a high-k dielectric layer, a work function metal layer, and a low resistance metal layer, in which the high-k dielectric layer is u-shaped. ... United Microelectronics Corporation

11/09/17 / #20170320727

Microelectromechanical system structure and method for fabricating the same

A microelectromechanical system structure and a method for fabricating the same are provided. A method for fabricating a mems structure includes the following steps. ... United Microelectronics Corporation

10/26/17 / #20170309727

Manufacturing method of patterned structure of semiconductor

A method of fabricating a patterned structure of a semiconductor device includes the following steps: providing a substrate having a target layer thereon; forming a patterned sacrificial layer on the target layer, wherein the patterned sacrificial layer consists of a plurality of sacrificial features; forming spacers respectively on sidewalls of each of the sacrificial features, wherein all of the spacers are arranged to have a layout pattern; and transferring the layout pattern to the target layer so as to form a first feature and a second feature, wherein the first feature comprises a vertical segment and a horizontal segment, the second feature comprises a vertical segment and a horizontal segment, and a distance between the vertical segment of the first feature and the vertical segment of the second feature is less than a minimum feature size generated by an exposure apparatus.. . ... United Microelectronics Corporation

10/26/17 / #20170309722

Semiconductor device having metal gate structure

A metal gate transistor includes a substrate, a metal gate on the substrate, and a source/drain region in the substrate adjacent to the metal gate. The metal gate includes a high-k dielectric layer, a bottom barrier metal (bbm) layer comprising tisin on the high-k dielectric layer, a tin layer on the bbm layer, a tial layer between the bbm layer and the tin layer, and a low resistance metal layer on the tin layer.. ... United Microelectronics Corporation

10/26/17 / #20170309708

Field effect transistor

A field effect transistor is provided in the present invention with an active area including a source region, a drain region, and a channel region. The width of the channel region is larger than the width of the source/drain regions, and at least one of the source region and the drain region is comb-shaped.. ... United Microelectronics Corporation

10/26/17 / #20170309621

Semiconductor device having gate structure with reduced threshold voltage and method for manufacturing the same

A semiconductor device is provided, including: a substrate having a first area and a second area; several first gate structures formed at the first area, and at least one of the first gate structures including a first hardmask on a first gate, and the first gate structure having a first gate length; several second gate structures formed at the second area, and at least one of the second gate structures including a second hardmask on a second gate, and the second gate structure having a second gate length. The first gate length is smaller than the second gate length, and the first hardmask contains at least a portion of nitrogen (n2)-based silicon nitride (sin) which is free of oh concentration.. ... United Microelectronics Corporation

10/26/17 / #20170309613

Electrostatic discharge protection semiconductor device and layout structure of esd protection semiconductor device

A layout structure of an esd protection semiconductor device includes a substrate, a first doped region, a pair of second doped regions, a pair of third doped regions, at least a first gate structure formed within the first doped region, and a drain region and a first source region formed at two sides of the first gate structure. The substrate, the first doped region and the third doped regions include a first conductivity type. ... United Microelectronics Corporation

10/26/17 / #20170309520

Semiconductor device and method for fabricating the same

A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a first metal gate and a second metal gate are formed on the substrate, in which the first metal gate includes a first work function metal layer, the second metal gate includes a second work function metal layer, the first metal gate and the second metal gate include different size, and the first work function metal layer and the second work function metal layer include different thickness.. ... United Microelectronics Corporation

10/26/17 / #20170309485

Apparatus for semiconductor wafer treatment and semiconductor wafer treatment

An apparatus for semiconductor wafer treatment includes a wafer holding unit configured to receive a single wafer, at least a solution supply unit configured to apply a solution onto the wafer and an irradiation unit configured to emit irradiation to the wafer. The irradiation unit further includes at least a plurality of first light sources configured to emit irradiation in fir range and a plurality of second light sources configured to emit irradiation in uv range.. ... United Microelectronics Corporation

10/12/17 / #20170294540

Semiconductor structure and method for manufacturing the same

A semiconductor structure and a method for manufacturing the same are provided. The semiconductor includes a substrate, two source/drain regions, a gate structure and two salicide layers. ... United Microelectronics Corporation

10/12/17 / #20170294539

Semiconductor device and method of fabricating semiconductor device

The present invention provides a semiconductor device, including a substrate, two gate structures disposed on a channel region of the substrate, an epitaxial layer disposed in the substrate between two gate structures, a first dislocation disposed in the epitaxial layer, wherein the profile of the first dislocation has at least two non-parallel slanting lines, and a second dislocation disposed adjacent to a top surface of the epitaxial layer, and the profile of the second dislocation has at least two non-parallel slanting lines.. . ... United Microelectronics Corporation

10/12/17 / #20170294523

Method for fabricating semiconductor device

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first organic layer on the substrate; patterning the first organic layer to form an opening; forming a second organic layer in the opening; and removing the first organic layer to form a patterned second organic layer on the substrate.. ... United Microelectronics Corporation

10/12/17 / #20170294508

Semiconductor device and method for fabricating the same

A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a gate structure is formed on the substrate. ... United Microelectronics Corporation

10/12/17 / #20170294429

Semiconductor layout structure

A semiconductor layout structure includes a substrate comprising a cell edge region and a dummy region abutting thereto, a plurality of dummy contact patterns disposed in the dummy region and arranged along a first direction, and a plurality of dummy gate patterns disposed in the dummy region and arranged along the first direction. The dummy contact patterns and the dummy gate patterns are alternately arranged. ... United Microelectronics Corporation








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