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Unity Semiconductor Corporation patents

Recent patent applications related to Unity Semiconductor Corporation. Unity Semiconductor Corporation is listed as an Agent/Assignee. Note: Unity Semiconductor Corporation may have other listings under different names/spellings. We're not affiliated with Unity Semiconductor Corporation, we're just tracking patents.

ARCHIVE: New 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "U" | Unity Semiconductor Corporation-related inventors




Date Unity Semiconductor Corporation patents (updated weekly) - BOOKMARK this page
02/02/17Vertical cross-point memory arrays
01/26/17High voltage switching circuitry for a cross-point array
01/12/17Array voltage regulating technique to enable data operations on large memory arrays with resistive memory elements
12/29/16Circuits and techniques to compensate memory access signals for variations of parameters in multiple layers of memory
12/22/16Low read current architecture for memory
11/03/16Global bit line pre-charge circuit that compensates for process, operating voltage, and temperature variations
10/13/16Vertical cross-point arrays for ultra-high-density memory applications
09/15/16Conductive metal oxide structures in non-volatile re-writable memory devices
06/16/16Access signal adjustment circuits and methods for memory cells in a cross-point array
01/07/16Memory element with a reactive metal layer
12/31/15Two-terminal reversibly switchable memory device
12/17/15Circuits and techniques to compensate memory access signals for variations of parameters in multiple layers of memory
10/22/15Global bit line pre-charge circuit that compensates for process, operating voltage, and temperature variations
09/17/15Preservation circuit and methods to maintain values representing data in one or more layers of memory
08/06/15High voltage switching circuitry for a cross-point array
06/25/15Access signal adjustment circuits and methods for memory cells in a cross-point array
05/21/15Array voltage regulating technique to enable data operations on large memory arrays with resistive memory elements
05/14/15Local bit lines and methods of selecting the same to access memory elements in cross-point arrays
04/09/15Vertical cross point arrays for ultra high density memory applications
02/26/15Circuits and techniques to compensate memory access signals for variations of parameters in multiple layers of memory
01/29/15Two-terminal reversibly switchable memory device
01/15/15Vertical gate nand memory devices
12/18/14Conductive metal oxide structures in non volatile re writable memory devices
12/18/14High voltage switching circuitry for a cross-point array
11/27/14Multi-layered conductive metal oxide structures and methods for facilitating enhanced performance characteristics of two-terminal memory cells
11/13/14Low read current architecture for memory
08/21/14Planar resistive memory integration
08/07/14Access signal adjustment circuits and methods for memory cells in a cross-point array
07/31/14Memory element with a reactive metal layer
05/22/14Programmable logic device structure using third dimensional memory
05/22/14Array voltage regulating technique to enable data operations on large cross-point memory arrays with resistive memory elements
05/22/14Preservation circuit and methods to maintain values representing data in one or more layers of memory
01/16/14Array operation using a schottky diode as a non-ohmic selection device
01/09/14Conductive metal oxide structures in non volatile re writable memory devices
11/21/13High voltage switching circuitry for a cross-point array
08/29/13Field programmable gate arrays using resistivity-sensitive memories
08/22/13Conductive metal oxide structures in non volatile re writable memory devices
08/22/13Circuits and techniques to compensate data signals for variations of parameters affecting memory cells in cross-point arrays
08/15/13Planar resistive memory integration
05/30/13Access signal adjustment circuits and methods for memory cells in a cross-point array
04/04/13Memory device using multiple tunnel oxide layers
04/04/13Multi layered conductive metal oxide structures and methods for facilitating enhanced performance characteristics of two terminal memory cells
02/21/13Structures and methods for facilitating enhanced cycling endurance of memory accesses to re-writable non volatile two terminal memory elements
02/21/13Vertical cross point arrays for ultra high density memory applications
01/03/13Multilayer cross-point memory array having reduced disturb susceptibility
12/13/12Memory array with local bitlines and local-to-global bitline pass gates and gain stages
12/13/12Array voltage regulating technique to enable data operations on large cross-point memory arrays with resistive memory elements
12/13/12Immersion platinum plating solution
12/06/12Local bit lines and methods of selecting the same to access memory elements in cross-point arrays
11/29/12Non-volatile memory device ion barrier
11/22/12Continuous plane of thin-film materials for a two-terminal cross-point memory
11/15/12Array operation using a schottky diode as a non-ohmic selection device
10/18/12Data retention structure for non-volatile memory
10/18/12Integrated circuits to control access to multiple layers of memory in a solid state drive
10/11/12Contemporaneous margin verification and memory access for memory cells in cross point memory arrays
10/11/12Method for indicating a non-flash nonvolatile multiple-type three-dimensional memory
08/30/12Digital potentiometer using third dimensional memory
08/23/12Oxygen ion implanted conductive metal oxide re-writeable non-volatile memory device
08/23/12Memory emulation in an image capture device
08/16/12Buffering systems for accessing multiple layers of memory in integrated circuits
08/16/12Memory emulation in a cellular telephone
08/16/12Integrated circuit with compress engine
08/16/12Securing non volatile data in rram
08/09/12Signal margin improvement for read operations in a cross-point memory array
07/12/12Access signal adjustment circuits and methods for memory cells in a cross-point array
Patent Packs
07/12/12Combined memories in integrated circuits
07/12/12System for accessing non-volatile memory
06/14/12Preservation circuit and methods to maintain values representing data in one or more layers of memory
06/14/12Buffering systems for accessing multiple layers of memory in integrated circuits
04/12/12Two terminal re writeable non volatile ion transport memory device
03/29/12Low read current architecture for memory
03/22/12System including vertically stacked embedded non flash re writable non volatile memory
03/22/12Integrated circuits using non volatile resistivity sensitive memory for emulation of embedded flash memory
03/22/12Memory device with vertically embedded non flash non volatile memory for emulation of nand flash memory
03/15/12Performing data operations using non volatile third dimension memory
03/15/12Dual ported non volatile fifo with third dimension memory
03/15/12Circuitry and indicating a memory
03/15/12Method for fabricating multi resistive state memory devices
03/08/12Securing non volatile data in an embedded memory device
02/23/12Conductive metal oxide structures in non volatile re writable memory devices
Patent Packs
02/16/12Non volatile memory device ion barrier
02/09/12Memory element with a reactive metal layer
02/02/12Conductive metal oxide structures in non volatile re writable memory devices
01/26/12Array operation using a schottky diode as a non ohmic selection device
01/26/12System for accessing non volatile memory
01/19/12Vertically fabricated beol non-volatile two-terminal cross-trench memory array with two-terminal memory elements and fabricating the same
12/29/11Memory device using a dual layer conductive metal oxide structure
12/29/11Memory device using ion implant isolated conductive metal oxide
12/22/11Combined memories in integrated circuits
12/15/11Programmable logic device structure using third dimensional memory
12/01/11Threshold device for a memory array
11/17/11Tri layer metal oxide rewritable non volatile two terminal memory element
11/17/11Write buffering systems for accessing multiple layers of memory in integrated circuits
11/03/11Contemporaneous margin verification and memory access for memory cells in cross-point memory arrays
10/06/11Vertically stacked third-dimensional embedded re-writeable non-volatile memory and registers
10/06/11Buffering systems for accessing multiple layers of memory in integrated circuits
10/06/11Integrated circuits to control access to multiple layers of memory in a solid state drive
09/22/11Immersion platinum plating solution
08/25/11Method of making a planar electrode
08/04/11Multi-resistive state memory device with conductive oxide electrodes
08/04/11Local bit lines and methods of selecting the same to access memory elements in cross-point arrays
08/04/11Memory architectures and techniques to enhance throughput for cross-point arrays
08/04/11Circuits and techniques to compensate data signals for variations of parameters affecting memory cells in cross-point arrays
08/04/11Circuits and techniques to compensate memory access signals for variations of parameters in multiple layers of memory
08/04/11Access signal adjustment circuits and methods for memory cells in a cross-point array
08/04/11Preservation circuit and methods to maintain values representing data in one or more layers of memory
07/28/11Memory device with vertically embedded non-flash non-volatile memory for emulation of nand flash memory
07/14/11Securing non-volatile data in an embedded memory device
07/07/11Field programmable gate arrays using resistivity-sensitive memories
07/07/11Integrated circuits and methods to compensate for defective non-volatile embedded memory in one or more layers of vertically stacked non-volatile embedded memory
Social Network Patent Pack
06/30/11Continuous plane of thin-film materials for a two-terminal cross-point memory
06/23/11Non-volatile memory device ion barrier
06/23/11Ion barrier cap
06/23/11Memory and methods of forming the same to enhance scalability of non-volatile two-terminal memory cells
06/16/11Read buffering systems for accessing multiple layers of memory in integrated circuits
06/09/11Continuous plane of thin-film materials for a two-terminal cross-point memory
06/09/11Method for accessing vertically stacked embedded non-flash re-writable non-volatile memory
05/26/11System for accessing non-volatile memory
05/19/11Memory emulation using resistivity-sensitive memory
05/05/11Performing data operations using non-volatile third dimension memory
Patent Packs
04/07/11Method for contemporaneous margin verification and memory access for memory cells in cross-point memory arrays
04/07/11Resistive memory device and manufacturing method thereof and operating method thereof
03/17/11State machines using non-volatile re-writeable two-terminal resistivity-sensitive memories
02/24/11Memory device with vertically embedded non-flash non-volatile memory for emulation of nand flash memory
02/17/11Securing non-volatile data in an embedded memory device
02/10/11Asic including vertically stacked embedded non-flash re-writable non-volatile memory
02/03/11System using non-volatile resistivity-sensitive memory for emulation of embedded flash memory
01/13/11Integrated circuits and methods to compensate for defective non-volatile embedded memory in one or more layers of vertically stacked non-volatile embedded memory
11/18/10Signal margin improvement for read operations in a cross-point memory array
11/18/10Fast data access through page manipulation
11/04/10Media player with non-volatile memory
10/28/10Performing data operations using non-volatile third dimension memory
10/21/10Continuous plane of thin-film materials for a two-terminal cross-point memory
10/14/10Preservation circuit and methods to maintain values representing data in one or more layers of memory
09/23/10Non-volatile register
09/16/10Columnar replacement of defective memory cells
09/02/10Non-volatile fifo with third dimension memory
09/02/10Circuitry and indicating a memory
08/12/10Low read current architecture for memory
08/05/10Non-volatile dual port third dimensional memory
08/05/10Multiple layers of memory implemented as different memory technology
08/05/10Data storage system with refresh in place
08/05/10Fuse elemetns based on two-terminal re-writeable non-volatile memory
06/24/10Memory device with band gap control
06/24/10Memory stack cladding
06/24/10Conductive oxide electrodes
06/24/10Configurable memory interface to provide serial and parallel access to memories
06/24/10Memory access circuits and layout of the same for cross-point memory arrays
06/24/10Multi-resistive state memory device with conductive oxide electrodes
06/24/10Conductive metal oxide structures in non-volatile re-writable memory devices
Patent Packs
06/24/10Digital potentiometer using third dimensional memory
06/24/10High voltage switching circuitry for a cross-point array
06/24/10Array operation using a schottky diode as a non-ohmic isolation device
06/24/10Memory cell formation using ion implant isolated conductive metal oxide
06/24/10Device fabrication
06/24/10Multi-structured memory
06/24/10Data storage system with non-volatile memory using both page write and block program and block erase
06/24/10Third dimensional memory with compress engine
06/24/10Protecting integrity of data in multi-layered memory with data redundancy
06/24/10Memory scrubbing in third dimension memory
06/10/10Buffering systems for accessing multiple layers of memory in integrated circuits
06/03/10Programmable logic device structure using third dimensional memory
06/03/10Field programmable gate arrays using resistivity sensitive memories
03/25/10Contemporaneous margin verification and memory access fr memory cells in cross point memory arrays
02/04/10Preservation circuit and methods to maintain values representing data in one or more layers of memory
01/14/10Memory emulation using resistivity sensitive memory
12/10/09Two-terminal reversibly switchable memory device
12/10/09Multi-terminal reversibly switchable memory device
09/24/09Scaleable memory systems using third dimension memory
09/17/09Memory using variable tunnel barrier widths
Social Network Patent Pack
09/10/09Data retention structure for non-volatile memory
08/27/09Four vertically stacked memory layers in a non-volatile re-writeable memory device
08/13/09Integated circuits and methods to control access to multiple layers of memory
08/06/09Integrated circuits to control access to multiple layers of memory
08/06/09Non-volatile register
08/06/09Integrated circults to control access to multiple layers of memory in a solid state drive
08/06/09Serial memory interface
07/16/09Securing data in memory device
07/09/09Programmable logic device structure using third dimensional memory
07/09/09Buffering systems for accessing multiple layers of memory in integrated circuits
07/09/09Buffering systems methods for accessing multiple layers of memory in integrated circuits
07/02/09Field programmable gate arrays using resistivity sensitive memories
07/02/09State machines using resistivity-sensitive memories
07/02/09Radio frequency identification transponder memory
07/02/09Non-volatile memories in interactive entertainment systems
07/02/09Memory sanitization
07/02/09Non-volatile processor register
06/25/09Media player with non-volatile memory
06/25/09Non-volatile memory compiler
06/25/09Solid state drive with non-volatile memory for a media device
Social Network Patent Pack
06/25/09Emulation of a nand memory system
06/25/09Method and system for accessing non-volatile memory
06/25/09Memory access protection
06/18/09Disturb control circuits and methods to control memory disturbs among multiple layers of memory
06/11/09Integrated circuits and methods to compensate for defective memory in multiple layers of memory
06/04/09Planar third dimensional memory with multi-port access
04/23/09Memory emulation using resistivity-sensitive memory
04/23/09Transient storage device emulation using resistivity-sensitive memory
04/16/09Memory emulation in a cellular telephone
03/05/09Memory emulation in an image capture device
03/05/09Memory emulation in an electronic organizer
02/19/09Multi-resistive state memory device with conductive oxide electrodes
02/19/09Multiple-type memory
02/19/09Circuitry and indicating a memory
01/14/10Memory emulation using resistivity sensitive memory







ARCHIVE: New 2016 2015 2014 2013 2012 2011 2010 2009



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