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Utac Headquarters Pte Ltd patents


Recent patent applications related to Utac Headquarters Pte Ltd. Utac Headquarters Pte Ltd is listed as an Agent/Assignee. Note: Utac Headquarters Pte Ltd may have other listings under different names/spellings. We're not affiliated with Utac Headquarters Pte Ltd, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "U" | Utac Headquarters Pte Ltd-related inventors


Multi-layer leadless semiconductor package and manufacturing the same

Device and method of forming the device are disclosed. A device includes a buildup package substrate with top and bottom surfaces and a plurality of interlevel dielectric (ILD) layers with interconnect structures printed layer by layer and includes a die region and a non-die region on the top surface. A... Utac Headquarters Pte Ltd

Semiconductor package with multiple molding routing layers and a manufacturing the same

Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a leadframe land grid array semiconductor package by using a laser to blast away un-designed conductive areas to... Utac Headquarters Pte Ltd

Semiconductor packages and methods of packaging semiconductor devices

Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a package substrate having first and second major surfaces. The package substrate includes a base substrate having a mold material and a plurality of interconnect structures including via contacts extending through the first to the... Utac Headquarters Pte Ltd

Semiconductor package with multiple molding routing layers and a manufacturing the same

Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using a laser to activate areas of each molding... Utac Headquarters Pte Ltd

Semiconductor package with multiple molding routing layers and a manufacturing the same

Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using an inkjet process to create conductive paths on... Utac Headquarters Pte Ltd

Semiconductor package with multiple molding routing layers and a manufacturing the same

Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using a laser to blast away un-designed conductive areas... Utac Headquarters Pte Ltd

Semiconductor packages and methods for forming semiconductor package

Semiconductor packages and methods for forming a semiconductor package are presented. The semiconductor package includes a package substrate having a die region on a first surface thereof. The package includes a die having a sensing element. The die is disposed in the die region and is electrically coupled to contact... Utac Headquarters Pte Ltd

Semiconductor packages and methods of packaging semiconductor devices

A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and... Utac Headquarters Pte Ltd

Methods for singulating semiconductor wafer

Methods for dicing a wafer is presented. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies on main device regions and are spaced apart from each other by dicing channels on the first major surface of the wafer.... Utac Headquarters Pte Ltd

Semiconductor packages and methods of packaging semiconductor devices

Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies and a plurality of external electrical contacts disposed on the first major surface of the wafer. The method... Utac Headquarters Pte Ltd








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This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. Freshpatents.com is not affiliated or associated with Utac Headquarters Pte Ltd in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Utac Headquarters Pte Ltd with additional patents listed. Browse our Agent directory for other possible listings. Page by FreshPatents.com

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