Via Alliance Semiconductor Co Ltd patents

Branch predictor that uses multiple byte offsets in hash of instruction block fetch address and branch pattern to generate conditional branch predictor indexes

A branch predictor has a block address useable to access a block of instruction bytes of an instruction cache and first/second byte offsets within the block of instruction bytes. Hashing logic hashes a branch pattern and respective first/second address formed from the block address and the respective first/second byte offsets... Via Alliance Semiconductor Co Ltd

Processing denormal numbers in fma hardware

A microprocessor includes FMA execution logic that determines whether to accumulate an accumulator operand C to the partial products of multiplier and multiplicand operands A and B in the partial product adder or in a second accumulation stage. The logic calculates an exponent delta of Aexp+Bexp−Cexp and determines the number... Via Alliance Semiconductor Co Ltd

Pipelined processor with multi-issue microcode unit having local branch decoder

A processor has an execution pipeline that executes microinstructions and an instruction translator that translates architectural instructions into the microinstructions. The instruction translator has a memory that holds microcode instructions and provides a fetch quantum of a plurality of microcode instructions per clock cycle, a queue that holds microcode instructions... Via Alliance Semiconductor Co Ltd

Apparatuses and methods for trusted module execution

A computer system including a processor and a memory is provided. The processor includes a microcode executing unit and a programmable fuse which stores trusted information which is pre-generated using China commercial cryptography algorithms. The memory is operatively coupled to the processor and is configured to store a trusted module... Via Alliance Semiconductor Co Ltd

Apparatuses and methods for trusted module execution

A computer system including a processor and a memory is provided. The memory is operatively coupled to the processor and is configured to store a trusted module and a digital certificate of the trusted module. The processor authenticates a digital signature of the digital certificate, and when the digital signature... Via Alliance Semiconductor Co Ltd

Processor with improved alias queue and store collision detection to reduce memory violations and load replays

A register alias table for a processor including an alias queue, load and store comparators, and dependency logic. Each entry of the alias queue stores instruction pointers of a pair of colliding load and store instructions that caused a memory violation and a valid value. The store comparator compares the... Via Alliance Semiconductor Co Ltd

Electronic structure process

An electronic structure process includes the following steps. A redistribution structure and a carrier plate are provided. A plurality of first bonding protruding portions and a first supporting structure are formed on the redistribution structure. A first encapsulated material is formed and filled between a first opening and the first... Via Alliance Semiconductor Co Ltd

Chip package process

A chip package process includes the following steps. A supporting structure and a carrier plate are provided. The supporting structure has a plurality of openings. The supporting structure is disposed on the carrier plate. A plurality of chips is disposed on the carrier plate. The chips are respectively located in... Via Alliance Semiconductor Co Ltd

Chip package array, and chip package

A chip package array including a plurality of chip packages is provided. The chip packages are suitable for array arrangement to form the chip package array. Each of the chip packages includes a redistribution structure, a supporting structure, a chip, and an encapsulated material. The supporting structure is disposed on... Via Alliance Semiconductor Co Ltd

Electronic structure, and electronic structure array

An electronic structure is provided with a redistribution structure and the following elements. A first supporting structure has a first opening and is disposed on a first surface of the redistribution structure. A second supporting structure has a second opening and is disposed on a second surface of the redistribution... Via Alliance Semiconductor Co Ltd

Interpolator

An interpolator includes a first delay circuit, a second delay circuit, and a tunable delay circuit. The first delay circuit delays a first input signal for a fixed delay time, so as generate a first output signal. The second delay circuit delays a second input signal for the fixed delay... Via Alliance Semiconductor Co Ltd

Single-ended-to-differential converter

A single-ended-to-differential converter for driving an LVDS (Low Voltage Differential Signaling) driving circuit includes a first converting circuit, a second converting circuit, and a controller. The first converting circuit converts an input signal into a first output signal. The first converting circuit has a tunable delay time. The second converting... Via Alliance Semiconductor Co Ltd

System and merging partial write result during retire phase

A processor including a physical register file, a rename table, mapping logic, size tracking logic, and merge logic. The rename table maps an architectural register with a larger index and a smaller index. The mapping logic detects a partial write instruction that specifies an architectural register that is already identified... Via Alliance Semiconductor Co Ltd

Processor with slave free list that handles overflow of recycled physical registers and recycling physical registers in a processor using a slave free list

A processor including physical registers, a reorder buffer, a master free list, a slave free list, a master recycle circuit, and a slave recycle circuit. The reorder buffer includes instruction entries in which each entry stores physical register indexes for recycling physical registers. The reorder buffer retires up to N... Via Alliance Semiconductor Co Ltd

Multi-threading processor and a scheduling method thereof

A processor includes an execution unit, a retirement module, a first retirement counter, a second retirement counter, and an adjustment module. The execution unit executes instructions of a first thread and a second thread by simultaneous multithreading. The retirement module retires the executed instructions of the first thread in order... Via Alliance Semiconductor Co Ltd

System and automatic power control system and bias current control circuit

A bias-current-control circuit is provided. The bias-current-control circuit includes a transconductance circuit, a constant-current source, and a current-mirror circuit. The transconductance circuit is connected to a node and detects a voltage signal to generate a first current. The constant-current source is connected to the node and generates a tail current.... Via Alliance Semiconductor Co Ltd

Switch and data accessing method thereof

A switch for transmitting data packets between at least one source node and at least one target node is provided. The switch includes a storage unit, a control unit, at least one receiving port and at least one transmitting port. The storage unit includes a plurality of storage blocks and... Via Alliance Semiconductor Co Ltd

Methods for rdo (rate-distortion optimization) based on fit-curves and apparatuses using the same

A method for RDO (Rate-Distortion Optimization) based on fit-curves contains at least the following steps: calculating a first fit-curve and a second fit-curve according to information regarding a first frame; carrying information regarding a second frame into the first and second fit-curves to calculate fit distortions and fit bit counts;... Via Alliance Semiconductor Co Ltd

Graphics processing system and power gating method thereof

A graphics processing system and a power gating method thereof is provided. The graphics processing system includes a bus interface, a graphics processing unit, and a power management unit. The graphics processing unit includes a plurality of partitions and a control circuit. When the bus interface has received an external... Via Alliance Semiconductor Co Ltd

Processor with memory controller including dynamically programmable functional unit

A processor including a memory controller for interfacing an external memory and a programmable functional unit (PFU). The PFU is programmed by a PFU program to modify operation of the memory controller, in which the PFU includes programmable logic elements and programmable interconnectors. For example, the PFU is programmed by... Via Alliance Semiconductor Co Ltd

System and determining memory ownership on cache line basis for detecting self-modifying code including code with instruction that overlaps cache line boundaries

A system and method for determining memory ownership on a cache line basis for detecting self-modifying code with instructions that overlap cache line boundaries. An ownership index and a cache line address are entered into the ownership queue for each cache line. The cache lines are translated into instructions, and... Via Alliance Semiconductor Co Ltd

System and determining memory ownership on cache line basis for detecting self-modifying code

System and method of determining memory ownership on cache line basis for detecting self-modifying code. An ownership queue stores cache line addresses and corresponding ownership indexes. The cache line data is translated into instructions, and each instruction is provided with an ownership index of an associated entry in the ownership... Via Alliance Semiconductor Co Ltd

System and determining memory ownership on cache line basis for detecting self-modifying code including modification of a cache line with an executing instruction

A processor that determines memory ownership on a cache line basis for detecting self-modifying code including modification of a cache line with an executing instruction. An ownership index and corresponding cache line address are entered for each cache line into an ownership queue. The ownership index is provided with each... Via Alliance Semiconductor Co Ltd

System and determining memory ownership on cache line basis for detecting self-modifying code including code with looping instructions

A system and method of determining memory ownership on a cache line basis for detecting self-modifying code including code with looping instructions. An ownership queue includes multiple entries for determining memory ownership on a cache line basis. An ownership index and a wrap bit are determined for each cache line... Via Alliance Semiconductor Co Ltd

Dynamic powering of cache memory by ways within multiple set groups based on utilization trends

A set associative cache memory comprises an M×N memory array of storage entries arranged as M sets by N ways, both M and N are integers greater than one. Within each group of P mutually exclusive groups of the M sets, the N ways are separately powerable. A controller, for... Via Alliance Semiconductor Co Ltd

Sanitize-aware dram controller

A controller for controlling a dynamic random access memory (DRAM) comprising a plurality of blocks. A block is one or more units of storage in the DRAM for which the DRAM controller can selectively enable or disable refreshing. The DRAM controller includes flags each for association with a block of... Via Alliance Semiconductor Co Ltd

Image compressing method based on jpeg-ls

An image compression method based on JPEG-LS is presented. In the method, the M×N pixels in the source image are divided into k groups. M, N, and k are all integers larger than one. Each group corresponds to a plurality of pixels among the M×N pixels. The decorrelation procedure and... Via Alliance Semiconductor Co Ltd

Pre-driver for driving low voltage differential signaling (lvds) driving circuit

A pre-driver for driving an LVDS (Low Voltage Differential Signaling) driving circuit is provided. The pre-driver includes a first inverter, a high-pass filter, and a second inverter. The first inverter has an input terminal coupled to an input node of the pre-driver, and an output terminal coupled to a first... Via Alliance Semiconductor Co Ltd

Duty cycle calibration circuit

A duty cycle calibration circuit includes a first signal-generating circuit, receiving a clock signal to generate a first signal and a second signal, wherein the second signal and the first signal are the inverse of each other and synchronous. The calibration circuit also includes a first transmission gate, supplying a... Via Alliance Semiconductor Co Ltd

Host interface controller and control storage device

A host interface controller having a first buffer set and a second buffer set operated in a ping-pong buffer mode by a control module to alternately work as a pre-fetch buffer set. When one buffer set between the first buffer set and the second buffer set works as the pre-fetch... Via Alliance Semiconductor Co Ltd

Host interface controller and control storage device

A host interface controller with improved boot up efficiency, which uses a buffer mode setting register to set the operation mode of a first and a second buffer set provided within the host interface controller. When a cache memory of a central processing unit (CPU) at the host side has... Via Alliance Semiconductor Co Ltd

Stride reference prefetcher

A processor including a cache memory, processing logic, access logic, stride mask logic, count logic, arbitration logic, and a prefetcher. The processing logic submits load requests to access cache lines of a memory page. The access logic updates an access vector for the memory page, in which the access logic... Via Alliance Semiconductor Co Ltd

Method and device for image processing

A device for image processing includes a first queue, a second queue, a cache, and a processor. The first queue is capable of receiving a first image tile. The processor is electrically connected to the first queue, the second queue, and the cache, respectively. The processor is capable of obtaining... Via Alliance Semiconductor Co Ltd

Measuring device

A measurement device measuring a current passing through a detection resistor coupled between a first node and a second node is provided. An interference elimination unit is coupled to the first and second nodes and selectively outputs the voltage of at least one of the first and second nodes according... Via Alliance Semiconductor Co Ltd

Compiler system for a processor with an expandable instruction set architecture for dynamically configuring execution resources

A compiler system that converts an application source program into an executable program according to a predetermined ISA executable by a general purpose processor. The processor includes a PEU that is programmable to execute a UDI. The compiler system includes a PEU programming tool that converts a functional description of... Via Alliance Semiconductor Co Ltd