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Via Alliance Semiconductor Co Ltd patents

Recent patent applications related to Via Alliance Semiconductor Co Ltd. Via Alliance Semiconductor Co Ltd is listed as an Agent/Assignee. Note: Via Alliance Semiconductor Co Ltd may have other listings under different names/spellings. We're not affiliated with Via Alliance Semiconductor Co Ltd, we're just tracking patents.

ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "V" | Via Alliance Semiconductor Co Ltd-related inventors




Date Via Alliance Semiconductor Co Ltd patents (updated weekly) - BOOKMARK this page
11/16/17Switch and data accessing method thereof
11/09/17Methods for rdo (rate-distortion optimization) based on fit-curves and apparatuses using the same
10/26/17Graphics processing system and power gating method thereof
10/26/17Processor with memory controller including dynamically programmable functional unit
10/26/17System and determining memory ownership on cache line basis for detecting self-modifying code including code with instruction that overlaps cache line boundaries
10/26/17System and determining memory ownership on cache line basis for detecting self-modifying code
10/26/17System and determining memory ownership on cache line basis for detecting self-modifying code including modification of a cache line with an executing instruction
10/26/17System and determining memory ownership on cache line basis for detecting self-modifying code including code with looping instructions
10/19/17Dynamic powering of cache memory by ways within multiple set groups based on utilization trends
10/19/17Sanitize-aware dram controller
10/12/17Image compressing method based on jpeg-ls
09/14/17Pre-driver for driving low voltage differential signaling (lvds) driving circuit
08/03/17Duty cycle calibration circuit
06/15/17Host interface controller and control storage device
06/15/17Host interface controller and control storage device
06/15/17Stride reference prefetcher
06/15/17Method and device for image processing
06/08/17Measuring device
06/08/17Compiler system for a processor with an expandable instruction set architecture for dynamically configuring execution resources
06/08/17Conversion system for a processor with an expandable instruction set architecture for dynamically configuring execution resources
06/08/17Processor with an expandable instruction set architecture for dynamically configuring execution resources
06/08/17Apparatuses for enqueuing kernels on a device-side
06/08/17Computing resource controller and control multiple engines to share a shared resource
06/08/17Processor with programmable prefetcher
06/08/17Processor with programmable prefetcher
06/08/17Host controller of high-speed data interface
06/08/17Computer system and operating method therefor
06/08/17Duty cycle calibration circuit
06/08/17Digital-to-analog converter and high-voltage tolerance circuit
06/08/17Axially and centrally symmetric current source array
06/08/17I/o circuit and data transmission control method
06/01/17Methods and apparatuses for generating machine code for driving an execution unit
06/01/17Method and device for processing graphics
06/01/17Method and device for merging graphic layers
06/01/17Method and device for displaying graphic layers
06/01/17Method and device for displaying graphic layers
06/01/17Data reception chip
06/01/17Control data reception chip
06/01/17Data reception chip
05/25/17Electronic device with recording functionality and recording thereof
05/25/17Circuit substrate and semiconductor package structure
05/18/17Chipset and server system using the same
05/18/17System and speculative parallel execution of cache line unaligned load instructions
05/18/17Methods for checking dependencies of data units and apparatuses using the same
05/18/17Methods for checking dependencies of data units and apparatuses using the same
05/18/17Methods for checking dependencies of data units and apparatuses using the same
05/04/17Prefetching with level of aggressiveness based on effectiveness by memory access type
05/04/17Chipset and host controller with capability of disk encryption
05/04/17Methods for blending resembling blocks and apparatuses using the same
05/04/17Graphic data compression device and graphic data compression method
04/13/17Neural network unit that performs stochastic rounding
04/13/17Apparatus employing user-specified binary point fixed point arithmetic
04/13/17Neural network unit with neural memory and array of neural processing units that collectively shift row of data received from neural memory
04/13/17Neural network unit with output buffer feedback and masking capability
04/13/17Direct execution by an execution unit of a micro-operation loaded into an architectural register file by an architectural instruction of a processor
04/13/17Processor with variable rate execution unit
04/13/17Mechanism for communication between architectural program running on processor and non-architectural program running on execution unit of the processor regarding shared resource
04/13/17Tri-configuration neural network unit
04/13/17Processor with architectural neural network execution unit
04/13/17Neural network unit with neural processing units dynamically configurable to process multiple data sizes
04/13/17Neural network unit with output buffer feedback for performing recurrent neural network computations
04/13/17Neural network unit with plurality of selectable output functions
04/13/17Neural network unit that performs concurrent lstm cell calculations
04/13/17Neural network unit with neural memory and array of neural processing units and sequencer that collectively shift row of data received from neural memory
04/13/17Processor with hybrid coprocessor/execution unit neural network unit
Patent Packs
04/13/17Multi-operation neural network unit
04/13/17Neural network unit that performs convolutions using collective shift register among array of neural processing units
04/13/17Neural network unit with output buffer feedback and masking capability with processing unit groups that operate as recurrent neural network lstm cells
04/13/17Neural processing unit that selectively writes back to neural memory either activation function output or accumulator value
04/13/17Neural network unit with shared activation function units
04/13/17Neural network unit employing user-supplied reciprocal for normalizing an accumulated value
04/06/17Chained split execution of fused compound arithmetic operations
03/30/17Methods and apparatuses for computing trigonometric functions with high precision
03/30/17Microprocessor with fused reservation stations structure
03/02/17Power-control devices
03/02/17System and accelerating arbitration by approximating relative ages
03/02/17Methods for combining instructions and apparatuses having multiple data pipes
03/02/17Methods for correcting bad pixels and apparatuses using the same
02/23/17Demosaicing methods and apparatuses using the same
02/23/17Methods for programmable a primitive setup in a 3d graphics pipeline and apparatuses using the same
Patent Packs
02/02/17Methods for generating hdr (high dynamic range) images and apparatuses using the same
12/29/16Graphics processing unit and associate graphics processing method
12/29/16Hardware data compressor using dynamic hash algorithm based on input block type
12/22/16On-chip sensor hub, and mobile device and multi-sensor management method therefor
12/08/16Mechanism to preclude load replays dependent on fuse array access in an out-of-order processor
12/08/16Multi-mode set associative cache memory dynamically configurable to selectively allocate into all or a subset of its ways depending on the mode
12/08/16Multiple data prefetchers that defer to one another based on prefetch effectiveness by memory access type
12/08/16Set associative cache memory with heterogeneous replacement policy
12/08/16Multi-mode set associative cache memory dynamically configurable to selectively select one or a plurality of its sets depending upon the mode
12/01/16Pattern detector for detecting hangs
12/01/16Mechanism to preclude load replays dependent on long load cycles in an out-of-order processor
12/01/16Mechanism to preclude load replays dependent on off-die control element access in an out-of-order processor
12/01/16Cache replacement policy that considers memory access type
12/01/16Load replay precluding mechanism
12/01/16Apparatus and method to preclude x86 special bus cycle load replays in an out-of-order processor
12/01/16Multi-core data array power gating restoral mechanism
12/01/16Mechanism to preclude uncacheable-dependent load replays in out-of-order processor
12/01/16Load replay precluding mechanism
12/01/16Apparatus and method to preclude non-core cache-dependent load replays in an out-of-order processor
12/01/16Apparatus and method to preclude load replays dependent on write combining memory space access in an out-of-order processor
12/01/16Apparatus and programmable load replay preclusion
12/01/16Mechanism to preclude load replays dependent on page walks in an out-of-order processor
12/01/16Conditional pattern detector for detecting hangs
12/01/16Distributed hang recovery logic
12/01/16Logic analyzer for detecting hangs
12/01/16Cache memory budgeted by chunks based on memory access type
12/01/16Dynamic cache replacement way selection based on address tag bits
12/01/16Central processing unit and method to verify mainboard data
11/24/16Mechanism to preclude i/o-dependent load replays in an out-of-order processor
11/24/16Processor including single invalidate page instruction
Social Network Patent Pack
11/17/16Processor including load ept instruction
11/17/16Hardware data compressor that maintains sorted symbol list concurrently with input block scanning
11/17/16Hardware data compressor that constructs and uses dynamic-prime huffman code tables
11/17/16Hardware data compressor that directly huffman encodes output tokens from lz77 engine
11/17/16Hardware data compressor with multiple string match search hash tables each based on different hash size
11/17/16Hardware data compressor using dynamic hash algorithm based on input block type
11/17/16Image de-noising methods and apparatuses using the same
11/17/16Methods for generating and employing a camera noise model and apparatuses using the same
11/10/16System and method to reduce load-store collision penalty in speculative out of order engine
11/03/16Core-specific fuse mechanism for a multi-core die
Patent Packs
11/03/16Apparatus and configurable redundant fuse banks
11/03/16Apparatus and extended cache correction
10/27/16Detection circuit
10/27/16Multi-core fuse decompression mechanism
10/27/16Apparatus and storage and decompression of configuration data
10/20/16Extended fuse reprogrammability mechanism
10/13/16Electronic package assembly
10/06/16System and distinguishing system management mode entries in a translation address cache of a processor
10/06/16Cache memory diagnostic writeback
09/22/16Methods for awb (automatic white balance) compensation and apparatuses using the same
09/15/16System and reissue parking for a microprocessor
09/08/16Parallelized multiple dispatch ordered queue arbitration
09/08/16Cache system with a primary cache and an overflow fifo cache
08/25/16Level-shift circuits compatible with multiple supply voltage
07/21/16Power saving mechanism to reduce load replays in out-of-order processor
07/07/16Fully associative cache memory budgeted by memory access type
06/23/16Simultaneous invalidation of all address translation cache entries associated with x86 process context identifier
06/23/16Multi-core programming restoring data arrays following a power gating event
06/23/16Multi-core data array power gating cache restoral programming mechanism
06/23/16Multi-core microprocessor power gating cache restoral programming mechanism
06/23/16Multi-core programming restoring data arrays following a power gating event
06/23/16Address translation cache that supports simultaneous invalidation of common context entries
06/16/16Cache system with a primary cache and an overflow cache that use different indexing schemes
06/16/16Mechanism to preclude load replays dependent on fuse array access in an out-of-order processor
06/16/16Mechanism to preclude i/o-dependent load replays in an out-of-order processor
06/16/16Mechanism to preclude uncacheable-dependent load replays in out-of-order processor
06/16/16Load replay precluding mechanism
06/16/16Mechanism to preclude load replays dependent on page walks in an out-of-order processor
06/16/16Mechanism to preclude load replays dependent on long load cycles in an out-of-order processor
06/16/16Programmable load replay precluding mechanism
Patent Packs
06/16/16Power saving mechanism to reduce load replays in out-of-order processor
06/16/16Mechanism to preclude shared ram-dependent load replays in an out-of-order processor
06/16/16Apparatus and method to preclude non-core cache-dependent load replays in an out-of-order processor
06/16/16Mechanism to preclude load replays dependent on off-die control element access in an out-of-order processor
06/16/16Apparatus and method to preclude x86 special bus cycle load replays in an out-of-order processor
06/16/16Apparatus and method to preclude load replays dependent on write combining memory space access in an out-of-order processor
06/16/16Apparatus and programmable load replay preclusion
06/16/16Programmable load replay precluding mechanism
06/16/16Circuit substrate and package structure
06/16/16Graphics processing unit and graphics processing method
06/16/16Advanced video coding and decoding chip and advanced video coding and decoding method
06/16/16Advanced video coding and decoding chip and advanced video coding and decoding method
06/09/16Peripheral interface circuit at host side and electronic system using the same
06/02/16Control cache coherency
05/26/16Cache memory with unified tag and sliced data
05/26/16Low voltage differential signaling (lvds) driving circuit
05/26/16Low voltage differential signaling (lvds) driving circuit
05/19/16System and performing hardware prefetch tablewalks having lowest tablewalk priority
05/05/16Circuit substrate and semiconductor package structure
02/11/16Efficient address translation caching in a processor that supports a large number of different address spaces
Social Network Patent Pack
01/07/16Non-atomic split-path fused multiply-accumulate
01/07/16Temporally split fused multiply-accumulate operation
01/07/16Standard format intermediate result
01/07/16Split-path heuristic for performing a fused fma operation
01/07/16Calculation control indicator cache
01/07/16Calculation control indicator cache
01/07/16Subdivision of a fused compound arithmetic operation
12/17/15Hold-time optimization circuit and receiver with the same
10/29/15Electrostatic discharge protection circuit
07/30/15Fractional use of prediction history storage for operating system routines
07/09/15Circuit board and electronic assembly
06/25/15Multi-core fuse decompression mechanism
06/25/15Apparatus and storage and decompression of configuration data
06/25/15Apparatus and configurable redundant fuse banks
06/25/15Apparatus and extended cache correction
06/25/15Core-specific fuse mechanism for a multi-core die
06/25/15Multi-core microprocessor configuration data compression and decompression system
06/25/15Extended fuse reprogrammability mechanism
06/18/15Apparatus and compression of configuration data
06/18/15Apparatus and rapid fuse bank access in a multi-core processor
Social Network Patent Pack
05/14/15Data storage system and management method thereof
04/16/15Level-shift circuits compatible with multiple supply voltage







ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009



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