Robot

Patent Pack (PDFs)

Research new robot inventions

Gaming

Patent Pack (PDFs)

Research the latest gaming inventions

Social Network

Patent Pack (PDFs)

Research new Social Network inventions

Drone

Patent Pack (PDFs)

Research new Drone inventions

Electric Vehicle

Patent Pack (PDFs)

Research the latest Electric Vehicle inventions

Smartphone

Patent Pack (PDFs)

Research latest Smartphone inventions

Patent Packs (Company, PDFs)

• 1,537+ Apple invention PDFs research ($39.95)
• 413+ Amazon invention PDFs ($29.95)
• 938+ Boeing invention PDFs ($29.95)
• 843+ Caterpillar invention PDFs ($29.95)
• 145+ Disney invention PDFs ($19.95)
• 636+ Facebook invention PDFs ($29.95)
• Ford invention PDFs ($39.95)
• 1,370+ General+Electric invention PDFs ($39.95)
• 1,400+ Google invention PDFs ($39.95)
• 456+ Medtronic invention PDFs ($29.95)
• 2,050+ Microsoft invention PDFs ($59.95)
• 219+ Monsanto invention PDFs
• 385+ Nike invention PDFs ($19.95)
• 2,528+ Qualcomm invention PDFs
• 1,962+ Sony invention PDFs ( $39.95)
• 2,470 Toyota invention PDFs

Patent Packs (Topic, PDFs)

• 250+ 3d Print invention PDFs ($19.95)
• 1,800+ Aircraft invention PDFs ($39.95)
• 350+ Augmented Reality invention PDFs ($19.95)
• 880+ Beverage invention PDFs ($29.95)
• 710+ Brain invention PDFs ($29.95)
• 700+ Cardiac invention PDFs ($29.95)
• 1,700+ Cloud Computing invention PDFs ($39.95)
• 110+ Drone invention PDFs ($19.95)
• 470+ Electric Vehicle invention PDFs ($29.95)
• 170+ Electronic Cigarette invention PDFs ($19.95)
• 580+ Golf invention PDFs ($29.95)
• 470+ Graphene invention PDFs ($29.95)
• 350+ Machine Learning invention PDFs ($19.95)
• 1,300+ Medical Device invention PDFs ($39.95)
• 1,300+ Robot invention PDFs ($39.95)
• 510+ Smartphone invention PDFs ($29.95)
• 950+ Social Network invention PDFs ($29.95)
• 180+ Solar invention PDFs ($19.95)

Robot

Patent Pack (PDFs)

Research new robot inventions

Gaming

Patent Pack (PDFs)

Research the latest gaming inventions

Social Network

Patent Pack (PDFs)

Research new Social Network inventions

Drone

Patent Pack (PDFs)

Research new Drone inventions

Electric Vehicle

Patent Pack (PDFs)

Research the latest Electric Vehicle inventions

Smartphone

Patent Pack (PDFs)

Research latest Smartphone inventions

Via Alliance Semiconductor Co Ltd patents

Date	Via Alliance Semiconductor Co Ltd patents (updated weekly) - BOOKMARK this page
08/03/17	Duty cycle calibration circuit
06/15/17	Host interface controller and control storage device
06/15/17	Host interface controller and control storage device
06/15/17	Stride reference prefetcher
06/15/17	Method and device for image processing
06/08/17	Measuring device
06/08/17	Compiler system for a processor with an expandable instruction set architecture for dynamically configuring execution resources
06/08/17	Conversion system for a processor with an expandable instruction set architecture for dynamically configuring execution resources
06/08/17	Processor with an expandable instruction set architecture for dynamically configuring execution resources
06/08/17	Apparatuses for enqueuing kernels on a device-side
06/08/17	Computing resource controller and control multiple engines to share a shared resource
06/08/17	Processor with programmable prefetcher
06/08/17	Processor with programmable prefetcher
06/08/17	Host controller of high-speed data interface
06/08/17	Computer system and operating method therefor
06/08/17	Duty cycle calibration circuit
06/08/17	Digital-to-analog converter and high-voltage tolerance circuit
06/08/17	Axially and centrally symmetric current source array
06/08/17	I/o circuit and data transmission control method
06/01/17	Methods and apparatuses for generating machine code for driving an execution unit
06/01/17	Method and device for processing graphics
06/01/17	Method and device for merging graphic layers
06/01/17	Method and device for displaying graphic layers
06/01/17	Method and device for displaying graphic layers
06/01/17	Data reception chip
06/01/17	Control data reception chip
06/01/17	Data reception chip
05/25/17	Electronic device with recording functionality and recording thereof
05/25/17	Circuit substrate and semiconductor package structure
05/18/17	Chipset and server system using the same
05/18/17	System and speculative parallel execution of cache line unaligned load instructions
05/18/17	Methods for checking dependencies of data units and apparatuses using the same
05/18/17	Methods for checking dependencies of data units and apparatuses using the same
05/18/17	Methods for checking dependencies of data units and apparatuses using the same
05/04/17	Prefetching with level of aggressiveness based on effectiveness by memory access type
05/04/17	Chipset and host controller with capability of disk encryption
05/04/17	Methods for blending resembling blocks and apparatuses using the same
05/04/17	Graphic data compression device and graphic data compression method
04/13/17	Neural network unit that performs stochastic rounding
04/13/17	Apparatus employing user-specified binary point fixed point arithmetic
04/13/17	Neural network unit with neural memory and array of neural processing units that collectively shift row of data received from neural memory
04/13/17	Neural network unit with output buffer feedback and masking capability
04/13/17	Direct execution by an execution unit of a micro-operation loaded into an architectural register file by an architectural instruction of a processor
04/13/17	Processor with variable rate execution unit
04/13/17	Mechanism for communication between architectural program running on processor and non-architectural program running on execution unit of the processor regarding shared resource
04/13/17	Tri-configuration neural network unit
04/13/17	Processor with architectural neural network execution unit
04/13/17	Neural network unit with neural processing units dynamically configurable to process multiple data sizes
04/13/17	Neural network unit with output buffer feedback for performing recurrent neural network computations
04/13/17	Neural network unit with plurality of selectable output functions
04/13/17	Neural network unit that performs concurrent lstm cell calculations
04/13/17	Neural network unit with neural memory and array of neural processing units and sequencer that collectively shift row of data received from neural memory
04/13/17	Processor with hybrid coprocessor/execution unit neural network unit
04/13/17	Multi-operation neural network unit
04/13/17	Neural network unit that performs convolutions using collective shift register among array of neural processing units
04/13/17	Neural network unit with output buffer feedback and masking capability with processing unit groups that operate as recurrent neural network lstm cells
04/13/17	Neural processing unit that selectively writes back to neural memory either activation function output or accumulator value
04/13/17	Neural network unit with shared activation function units
04/13/17	Neural network unit employing user-supplied reciprocal for normalizing an accumulated value
04/06/17	Chained split execution of fused compound arithmetic operations
03/30/17	Methods and apparatuses for computing trigonometric functions with high precision
03/30/17	Microprocessor with fused reservation stations structure
03/02/17	Power-control devices
03/02/17	System and accelerating arbitration by approximating relative ages
03/02/17	Methods for combining instructions and apparatuses having multiple data pipes
03/02/17	Methods for correcting bad pixels and apparatuses using the same
02/23/17	Demosaicing methods and apparatuses using the same
02/23/17	Methods for programmable a primitive setup in a 3d graphics pipeline and apparatuses using the same
02/02/17	Methods for generating hdr (high dynamic range) images and apparatuses using the same
12/29/16	Graphics processing unit and associate graphics processing method
12/29/16	Hardware data compressor using dynamic hash algorithm based on input block type
12/22/16	On-chip sensor hub, and mobile device and multi-sensor management method therefor
12/08/16	Mechanism to preclude load replays dependent on fuse array access in an out-of-order processor
12/08/16	Multi-mode set associative cache memory dynamically configurable to selectively allocate into all or a subset of its ways depending on the mode
12/08/16	Multiple data prefetchers that defer to one another based on prefetch effectiveness by memory access type
12/08/16	Set associative cache memory with heterogeneous replacement policy
12/08/16	Multi-mode set associative cache memory dynamically configurable to selectively select one or a plurality of its sets depending upon the mode
12/01/16	Pattern detector for detecting hangs
12/01/16	Mechanism to preclude load replays dependent on long load cycles in an out-of-order processor
12/01/16	Mechanism to preclude load replays dependent on off-die control element access in an out-of-order processor
12/01/16	Cache replacement policy that considers memory access type
12/01/16	Load replay precluding mechanism
12/01/16	Apparatus and method to preclude x86 special bus cycle load replays in an out-of-order processor
12/01/16	Multi-core data array power gating restoral mechanism
12/01/16	Mechanism to preclude uncacheable-dependent load replays in out-of-order processor
12/01/16	Load replay precluding mechanism
12/01/16	Apparatus and method to preclude non-core cache-dependent load replays in an out-of-order processor
12/01/16	Apparatus and method to preclude load replays dependent on write combining memory space access in an out-of-order processor
12/01/16	Apparatus and programmable load replay preclusion
12/01/16	Mechanism to preclude load replays dependent on page walks in an out-of-order processor
12/01/16	Conditional pattern detector for detecting hangs
12/01/16	Distributed hang recovery logic
12/01/16	Logic analyzer for detecting hangs
12/01/16	Cache memory budgeted by chunks based on memory access type
12/01/16	Dynamic cache replacement way selection based on address tag bits
12/01/16	Central processing unit and method to verify mainboard data
11/24/16	Mechanism to preclude i/o-dependent load replays in an out-of-order processor
11/24/16	Processor including single invalidate page instruction
11/17/16	Processor including load ept instruction
11/17/16	Hardware data compressor that maintains sorted symbol list concurrently with input block scanning
11/17/16	Hardware data compressor that constructs and uses dynamic-prime huffman code tables
11/17/16	Hardware data compressor that directly huffman encodes output tokens from lz77 engine
11/17/16	Hardware data compressor with multiple string match search hash tables each based on different hash size
11/17/16	Hardware data compressor using dynamic hash algorithm based on input block type
11/17/16	Image de-noising methods and apparatuses using the same
11/17/16	Methods for generating and employing a camera noise model and apparatuses using the same
11/10/16	System and method to reduce load-store collision penalty in speculative out of order engine
11/03/16	Core-specific fuse mechanism for a multi-core die
11/03/16	Apparatus and configurable redundant fuse banks
11/03/16	Apparatus and extended cache correction
10/27/16	Detection circuit
10/27/16	Multi-core fuse decompression mechanism
10/27/16	Apparatus and storage and decompression of configuration data
10/20/16	Extended fuse reprogrammability mechanism
10/13/16	Electronic package assembly
10/06/16	System and distinguishing system management mode entries in a translation address cache of a processor
10/06/16	Cache memory diagnostic writeback
09/22/16	Methods for awb (automatic white balance) compensation and apparatuses using the same
09/15/16	System and reissue parking for a microprocessor
09/08/16	Parallelized multiple dispatch ordered queue arbitration
09/08/16	Cache system with a primary cache and an overflow fifo cache
08/25/16	Level-shift circuits compatible with multiple supply voltage
07/21/16	Power saving mechanism to reduce load replays in out-of-order processor
07/07/16	Fully associative cache memory budgeted by memory access type
06/23/16	Simultaneous invalidation of all address translation cache entries associated with x86 process context identifier
06/23/16	Multi-core programming restoring data arrays following a power gating event
06/23/16	Multi-core data array power gating cache restoral programming mechanism
06/23/16	Multi-core microprocessor power gating cache restoral programming mechanism
06/23/16	Multi-core programming restoring data arrays following a power gating event
06/23/16	Address translation cache that supports simultaneous invalidation of common context entries
06/16/16	Cache system with a primary cache and an overflow cache that use different indexing schemes
06/16/16	Mechanism to preclude load replays dependent on fuse array access in an out-of-order processor
06/16/16	Mechanism to preclude i/o-dependent load replays in an out-of-order processor
06/16/16	Mechanism to preclude uncacheable-dependent load replays in out-of-order processor
06/16/16	Load replay precluding mechanism
06/16/16	Mechanism to preclude load replays dependent on page walks in an out-of-order processor
06/16/16	Mechanism to preclude load replays dependent on long load cycles in an out-of-order processor
06/16/16	Programmable load replay precluding mechanism
06/16/16	Power saving mechanism to reduce load replays in out-of-order processor
06/16/16	Mechanism to preclude shared ram-dependent load replays in an out-of-order processor
06/16/16	Apparatus and method to preclude non-core cache-dependent load replays in an out-of-order processor
06/16/16	Mechanism to preclude load replays dependent on off-die control element access in an out-of-order processor
06/16/16	Apparatus and method to preclude x86 special bus cycle load replays in an out-of-order processor
06/16/16	Apparatus and method to preclude load replays dependent on write combining memory space access in an out-of-order processor
06/16/16	Apparatus and programmable load replay preclusion
06/16/16	Programmable load replay precluding mechanism
06/16/16	Circuit substrate and package structure
06/16/16	Graphics processing unit and graphics processing method
06/16/16	Advanced video coding and decoding chip and advanced video coding and decoding method
06/16/16	Advanced video coding and decoding chip and advanced video coding and decoding method
06/09/16	Peripheral interface circuit at host side and electronic system using the same
06/02/16	Control cache coherency
05/26/16	Cache memory with unified tag and sliced data
05/26/16	Low voltage differential signaling (lvds) driving circuit
05/26/16	Low voltage differential signaling (lvds) driving circuit
05/19/16	System and performing hardware prefetch tablewalks having lowest tablewalk priority
05/05/16	Circuit substrate and semiconductor package structure
02/11/16	Efficient address translation caching in a processor that supports a large number of different address spaces
01/07/16	Non-atomic split-path fused multiply-accumulate
01/07/16	Temporally split fused multiply-accumulate operation
01/07/16	Standard format intermediate result
01/07/16	Split-path heuristic for performing a fused fma operation
01/07/16	Calculation control indicator cache
01/07/16	Calculation control indicator cache
01/07/16	Subdivision of a fused compound arithmetic operation
12/17/15	Hold-time optimization circuit and receiver with the same
10/29/15	Electrostatic discharge protection circuit
07/30/15	Fractional use of prediction history storage for operating system routines
07/09/15	Circuit board and electronic assembly
06/25/15	Multi-core fuse decompression mechanism
06/25/15	Apparatus and storage and decompression of configuration data
06/25/15	Apparatus and configurable redundant fuse banks
06/25/15	Apparatus and extended cache correction
06/25/15	Core-specific fuse mechanism for a multi-core die
06/25/15	Multi-core microprocessor configuration data compression and decompression system
06/25/15	Extended fuse reprogrammability mechanism
06/18/15	Apparatus and compression of configuration data
06/18/15	Apparatus and rapid fuse bank access in a multi-core processor
05/14/15	Data storage system and management method thereof
04/16/15	Level-shift circuits compatible with multiple supply voltage