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Via Alliance Semiconductor Co Ltd patents


Recent patent applications related to Via Alliance Semiconductor Co Ltd. Via Alliance Semiconductor Co Ltd is listed as an Agent/Assignee. Note: Via Alliance Semiconductor Co Ltd may have other listings under different names/spellings. We're not affiliated with Via Alliance Semiconductor Co Ltd, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "V" | Via Alliance Semiconductor Co Ltd-related inventors


Interpolator

An interpolator includes a first delay circuit, a second delay circuit, and a tunable delay circuit. The first delay circuit delays a first input signal for a fixed delay time, so as generate a first output signal. The second delay circuit delays a second input signal for the fixed delay... Via Alliance Semiconductor Co Ltd

Single-ended-to-differential converter

A single-ended-to-differential converter for driving an LVDS (Low Voltage Differential Signaling) driving circuit includes a first converting circuit, a second converting circuit, and a controller. The first converting circuit converts an input signal into a first output signal. The first converting circuit has a tunable delay time. The second converting... Via Alliance Semiconductor Co Ltd

System and merging partial write result during retire phase

A processor including a physical register file, a rename table, mapping logic, size tracking logic, and merge logic. The rename table maps an architectural register with a larger index and a smaller index. The mapping logic detects a partial write instruction that specifies an architectural register that is already identified... Via Alliance Semiconductor Co Ltd

Processor with slave free list that handles overflow of recycled physical registers and recycling physical registers in a processor using a slave free list

A processor including physical registers, a reorder buffer, a master free list, a slave free list, a master recycle circuit, and a slave recycle circuit. The reorder buffer includes instruction entries in which each entry stores physical register indexes for recycling physical registers. The reorder buffer retires up to N... Via Alliance Semiconductor Co Ltd

Multi-threading processor and a scheduling method thereof

A processor includes an execution unit, a retirement module, a first retirement counter, a second retirement counter, and an adjustment module. The execution unit executes instructions of a first thread and a second thread by simultaneous multithreading. The retirement module retires the executed instructions of the first thread in order... Via Alliance Semiconductor Co Ltd

System and automatic power control system and bias current control circuit

A bias-current-control circuit is provided. The bias-current-control circuit includes a transconductance circuit, a constant-current source, and a current-mirror circuit. The transconductance circuit is connected to a node and detects a voltage signal to generate a first current. The constant-current source is connected to the node and generates a tail current.... Via Alliance Semiconductor Co Ltd

Switch and data accessing method thereof

A switch for transmitting data packets between at least one source node and at least one target node is provided. The switch includes a storage unit, a control unit, at least one receiving port and at least one transmitting port. The storage unit includes a plurality of storage blocks and... Via Alliance Semiconductor Co Ltd

Methods for rdo (rate-distortion optimization) based on fit-curves and apparatuses using the same

A method for RDO (Rate-Distortion Optimization) based on fit-curves contains at least the following steps: calculating a first fit-curve and a second fit-curve according to information regarding a first frame; carrying information regarding a second frame into the first and second fit-curves to calculate fit distortions and fit bit counts;... Via Alliance Semiconductor Co Ltd

Graphics processing system and power gating method thereof

A graphics processing system and a power gating method thereof is provided. The graphics processing system includes a bus interface, a graphics processing unit, and a power management unit. The graphics processing unit includes a plurality of partitions and a control circuit. When the bus interface has received an external... Via Alliance Semiconductor Co Ltd

Processor with memory controller including dynamically programmable functional unit

A processor including a memory controller for interfacing an external memory and a programmable functional unit (PFU). The PFU is programmed by a PFU program to modify operation of the memory controller, in which the PFU includes programmable logic elements and programmable interconnectors. For example, the PFU is programmed by... Via Alliance Semiconductor Co Ltd

System and determining memory ownership on cache line basis for detecting self-modifying code including code with instruction that overlaps cache line boundaries

A system and method for determining memory ownership on a cache line basis for detecting self-modifying code with instructions that overlap cache line boundaries. An ownership index and a cache line address are entered into the ownership queue for each cache line. The cache lines are translated into instructions, and... Via Alliance Semiconductor Co Ltd

System and determining memory ownership on cache line basis for detecting self-modifying code

System and method of determining memory ownership on cache line basis for detecting self-modifying code. An ownership queue stores cache line addresses and corresponding ownership indexes. The cache line data is translated into instructions, and each instruction is provided with an ownership index of an associated entry in the ownership... Via Alliance Semiconductor Co Ltd

System and determining memory ownership on cache line basis for detecting self-modifying code including modification of a cache line with an executing instruction

A processor that determines memory ownership on a cache line basis for detecting self-modifying code including modification of a cache line with an executing instruction. An ownership index and corresponding cache line address are entered for each cache line into an ownership queue. The ownership index is provided with each... Via Alliance Semiconductor Co Ltd

System and determining memory ownership on cache line basis for detecting self-modifying code including code with looping instructions

A system and method of determining memory ownership on a cache line basis for detecting self-modifying code including code with looping instructions. An ownership queue includes multiple entries for determining memory ownership on a cache line basis. An ownership index and a wrap bit are determined for each cache line... Via Alliance Semiconductor Co Ltd

Dynamic powering of cache memory by ways within multiple set groups based on utilization trends

A set associative cache memory comprises an M×N memory array of storage entries arranged as M sets by N ways, both M and N are integers greater than one. Within each group of P mutually exclusive groups of the M sets, the N ways are separately powerable. A controller, for... Via Alliance Semiconductor Co Ltd

Sanitize-aware dram controller

A controller for controlling a dynamic random access memory (DRAM) comprising a plurality of blocks. A block is one or more units of storage in the DRAM for which the DRAM controller can selectively enable or disable refreshing. The DRAM controller includes flags each for association with a block of... Via Alliance Semiconductor Co Ltd

Image compressing method based on jpeg-ls

An image compression method based on JPEG-LS is presented. In the method, the M×N pixels in the source image are divided into k groups. M, N, and k are all integers larger than one. Each group corresponds to a plurality of pixels among the M×N pixels. The decorrelation procedure and... Via Alliance Semiconductor Co Ltd

Pre-driver for driving low voltage differential signaling (lvds) driving circuit

A pre-driver for driving an LVDS (Low Voltage Differential Signaling) driving circuit is provided. The pre-driver includes a first inverter, a high-pass filter, and a second inverter. The first inverter has an input terminal coupled to an input node of the pre-driver, and an output terminal coupled to a first... Via Alliance Semiconductor Co Ltd

Duty cycle calibration circuit

A duty cycle calibration circuit includes a first signal-generating circuit, receiving a clock signal to generate a first signal and a second signal, wherein the second signal and the first signal are the inverse of each other and synchronous. The calibration circuit also includes a first transmission gate, supplying a... Via Alliance Semiconductor Co Ltd

Host interface controller and control storage device

A host interface controller having a first buffer set and a second buffer set operated in a ping-pong buffer mode by a control module to alternately work as a pre-fetch buffer set. When one buffer set between the first buffer set and the second buffer set works as the pre-fetch... Via Alliance Semiconductor Co Ltd

Host interface controller and control storage device

A host interface controller with improved boot up efficiency, which uses a buffer mode setting register to set the operation mode of a first and a second buffer set provided within the host interface controller. When a cache memory of a central processing unit (CPU) at the host side has... Via Alliance Semiconductor Co Ltd

Stride reference prefetcher

A processor including a cache memory, processing logic, access logic, stride mask logic, count logic, arbitration logic, and a prefetcher. The processing logic submits load requests to access cache lines of a memory page. The access logic updates an access vector for the memory page, in which the access logic... Via Alliance Semiconductor Co Ltd

Method and device for image processing

A device for image processing includes a first queue, a second queue, a cache, and a processor. The first queue is capable of receiving a first image tile. The processor is electrically connected to the first queue, the second queue, and the cache, respectively. The processor is capable of obtaining... Via Alliance Semiconductor Co Ltd

Measuring device

A measurement device measuring a current passing through a detection resistor coupled between a first node and a second node is provided. An interference elimination unit is coupled to the first and second nodes and selectively outputs the voltage of at least one of the first and second nodes according... Via Alliance Semiconductor Co Ltd

Compiler system for a processor with an expandable instruction set architecture for dynamically configuring execution resources

A compiler system that converts an application source program into an executable program according to a predetermined ISA executable by a general purpose processor. The processor includes a PEU that is programmable to execute a UDI. The compiler system includes a PEU programming tool that converts a functional description of... Via Alliance Semiconductor Co Ltd

Conversion system for a processor with an expandable instruction set architecture for dynamically configuring execution resources

A conversion system that converts a standard executable program according to a predetermined ISA into a custom executable program executable by a general purpose processor. The processor includes a PEU that is programmable to execute a UDI. The conversion system includes a PEU programming tool that converts a functional description... Via Alliance Semiconductor Co Ltd

Processor with an expandable instruction set architecture for dynamically configuring execution resources

A processor with an expandable instruction set architecture for dynamically configuring execution resources. The processor includes a programmable execution unit (PEU) that may be programmed to perform a user-defined function in response to a user-defined instruction (UDI). The PEU includes programmable logic elements and programmable interconnectors that are collectively programmed... Via Alliance Semiconductor Co Ltd

Apparatuses for enqueuing kernels on a device-side

An apparatus for enqueuing kernels on a device-side is introduced to incorporate with at least a MXU (Memory Access Unit) and a CSP (Command Stream Processor): The CSP, after receiving a first command from the MXU, executes commands of a ring buffer, thereby enabling an EU (Execution Unit) to direct... Via Alliance Semiconductor Co Ltd

Computing resource controller and control multiple engines to share a shared resource

A computing resource controller controlling how multiple engines share a shared resource. The controller has an arbiter, a monitoring module, an arbiter strategy control center, and an arbiter parameter updating module. The arbiter allocates access rights to the shared resource to the engines. The monitor module monitors the demands for... Via Alliance Semiconductor Co Ltd

Processor with programmable prefetcher

A processor including a programmable prefetcher for prefetching information from an external memory. The programmable prefetcher includes a load monitor, a programmable prefetch engine, and a prefetch requester. The load monitor tracks load requests issued by the processor to retrieve information from the external memory. The programmable prefetch engine is... Via Alliance Semiconductor Co Ltd

Processor with programmable prefetcher

A processor including a front end, at least one load pipeline, and a memory system that further includes a programmable prefetcher for prefetching information from an external memory. The front end converts fetched program instructions into microinstructions including load microinstructions and dispatches microinstructions for execution. The load pipeline executes dispatched... Via Alliance Semiconductor Co Ltd

Host controller of high-speed data interface

A host controller with suppressed data jitter is shown, which uses a logical physical layer (LPHY) to provide groups of low-speed data, uses a clock-domain-crossing transmitter (TXCDC) to transmit the groups of the low-speed data to the corresponding electrical physical layers (EPHYs), uses the EPHYs to convert the groups of... Via Alliance Semiconductor Co Ltd

Computer system and operating method therefor

Code upgrades for computer components. After being powered on, a central processing unit (CPU) of a computer system loads a start-up authenticated code module (start-up ACM) to an authenticated code execution area (ACEA) within the CPU to be authenticated. When the start-up ACM passes authentication, the CPU executes the start-up... Via Alliance Semiconductor Co Ltd

Duty cycle calibration circuit

A signal-generating circuit includes a first P-type transistor, a second P-type transistor, a first N-type transistor, a second N-type transistor, a first inverter, a second inverter, and a third inverter. The first P-type transistor supplies a supply voltage to a first node according to an input signal. Both of the... Via Alliance Semiconductor Co Ltd

Digital-to-analog converter and high-voltage tolerance circuit

A digital-to-analog converter (DAC) and a high-voltage tolerance circuit are provided. The DAC includes a high-voltage tolerance circuit. The high-voltage tolerance circuit is configured to generate a reference voltage, and select the reference voltage or a first power-source voltage to control the node voltage of each branch of an operational... Via Alliance Semiconductor Co Ltd

06/08/17 / #20170163280

Axially and centrally symmetric current source array

A current source device having a current source array includes a plurality of current source units, a plurality of least significant bits, and a plurality of most significant bits. The current source units are arranged along a plurality rows and columns of a current source array. Each of the least... Via Alliance Semiconductor Co Ltd

06/08/17 / #20170163543

I/o circuit and data transmission control method

The arbiter receives the time-out transmission requests and the normal transmission requests, and selects one of the buffers from all of the time-out transmission requests and the normal transmission requests.... Via Alliance Semiconductor Co Ltd

06/01/17 / #20170153849

Methods and apparatuses for generating machine code for driving an execution unit

A method for generating machine code for driving an execution unit is introduced to incorporate with at least the following steps: Data access instructions of a kernel, which are associated with the same memory surface, are collected. An address pattern associated with the data access instructions is analyzed to generate... Via Alliance Semiconductor Co Ltd

06/01/17 / #20170154401

Method and device for processing graphics

A method for processing graphics is provided. The method includes: establishing streams corresponding to graphic layers drawn by at least one application; adding a one-shot signal to the end of the last stream of the streams; packaging the streams with the one-shot signal to form a packet; and transmitting the... Via Alliance Semiconductor Co Ltd

06/01/17 / #20170154447

Method and device for merging graphic layers

A method for merging graphic layers is provided. The method includes: receiving a plurality of graphic layers in a current frame; assigning sequence numbers to the graphic layers according to an overlay order; judging whether a first graphic layer and a second graphic layer vary in a period; merging the... Via Alliance Semiconductor Co Ltd

06/01/17 / #20170154448

Method and device for displaying graphic layers

A method for displaying graphic layers is provided. The method includes: receiving a plurality of graphic layers; assigning sequence numbers to the graphic layers according to an overlay order; assigning a weight value to each graphic layer according to a manner; establishing a layer order according to the sequence numbers... Via Alliance Semiconductor Co Ltd

06/01/17 / #20170154449

Method and device for displaying graphic layers

A method for displaying graphic layers is provided. The method includes: receiving a plurality of graphic layers; assigning sequence numbers to the graphic layers according to an overlay order; and displaying the graphic layers in a sequence order according to the sequence numbers.... Via Alliance Semiconductor Co Ltd

06/01/17 / #20170154653

Data reception chip

A data reception chip coupled to an external memory including a first input-output pin configured to output first data and including a comparison module and a voltage generation module is provided. The comparison module is coupled to the first input-output pin to receive the first data and to compare the... Via Alliance Semiconductor Co Ltd

06/01/17 / #20170154654

Control data reception chip

A control method for a data reception chip. The data reception chip includes a voltage generation module including a plurality of resistors and a selection unit. The resistors are connected in series with one another and divide an operation voltage to generate a plurality of divided voltages. The selection unit... Via Alliance Semiconductor Co Ltd

06/01/17 / #20170154669

Data reception chip

A data reception chip coupled to an external memory comprising a first input-output pin to output first data and including a comparison module and a voltage generation module is provided. The comparison module is coupled to the first input-output pin to receive the first data and compares the first data... Via Alliance Semiconductor Co Ltd

05/25/17 / #20170147426

Electronic device with recording functionality and recording thereof

An electronic device includes functional modules, gates, monitor module, signal control module and record module. The functional modules are operated on clock signal for generating request instruction and response signal. The gate is coupled to the functional modules for transmitting request instruction and response signal to functional module on enable... Via Alliance Semiconductor Co Ltd

05/25/17 / #20170148720

Circuit substrate and semiconductor package structure

A circuit substrate for a chip bonding thereon includes a core substrate having a chip-side surface and a bump-side surface opposite to the chip-side surface, a first through via plug passing through the core substrate, a pad disposed on the bump-side surface, in contact with the first through via plug,... Via Alliance Semiconductor Co Ltd

05/18/17 / #20170139592

Chipset and server system using the same

A chipset implemented in a server node of a server system and including an embedded management controller is disclosed. The chipset also includes a northbridge and southbridge. The embedded management controller collects inner-node information of the server node for server system management. The embedded management controller is coupled to a... Via Alliance Semiconductor Co Ltd

05/18/17 / #20170139718

System and speculative parallel execution of cache line unaligned load instructions

A system and method of performing speculative parallel execution of a cache line unaligned load instruction including speculatively predicting whether a load instruction is unaligned with a cache memory, marking the load instruction as unaligned and issuing the instruction to a scheduler, dispatching the unaligned load instruction in parallel to... Via Alliance Semiconductor Co Ltd

05/18/17 / #20170140496

Methods for checking dependencies of data units and apparatuses using the same

A memory-access completion notification associated with a data unit is received from a thread of a pixel shader. A processing status associated with the data unit is obtained from a window buffer. The processing status is updated to indicate that the data unit has not been processed by any thread.... Via Alliance Semiconductor Co Ltd

05/18/17 / #20170140499

Methods for checking dependencies of data units and apparatuses using the same

A memory access request associated with a data unit is received from a first thread of a pixel shader. A processing status associated with the data unit is obtained from a window buffer. It is determined whether the data unit is being processed by a second thread. If so, a... Via Alliance Semiconductor Co Ltd

05/18/17 / #20170140568

Methods for checking dependencies of data units and apparatuses using the same

A first request is received from a window checker, requesting to read cell data from a window buffer or write cell data into the window buffer, where the first request contains at least first cell index. A second request is received from a window releaser, requesting to read cell data... Via Alliance Semiconductor Co Ltd

05/04/17 / #20170123985

Prefetching with level of aggressiveness based on effectiveness by memory access type

A processor includes a prefetcher that prefetches data in response to memory accesses, wherein each memory access has an associated memory access type (MAT) of a plurality of predetermined MATs. The processor also includes a table that holds scores that indicate effectiveness of the prefetcher to prefetch data with respect... Via Alliance Semiconductor Co Ltd

05/04/17 / #20170124337

Chipset and host controller with capability of disk encryption

A chipset and a host controller, including a storage host controller for a storage device and an encryption and decryption engine that is implemented by hardware. The storage host controller analyzes a write command to obtain write command information, and provides the write command information and write data to the... Via Alliance Semiconductor Co Ltd

05/04/17 / #20170124684

Methods for blending resembling blocks and apparatuses using the same

A method for blending resembling blocks, performed by a processing unit, at least contains: determining a target block of a frame to be fused; determining a search window for the target block and obtaining m neighboring blocks from the search window; calculating the difference between the target block and each... Via Alliance Semiconductor Co Ltd

05/04/17 / #20170124729

Graphic data compression device and graphic data compression method

A graphic data compression device includes a processing unit for processing graphic data and a mixed-type compression unit for compressing the data processed by the processing unit. The mixed-type compression unit includes a lossless compression module and a nearly-lossless compression module. The lossless compression module performs a compression on processed... Via Alliance Semiconductor Co Ltd

04/13/17 / #20170102920

Neural network unit that performs stochastic rounding

A neural network unit includes a random bit source that generates random bits and a plurality of neural processing units (NPU). Each NPU includes an accumulator into which the NPU accumulates a plurality of products as an accumulated value and a rounder that receives the random bits from the random... Via Alliance Semiconductor Co Ltd

04/13/17 / #20170102921

Apparatus employing user-specified binary point fixed point arithmetic

An apparatus includes a plurality of arithmetic logic units each having an accumulator and an integer arithmetic unit that receives and performs integer arithmetic operations on integer inputs and accumulates integer results of a series of the integer arithmetic operations into the accumulator as an integer accumulated value. A register... Via Alliance Semiconductor Co Ltd

04/13/17 / #20170102940

Neural network unit with neural memory and array of neural processing units that collectively shift row of data received from neural memory

An array of N processing units (PU) each has: an accumulator; an arithmetic unit performs an operation on first, second and third inputs to generate a result to store in the accumulator, the first input receives the accumulator output; a weight input is received by the second input to the... Via Alliance Semiconductor Co Ltd

04/13/17 / #20170102941

Neural network unit with output buffer feedback and masking capability

An output buffer holds N words arranged as N/J mutually exclusive output buffer word groups (OBWG) of J words each. N processing units (PU) are arranged as N/J mutually exclusive PU groups each having an associated OBWG. Each PU has an accumulator, an arithmetic unit, and first and second multiplexed... Via Alliance Semiconductor Co Ltd

04/13/17 / #20170102945

Direct execution by an execution unit of a micro-operation loaded into an architectural register file by an architectural instruction of a processor

A processor includes an architectural register file loadable with micro-operations by architectural instructions of an architectural instruction set of the processor and an execution unit that executes instructions. The instructions are either architectural instructions or microinstructions into which architectural instructions are translated. The execution unit includes a decoder that decodes... Via Alliance Semiconductor Co Ltd

04/13/17 / #20170103040

Processor with variable rate execution unit

A processor has functional units that fetch and decode architectural instructions of an architectural instruction set at a first rate, a register that stores a value of an indicator programmable by execution of an architectural instruction of the architectural instruction set, and an execution unit. The execution unit includes a... Via Alliance Semiconductor Co Ltd

04/13/17 / #20170103041

Mechanism for communication between architectural program running on processor and non-architectural program running on execution unit of the processor regarding shared resource

Functional units of a processor fetch and decode architectural instructions of an architectural program. The architectural instructions are of an architectural instruction set of the processor. An execution unit includes first and second memories, a register and processing units. The first memory holds data in rows with addresses. The second... Via Alliance Semiconductor Co Ltd

04/13/17 / #20170103300

Tri-configuration neural network unit

A neural network unit configurable to first/second/third configurations has N narrow and N wide accumulators, multipliers and adders. Each multiplier performs a narrow/wide multiply on first and second narrow/wide inputs to generate a narrow/wide product. A first adder input receives a corresponding narrow/wide accumulator's output and third input receives a... Via Alliance Semiconductor Co Ltd

04/13/17 / #20170103301

Processor with architectural neural network execution unit

A processor has an instruction fetch unit that fetches ISA instructions from memory and execution units that perform operations on instruction operands to generate results according to the processor's ISA. A hardware neural network unit (NNU) execution unit performs computations associated with artificial neural networks (ANN). The NNU has an... Via Alliance Semiconductor Co Ltd

Patent Packs
04/13/17 / #20170103302

Neural network unit with neural processing units dynamically configurable to process multiple data sizes

A neural network unit. A register holds an indicator that specifies narrow and wide configurations. A first memory holds rows of 2N/N narrow/wide weight words in the narrow/wide configuration. A second memory holds rows of 2N/N narrow/wide data words in the narrow/wide configuration. An array of neural processing units (NPU)... Via Alliance Semiconductor Co Ltd

04/13/17 / #20170103303

Neural network unit with output buffer feedback for performing recurrent neural network computations

A neural network unit has at least one RAM, an output buffer and an array of neural processing units that: read first time step context layer node values from the output buffer; read second time step input layer node values from the RAM; generate second time step hidden layer node... Via Alliance Semiconductor Co Ltd

04/13/17 / #20170103304

Neural network unit with plurality of selectable output functions

A neural network unit includes a register programmable with a control value, a plurality of neural processing units (NPU), and a plurality of activation function units (AFU). Each NPU includes an arithmetic logic unit (ALU) that performs arithmetic and logical operations on a sequence of operands to generate a sequence... Via Alliance Semiconductor Co Ltd

04/13/17 / #20170103305

Neural network unit that performs concurrent lstm cell calculations

An output buffer holds N words arranged as N/J mutually exclusive output buffer word groups (OBWG) of J words each of the N words. N processing units (PU) are arranged as N/J mutually exclusive PU groups. Each PU group has an associated OBWG. Each PU includes an accumulator and an... Via Alliance Semiconductor Co Ltd

04/13/17 / #20170103306

Neural network unit with neural memory and array of neural processing units and sequencer that collectively shift row of data received from neural memory

An array of N processing units (PU) each has: an accumulator; an arithmetic unit performs an operation on first, second and third inputs to generate a result to store in the accumulator, the first input receives the accumulator output; a weight input is received by the second input to the... Via Alliance Semiconductor Co Ltd

04/13/17 / #20170103307

Processor with hybrid coprocessor/execution unit neural network unit

A processor includes a front-end portion that issues instructions to execution units that execute the issued instructions. A hardware neural network unit (NNU) execution unit includes a first memory that holds data words associated with artificial neural networks (ANN) neuron outputs, a second memory that holds weight words associated with... Via Alliance Semiconductor Co Ltd

04/13/17 / #20170103310

Multi-operation neural network unit

A neural network unit (NNU) includes N neural processing units (NPU). Each NPU has an arithmetic unit and an accumulator. First and second multiplexed registers of the N NPUs collectively selectively operate as respective first and second N-word rotaters. First and second memories respectively hold rows of N weight/data words... Via Alliance Semiconductor Co Ltd

04/13/17 / #20170103311

Neural network unit that performs convolutions using collective shift register among array of neural processing units

A neural network unit has a first memory that holds elements of a data matrix and a second memory that holds elements of a convolution kernel. An array of neural processing units (NPU) each have a multiplexed register that receives a corresponding element of a row from the first memory... Via Alliance Semiconductor Co Ltd

04/13/17 / #20170103312

Neural network unit with output buffer feedback and masking capability with processing unit groups that operate as recurrent neural network lstm cells

An output buffer holds N words arranged as N/J mutually exclusive output buffer word groups (OBWG) of J words each. N processing units (PU) are arranged as N/J mutually exclusive PU groups each having an associated OBWG. Each PU has an accumulator, arithmetic unit, and first and second multiplexed registers... Via Alliance Semiconductor Co Ltd

04/13/17 / #20170103319

Neural processing unit that selectively writes back to neural memory either activation function output or accumulator value

A neural network unit includes a programmable indicator, a first memory that holds first operands, a second memory that holds second operands, neural processing units (NPU), and activation units. Each NPU has an accumulator and an arithmetic unit that performs a series of multiply operations on pairs of the first... Via Alliance Semiconductor Co Ltd

04/13/17 / #20170103320

Neural network unit with shared activation function units

A neural network unit includes first and second memories that hold rows of respective N weight and data words and provides a row of them to N corresponding neural processing units (NPU), respectively. The N NPUs each have an accumulator and an arithmetic unit that performs a series of multiply... Via Alliance Semiconductor Co Ltd

04/13/17 / #20170103321

Neural network unit employing user-supplied reciprocal for normalizing an accumulated value

A neural network unit including a register programmable with a representation of a reciprocal value of a divisor and a plurality of neural processing units (NPU). Each NPU has an ALU, an accumulator, and a reciprocal multiplier unit. The ALU performs arithmetic and logical operations on a sequence of operands... Via Alliance Semiconductor Co Ltd

04/06/17 / #20170097824

Chained split execution of fused compound arithmetic operations

A microprocessor is configured for unchained and chained modes of split execution of a fused compound arithmetic operation. In both modes of split execution, a first execution unit executes only a first part of the fused compound arithmetic operation and produces an intermediate result thereof, and a second instruction execution... Via Alliance Semiconductor Co Ltd

03/30/17 / #20170090871

Methods and apparatuses for computing trigonometric functions with high precision

A method for computing trigonometric functions, performed by an ALU (Arithmetic Logic Unit) in coordination with an SFU (Special Function Unit), is introduced to contain at least the following steps. The ALU computes a remainder r and a reduction value x* corresponding to an input parameter x. The SFU computes... Via Alliance Semiconductor Co Ltd

03/30/17 / #20170090934

Microprocessor with fused reservation stations structure

A microprocessor with a fused reservation stations (RS) structure including a primary RS, a secondary RS, and a bypass system. The primary RS has an input for receiving issued instructions, has a push output for pushing the issued instructions to the secondary RS, and has at least one bypass output... Via Alliance Semiconductor Co Ltd

Patent Packs
03/02/17 / #20170060221

Power-control devices

A power-control device for generating and controlling a supply voltage is provided. The power-control device includes a variant delay chain with a delay length, a sampling circuit, a comparison circuit, and a power manager. The variant delay chain receives an initial signal and performs a delay operation on the initial... Via Alliance Semiconductor Co Ltd

03/02/17 / #20170060581

System and accelerating arbitration by approximating relative ages

An arbiter that performs accelerated arbitration by approximating relative ages including a memory, blur logic, and grant logic. Multiple entries arbitrate for one or more resources. The memory stores age values each providing a relative age between each pair of entries, and further stores blurred age values. The entries are... Via Alliance Semiconductor Co Ltd

03/02/17 / #20170060594

Methods for combining instructions and apparatuses having multiple data pipes

A method for combining instructions, performed by a compiler, containing at least the following steps. First instructions are obtained, where each performs one of a calculation operation, a comparison operation, a logic operation, a selection operation, a branching operation, a LD/ST (Load/Store) operation, a SMP (sampling) operation and a complicated... Via Alliance Semiconductor Co Ltd

03/02/17 / #20170064228

Methods for correcting bad pixels and apparatuses using the same

A method for correcting bad pixels, performed by a processing unit, at least contains: reading a block of a frame; labeling each pixel of the block as a good pixel, a weak pixel, or a bad pixel; detecting a weak-pixel pair from the block, which includes two pixels labeled as... Via Alliance Semiconductor Co Ltd

02/23/17 / #20170053379

Demosaicing methods and apparatuses using the same

A method for demosaicing, performed by a processing unit, at least containing: acquiring a frame with a Bayer pattern, wherein the Bayer pattern has alternating red (R), green (G) and blue (B) pixels; calculating a green (RG) value for each R pixel; calculating a green (BG) value for each B... Via Alliance Semiconductor Co Ltd

02/23/17 / #20170053429

Methods for programmable a primitive setup in a 3d graphics pipeline and apparatuses using the same

A method for a programmable primitive setup in a 3D graphics pipeline is introduced to contain at least the following steps. Information about first and third primitives is obtained from a buffer. The information about all or a portion of the first primitives is packed and sent to an SS... Via Alliance Semiconductor Co Ltd

02/02/17 / #20170034414

Methods for generating hdr (high dynamic range) images and apparatuses using the same

A method for generating HDR (High Dynamic Range) images, performed by a processing unit, is introduced to at least contain: acquiring a frame 0 and a frame 1; calculating a first MV (Motion Vector) between the frame 0 and the frame 1; acquiring a frame 2; predicting a second MV... Via Alliance Semiconductor Co Ltd








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This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. Freshpatents.com is not affiliated or associated with Via Alliance Semiconductor Co Ltd in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Via Alliance Semiconductor Co Ltd with additional patents listed. Browse our Agent directory for other possible listings. Page by FreshPatents.com

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