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Via Technologies Inc patents

Recent patent applications related to Via Technologies Inc. Via Technologies Inc is listed as an Agent/Assignee. Note: Via Technologies Inc may have other listings under different names/spellings. We're not affiliated with Via Technologies Inc, we're just tracking patents.

ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "V" | Via Technologies Inc-related inventors




Date Via Technologies Inc patents (updated weekly) - BOOKMARK this page
10/05/17Memory apparatus and energy-saving control method thereof
10/05/17Memory apparatus and energy-saving control method thereof
09/28/17Operating system and control method thereof
09/28/17Non-volatile memory apparatus and operating method thereof
09/28/17Non-volatile memory apparatus and operating method thereof
09/28/17Non-volatile memory apparatus and empty page detection method thereof
07/27/17Controller device and operation non-volatile memory with 3-dimensional architecture
07/20/17Non-volatile memory apparatus and on-the-fly self-adaptive read voltage adjustment method thereof
07/06/17Natural language comprehension system
05/04/17Non-volatile memory device and control method thereof
05/04/17Non-volatile memory device and read method thereof
05/04/17Optical transmitter and method thereof
04/20/17Apparatus and dynamically aligned source synchronous receiver
04/20/17Apparatus and dynamically aligned source synchronous receiver
04/13/17Apparatus and automatically aligning data signals and strobe signals on a source syncrhonous bus
04/13/17Apparatus and automatically aligning data signals and strobe signals on a source syncrhonous bus
04/13/17Apparatus and locally optimizing source synchronous data strobes
04/13/17Source synchronous data strobe misalignment compensation mechanism
04/06/17Event-based securing bios in a trusted computing system during execution
04/06/17Event-based securing bios in a trusted computing system during execution
04/06/17Event-based securing bios in a trusted computing system during execution
04/06/17Event-based securing bios in a trusted computing system during execution
04/06/17Event-based securing bios in a trusted computing system during execution
04/06/17Event-based securing bios in a trusted computing system during execution
04/06/17Event-based securing bios in a trusted computing system during execution
04/06/17Event-based securing bios in a trusted computing system during execution
03/16/17Sorting data documents and display sorting landmark data
03/09/17Multi-core microprocessor that dynamically designates one of its processing cores as the bootstrap processor
03/09/17Slicer apparatus and calibration method thereof
03/02/17Paddle card and plug-cable assembly
02/16/17Programmable secure bios mechanism in a trusted computing system
02/16/17Jtag-based secure bios mechanism in a trusted computing system
02/16/17Fuse-enabled secure bios mechanism in a trusted computing system
02/16/17Fuse-enabled secure bios mechanism with override feature
02/16/17Control circuit, connection line and control method thereof
02/09/17Memory chips and data protection methods
01/26/17Circuit substrate, semiconductor package and process for fabricating the same
01/05/17Single-core wakeup multi-core synchronization mechanism
01/05/17Control chip and control system utilizing the same
12/01/16Propagation of updates to per-core-instantiated architecturally-visible storage resource
10/27/16Interface chip and built-in self-test method therefor
10/27/16Battery management system
10/27/16Method for building language model, speech recognition method and electronic apparatus
10/06/16Programmable cable and programming method thereof
09/22/16Hub devices and methods for initializing hub device
09/15/16Adaptive contrast enhancement apparatus and method
09/08/16Usb chipset
09/01/16Hub, operation system, and control method thereof
08/18/16Microprocessor using compressed and uncompressed microcode storage
07/21/16Power management synchronization messaging system
07/21/16Domain-differentiated power state coordination system
07/14/16Microprocessor with arm and x86 instruction length decoders
07/07/16Smart door system and identification system background
06/30/16Power supply system and power control circuit thereof
06/23/16Power state transitioning procedure for a multi-core processor
06/09/16Centralized synchronization mechanism for a multi-core processor
06/09/16Asymmetric processor with cores that support different isa instruction subsets
05/26/16Integrated circuit device
05/26/16Integrated circuit device
04/21/16Dynamically updating hardware prefetch trait to exclusive or shared at program detection
04/21/16Dynamically updating hardware prefetch trait to exclusive or shared in multi-memory access agent system
04/21/16Hardware resource accessing accessing hardware resources in browser-based operating systems and machine-readable storage medium thereof
04/14/16Decryption of encrypted instructions using keys selected on basis of instruction fetch address
04/14/16Microprocessor with secure execution mode and store key instructions
04/14/16Microprocessor with on-the-fly switching of decryption keys
Patent Packs
04/14/16Key expansion logic using decryption key primitives
04/07/16Compressing instruction queue for a microprocessor
03/17/16Pin arrangement and electronic assembly
02/25/16Progress recording method and recovering encoding operation on storage device
01/21/16Through-hole layout structure, circuit board, and electronic assembly
12/10/15Audio decoding using modulator-demodulator
12/03/15Processor that leapfrogs mov instructions
12/03/15Delay line circuits and semiconductor integrated circuits
12/03/15Delay line circuits and semiconductor integrated circuits
11/26/15Mechanism for charging portable device with usb dock
11/26/15Multi-core restoring data arrays following a power gating event
11/26/15Multi-core data array power gating restoral mechanism
11/26/15Dynamically configurable system based on cloud-collaborative experimentation
11/26/15Multi-core microprocessor power gating cache restoral mechanism
11/26/15Apparatus and repairing cache arrays in a multi-core microprocessor
Patent Packs
11/26/15Semiconductor device having inductor
11/26/15Dynamic system configuration based on cloud-collaborative experimentation
11/12/15Flash memory control chip and data storage device and flash memory control method
11/05/15System and managing expansion read-only memory and management host thereof
10/29/15Flash memory controller and data storage device and flash memory control method
10/29/15Selective prefetching of physically sequential cache line to cache line that includes loaded page table entry
10/22/15Process for fabricating the same
10/22/15Isolation circuit
09/10/15System and assigning virtual functions and management host thereof
08/13/15Processor that performs approximate computing instructions
08/13/15Processor with approximate computing functional unit
08/13/15Data storage device and data checking and correction for volatile memory
08/13/15Processor that recovers from excessive approximate computing error
08/13/15Data storage device and data scrambling and descrambling method
08/13/15Electrostatic discharge protection device
07/30/15Dynamic cache enlarging by counting evictions
07/23/15Low-offset bandgap circuit and offset-cancelling circuit therein
07/23/15Optical transmission device and optical transceiver module
07/16/15Differential signal transmitters
07/09/15Memory chips and data protection methods
06/11/15Intermediate electronic device, operating the intermediate electronic device and electronic system
05/14/15Apparatus and securing bios in a trusted computing system
05/14/15Secure bios mechanism in a trusted computing system
05/14/15Event-based securing bios in a trusted computing system during execution
05/14/15Partition-based securing bios in a trusted computing system during execution
05/14/15Secure bios tamper protection mechanism
05/07/15Probe card
04/23/15Method for building acoustic model, speech recognition method and electronic apparatus
04/23/15Speech recognition method and electronic apparatus
04/23/15Method for building language model, speech recognition method and electronic apparatus
Social Network Patent Pack
04/23/15Speech recognition method and electronic apparatus using the method
04/23/15Microprocessor with compressed and uncompressed microcode memories
04/23/15Selectively compressed microcode
03/26/15Microprocessor with integrated nop slide detector
03/26/15Interface controller, external electronic device, and external electronic device control method
03/26/15Dynamically reconfigurable microprocessor
03/19/15Memory device and operating method thereof
03/12/15Adaptive usb charging method and system
03/05/15Circuit substrate, semicondutor package structure and process for fabricating a circuit substrate
03/05/15Single-core wakeup multi-core synchronization mechanism
Patent Packs
03/05/15Multi-core synchronization mechanism with interrupts on sync condition
03/05/15Dynamic designation of the bootstrap processor in a multi-core microprocessor
03/05/15Multi-core hardware semaphore
03/05/15Service processor patch mechanism
03/05/15Microprocessor with boot indicator that indicates a boot isa of the microprocessor as either the x86 isa or the arm isa
03/05/15Inter-core communication via uncore ram
03/05/15Propagation of updates to per-core-instantiated architecturally-visible storage resource
03/05/15Dynamic reconfiguration of multi-core processor
03/05/15Selective designation of multiple cores as bootstrap processor in a multi-core microprocessor
03/05/15Method for reducing power consumption in electronic apparatus
03/05/15Core synchronization mechanism in a multi-die multi-core microprocessor
03/05/15Multi-core synchronization mechanism
03/05/15Propagation of microcode patches to multiple cores in multicore microprocessor
02/26/15Apparatus and rapid fuse bank access in a multi-core processor
02/26/15Extended fuse reprogrammability mechanism
02/26/15Multi-core microprocessor configuration data compression and decompression system
02/26/15Microprocessor mechanism for decompression of cache correction data
02/26/15Apparatus and compression and decompression of microprocessor configuration data
02/26/15Multi-core fuse decompression mechanism
02/26/15Apparatus and extended cache correction
02/26/15Apparatus and compression of configuration data
02/26/15Apparatus and configurable redundant fuse banks
02/26/15Apparatus and storage and decompression of configuration data
02/26/15Core-specific fuse mechanism for a multi-core die
02/26/15Correctable configuration data compression and decompression system
02/19/15Common mode modulation with current compensation
02/12/15Image transmission apparatus and image processing method thereof
02/12/15Circuitry and driving laser with temperature compensation
02/12/15Optical transceiver modules, optical transmission devices, and optical transmission methods
02/12/15Dynamic and selective core disablement and reconfiguration in a multi-core processor
Patent Packs
01/15/15Data storage device and flash memory control method
01/15/15Method for using voiceprint identification to operate voice recognition and electronic device thereof
01/15/15Data storage device and flash memory control method
01/08/15Region labeling of data documents
01/08/15Sorting data documents and display sorting landmark data
01/01/15Multimedia broadcasting system in multiple node structure and multimedia broadcasting control method thereof
12/11/14Digital power gating with controlled resume
12/11/14Digital power gating with global voltage shift
12/11/14Digital power gating with programmable control parameter
11/27/14Microprocessor that fuses if-then instructions
10/30/14Fast dynamic register with transparent latch
10/30/14Scannable fast dynamic register
10/23/14External electronic device and interface controller and external electronic device control method
10/16/14State machine circuit and state adjusting method
10/16/14Transmittal system and connection device
10/16/14Voice control method and mobile terminal apparatus
10/16/14Voice control method, mobile terminal device, and voice control system
10/02/14Circuit substrate, semiconductor package and process for fabricating the same
10/02/14Uncore microcode rom
10/02/14Universal serial bus hub and control method thereof
Social Network Patent Pack
10/02/14Asymmetric multi-core processor with native switching mechanism
09/25/14Bounding box prefetcher
09/11/14Communicating prefetchers in a microprocessor
08/07/14Integrated circuit using i2c bus and control method thereof
08/07/14Non-volatile memory apparatus and operating method thereof
08/07/14Computer system having voice-control function and voice-control method
07/31/14Semiconductor device having inductor
07/24/14Output buffers
07/24/14Source synchronous bus signal alignment compensation mechanism
07/24/14Apparatus and dynamic alignment of source synchronous bus signals
07/24/14Apparatus and locally optimizing source synchronous data strobes
07/24/14Automatic source synchronous bus signal alignment compensation mechanism
07/24/14Apparatus and dynamically aligned source synchronous receiver
07/10/14Apparatus for generating a decryption key for use to decrypt a block of encrypted instruction data being fetched from an instruction cache in a microprocessor
07/10/14Method for encrypting a program for subsequent execution by a microprocessor configured to decrypt and execute the encrypted program
07/10/14Microprocessor that securely decrypts and executes encrypted instructions
07/10/14Microprocessor that facilitates task switching between encrypted and unencrypted programs
07/10/14Method for power management and an electronic system using the same
07/03/14Method for correcting a speech response and natural language dialogue system
07/03/14Natural language dialogue method and natural language dialogue system
Social Network Patent Pack
07/03/14Search method, search system, and natural language comprehension system
06/19/14Soft-start circuits and power suppliers using the same
06/19/14Power state synchronization in a multi-core processor
06/12/14Distributed management of a shared clock source to a multi-core microprocessor
05/29/14Voice control device and voice control method
05/15/14Battery management system and electric vehicle
05/08/14Electronic device and booting method
04/24/14Progress recording method and recovering encoding operation on storage device
04/24/14Electronic device and secure boot method
04/24/14Method and rendering overlapped objects
04/10/14Power supply system and power control circuit thereof
04/03/14Display system and display video wall
03/27/14Multi-core dies produced by reticle set modification
03/27/14Transmission circuit for i/o interface and signal transmission method thereof
03/20/14Circuit substrate and process for fabricating the same
02/27/14Usb transaction translator and usb transaction translation method
02/27/14Revokeable msr password protection
02/13/14Data transmission system and method thereof
02/13/14Wireless video camera and connection methods including a usb emulation
01/23/14Hardware resource accessing accessing hardware resources in browser-based operating systems and machine-readable storage medium thereof
01/09/14Prefetching of next physically sequential cache line after cache line that includes loaded page table entry
01/09/14Conditional load instructions in an out-of-order execution microprocessor
01/02/14Circuit substrate
01/02/14Data prefetcher with complex stride predictor
12/19/13De-noise circuit and de-noise differential signals and chip for receiving differential signals
12/12/13Saturation detector
12/05/13Graphics processing unit and management method thereof
11/28/13Deadlock/livelock resolution using service processor
11/21/13Running state power saving via reduced instructions per clock operation
11/14/13Hub control chip
Social Network Patent Pack
11/14/13Microprocessor that makes 64-bit general purpose registers available in msr address space while operating in non-64-bit mode
11/14/13Microprocessor that enables arm isa program to access 64-bit general purpose registers written by x86 isa program
11/07/13Operation system and control method thereof
10/10/13Cloud-computing graphic server
10/03/13Method of managing multiple wireless video traffic and electronic device thereof
09/05/13Receiver and signal testing method thereof
08/29/13Frequency-control circuits and signal generation devices using the same
08/29/13Networked applications with client-caching of executable modules
08/22/13Fabricating circuit board and circuit board
07/25/13Rechargeable battery module and battery charging method
07/25/13Rechargeable battery module and battery charging method
07/25/13Discharge curve calibration system and calibration initial discharging curve of battery
07/25/13Usb hub for supplying power and method thereof
07/11/13Chip package structure
07/11/13Data transmission methods and hub devices utilizing the same
07/11/13Multi-core processor system, dynamic power management method thereof and control apparatus thereof
07/11/13Systems and methods for error checking and correcting for memory module
06/27/13Image codec engine
06/13/13Capacitor structure
06/13/13Usb charging module
06/13/13Apparatus for coupling to a usb device and a host and method thereof
06/13/13Bridging device and power saving method thereof
05/23/13Active optical cable and electronic device using the same
05/23/13Bridging device and power saving method thereof
05/16/13Circuit and controlling battery
05/09/13Single-point-multi-finger gestures for touch panel
05/09/13Electrostatic discharge protection device
04/25/13Duty adjustment circuits and signal generation devices using the same
04/25/13Computer distributing interrupt tasks thereof







ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009



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