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Via Technologies Inc patents


Recent patent applications related to Via Technologies Inc. Via Technologies Inc is listed as an Agent/Assignee. Note: Via Technologies Inc may have other listings under different names/spellings. We're not affiliated with Via Technologies Inc, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "V" | Via Technologies Inc-related inventors


 new patent  Low-density parity-check apparatus and operation method thereof

The ldpc apparatus includes an ldpc iteration calculating circuit, a decision-bit storage circuit, and a convergence detection circuit. The ldpc iteration calculating circuit performs an ldpc iteration calculation to obtain a new decision bit value of a corresponding variable node. ... Via Technologies Inc

 new patent  Low-density parity-check apparatus and matrix trapping set breaking method

A low-density parity-check (ldpc) apparatus and a matrix trapping set breaking method are provided. The ldpc apparatus includes a logarithm likelihood ratio (llr) mapping circuit, a variable node (vn) calculation circuit, an adjustment circuit, a check nodes (cn) calculation circuit and a controller. ... Via Technologies Inc

 new patent  Non-volatile memory apparatus and garbage collection method thereof

A non-volatile memory (nvm) apparatus and a garbage collection method thereof are provided. The nvm apparatus includes a nvm and a controller. ... Via Technologies Inc

 new patent  Non-volatile memory apparatus and iteration sorting method thereof

A non-volatile memory (nvm) apparatus and an iteration sorting method thereof are provided. The nvm apparatus performs the iteration sorting method to select one target block from a plurality of blocks of a nvm, and to perform a management operation on the target block. ... Via Technologies Inc

 new patent  Interface chip and test method therefor

A built-in self-test mechanism for an interface chip. During a loopback test procedure, a transmission terminal of the interface chip is coupled back to the interface chip by a reception terminal of the interface chip and a loopback test circuit within the interface chip generates a test sequence which includes a synchronization section and a section of repeated test code. ... Via Technologies Inc

Paddle card and plug-cable assembly

A paddle card includes a circuit board, a pad group and first to fourth shielding planes. The circuit board has an upper surface and a lower surface opposite to each other. ... Via Technologies Inc

Non-volatile memory apparatus and address classification method thereof

A non-volatile memory (nvm) apparatus and an address classification method thereof are provided. The nvm apparatus includes a nvm and a controller. ... Via Technologies Inc

Charger and power delivery control chip and charging method thereof

A charger and a power delivery control chip and a charging method thereof are provided. Resistance values of equivalent resistances corresponding to a power supply bus are calculated according to a charging current and voltage sensing signals respectively provided by chips of a first connector and a second connector. ... Via Technologies Inc

Bridge device

A bridge device including a first connector, a first transceiver, a second connector, a second transceiver, a voltage processor, and a controller is provided. The first connector is configured to couple to a host and includes a first pin. ... Via Technologies Inc

Energy regulation circuit and operation system utilizing the same

An energy regulation circuit is provided. A first voltage regulator adjusts an input voltage to generate an adjustment voltage. ... Via Technologies Inc

Energy regulation circuit and operation system utilizing the same

An energy regulation circuit including a first voltage regulator, a processor, a second voltage regulator, and a controller is provided. The first voltage regulator adjusts an input voltage to generate an adjustment voltage. ... Via Technologies Inc

Microprocessor that fuses if-then instructions

A microprocessor performs an if-then (it) instruction and an associated it block by extracting condition information from the it instruction and for each instruction of the it block: determining a respective condition for the instruction using the extract condition information, translating the instruction into a microinstruction, and conditionally executing the microinstruction based on the respective condition. For a first instruction, the translating comprises fusing the it instruction with the first it block instruction. ... Via Technologies Inc

Semiconductor device having inductor

A semiconductor device includes first and second winding portions disposed in a first level of an insulating layer and surrounding a center region thereof. Each of the winding portions includes conductive lines arranged from the inside to the outside. ... Via Technologies Inc

Method and apparatus for processing surrounding images of vehicle

A method and an apparatus for processing surrounding images of a vehicle are provided. In the method, plural cameras disposed on the vehicle are used to capture images of plural perspective views surrounding the vehicle. ... Via Technologies Inc

11/09/17 / #20170324943

Driver-assistance method and a driver-assistance apparatus

A driver-assistance method and a driver-assistance apparatus are provided. In the method, a movement trajectory of wheels in surroundings of a vehicle when the vehicle moves are calculated. ... Via Technologies Inc

10/05/17 / #20170285989

Memory apparatus and energy-saving control method thereof

A memory apparatus and an energy-saving control method thereof are provided. The internal clock signal sent to a specific circuit group is stopped outputting when it is determined that no processing command is to be processed currently and current events are finished being processed, so as to reduce power consumption of a control chip.. ... Via Technologies Inc

10/05/17 / #20170285718

Memory apparatus and energy-saving control method thereof

A memory apparatus and an energy-saving control method thereof are provided. The memory apparatus includes a plurality of non-volatile memory units and a control chip, and the control chip includes a specific circuit group, a memory control unit and an energy-saving control unit. ... Via Technologies Inc

09/28/17 / #20170277589

Non-volatile memory apparatus and empty page detection method thereof

A non-volatile memory (nvm) apparatus and an empty page detection method thereof are provided. The nvm apparatus includes a nvm and a controller. ... Via Technologies Inc

09/28/17 / #20170277472

Non-volatile memory apparatus and operating method thereof

A non-volatile memory apparatus including a non-volatile storage circuit, a main memory and a controller, and an operating method thereof are provided. Each of a plurality of logical block address groups includes a plurality of logical block addresses. ... Via Technologies Inc

09/28/17 / #20170277471

Non-volatile memory apparatus and operating method thereof

A non-volatile memory apparatus including a non-volatile storage circuit, a main memory and a controller, and an operating method thereof are provided. Each of a plurality of logical block address groups includes a plurality of logical block addresses. ... Via Technologies Inc

09/28/17 / #20170277240

Operating system and control method thereof

An operating system including a voltage converter, a processing circuit, and a protector is provided. The voltage converter converts an input voltage according to a feedback voltage to generate an output voltage. ... Via Technologies Inc

07/27/17 / #20170212801

Controller device and operation method for non-volatile memory with 3-dimensional architecture

A controller device and an operation method for a non-volatile memory with 3-dimensional architecture are provided. The controller device includes an error checking and correcting (ecc) circuit and a controller. ... Via Technologies Inc

07/20/17 / #20170206953

Non-volatile memory apparatus and on-the-fly self-adaptive read voltage adjustment method thereof

A non-volatile memory apparatus includes a non-volatile storage circuit and a controller. The non-volatile storage circuit reads a corresponding data voltage set, and converts the corresponding data voltage set to the corresponding data in accordance with the read-voltage parameter of the controller. ... Via Technologies Inc

07/06/17 / #20170193038

Natural language comprehension system

A search method, a search system, and a natural language comprehension system are provided. The search system includes a structured database and a search engine. ... Via Technologies Inc

05/04/17 / #20170124860

Optical transmitter and method thereof

A method and an optical transmitter utilizing the same are provided. The method, adopted by an optical transmitter, transmitting data signal and control signal to an optical receiver of an target device, including: providing a data signal in a first frequency band; providing a control signal in a second frequency band; combining the data signal in the first frequency band and the control signal in the second frequency band to generate a combined signal; and converting the combined signal into an outgoing optical signal to be transmitted to the optical receiver; wherein the control signal is arranged for controlling the target device.. ... Via Technologies Inc

05/04/17 / #20170123905

Non-volatile memory device and read method thereof

A non-volatile memory device including a non-volatile memory and a controller is provided. The controller establishes a standard table and at least one priority table according to a read table stored in the non-volatile memory. ... Via Technologies Inc

05/04/17 / #20170123870

Non-volatile memory device and control method thereof

A non-volatile memory device including a non-volatile memory and a controller is provided. The non-volatile memory includes a plurality of closed blocks and a plurality of open blocks. ... Via Technologies Inc

04/20/17 / #20170110163

Apparatus and method for dynamically aligned source synchronous receiver

An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a replica radial distribution element, a bit lag control element, and a synchronous lag receiver. ... Via Technologies Inc

04/20/17 / #20170109306

Apparatus and method for dynamically aligned source synchronous receiver

A method is provided that compensates for misalignment on a synchronous data bus. The method includes: replicating propagation path lengths, loads, and buffering of a radial distribution network for a strobe; receiving a first signal, and generating a second signal by employing the replicated propagation path lengths, loads, and buffering; when an update signal is asserted, when an update signal is asserted, measuring a propagation time beginning with assertion of the first signal and ending with assertion of the second signal by selecting one of a plurality of successively delayed versions of the first signal that coincides with the assertion of the second signal, wherein said selecting comprises incrementing and decrementing bus states of select inputs on a mux, wherein the plurality of successively delayed versions of the first signal comprises inputs to the mux; gray encoding a value on a lag bus that indicates the propagation time; and receiving one of a plurality of radially distributed strobes and a data bit, and delaying registering of the data bit by the propagation time. ... Via Technologies Inc

04/13/17 / #20170103790

Source synchronous data strobe misalignment compensation mechanism

An apparatus is provided that compensates for misalignment on a synchronous data bus, the apparatus includes a replica radial distribution element, a bit lag control element, and a synchronous lag receiver. The replica radial distribution element is configured to receive a lag pulse signal, and is configured to generate a replicated strobe signal, where the replica radial distribution network includes replicated propagation path lengths, loads, and buffering of a radial distribution network for a strobe. ... Via Technologies Inc

04/13/17 / #20170103035

Apparatus and method for locally optimizing source synchronous data strobes

An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a replica radial distribution element, a bit lag control element, and a synchronous lag receiver. ... Via Technologies Inc

04/13/17 / #20170102734

Apparatus and method for automatically aligning data signals and strobe signals on a source syncrhonous bus

An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a replica radial distribution element, a joint test action group (jtag) interface, and a bit lag control element. ... Via Technologies Inc

04/13/17 / #20170102733

Apparatus and method for automatically aligning data signals and strobe signals on a source syncrhonous bus

An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a replica radial distribution element, a joint test action group (jtag) interface, and a bit lag control element. ... Via Technologies Inc

04/06/17 / #20170098083

Event-based apparatus and method for securing bios in a trusted computing system during execution

An apparatus is provided for protecting a basic input/output system (bios) in a computing system. The apparatus includes a bios read only memory (rom), an event detector, and a tamper detector. ... Via Technologies Inc

04/06/17 / #20170098082

Event-based apparatus and method for securing bios in a trusted computing system during execution

An apparatus is provided for protecting a basic input/output system (bios) in a computing system. The apparatus includes a bios read only memory (rom), an event detector, and a tamper detector. ... Via Technologies Inc

04/06/17 / #20170098081

Event-based apparatus and method for securing bios in a trusted computing system during execution

An apparatus is provided for protecting a basic input/output system (bios) in a computing system. The apparatus includes a bios read only memory (rom), an event detector, and a tamper detector. ... Via Technologies Inc

04/06/17 / #20170098080

Event-based apparatus and method for securing bios in a trusted computing system during execution

An apparatus is provided for protecting a basic input/output system (bios) in a computing system. The apparatus includes a bios read only memory (rom), an event detector, and a tamper detector. ... Via Technologies Inc

04/06/17 / #20170098079

Event-based apparatus and method for securing bios in a trusted computing system during execution

An apparatus is provided for protecting a basic input/output system (bios) in a computing system. The apparatus includes a bios read only memory (rom), an event detector, and a tamper detector. ... Via Technologies Inc

04/06/17 / #20170098078

Event-based apparatus and method for securing bios in a trusted computing system during execution

An apparatus is provided for protecting a basic input/output system (bios) in a computing system. The apparatus includes a bios read only memory (rom), an event detector, and a tamper detector. ... Via Technologies Inc

04/06/17 / #20170098077

Event-based apparatus and method for securing bios in a trusted computing system during execution

An apparatus is provided for protecting a basic input/output system (bios) in a computing system. The apparatus includes a bios read only memory (rom), an event detector, and a tamper detector. ... Via Technologies Inc

04/06/17 / #20170098076

Event-based apparatus and method for securing bios in a trusted computing system during execution

An apparatus is provided for protecting a basic input/output system (bios) in a computing system. The apparatus includes a bios read only memory (rom), an event detector, and a tamper detector. ... Via Technologies Inc

03/16/17 / #20170075911

Sorting method of data documents and display method for sorting landmark data

A sorting method of data documents is provided, adapted to an electronic device. The sort method includes the following steps: retrieving a plurality of keywords from contents of a plurality of data documents; retrieving a keyword ranking corresponding to the at least one first keyword by a search engine; searching a keyword category corresponding to the at least one first keyword; and inputting the at least one first keyword, the keyword ranking and the keyword category of each of the at least one first keyword into a sort algorithm thereby outputting a predicting ranking of the first data document to sort the first data document, wherein the sort algorithm is generated based on contents of a plurality of second data documents and a current ranking of each of the plurality of second data documents.. ... Via Technologies Inc

03/09/17 / #20170070373

Slicer apparatus and calibration method thereof

A slicer apparatus and a calibration method thereof are provided. A differential reference signal pair used for performing an error slicing operation is adjusted, so as to calibrate an offset voltage of the slicer apparatus.. ... Via Technologies Inc

03/09/17 / #20170068546

Multi-core microprocessor that dynamically designates one of its processing cores as the bootstrap processor

A microprocessor includes an indicator and a plurality of processing cores. Each of the plurality of processing cores is configured to generate a default core id and to sample the indicator. ... Via Technologies Inc

03/02/17 / #20170062991

Paddle card and plug-cable assembly

A paddle card includes a circuit board, a pad group and ground planes. The circuit board has an upper surface and a lower surface opposite to each other. ... Via Technologies Inc

02/16/17 / #20170047908

Control circuit, connection line and control method thereof

A control circuit disposed in a connection line including a first power pin and a second power pin and including a native n-type transistor, a first impedance unit, and a second impedance unit is provided. The native n-type transistor includes a first gate, a first drain and a first source. ... Via Technologies Inc

02/16/17 / #20170046517

Fuse-enabled secure bios mechanism with override feature

An apparatus is provided for protecting a basic input/output system (bios) in a computing system. The apparatus includes a bios read only memory (rom), a tamper detector, a random number generator, a jtag control chain, a fuse, a machine specific register, and an access controller. ... Via Technologies Inc

02/16/17 / #20170046516

Fuse-enabled secure bios mechanism in a trusted computing system

An apparatus is provided for protecting a basic input/output system (bios) in a computing system. The apparatus includes a bios read only memory (rom), a tamper detector, a random number generator, a jtag control chain, a fuse, and an access controller. ... Via Technologies Inc

02/16/17 / #20170046515

Jtag-based secure bios mechanism in a trusted computing system

An apparatus is provided for protecting a basic input/output system (bios) in a computing system. The apparatus includes a bios read only memory (rom), a tamper detector, a random number generator, and a jtag control chain. ... Via Technologies Inc

02/16/17 / #20170046514

Programmable secure bios mechanism in a trusted computing system

An apparatus is provided for protecting a basic input/output system (bios) in a computing system. The apparatus includes a bios read only memory (rom), a tamper detector, a random number generator, and a jtag control chain. ... Via Technologies Inc

02/09/17 / #20170038988

Memory chips and data protection methods

A memory chip coupled to a host includes a memory and a controller. The memory is pre-loaded with a plurality of boot images, wherein the boot images have the same content. ... Via Technologies Inc

01/26/17 / #20170025343

Circuit substrate, semiconductor package and process for fabricating the same

A circuit substrate has the following elements. A stacked circuit structure has a first surface and a second surface opposite thereto surface. ... Via Technologies Inc

01/05/17 / #20170005648

Control chip and control system utilizing the same

A control chip coupled to a first input/output pin and a second input/output pin and including a first interface module, a second interface module, a first switching unit, and a control unit is provided. The first interface module includes a first pin electrically connected to the first input/output pin and a second pin. ... Via Technologies Inc

01/05/17 / #20170003707

Single-core wakeup multi-core synchronization mechanism

A microprocessor includes a plurality of cores, a shared cache memory, and a control unit that individually puts each core to sleep by stopping its clock signal. Each core executes a sleep instruction and responsively makes a respective request of the control unit to put the core to sleep, which the control unit responsively does, and detects when all the cores have made the respective request and responsively wakes up only the last requesting cores. ... Via Technologies Inc








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