Real Time Touch



new TOP 200 Companies filing patents this week

new Companies with the Most Patent Filings (2010+)




Real Time Touch

Similar
Filing Names

Via Technologies Inc
Via Technologies Inc_20100107
Via Technologies Inc_20131212
Via Technologies Inc_20100114

Via Technologies Inc patents


Recent patent applications related to Via Technologies Inc. Via Technologies Inc is listed as an Agent/Assignee. Note: Via Technologies Inc may have other listings under different names/spellings. We're not affiliated with Via Technologies Inc, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "V" | Via Technologies Inc-related inventors


Semiconductor device having inductor

A semiconductor device includes first and second winding portions disposed in a first level of an insulating layer and surrounding a center region thereof. Each of the winding portions includes conductive lines arranged from the inside to the outside. First and second extending conductive lines are disposed in the first... Via Technologies Inc

Driver-assistance method and a driver-assistance apparatus

A driver-assistance method and a driver-assistance apparatus are provided. In the method, a movement trajectory of wheels in surroundings of a vehicle when the vehicle moves are calculated. Multiple cameras disposed on the vehicle are used to capture images of multiple perspective views surrounding the vehicle, and the images of... Via Technologies Inc

Method and processing surrounding images of vehicle

A method and an apparatus for processing surrounding images of a vehicle are provided. In the method, plural cameras disposed on the vehicle are used to capture images of plural perspective views surrounding the vehicle. The images of the perspective views are transformed into images of a top view. An... Via Technologies Inc

Memory apparatus and energy-saving control method thereof

A memory apparatus and an energy-saving control method thereof are provided. The memory apparatus includes a plurality of non-volatile memory units and a control chip, and the control chip includes a specific circuit group, a memory control unit and an energy-saving control unit. The memory control unit controls an access... Via Technologies Inc

Memory apparatus and energy-saving control method thereof

A memory apparatus and an energy-saving control method thereof are provided. The internal clock signal sent to a specific circuit group is stopped outputting when it is determined that no processing command is to be processed currently and current events are finished being processed, so as to reduce power consumption... Via Technologies Inc

Operating system and control method thereof

An operating system including a voltage converter, a processing circuit, and a protector is provided. The voltage converter converts an input voltage according to a feedback voltage to generate an output voltage. The processing circuit is coupled to the voltage converter and processes the output voltage according to a control... Via Technologies Inc

Non-volatile memory apparatus and operating method thereof

A non-volatile memory apparatus including a non-volatile storage circuit, a main memory and a controller, and an operating method thereof are provided. Each of a plurality of logical block address groups includes a plurality of logical block addresses. Each of the logical block address groups is assigned a group read-count... Via Technologies Inc

Non-volatile memory apparatus and operating method thereof

A non-volatile memory apparatus including a non-volatile storage circuit, a main memory and a controller, and an operating method thereof are provided. Each of a plurality of logical block address groups includes a plurality of logical block addresses. Each of the logical block address groups is assigned with a group... Via Technologies Inc

Non-volatile memory apparatus and empty page detection method thereof

A non-volatile memory (NVM) apparatus and an empty page detection method thereof are provided. The NVM apparatus includes a NVM and a controller. The controller reads the content of a memory page of the NVM. The controller performs Low Density Parity Check (LDPC) decoding for at least one codeword of... Via Technologies Inc

Controller device and operation non-volatile memory with 3-dimensional architecture

A controller device and an operation method for a non-volatile memory with 3-dimensional architecture are provided. The controller device includes an error checking and correcting (ECC) circuit and a controller. The controller is coupled to the non-volatile memory and the ECC circuit. The controller may access a target wordline of... Via Technologies Inc

Non-volatile memory apparatus and on-the-fly self-adaptive read voltage adjustment method thereof

A non-volatile memory apparatus includes a non-volatile storage circuit and a controller. The non-volatile storage circuit reads a corresponding data voltage set, and converts the corresponding data voltage set to the corresponding data in accordance with the read-voltage parameter of the controller. The controller decides whether to perform the on-the-fly... Via Technologies Inc

Natural language comprehension system

A search method, a search system, and a natural language comprehension system are provided. The search system includes a structured database and a search engine. The structured database stores a plurality of records, each of which has a title field and a content field. The title field includes at least... Via Technologies Inc

Non-volatile memory device and control method thereof

A non-volatile memory device including a non-volatile memory and a controller is provided. The non-volatile memory includes a plurality of closed blocks and a plurality of open blocks. The controller derives a ratio value according to the write workload of the non-volatile memory between a first time point and a... Via Technologies Inc

Non-volatile memory device and read method thereof

A non-volatile memory device including a non-volatile memory and a controller is provided. The controller establishes a standard table and at least one priority table according to a read table stored in the non-volatile memory. The probability that the controller utilizes the read voltages corresponding to the indexes recorded in... Via Technologies Inc

Optical transmitter and method thereof

A method and an optical transmitter utilizing the same are provided. The method, adopted by an optical transmitter, transmitting data signal and control signal to an optical receiver of an target device, including: providing a data signal in a first frequency band; providing a control signal in a second frequency... Via Technologies Inc

Apparatus and dynamically aligned source synchronous receiver

A method is provided that compensates for misalignment on a synchronous data bus. The method includes: replicating propagation path lengths, loads, and buffering of a radial distribution network for a strobe; receiving a first signal, and generating a second signal by employing the replicated propagation path lengths, loads, and buffering;... Via Technologies Inc

Apparatus and dynamically aligned source synchronous receiver

An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a replica radial distribution element, a bit lag control element, and a synchronous lag receiver. The replica radial distribution element is configured to receive a first signal, and is configured to generate a second... Via Technologies Inc

Apparatus and automatically aligning data signals and strobe signals on a source syncrhonous bus

An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a replica radial distribution element, a Joint Test Action Group (JTAG) interface, and a bit lag control element. The replica radial distribution element is configured to receive a lag pulse signal, and is configured... Via Technologies Inc

Apparatus and automatically aligning data signals and strobe signals on a source syncrhonous bus

An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a replica radial distribution element, a Joint Test Action Group (JTAG) interface, and a bit lag control element. The replica radial distribution element is configured to receive a lag pulse signal, and is configured... Via Technologies Inc

Apparatus and locally optimizing source synchronous data strobes

An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a replica radial distribution element, a bit lag control element, and a synchronous lag receiver. The replica radial distribution element is configured to receive a lag pulse signal, and is configured to generate a... Via Technologies Inc

Source synchronous data strobe misalignment compensation mechanism

An apparatus is provided that compensates for misalignment on a synchronous data bus, the apparatus includes a replica radial distribution element, a bit lag control element, and a synchronous lag receiver. The replica radial distribution element is configured to receive a lag pulse signal, and is configured to generate a... Via Technologies Inc

Event-based securing bios in a trusted computing system during execution

An apparatus is provided for protecting a basic input/output system (BIOS) in a computing system. The apparatus includes a BIOS read only memory (ROM), an event detector, and a tamper detector. The BIOS ROM has BIOS contents that are stored as plaintext, and an encrypted message digest, where the encrypted... Via Technologies Inc

Event-based securing bios in a trusted computing system during execution

An apparatus is provided for protecting a basic input/output system (BIOS) in a computing system. The apparatus includes a BIOS read only memory (ROM), an event detector, and a tamper detector. The BIOS ROM has BIOS contents that are stored as plaintext, and an encrypted message digest, where the encrypted... Via Technologies Inc

Event-based securing bios in a trusted computing system during execution

An apparatus is provided for protecting a basic input/output system (BIOS) in a computing system. The apparatus includes a BIOS read only memory (ROM), an event detector, and a tamper detector. The BIOS ROM has BIOS contents that are stored as plaintext, and an encrypted message digest, where the encrypted... Via Technologies Inc

Event-based securing bios in a trusted computing system during execution

An apparatus is provided for protecting a basic input/output system (BIOS) in a computing system. The apparatus includes a BIOS read only memory (ROM), an event detector, and a tamper detector. The BIOS ROM has BIOS contents that are stored as plaintext, and an encrypted message digest, where the encrypted... Via Technologies Inc

Event-based securing bios in a trusted computing system during execution

An apparatus is provided for protecting a basic input/output system (BIOS) in a computing system. The apparatus includes a BIOS read only memory (ROM), an event detector, and a tamper detector. The BIOS ROM has BIOS contents that are stored as plaintext, and an encrypted message digest, where the encrypted... Via Technologies Inc

Event-based securing bios in a trusted computing system during execution

An apparatus is provided for protecting a basic input/output system (BIOS) in a computing system. The apparatus includes a BIOS read only memory (ROM), an event detector, and a tamper detector. The BIOS ROM has BIOS contents that are stored as plaintext, and an encrypted message digest, where the encrypted... Via Technologies Inc

Event-based securing bios in a trusted computing system during execution

An apparatus is provided for protecting a basic input/output system (BIOS) in a computing system. The apparatus includes a BIOS read only memory (ROM), an event detector, and a tamper detector. The BIOS ROM has BIOS contents that are stored as plaintext, and an encrypted message digest, where the encrypted... Via Technologies Inc

Event-based securing bios in a trusted computing system during execution

An apparatus is provided for protecting a basic input/output system (BIOS) in a computing system. The apparatus includes a BIOS read only memory (ROM), an event detector, and a tamper detector. The BIOS ROM has BIOS contents that are stored as plaintext, and an encrypted message digest, where the encrypted... Via Technologies Inc

Sorting data documents and display sorting landmark data

A sorting method of data documents is provided, adapted to an electronic device. The sort method includes the following steps: retrieving a plurality of keywords from contents of a plurality of data documents; retrieving a keyword ranking corresponding to the at least one first keyword by a search engine; searching... Via Technologies Inc

Multi-core microprocessor that dynamically designates one of its processing cores as the bootstrap processor

A microprocessor includes an indicator and a plurality of processing cores. Each of the plurality of processing cores is configured to generate a default core ID and to sample the indicator. When the indicator indicates a first predetermined value, the default core ID generated by a default one of the... Via Technologies Inc

Slicer apparatus and calibration method thereof

A slicer apparatus and a calibration method thereof are provided. A differential reference signal pair used for performing an error slicing operation is adjusted, so as to calibrate an offset voltage of the slicer apparatus.... Via Technologies Inc

Paddle card and plug-cable assembly

A paddle card includes a circuit board, a pad group and ground planes. The circuit board has an upper surface and a lower surface opposite to each other. The pad group is adapted to connect wires of a cable or terminals of a plug, and includes a pair of upper... Via Technologies Inc

Programmable secure bios mechanism in a trusted computing system

An apparatus is provided for protecting a basic input/output system (BIOS) in a computing system. The apparatus includes a BIOS read only memory (ROM), a tamper detector, a random number generator, and a JTAG control chain. The BIOS ROM includes BIOS contents stored as plaintext, and an encrypted message digest,... Via Technologies Inc

Jtag-based secure bios mechanism in a trusted computing system

An apparatus is provided for protecting a basic input/output system (BIOS) in a computing system. The apparatus includes a BIOS read only memory (ROM), a tamper detector, a random number generator, and a JTAG control chain. The BIOS ROM includes BIOS contents stored as plaintext, and an encrypted message digest,... Via Technologies Inc

02/16/17 / #20170046516

Fuse-enabled secure bios mechanism in a trusted computing system

An apparatus is provided for protecting a basic input/output system (BIOS) in a computing system. The apparatus includes a BIOS read only memory (ROM), a tamper detector, a random number generator, a JTAG control chain, a fuse, and an access controller. The BIOS ROM includes BIOS contents stored as plaintext,... Via Technologies Inc

02/16/17 / #20170046517

Fuse-enabled secure bios mechanism with override feature

An apparatus is provided for protecting a basic input/output system (BIOS) in a computing system. The apparatus includes a BIOS read only memory (ROM), a tamper detector, a random number generator, a JTAG control chain, a fuse, a machine specific register, and an access controller. The BIOS ROM includes BIOS... Via Technologies Inc

02/16/17 / #20170047908

Control circuit, connection line and control method thereof

A control circuit disposed in a connection line including a first power pin and a second power pin and including a native N-type transistor, a first impedance unit, and a second impedance unit is provided. The native N-type transistor includes a first gate, a first drain and a first source.... Via Technologies Inc

02/09/17 / #20170038988

Memory chips and data protection methods

A memory chip coupled to a host includes a memory and a controller. The memory is pre-loaded with a plurality of boot images, wherein the boot images have the same content. The controller is coupled to the memory, and processes data transmissions between the memory chip and the host, wherein... Via Technologies Inc

01/26/17 / #20170025343

Circuit substrate, semiconductor package and process for fabricating the same

A circuit substrate has the following elements. A stacked circuit structure has a first surface and a second surface opposite thereto surface. A first patterned inner conductive layer is disposed on the first surface and has multiple pads. A first patterned outer conductive layer is disposed on the patterned inner... Via Technologies Inc

01/05/17 / #20170003707

Single-core wakeup multi-core synchronization mechanism

A microprocessor includes a plurality of cores, a shared cache memory, and a control unit that individually puts each core to sleep by stopping its clock signal. Each core executes a sleep instruction and responsively makes a respective request of the control unit to put the core to sleep, which... Via Technologies Inc

01/05/17 / #20170005648

Control chip and control system utilizing the same

A control chip coupled to a first input/output pin and a second input/output pin and including a first interface module, a second interface module, a first switching unit, and a control unit is provided. The first interface module includes a first pin electrically connected to the first input/output pin and... Via Technologies Inc








ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009



###

This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. Freshpatents.com is not affiliated or associated with Via Technologies Inc in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Via Technologies Inc with additional patents listed. Browse our Agent directory for other possible listings. Page by FreshPatents.com

###