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Western Digital Technologies Inc patents


Recent patent applications related to Western Digital Technologies Inc. Western Digital Technologies Inc is listed as an Agent/Assignee. Note: Western Digital Technologies Inc may have other listings under different names/spellings. We're not affiliated with Western Digital Technologies Inc, we're just tracking patents.

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 new patent  Linked storage system and host system error correcting code

Described herein are enhancements for providing error correction in writing and reading data to and from a data storage device. In one implementation, an encoder matrix is used to generate, for a data set, first error correcting code (ECC) parity data on a host system, and second ECC parity data... Western Digital Technologies Inc

 new patent  Surface treatment of magnetic recording heads for improving the robustness thereof

In one embodiment, a method includes forming a structure having a first region including a ceramic material, a second region including a plurality of particles disposed in a ceramic matrix material, and a magnetic head assembly disposed in the first region. The method also includes directing a first ion beam... Western Digital Technologies Inc

 new patent  Three terminal sot memory cell with anomalous hall effect

A method and apparatus for deterministically switching a free layer in a spin orbit torque magnetoresistive random access memory (SOT-MRAM) cell is disclosed herein. In one embodiment, an SOT-MRAM memory cell is provided. The SOT-MRAM memory cell includes a magnetic tunnel junction, a ferromagnetic bias layer, and an antiferromagnetic layer.... Western Digital Technologies Inc

 new patent  Bi-directional rram decoder-driver

The present disclosure generally relates to the fabrication of and methods for creating a reversible tri-state memory device which provides both forward and reverse write and read drive to a bi-directional RRAM cell, thus allowing writing in the forward and reverse directions. The memory device, however, utilizes a single transistor... Western Digital Technologies Inc

System and methodology for low latency error management within a shared non-volatile memory architecture

Various aspects directed towards facilitating error management within a shared non-volatile memory (NVM) architecture are disclosed. Data is stored in an NVM array, and error correction vector (ECV) information associated with the NVM array is stored in a content addressable memory (CAM). A parallel query of the NVM array and... Western Digital Technologies Inc

Self-virtualizing flash memory for solid state drive

In general, a controller may perform a self-virtualization technique. The storage device may include storage access comprising multiple cells, and a controller. The controller may determine a maximum amount of storage access for a virtual machine workload when each cell is configured in a first level mode having a maximum... Western Digital Technologies Inc

System and methodology that facilitates error management within a shared non-volatile memory architecture

Various aspects directed towards facilitating error management within a shared non-volatile memory (NVM) architecture are disclosed. Data programmed into a plurality NVM cells is encoded prior to programming, and a range of programmability associated with each of the plurality of NVM cells is determined when the plurality of NVM cells... Western Digital Technologies Inc

System and methodology for error management within a shared non-volatile memory architecture using bloom filters

Various aspects directed towards facilitating error management within a shared non-volatile memory (NVM) architecture are disclosed. Data is stored in an NVM, and error correction vector (ECV) information associated with the NVM is stored in an error tracking table (ETT) within one of a dynamic random access memory (DRAM) or... Western Digital Technologies Inc

Magnetic storage system multi-sensor signal prediction health controller

In general, techniques are described for monitoring health of a head in a magnetic data storage drive. A health controller may be configured to receive multi-variate sensor signals indicative of a respective reference value at least one head parameter, wherein the respective reference value is based in part on at... Western Digital Technologies Inc

Non-volatile storage system with integrated compute engine and optimized use of local fast memory

A memory system (e.g. a solid state drive) includes one or more non-volatile memory die, a controller in communication with the memory die, a local memory connected to (or part of) the controller and a compute engine inside the memory system that is near the location of the data and... Western Digital Technologies Inc

Search of nas data through association of errors

A computer-perceptible search input, whether typed, spoken, based upon machine vision, detection and/or interpretation of gestures, for example, may be received by a computing device from a single user. The received input by the single user may be matched with one or more stored digital items based upon prior inputs... Western Digital Technologies Inc

Embedding analyzer functionality in storage devices

A method includes receiving, at an interface of a storage device and from a host device, an electrical signal representative of data. The storage device includes a mass storage device. The method also includes splitting, at the interface, the electrical signal representative of the data into a first data stream... Western Digital Technologies Inc

Stackable sleds for storing electronic devices

Described herein is a first system that includes sleds each having sidewalls, a mounting plate, and a first cover. The first cover is movable relative to the sidewalls between a closed position and an open position. The first cover includes at least one first opening. The system additionally includes at... Western Digital Technologies Inc

Adhesive cover seal for hermetically-sealed data storage device

A data storage device involves a plurality of continuous sidewalls and corner portions of a tub cover overlapping with and hermetically sealed with a corresponding plurality of sidewalls and corners of an enclosure base using an epoxy adhesive. Base protrusions and/or cover dimples may be used to set a suitable... Western Digital Technologies Inc

Transfer of object memory references in a data storage device

Herein are data storage devices that transfer a reference to a data object during a storage operation. The data storage devices include a host controller configured to obtain a reference of an object stored in a shared memory system for writing to a storage media controlled by a drive controller.... Western Digital Technologies Inc

Adhesive cover seal for hermetically-sealed data storage device

A data storage device involves a plurality of sidewalls of a bent sheet metal cover, either pre-formed or shaped-in-place, overlapping with and hermetically sealed with a corresponding plurality of sidewalls of an enclosure base, using an applied epoxy adhesive. Base protrusions and/or cover dimples may be used to set a... Western Digital Technologies Inc

Tilted synthetic antiferromagnet polarizer/reference layer for stt-mram bits

Embodiments disclosed herein generally relate to a multilayer magnetic device, and specifically to a spin-torque transfer magnetoresistive random access memory (STT-MRAM) device which provides for a reduction in the amount of current required for switching individual bits. As such, a polarizing reference layer consisting of a synthetic antiferromagnet (SAF) structure... Western Digital Technologies Inc

Optimized n-stream sequential media playback caching method and system

A method of caching data for a set of streams serviced from a data storage device, said method including receiving requests for a set of streams, determining a number of zones in a cache based on the number of streams requested, determining a respective consumption rate for each stream, and... Western Digital Technologies Inc

Data storage system with multimedia assets

Systems and methods are disclosed for storing multimedia assets (or other data objects) in a storage array. Portions of the multimedia asset may be stored on different chunks of the storage drives in the storage array based on an access frequency level for a portion, an importance level for the... Western Digital Technologies Inc

Declustered array of storage devices with chunk groups and support for multiple erasure schemes

Embodiments of a declustered, fault-tolerant array of storage devices for use with computer, networked, cloud-based, and other data storage applications are described. In some embodiments, the array generates a chunk group mapping with a high utilization of storage device space, provides evenly distributed hot spares, supports multiple erasure schemes including... Western Digital Technologies Inc

Autonomously operating light emitting devices providing detection and warning of hazardous condition on path of travel

A system is disclosed comprising a plurality of light emitting devices located along a path of travel, each light emitting device comprising a light emitting source, a sensor, a communication module, and a processor, wherein when a first one of the plurality of light emitting devices is activated, the processor... Western Digital Technologies Inc

Electrical feed-through and connector configuration

An electrical feed-through assembly includes electrically conductive pins having a top apex and a bottom apex, where the pins extend through at least a majority of an electrically non-conductive material. The top apexes, the bottom apexes, or both the top and bottom apexes of the pins have an electrically conductive... Western Digital Technologies Inc

Error locator polynomial decoder and method

A decoder configured to decode a representation of the codeword includes an error locator polynomial generator circuit. The error locator polynomial circuit is configured to generate an error locator polynomial based on a decode operation that includes iteratively adjusting values of a first polynomial, a second polynomial, a third polynomial,... Western Digital Technologies Inc

Pervasive drive operating statistics on sas drives

A method is described that includes generating, by a controller of a storage device, operating statistics associated with an operating state of the storage device. The method includes receiving, by the controller and from a host device, a non-interrupt command frame that requests transfer of data blocks between the storage... Western Digital Technologies Inc

Library for seamless management of storage devices

An approach for using a storage library to translate commands from one command language into a different command language. The approach includes receiving a storage request in a command language from an application. The storage request is directed to a target storage device that uses a different command language. The... Western Digital Technologies Inc

Ecc and raid-type decoding

A device includes a memory and a controller coupled to the memory. The controller is configured to read a codeword from a physical location of the memory. The controller is configured to write an inverse bit string to the physical location of the memory, the inverse bit string based on... Western Digital Technologies Inc

Asynchronous drive telemetry data notification

A method is disclosed that includes, generating, by a controller of a storage device, telemetry data associated with the storage device and stored in a memory device of the storage device. The method further includes determining, by the controller, a telemetry data loss warning condition indicating that a portion of... Western Digital Technologies Inc

Incremental background media scan

In general, a storage device may perform an incremental background media scan. The storage device includes a data storage portion comprising a plurality of blocks. The storage device also includes a controller configured to perform the scan to determine whether to perform maintenance on the page. As such, the controller... Western Digital Technologies Inc

Trim management in solid state drives

A storage device may include a data storage portion, including a plurality of blocks of data, and a controller. The controller may be configured to receive a command that includes an inherent trim request for the plurality of blocks of data. The controller may be configured to perform a trim... Western Digital Technologies Inc

Stream management for storage devices

In general, techniques are described for stream management in storage devices. A storage device comprising a memory device and a processor may be configured to perform the techniques. The processor may detect a stream collision in which a host device writes a first version of a logical block (LB) to... Western Digital Technologies Inc

Mechanical shock mitigation for data storage

A device adapted to capture surveillance data that includes a disk and a Non-Volatile Solid-State Memory (NVSM). The surveillance data is received in a buffer of the device for storage on the disk, and an input is received indicating a level of mechanical shock. It is determined whether the input... Western Digital Technologies Inc

Embedding protocol parameters in data streams between host devices and storage devices

A method includes receiving, by a storage device and from a host device, a set of protocol parameters initialized by the host device. The set of protocol parameters are used to facilitate data transfer between the host device and the storage device. The method also includes determining that a threshold... Western Digital Technologies Inc

Error mitigation for 3d nand flash memory

NAND cell error remediation technologies are disclosed. The remediation technologies are applicable to 3D NAND. In one example, a storage device may include a processor and a memory device comprising NAND flash memory. The processor is configured to detect an error condition associated with a first page of the NAND... Western Digital Technologies Inc

Aggregated metadata transfer at a data storage device

A memory control circuit includes a metadata aggregate buffer configured to store a first plurality of consecutive metadata packets. The memory control circuit also includes control circuitry configured to send aggregated metadata to a memory via a first packet. The aggregated metadata includes at least two metadata packets of the... Western Digital Technologies Inc

Data storage device enclosure

A Data Storage Device (DSD) enclosure includes a chassis and at least one backplane mounted in the chassis. According to one aspect, each backplane includes a row of DSD slots and a switch slot located in a middle portion of the row of DSD slots. A plurality of signal traces... Western Digital Technologies Inc

03/01/18 / #20180061450

Switching period control of microwave assisted magnetic recording for pole erasure suppression

A magnetic recording system for preventing data loss resulting magnetic oscillator current. The magnetic recording system includes a magnetic write head with a magnetic write pole, a magnetic oscillator near the magnetic write pole, and a write coil for magnetizing the write pole. Circuitry is connected with the magnetic write... Western Digital Technologies Inc

02/22/18 / #20180052766

Non-volatile storage system with compute engine to accelerate big data applications

A memory system (e.g. a solid state drive) includes one or more non-volatile memory die, a controller in communication with the memory die and a compute engine inside the memory system that is near the location of the data and can be used to perform common data manipulation operations.... Western Digital Technologies Inc

02/15/18 / #20180047430

Hermetically-sealed data storage device for increased disk diameter

A data storage device involves inner surfaces of sidewalls of a second cover overlapping with and adhesively bonded with the outer surfaces of sidewalls of an enclosure base having an uppermost top surface, where the second cover or an underlying first cover are removably adhered to the uppermost top surface... Western Digital Technologies Inc

02/08/18 / #20180039413

Identifying disk drives and processing data access requests

Systems and methods are disclosed for identifying disk drives and processing data access requests. A disk drive may be identified as an Advanced Host Controller Interface (AHCI) drive, a Non-Volatile Memory Express (NVME) drive, and/or an ATA packet interface (ATAPI) drive. Data access requests for the disk drive may be... Western Digital Technologies Inc

02/01/18 / #20180032267

Extensible storage system controller

A storage system controller chip includes routing circuitry comprising a host interface for coupling to a host device and an extension interface for coupling to a secondary controller chip. A host controller is coupled to a logical interface of the routing circuitry for receiving a host data access command from... Western Digital Technologies Inc

02/01/18 / #20180032261

Efficient data management through compressed data interfaces

A system and method for efficiently managing data through compression interfaces may include receiving, by a controller, data, generating, by the controller, a compressed payload based on the data, generating, by the controller, metadata describing the compressed payload, the metadata including fixed size metadata and variable size metadata, generating, by... Western Digital Technologies Inc

02/01/18 / #20180032268

Adaptive wear levelling

A device that provides for adaptive wear levelling includes at least one processor. The at least one processor utilizes sets of blocks of flash memory circuits for data storage operations, each set of blocks including a block from each flash memory circuit and at least some of the blocks being... Western Digital Technologies Inc

02/01/18 / #20180032274

Processing data access requests from multiple interfaces for data storage devices

Systems and methods are disclosed for processing data access requests received from a direct access storage (DAS) interface and/or a network access storage (NAS) interface. The data access requests may be received from the DAS interface and the NAS interface substantially simultaneously. The data access requests may be scheduled based... Western Digital Technologies Inc

02/01/18 / #20180032395

Erasure correcting coding using temporary erasure data

In an illustrative example, a data storage device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes an erasure correcting code engine configured to generate first erasure recovery data and temporary erasure recovery data in a volatile memory at least partially based on first... Western Digital Technologies Inc

02/01/18 / #20180033458

Enhanced write pole and return pole for improved areal density

A system, according to one embodiment, includes: a main pole; and a trailing shield. A first distance D1 is defined in a track direction between the trailing shield and a pole tip region of the main pole; and a second distance D2 is defined in the track direction between the... Western Digital Technologies Inc

02/01/18 / #20180034475

Repair-optimal parity code

Techniques for generating parities and repairing data erasures using repair-optimal parities are disclosed. The system includes an encoding module, which receives a request to recreate data for a subset of a plurality of content stores. The encoding module generates a new first parity and a new second parity using a... Western Digital Technologies Inc

02/01/18 / #20180034476

Hierarchical variable code rate error correction coding

A system for hierarchical variable code rate error correction coding may include at least one circuit that is configured to identify a row of a hierarchical portion of a generator matrix that corresponds to a determined code rate, determine a number of information bits to apply to the hierarchical portion... Western Digital Technologies Inc

02/01/18 / #20180034479

Non-binary encoding for non-volatile memory

A data storage system and method are provided for storing data in non-volatile memory devices. Binary data is received for storage in a non-volatile memory device. The binary data is converted into non-binary data comprising base-X values, where X is an integer greater than two. The non-binary data is encoded... Western Digital Technologies Inc

02/01/18 / #20180034484

Non-binary decoding using tensor product transforms

A method and data storage system receives a confidence vector for a non-binary symbol value read from a memory cell of a non-volatile memory device, where the confidence vector includes a first plurality of confidence values and transforms the first plurality of confidence values into a first plurality of likelihood... Western Digital Technologies Inc

02/01/18 / #20180034895

Program recording webification

A method of providing a program recording to a user includes: accessing an application service provider that includes a program database via a first connection over a network with a user processor; selecting, with the user processor, a program recording to be received at the location of the user processor;... Western Digital Technologies Inc

01/25/18 / #20180024737

Systems and methods for classifying data in solid state drives

Systems and methods for writing data to a storage are disclosed. The disclosed systems and methods can receive, by a target device in communication with a host, a first write request from the host to write first data to the storage in communication with the target device. The disclosed systems... Western Digital Technologies Inc

01/25/18 / #20180024743

Dual-ported pci express-based storage cartridge including single-ported storage controllers

A storage cartridge may include a storage controller comprising a single PCIe port and a PCIe switch. The PCIe switch may include a first PCIe port communicatively coupled to a first PCIe fabric, a second PCIe port communicatively coupled to a second, different PCIe fabric, and a third PCIe port... Western Digital Technologies Inc

01/25/18 / #20180024751

Metadata management on a storage device

A storage device may include a data storage portion including a set of blocks designated to store metadata and a controller. The controller may be configured to write first metadata at a first location designated by a first pointer. The first location may reference a block that does not contain... Western Digital Technologies Inc

01/25/18 / #20180024759

Indirection-based storage system backups

A data storage system comprising, a storage device having segments that are configured to store data, and a storage logic coupled to the storage device that manages storage of data on the storage device using a translation table. The storage logic is executable to receive a first marker as part... Western Digital Technologies Inc

01/25/18 / #20180024767

Reference set construction for data deduplication

By way of example, a data storage system may comprise a non-transitory storage device storing data blocks in chunks, and a storage logic coupled to the non-transitory storage device that manages storage of data on the storage device. The storage logic is executable to receive a data stream including one... Western Digital Technologies Inc

01/25/18 / #20180024919

Mapping tables for storage devices

In some examples, a storage device includes a first non-volatile memory array configured to store data from a host device and the storage device and a second non-volatile memory array configured to store data from the storage device, wherein the second non-volatile memory array is separate from the first non-volatile... Western Digital Technologies Inc

01/25/18 / #20180025046

Reference set construction for data deduplication

By way of example, a data storage system may comprise, a non-transitory storage device storing data blocks in chunks, and a storage logic coupled to the non-transitory storage device that manages storage of data on the storage device. The storage logic is executable to receive a data stream for storage... Western Digital Technologies Inc

01/25/18 / #20180025746

Low magnetic flux density interface layer for spin torque oscillator

A magnetic field-assisted magnetic recording (MAMR) head is provided, which includes a recording main pole, a seed layer, and a spin torque oscillator (STO) positioned over the main pole, in this order, in a stacking direction from a leading side to a trailing side of the recording head. The STO... Western Digital Technologies Inc

01/18/18 / #20180018259

Apparatus and low power low latency high capacity storage class memory

A method and a storage system are provided for implementing enhanced solid state storage class memory (eSCM) including a direct attached dual in line memory (DIMM) card containing Dynamic Random Access Memory (DRAM), and at least one 5 non-volatile memory, for example, Phase Change Memory (PCM), Resistive RAM (ReRAM), Spin-Transfer-Torque... Western Digital Technologies Inc

01/18/18 / #20180018287

Method to generate pattern data over garbage data when encryption parameters are changed

A memory device including at least one memory location for storing information representing data written using a first encryption/decryption method, and a read channel using a second encryption/decryption method for reading and decrypting information as written is disclosed. The memory device also includes an apparatus that prevents the reading of... Western Digital Technologies Inc

01/04/18 / #20180003743

Connection cable with voltage level indicator

Systems and methods are disclosed for determining an input voltage level of an input voltage received by a connection cable. A monitoring component may determine whether the input voltage level matches one of a plurality of voltage levels. The connection cable may include an indicator component that may indicate which... Western Digital Technologies Inc

01/04/18 / #20180004264

Integrated circuit power distribution with threshold switches

To provide enhanced power distribution in integrated circuits, solid state memory arrays, or other solid state devices, various systems, architectures, apparatuses, and methods, are provided herein. In a first example, an integrated circuit power distribution system is provided. The system includes a first power distribution bus coupled to a current... Western Digital Technologies Inc

01/04/18 / #20180004559

Controlling access to namespaces of a storage device

A method includes receiving, by virtual machine manager and from a virtual machine, a request for a set of namespace identifiers corresponding to a set of namespaces associated with one or more storage devices. The method also includes determining, by the virtual machine manager, one or more namespaces associated with... Western Digital Technologies Inc

01/04/18 / #20180005652

Coupled soft bias scissor type sensor

A magnetic read head is provided, comprising a bottom magnetic shield, a first free magnetic layer, a second free magnetic layer, and a top magnetic shield, arranged from bottom to top in this order in a stacking direction from a leading side to a trailing side of the read head.... Western Digital Technologies Inc

12/28/17 / #20170372730

Magnetic tunnel junction (mtj) free layer damping reduction

In one embodiment, a system includes a sensor, the sensor having a free layer, a ferromagnetic spin sink layer spaced from the free layer, the spin sink layer being operative to reduce a spin-induced damping in the free layer during operation of the sensor, and a nonmagnetic spacer layer positioned... Western Digital Technologies Inc

Patent Packs
12/28/17 / #20170372763

Tilted synthetic antiferromagnet polarizer/reference layer for stt-mram bits

Embodiments disclosed herein generally relate to a multilayer magnetic device, and specifically to a spin-torque transfer magnetoresistive random access memory (STT-MRAM) device which provides for a reduction in the amount of current required for switching individual bits. As such, a polarizing reference layer consisting of a synthetic antiferromagnet (SAF) structure... Western Digital Technologies Inc

12/28/17 / #20170374744

Heat-sinking components mounted on printed boards

In some examples, a method may include coupling a printed board assembly (PBA) to a fixture. In some examples, the PBA may include a printed board and a plurality of components that are electrically and mechanically coupled to the printed board, where each of the plurality of components defines a... Western Digital Technologies Inc

12/21/17 / #20170364459

Coherent controller

A system includes a bus, at least one processor coupled to the bus, and a storage device coupled to the bus. The storage device includes storage class memory, a buffer; and a controller. The controller is configured to receive an instruction to provide data to the bus. Responsive to receiving... Western Digital Technologies Inc

12/21/17 / #20170365280

Multi-track reader for improved signal to noise ratio

A system according to one embodiment includes a magnetic head having a plurality of sensors arranged to simultaneously read at least three immediately adjacent data tracks on a magnetic medium, wherein none of the sensors share more than one lead with any other of the sensors. Such embodiment may be... Western Digital Technologies Inc

12/21/17 / #20170365282

Texture-control layer for spin torque oscillator

A magnetic field-assisted magnetic recording (MAMR) head is provided, which includes a recording main pole and a texture control layer (TCL), a seed control layer, and a spin torque oscillator (STO) positioned over the main pole, in this order, in a stacking direction from a leading side to a trailing... Western Digital Technologies Inc

12/21/17 / #20170365605

Non-volatile schottky barrier field effect transistor

The present disclosure generally relates to an apparatus for high density memory with integrated logic. A three terminal ReRAM device, which includes a p-n junction and a Schottky barrier, that can switch from a low resistive state to a high resistive state is provided. The Schottky transistor memory device includes... Western Digital Technologies Inc

12/21/17 / #20170365641

Non-volatile double schottky barrier memory cell

A three terminal ReRAM device, which combines a Schottky barrier transistor and a Schottky barrier ReRAM into a single device is provided. The Schottky transistor memory device includes a source region, a drain region, and a gate electrode. Between the source and drain regions, the ReRAM material is present. The... Western Digital Technologies Inc

12/14/17 / #20170357571

Memory unit assignment and selection for internal memory operations in data storage systems

Disclosed embodiments are directed to systems and methods for assigning and selecting memory units for internal memory operations in data storage systems. The embodiments can improve the efficiency of garbage collection operations by directing dynamic data into memory units with a relatively lower P/E count, directing static and system data... Western Digital Technologies Inc

12/14/17 / #20170358626

Vertical memory structure with array interconnects and producing the same

Disclosed herein is a method and apparatus for fabricating a memory device. The memory device has a vertical stack of alternating layers of conductive and insulating layers wherein a top layer and a bottom layer are insulating layers. A plurality of vias is formed through the vertical stack from the... Western Digital Technologies Inc

12/14/17 / #20170359400

Extending representational state transfer application program interface (rest api) functionality

The present disclosure relates to a system and methods for extending the REST API. In particular, the disclosure relates to methods including receiving a request to modify a first version of a resource in a first collection, the first version of the resource associated with a first identifier identifying the... Western Digital Technologies Inc

12/07/17 / #20170351431

Resizing namespaces for storage devices

A method may include receiving, by a controller of a storage device and from a host device, a command to resize a first namespace of a plurality of namespaces stored in a non-volatile memory device of the storage device. The method may further include, relocating, by the controller, a physical... Western Digital Technologies Inc

12/07/17 / #20170351572

Methods and systems for implementing redundancy in memory controllers

The present disclosure relates to methods and systems for implementing redundancy in memory controllers. The disclosed systems and methods utilize a row of memory blocks, such that each memory block in the row is associated with an independent media unit. Failures of the media units are not correlated, and therefore,... Western Digital Technologies Inc

12/07/17 / #20170352423

Data retention flags in solid-state drives

Systems and methods for managing data retention in a solid-state storage system utilizing data retention flag bytes are disclosed. A data storage device includes a non-volatile memory comprising a plurality of non-volatile memory devices and a controller configured to write data to a memory unit of the non-volatile memory array... Western Digital Technologies Inc

12/07/17 / #20170352702

Bottom pinned sot-mram bit structure and fabrication

Embodiments of the present disclosure generally relate to data storage and computer memory systems, and more particularly, to a SOT-MRAM chip architecture. The SOT-MRAM chip architecture includes a plurality of leads, a plurality of memory cells, and a plurality of transistors. The leads may be made of a material having... Western Digital Technologies Inc

11/30/17 / #20170344287

Atomic write command support in a solid state drive

A method of performing an atomic write command in a data storage device comprising a volatile memory and a plurality of non-volatile memory devices configured to store a plurality of physical pages. The method may comprise storing data in a plurality of logical pages (L-Pages), each associated with a logical... Western Digital Technologies Inc

Patent Packs
11/30/17 / #20170345510

Temperature variation compensation

A device includes a memory and a controller coupled to the memory. The controller is configured to determine a temperature-based value of a search parameter in response to detecting that an error rate of a codeword read from the memory exceeds a threshold error rate. The controller is further configured... Western Digital Technologies Inc

11/23/17 / #20170336990

Multi-tier scheme for logical storage management

A storage device may include a controller and a memory array including a plurality of dies arranged into a plurality of channels. In some examples, the controller may be configured to define, from the memory array, a plurality of die-sets based on respective chip enable lines associated with the plurality... Western Digital Technologies Inc

11/23/17 / #20170337987

Self-testing a storage device via system management bus interface

A system and method are provided for self-testing one or more digital data storage drives. In particular, a drive tester system connects to the one or more digital data storage drives via a standard two-wire interface, such as a system management bus interface or an I2C interface. The drive tester... Western Digital Technologies Inc

11/23/17 / #20170338281

Resistive memory device by substrate reduction

To provide enhanced data storage devices and systems, various systems, architectures, apparatuses, and methods, are provided herein. In a first example, a resistive memory device is provided. The resistive memory device comprises a substrate, and an active region having resistance properties that can be modified to store one or more... Western Digital Technologies Inc

11/16/17 / #20170329372

Component placement within a solid state drive

A component mount for a data storage device (DSD). The component mount includes a flexible member or printed circuit board assembly (PCBA) including a pad for electrically connecting to a printed circuit board (PCB) of the DSD. At least one capacitor is mounted on the flexible member or PCBA, and... Western Digital Technologies Inc

11/16/17 / #20170330620

Planar variable resistance memory

An example memory device includes a planar semiconductor substrate layer; a planar variable resistance layer disposed above the planar semiconductor substrate layer; a planar channel layer disposed above the planar variable resistance layer; and one or more gates positioned along a length of the memory device and above the planar... Western Digital Technologies Inc

11/09/17 / #20170322897

Systems and methods for processing a submission queue

A data storage device includes a memory and a controller coupled to the memory. The controller is configured to select a submission queue from a set of submission queues of an access device based at least in part on availability of space in a completion queue of the access device.... Western Digital Technologies Inc

11/09/17 / #20170323657

Data storage device modifying write operation when a laser mode hop is detected

A data storage device is disclosed comprising a first head actuated over a first disk surface, wherein the first head comprises a laser configured to heat the first disk surface while writing data to the first disk surface. A write power is applied to the laser and a first write... Western Digital Technologies Inc

11/02/17 / #20170315756

Data management for a data storage device

Managing data stored in at least one Data Storage Device (DSD) includes generating a Linear Tape File System (LTFS) write or read command including an LTFS block address. The generated LTFS command is for writing or reading data in an LTFS data partition, writing or reading metadata in the LTFS... Western Digital Technologies Inc

11/02/17 / #20170315851

Collision detection for slave storage devices

A method includes transmitting, by a controller of a storage device, a first bit on a data line. The method further includes responsive to transmitting the first bit on the data line, determining, by the controller, a line level of the data line. The method further includes responsive to determining... Western Digital Technologies Inc

11/02/17 / #20170317142

Sidewall insulated resistive memory devices

To provide enhanced data storage devices and systems, various systems, architectures, apparatuses, and methods, are provided herein. In a first example, a resistive memory device is provided. The resistive memory device includes an active region having resistance properties that can be modified to store one or more data bits in... Western Digital Technologies Inc

11/02/17 / #20170317280

Nonvolatile bipolar junction memory cell

The present disclosure generally relates to an apparatus for a three terminal nonvolatile memory cell. Specifically, a three terminal nonvolatile bipolar junction transistor. The bipolar junction memory device includes a collector layer, a base layer disposed on the collector layer, an emitter layer disposed on the base layer, and a... Western Digital Technologies Inc

10/26/17 / #20170308302

Storage management in hybrid drives

Methods for deciding whether to store data in a non-volatile semiconductor memory (NVSM) storage portion of a hybrid drive including the NVSM storage portion and a disk storage portion are provided. One such method involves generating a queue for storing candidate addresses and a priority level for each of the... Western Digital Technologies Inc

10/19/17 / #20170300234

Preloading of directory data in data storage devices

Systems and methods are disclosed for providing directory data access in a data storage system. A network-attached storage device (NAS) includes a host interface for communicating with a host, an interface for communicating with a data storage drive associated with the NAS, a cache memory, and a controller configured to... Western Digital Technologies Inc

10/19/17 / #20170300249

Validity tracking for garbage collection

A storage device may include at least one memory device logically divided into a plurality of blocksets and a controller. The controller may be configured to receive a command to execute a garbage collection operation on a first blockset of the plurality of blocksets. The controller may be further configured... Western Digital Technologies Inc

10/19/17 / #20170300256

Read disturb compensation using weighted programming patterns

A data storage device includes a solid-state non-volatile memory including a plurality of memory cells and a controller. The controller is configured to reduce a read disturb effect of at least a portion of the solid-state non-volatile memory at least in part by receiving or accessing data to be written... Western Digital Technologies Inc

10/19/17 / #20170300423

Wear leveling in storage devices

A system may include a plurality of memory cells and a processor. The plurality of memory cells may include a plurality of physical locations at which data is stored. The processor may be configured to determine whether to swap physical locations of data stored at logical block addresses in the... Western Digital Technologies Inc

10/19/17 / #20170301677

Nano-imprinted self-aligned multi-level processing method

The present disclosure generally relates to fine geometry electrical circuits and methods of manufacture thereof. More specifically, methods for forming 3D cross-point memory arrays using a single nano-imprint lithography step and no photolithography are disclosed. The method includes imprinting a multilevel topography pattern, transferring the multilevel topography pattern to a... Western Digital Technologies Inc

10/19/17 / #20170301729

Nano-imprinted self-aligned multi-level processing method

The present disclosure generally relates to fine geometry electrical circuits and methods of manufacture thereof. More specifically, methods for forming 3D cross-point memory arrays using a single nano-imprint lithography step and no photolithography are disclosed. The method includes imprinting a multilevel topography pattern, transferring the multilevel topography pattern to a... Western Digital Technologies Inc

10/19/17 / #20170301732

Dual ots memory cell selection means and method

A 3D cross-point memory array includes a bitline and a word line. Both the bitline and the word line have multiple selector switches. Each switch of a corresponding bitline or word line is connected to a horizontal conductor or a vertical conductor so that a given bitline or word line... Western Digital Technologies Inc

10/19/17 / #20170303412

Shroud for an electronic device

A shroud including a body comprising a first side, a second side opposite the first side, and a printed circuit board assembly (“PCBA”) reception unit configured to receive a PCBA unit of an electronic device, wherein the PCBA unit comprises multiple light emitting diode (“LED”) units which emit multiple light... Western Digital Technologies Inc








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