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Xilinx Inc patents

Recent patent applications related to Xilinx Inc. Xilinx Inc is listed as an Agent/Assignee. Note: Xilinx Inc may have other listings under different names/spellings. We're not affiliated with Xilinx Inc, we're just tracking patents.

ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "X" | Xilinx Inc-related inventors




Date Xilinx Inc patents (updated weekly) - BOOKMARK this page
08/17/17 new patent  Chip package assembly with power management integrated circuit and integrated circuit die
08/03/17System-level interconnect ring for a programmable integrated circuit
08/03/17Active-by-active programmable device
07/20/17Channel selection in multi-channel switching network
06/15/17Hardware power-on initialization of an soc through a dedicated processor
06/08/17Folding duplicate instances of modules in a circuit design
05/11/17Method for increasing active inductor operating range and peaking gain
05/04/17Multistage boot image loading by configuration of a bus interface
04/27/17Methods and circuits for debugging circuit designs
04/20/17Interposer-less stack die interconnect
04/06/17Direct memory access for programmable logic device configuration
04/06/17Interactive multi-step physical synthesis
03/30/17Stacked silicon package assembly having an enhanced lid
03/02/17Transmitter circuit for and methods of generating a modulated signal in a transmitter
02/02/17Offset insensitive quadrature clock error correction and duty cycle calibration for high-speed clocking
01/19/17Circuits for and methods of generating a modulated signal in a transmitter
01/12/17Method and design of low sheet resistance meol resistors
01/12/17M-path filter with outer and inner channelizers for passband bandwidth adjustment
01/12/17Variable bandwidth filtering
01/05/17Variable code rate solid-state drive
01/05/17Moving mean and magnitude dual path digital predistortion
12/01/16Channel adaptive adc-based receiver
11/24/16Transmitter configured for test signal injection to test ac-coupled interconnect
11/03/16Reconfigurable fractional-n frequency generation for a phase-locked loop
10/06/16Multiplexer-based ternary content addressable memory
10/06/16Method and circuits for communication in multi-die packages
09/29/16Adaptive video direct memory access module
09/22/16Analog switch having reduced gate-induced drain leakage
09/22/16Noise-shaping crest factor reduction with polyphase transforming
09/08/16Circuits and methods for inter-processor communication
09/01/16Current-mode logic circuit having a wide operating range
07/28/16Circuits for and methods of controlling the operation of a hybrid memory system
07/14/16Processing system network controller with interface to programmable logic
06/09/16Phase-locked loop with an adjustable output divider
06/09/16Latency control in a transmitter/receiver buffer
05/12/16Heterogeneous multiprocessor platform targeting programmable integrated circuits
05/12/16Processing system display controller interface to programmable logic
05/12/16Calibration in a control device receiving from a source synchronous interface
05/12/16Power management system for integrated circuits
05/05/16Methods and circuits for deadlock avoidance
04/28/16Circuits for and methods of controlling power within an integrated circuit
04/21/16Dynamic selection of output delay in a memory control device
04/07/16In-die transistor characterization in an ic
04/07/16In-die transistor characterization in an ic
04/07/16Circuits for and methods of processing data in an integrated circuit device
03/24/16Managing memory in a multiprocessor system
03/17/16Lane-to-lane de-skew for transmitters
03/03/16Multi-chip silicon substrate-less chip packaging
02/25/16Mechanism for inter-processor interrupts in a heterogeneous multiprocessor system
02/25/16Programmable single-supply level-shifter circuit
02/18/16Sub-system power management control
02/18/16Virtualization of memory for programmable logic
02/18/16Capacitor structure in an integrated circuit
02/18/16Interconnect circuits having low threshold voltage p-channel transistors for a programmable integrated circuit
02/18/16Adaptive optical channel compensation
01/28/16System-on-chip intellectual property block discovery
01/07/16Bridging inter-bus communications
12/10/15Circuits for and methods of enabling the access to data
12/10/15Optical communication circuits
12/10/15Optical communication circuits
12/03/15Extracting system architecture in high level synthesis
12/03/15Integrated circuit package with thermal neutron shielding
10/29/15Virtualization of programmable integrated circuits
10/01/15Thin profile metal trace to suppress skin effect and extend package interconnect bandwidth
08/20/15Authentication using public keys and session keys
Patent Packs
08/06/15Low insertion loss package pin structure and method
07/02/15Semiconductor device having bucket-shaped under-bump metallizaton and forming same
06/25/15Data receivers and methods of implementing data receivers in an integrated circuit
06/11/15Memory arrangement for implementation of high-throughput key-value stores
05/28/15High quality factor inductive and capacitive circuit structure
05/28/15Multi-path digital pre-distortion
05/07/15Solder bump arrangements for large area analog circuitry
05/07/15Serdes receiver oversampling rate
04/16/15Multi-threaded low-level startup for system boot efficiency
03/12/15Removal of electrostatic charges from interposer for die attachment
03/05/15Input/output circuits and methods of implementing an input/output circuit
02/26/15Method and suppressing metal-gate cross-diffusion in semiconductor technology
01/15/15Switch supporting voltages greater than supply
01/08/15Monolithic integrated circuit die having modular die regions stitched together
01/01/15Windowing for high-speed analog-to-digital conversion
Patent Packs
12/25/14Compilation of system designs
10/23/14Semiconductor package having ic dice and voltage tuners
09/18/14Multi-layer core organic package substrate
09/18/14Circuits for and methods of implementing a gain stage in an integrated circuit
09/18/14Calibration of a switching instant of a switch
09/18/14Timestamp correction in a multi-lane communication link with skew
09/18/14Multi-boot or fallback boot of a system-on-chip using a file-based boot device
09/18/14Analog block and test blocks for testing thereof
09/18/14Modular and scalable cyclic redundancy check computation circuit
09/11/14Substrate-less interposer technology for a stacked silicon interconnect technology (ssit) product
09/11/14Package integrity monitor with sacrificial bumps
09/11/14Integrated circuit devices having memory and methods of implementing memory in an integrated circuit device
07/24/14Single reticle approach for multiple patterning technology
07/17/14Circuit for and enabling the discharge of electric charge in an integrated circuit
06/19/14On-the-fly technical support
05/29/14Integrated circuit having improved radiation immunity
05/15/14Clock network architecture
05/15/14System and reducing effects of switched capacitor kickback noise
05/15/14Configurable embedded memory system
05/15/14Digital pre-distortion in a communication network
05/01/14Inductor structure with pre-defined current return
04/03/14Method of testing a semiconductor structure
04/03/14Plesiochronous clock generation for parallel wireline transceivers
03/27/14Noise attenuation wall
03/27/14Reducing the effect of parasitic mismatch at amplifier inputs
03/27/14Clock domain boundary crossing using an asynchronous buffer
02/20/14Integrated circuit having improved radiation immunity
02/20/14Flexible sized die for use in multi-die integrated circuit
02/20/14Recursion unit scheduling
01/30/14Receiver having a wide common mode input range
Social Network Patent Pack
01/16/14Methods for flip chip stacking
12/19/13Oversized interposer
12/05/13Distortion tolerant clock and data recovery
10/24/13Conductor structure with integrated via element
09/26/13Parallel encoding for non-binary linear block code
08/22/13Stacked die assembly
08/22/13High voltage rc-clamp for electrostatic discharge (esd) protection
08/08/13Reducing stress in multi-die integrated circuit structures
07/18/13Integrated circuit connectivity using flexible circuitry
07/18/13Resonator circuit and generating a resonating output signal
Patent Packs
07/11/13Integrated circuit package and assembling an integrated circuit package
07/11/13Driver circuit and generating an output signal
06/20/13Systems and methods for changing decoding parameters in a communication system
06/20/13Apparatus and reference symbol transmission in an ofdm system
06/13/13Contention-free memory arrangement
06/13/13Reduction in decoder loop iterations
06/06/13Minimum mean square error processing
05/30/13Minimum mean square error processing
05/30/13Circuit for and enabling the transfer of data by an integrated circuit
05/09/13Embedded memory and dedicated processor structure within an integrated circuit
04/25/13Systems and methods for digital processing based on active signal channels of a communication system
04/25/13Mixed-signal radio frequency receiver implementing multi-mode spur avoidance
04/18/13Multi-die integrated circuit structure with heat sink
04/18/13Parallel processing of network packets
03/14/13Interdigitated capacitor having digits of varying width
01/31/13Decoder circuit for down-sampling a differential manchester encoding
01/24/13Inductive structure formed using through silicon vias
01/24/13Integrated circuit enabling the communication of data and a communicating data in an integrated circuit
01/10/13Method and self-annealing multi-die interconnect redundancy control
01/03/13Receiver circuit
12/27/12Integrated circuit design using through silicon vias
12/20/12Stress-aware design for integrated circuits
10/04/12Interposer having an inductor
09/27/12Symmetrical center tap inductor structure
09/27/12Integrated circuit inductor having a patterned ground shield
09/13/12Calibrating device performance within an integrated circuit
08/30/12Integrated circuit with programmable circuitry and an embedded processor system
08/23/12Multiple-loop symmetrical inductor
08/09/12Extended under-bump metal layer for blocking alpha particles in a semiconductor device
07/26/12T-coil network design for improved bandwidth and electrostatic discharge immunity
Patent Packs
07/19/12Extending a processor system within an integrated circuit
07/19/12Power management within an integrated circuit
06/07/12Power distribution network
06/07/12Disposing underfill in an integrated circuit structure
06/07/12Semiconductor device with stacked power converter
05/24/12Classifying a criticality of a soft error and mitigating the soft error based on the criticality
05/17/12Through silicon via with improved reliability
05/17/12Multichip module for communications
04/26/12Lead-free structures in a semiconductor device
04/19/12Tunable resonant circuit in an integrated circuit
04/19/12Multiple-loop symmetrical inductor
03/29/12Corner structure for ic die
03/08/12Protecting against differential power analysis attacks on decryption keys
03/08/12Protecting against differential power analysis attacks on sensitive data
02/09/12Air through-silicon via structure
01/26/12Configuration of a multi-die integrated circuit
01/12/12Integrated circuit device with stress reduction layer
01/05/12Electro-static discharge protection for die of a multi-chip module
12/29/11Testing die-to-die bonding and rework
12/08/11Strobe signal management to clock data into a system
Social Network Patent Pack
12/08/11Dynamic detection of a strobe signal within an integrated circuit
12/08/11Input/output bank architecture for an integrated circuit
12/08/11Scalable memory interface system
12/01/11Through-silicon vias with low parasitic capacitance
12/01/11Differential comparator circuit having a wide common mode input range
11/10/11Device specific configuration of operating voltage
10/20/11Lockstep synchronization and maintenance
10/13/11Varactor circuit and voltage-controlled oscillation
10/13/11Stacked dual inductor structure
10/13/11Method and integrated circuit for secure encryption and decryption
09/15/11System and pilot tone assisted selected mapping
09/08/11Multi-chip integrated circuit
09/08/11Programmable integrated circuit with mirrored interconnect structure
09/01/11Semiconductor device having bucket-shaped under-bump metallization and forming same
08/04/11Method and interconnect layout in an integrated circuit
06/23/11Hybrid integrated circuit device
05/26/11Extended under-bump metal layer for blocking alpha particles in a semiconductor device
05/26/11Femtocell configuration using spectrum sensing
05/26/11Minimum mean square error processing
05/12/11T-coil network design for improved bandwidth and electrostatic discharge immunity
Social Network Patent Pack
04/28/11High impedance electrical connection via
03/10/11Shared electrostatic discharge protection for integrated circuit output drivers
02/03/11Enhanced immunity from electrostatic discharge
01/20/11Apparatus and testing of stacked die structure
12/23/10Sphere detector performing depth-first search until terminated
12/09/10Apparatus and predictive over-drive detection
10/28/10Peak-to-average power ratio reduction with bounded error vector magnitude
10/14/10Integrated circuit device with stress reduction layer
08/12/10Integrated circuit having a circuit for and providing intensity correction for a video
08/05/10Barrier layer to prevent conductive anodic filaments
08/05/10Techniques for improving transistor-to-transistor stress uniformity
08/05/10Method and detecting and correcting errors in a parallel to serial circuit
07/29/10Circuit for and reducing power consumption in input ports of an integrated circuit
07/29/10Method and apparatus to reduce footprint of esd protection within an integrated circuit
07/29/10Digital signal processing block with preadder stage
07/29/10Method of and circuit for implementing a filter in an integrated circuit
07/22/10Generic buffer circuits and methods for out of band signaling
06/10/10Data storage system with removable memory module having parallel channels of dram memory and flash memory
05/27/10Integrated capacitor with alternating layered segments
05/27/10Shielding for integrated capacitors
05/27/10Integrated capicitor with cabled plates
05/27/10Integrated capacitor with array of crosses
05/27/10Integrated capacitor with interlinked lateral fins
05/27/10Common centroid electrostatic discharge protection for integrated circuit devices
04/01/10Method and counter-based clock signal adaptation
03/18/10Address generation
03/04/10Method of and circuit for reducing distortion in a power amplifier
02/18/10Mimo symbol detection for snr higher and lower than a threshold
01/14/10Detecting in-phase and quadrature-phase amplitudes of mimo communications
01/14/10Symbol detection in a mimo communication system
Social Network Patent Pack
11/26/09Clock generation using a fractional phase detector
11/26/09Circuit for and receiving video data
11/05/09Configurable transactional memory for synchronizing transactions
09/17/09Detector using limited symbol candidate generation for mimo communication systems
09/17/09Creating a standard cell circuit design from a programmable logic device circuit design
09/10/09Integrated circuit with mosfet fuse element
09/10/09Semiconductor assembly having reduced thermal spreading resistance and methods of making same
08/27/09Partial reconfiguration for a mimo-ofdm communication system
08/27/09Block boundary detection for a wireless communication system
08/20/09Circuit for and minimizing power consumption in an integrated circuit device
07/09/09Reduction of jitter in a semiconductor device by controlling printed ciucuit board and package substrate stackup
06/25/09Formation of a hybrid integrated circuit device
06/11/09Interrupt controller for invoking service routines with associated priorities
05/14/09Characterizing circuit performance by separating device and interconnect impact on signal delay
05/07/09Analog front-end having built-in equalization and applications thereof
04/30/09Method of and circuit for protecting a transistor formed on a die







ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009



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