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Xilinx Inc patents


Recent patent applications related to Xilinx Inc. Xilinx Inc is listed as an Agent/Assignee. Note: Xilinx Inc may have other listings under different names/spellings. We're not affiliated with Xilinx Inc, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "X" | Xilinx Inc-related inventors


Method and apparatus for assembling and testing a multi-integrated circuit package

An example clamping assembly tray for packaging a semiconductor device includes a frame having a bottom surface and side walls extending from the bottom surface that define a cavity; and a compressible member disposed on the bottom surface of the frame within the cavity, where a top portion of the compressible member provides a support surface for supporting the semiconductor device, the support surface being between the bottom surface and a top edge of the side walls.. . ... Xilinx Inc

Segmented electro-absorption modulation

Systems and methods therefor relating generally to electro-absorption modulation are disclosed. In a system thereof, a waveguide is for propagating an optical signal. ... Xilinx Inc

Programmable clock monitor

An apparatus can include an interface circuit configured to receive an operating parameter and a control circuit coupled to the interface circuit and configured to store the operating parameter. The apparatus also can include a clock error detection circuit coupled to the control circuit. ... Xilinx Inc

Impedance and swing control for voltage-mode driver

A driver circuit includes a plurality of output circuits coupled in parallel between a differential input and a differential output and having a first common node and a second common node. Each of the plurality of output circuits includes a series combination of a pair of inverters and a pair of resistors, coupled between the differential input and the differential output; first source terminals of the pair of inverters coupled to the first common node; and second source terminals of the pair of inverters coupled to the second common node. ... Xilinx Inc

Stacked columnar integrated circuits

An example semiconductor device includes a first integrated circuit (ic) die including a first column of cascade-coupled resource blocks; a second ic die including a second column of cascade-coupled resource blocks, where an active side of the second ic die is mounted to an active side of the first ic die; and a plurality of electrical connections between the active side of the first ic and the active side of the second ic, the plurality of electrical connections including at least one electrical connection between the first column of cascade-coupled resource blocks and the second column of cascade-coupled resource blocks.. . ... Xilinx Inc

Methods and circuits for preventing hold time violations

Aspects of various embodiments of the present disclosure are directed to methods and circuits for preventing hold time violations in clock synchronized circuits. In an example implementation, a circuit includes at least a first flip-flop, a second flip-flop, and a level-sensitive latch connected in a signal path from the first flip-flop to the second flip-flop. ... Xilinx Inc

Substrate noise isolation structures for semiconductor devices

An example a semiconductor device includes a first circuit and a second circuit formed in a semiconductor substrate. The semiconductor device further includes a first guard structure formed in the semiconductor substrate and disposed between the first circuit and the second circuit, the first guard structure including first discontinuous pairs of n+ and p+ diffusions disposed along a first axis. ... Xilinx Inc

Integrated circuit with shielding structures

A semiconductor device includes an interconnect structure disposed over a semiconductor substrate. The interconnect structure includes a first device disposed in a first portion of the interconnect structure. ... Xilinx Inc

Dynamic power reduction in circuit designs and circuits

Reducing dynamic power consumption for a circuit can include analyzing, using a processor, a netlist specifying the circuit to determine a block of combinatorial circuitry in a first signal path with at least a threshold amount of switching activity and detecting, using the processor, a second signal path coupled to the block of combinatorial circuitry by a sequential circuit element. The second signal path has a delay that meets a target signal path requirement. ... Xilinx Inc

Area-efficient high-accuracy bandgap voltage reference circuit

An integrated circuit includes a reference voltage circuit. The reference voltage circuit includes a bipolar junction transistor (bjt) configured to receive a first current during a first phase of a clock cycle to generate a first base-emitter junction voltage, and receive a second current during a second phase of the clock cycle to generate a second base-emitter junction voltage. ... Xilinx Inc

Versatile testing system

A chip package assembly testing system and method for testing a chip package assembly are provided herein. In one example, an ic test system is provide that includes a robot, an input queuing station, an output queuing station, and a test station. ... Xilinx Inc

Standalone interface for stacked silicon interconnect (ssi) technology integration

Methods and apparatus are described for adding one or more features (e.g., high bandwidth memory (hbm)) to an existing qualified stacked silicon interconnect (ssi) technology programmable ic die (e.g., a super logic region (slr)) without changing the programmable ic die (e.g., adding or removing blocks). One example integrated circuit (ic) package generally includes a package substrate; at least one interposer disposed above the package substrate and comprising a plurality of interconnection lines; a programmable ic die disposed above the interposer; a fixed feature die disposed above the interposer; and an interface die disposed above the interposer and configured to couple the programmable ic die to the fixed feature die using a first set of interconnection lines routed through the interposer between the programmable ic die and the interface die and a second set of interconnection lines routed through the interposer between the interface die and the fixed feature die.. ... Xilinx Inc

Impedance and swing control for voltage-mode driver

A driver circuit includes a plurality of output circuits coupled in parallel between a differential input and a differential output and having a first common node and a second common node. Each of the plurality of output circuits includes a series combination of a pair of inverters and a pair of resistors, coupled between the differential input and the differential output; first source terminals of the pair of inverters coupled to the first common node; and second source terminals of the pair of inverters coupled to the second common node. ... Xilinx Inc

Binary neural networks on progammable integrated circuits

In an example, a circuit of a neural network implemented in an integrated circuit (ic) includes a layer of hardware neurons, the layer including a plurality of inputs, a plurality of outputs, a plurality of weights, and a plurality of threshold values, each of the hardware neurons including: a logic circuit having inputs that receive first logic signals from at least a portion of the plurality of inputs and outputs that supply second logic signals corresponding to an exclusive nor (xnor) of the first logic signals and at least a portion of the plurality of weights; a counter circuit having inputs that receive the second logic signals and an output that supplies a count signal indicative of the number of the second logic signals having a predefined logic state; and a compare circuit having an input that receives the count signal and an output that supplies a logic signal having a logic state indicative of a comparison between the count signal and a threshold value of the plurality of threshold values; wherein the logic signal output by the compare circuit of each of the hardware neurons is provided as a respective one of the plurality of outputs.. . ... Xilinx Inc

02/01/18 / #20180033753

Heterogeneous ball pattern package

Methods and apparatus are described for strategically arranging conductive elements (e.g., solder balls) of an integrated circuit (ic) package (and the corresponding conductive pads of a circuit board for electrical connection with the ic package) using a plurality of different pitches. One example integrated circuit (ic) package generally includes an integrated circuit die and an arrangement of electrically conductive elements coupled to the integrated circuit die. ... Xilinx Inc

01/18/18 / #20180017619

Modular testing system with versatile robot

A chip package assembly testing system and method for testing a chip package assembly are provided herein. In one example, the testing system includes a robot disposed in an enclosure and having a range of motion operable to transfer a chip package assembly between any of a first queuing station, a second queuing station and a plurality of test stations. ... Xilinx Inc

01/11/18 / #20180013435

Method and apparatus for clock phase generation

A method, non-transitory computer readable medium, and circuit for clock phase generation are disclosed. The circuit includes an injection locked oscillator, a loop controller, and a phase interpolator. ... Xilinx Inc

12/28/17 / #20170373692

Circuit for and method of implementing a scan chain in programmable resources of an integrated circuit

A circuit for implementing a scan chain in programmable resources of an integrated circuit is described. The circuit comprises a programmable element configured to receive an input signal and generate an output signal based upon the input signal; a selection circuit configured to receive the output signal generated by the programmable element at a first input and to receive a scan chain input signal at a second input, wherein the selection circuit generates a selected output signal in response to a selection circuit control signal; and a register configured to receive the selected output signal of the selection circuit.. ... Xilinx Inc

12/28/17 / #20170372979

Stacked silicon package assembly having conformal lid

A chip package assembly and method for fabricating the same are provided which utilize a conformal lid to improve the chip package assembly from deformation. In one example, a chip package assembly is provided that includes integrated circuit (ic) dies, a packaging substrate, and a lid. ... Xilinx Inc

11/30/17 / #20170346455

Circuit for and method of receiving an input signal

A circuit for receiving an input signal is described. The receiver comprises a first receiver input configured to receive a first input of a differential input signal; a second receiver input configured to receive a second input of a differential input signal; a differential pair having an inverting input and a non-inverting input; a first impedance matching element coupled to the differential pair, wherein the first impedance matching element provides dc impedance matching from the inverting input and non-inverting input of the differential pair; and a second impedance matching element coupled to the differential pair, wherein the second impedance matching element provides ac impedance matching from the inverting input and non-inverting input of the differential pair.. ... Xilinx Inc

11/30/17 / #20170344482

Memory pre-fetch for virtual memory

Virtual memory pre-fetch requests are generated for a virtual memory and a multiple port memory management unit (mmu) circuit. Virtual memory access requests sent to a particular port of the mmu circuit are monitored. ... Xilinx Inc

10/05/17 / #20170287919

Single event upset (seu) mitigation for finfet technology using fin topology

Front end circuits that include a finfet transistor are described herein. In one example, the front end circuit has a finfet transistor that includes a channel region wrapped by a metal gate, the channel region connecting a source and drain fins. ... Xilinx Inc

09/14/17 / #20170264467

Half-rate integrating decision feedback equalization with current steering

Apparatuses and method relating to dfe include a decision feedback equalizer with first and second integrating summers configured to receive an input differential signal. A bias current circuit is configured to alternate biasing of the first and second integrating summers. ... Xilinx Inc

08/24/17 / #20170244371

Linear gain code interleaved automatic gain control circuit

An example automatic gain control (agc) circuit includes a base current-gain circuit having a programmable source degeneration resistance responsive to first bits of an agc code word. The agc circuit further includes a programmable current-gain circuit, coupled between an input and an output of the base current-gain circuit, having a programmable current source responsive to second bits of the agc code word. ... Xilinx Inc

08/17/17 / #20170236809

Chip package assembly with power management integrated circuit and integrated circuit die

A chip package assembly is provided that includes a substrate, at least one integrated circuit (ic) die and a power management integrated circuit (pmic). In one example, the ic die of the chip package assembly is disposed on a first surface of the substrate. ... Xilinx Inc

08/03/17 / #20170220509

Active-by-active programmable device

An example integrated circuit (ic) system includes a package substrate having a programmable integrated circuit (ic) and a companion ic mounted thereon, the programmable ic including a programmable fabric and the companion ic including application circuitry. The ic system further includes a system-in-package (sip) bridge including a first sip io circuit disposed in the programmable ic, a second sip io circuit disposed in the companion ic, and conductive interconnect on the package substrate electrically coupling the first sip io circuit and the second sip io circuit. ... Xilinx Inc

08/03/17 / #20170220508

System-level interconnect ring for a programmable integrated circuit

An example programmable integrated circuit (ic) includes a programmable fabric having a programmable interconnect and wire tracks adjacent to at least one edge of the programmable fabric. The programmable ic further includes at least one ring node integrated with at least one edge of the programmable fabric, the at least one ring node coupled between the programmable interconnect and the wire tracks. ... Xilinx Inc

07/20/17 / #20170207998

Channel selection in multi-channel switching network

Methods and systems are disclosed for selecting channels for routing signals in a multi-channel switching network. In an example implementation, pairs of the signals that can be routed together over one channel in the multi-channel switching network are determined. ... Xilinx Inc

06/15/17 / #20170168841

Hardware power-on initialization of an soc through a dedicated processor

In an example, a system-on-chip (soc) includes a hardware power-on-reset (por) sequencer circuit coupled to a por pin. The soc further includes a platform management unit (pmu) circuit, coupled to the hardware por sequencer circuit, the pmu including one or more central processing units (cpus) and a read only memory (rom). ... Xilinx Inc

06/08/17 / #20170161419

Folding duplicate instances of modules in a circuit design

Disclosed approaches for processing a circuit design include identifying duplicate instances of a module in a representation of the circuit design. A processor circuit performs folding operations for at least one pair of the duplicate instances of the module. ... Xilinx Inc

05/11/17 / #20170134009

Method for increasing active inductor operating range and peaking gain

Methods and apparatus are described for a differential active inductor load for inductive peaking in which cross-coupled capacitive elements are used to cancel out, or at least reduce, the limiting effect of the gate-to-drain capacitance (cgd) of transistors in the active inductor load. The cross-coupled capacitive elements extend the range over which the active inductor load behaves inductively and increase the quality factor (q) of each active inductor. ... Xilinx Inc

05/04/17 / #20170123815

Multistage boot image loading by configuration of a bus interface

An integrated circuit (ic) that includes a processor circuit can be booted by receiving, using a storage interface circuit of the ic, a first boot image from a nonvolatile memory chip. The first boot image is executed on a processor circuit of the ic to configure a bus interface module that is designed to communicate with a host device over a communication bus that links multiple devices and the ic. ... Xilinx Inc

04/27/17 / #20170115348

Methods and circuits for debugging circuit designs

Various example implementations are directed to circuits and methods for debugging circuit designs. According to an example implementation, waveform data is captured, for a set of signals produced by a circuit design during operation. ... Xilinx Inc

04/20/17 / #20170110407

Interposer-less stack die interconnect

Techniques for providing a semiconductor assembly having an interconnect die for die-to-die interconnection, an ic package, a method for manufacturing, and a method for routing signals in an ic package are described. In one implementation, a semiconductor assembly is provided that includes a first interconnect die coupled to a first integrated circuit (ic) die and a second ic die by inter-die connections. ... Xilinx Inc

04/06/17 / #20170098024

Interactive multi-step physical synthesis

A processor-implemented method is provided for placing and routing a circuit design. A first netlist is generated for the circuit design. ... Xilinx Inc

04/06/17 / #20170097910

Direct memory access for programmable logic device configuration

Using a storage interface circuit of a programmable ic, a first set of configuration data can be communicated between a storage circuit and the programmable ic. Using the first set of configuration data, the programmable ic can be programmed to include: a bus interface module that is designed to interface with a host device over a communication bus that links multiple devices, and an internal configuration access interface that is designed to interface between the bus interface module and programmable logic of the programmable ic. ... Xilinx Inc

03/30/17 / #20170092619

Stacked silicon package assembly having an enhanced lid

A method and apparatus are provided which improve heat transfer between a lid and an ic die of an ic (chip) package. In one embodiment, a chip package is provided that includes a first ic die, a package substrate, a lid and a stiffener. ... Xilinx Inc

03/02/17 / #20170063580

Transmitter circuit for and methods of generating a modulated signal in a transmitter

A transmitter circuit for generating a modulated signal in a transmitter of an integrated circuit is described. The transmitter circuit comprises a multiplexing stage having a multiplexing circuit configured to receive a differential input signal and to generate a differential output signal at a first output node of a first current path and at a second output node of a second current path, the multiplexing stage having a gain circuit configured to increase the swing of the differential output signal generated at the first output node and the second output node. ... Xilinx Inc

02/02/17 / #20170033774

Offset insensitive quadrature clock error correction and duty cycle calibration for high-speed clocking

Techniques for correcting clock distortion. The techniques include use of circuitry for detecting and correcting duty cycle distortion and quadrature clock phase distortion. ... Xilinx Inc

01/19/17 / #20170019278

Circuits for and methods of generating a modulated signal in a transmitter

A circuit for generating a modulated signal in a transmitter of an integrated circuit is disclosed. The circuit comprises a transmitter driver circuit having a first current path for receiving a first input signal of a pair of differential input signals and a second current path for receiving a second input signal of the pair of differential input signals, the transmitter driver circuit comprising a tail current path coupled to each of the first current path and the second current path; a first current source coupled between a first reference voltage and ground, wherein a first current of the first current source is proportional to the tail current of the tail current path; a first pull-up current source coupled between the first reference voltage and a first output node of the transmitter driver circuit; and a second pull-up current source coupled between the first reference voltage and a second output node of the transmitter driver circuit. ... Xilinx Inc

01/12/17 / #20170012598

Variable bandwidth filtering

An apparatus, and related method, relates generally to viable bandwidth filtering. In such an apparatus, an analysis filter bank has path filters associated with different bandwidths and is configured for filtering and transforming an input signal having a first bandwidth into a first interleaved output. ... Xilinx Inc

01/12/17 / #20170012596

M-path filter with outer and inner channelizers for passband bandwidth adjustment

Disclosed is apparatus and method to filter a signal. In such an apparatus, an outer polyphase filter is configured for receiving an input signal and for channelizing the input signal into outer filtered samples. ... Xilinx Inc

01/12/17 / #20170012041

Method and design of low sheet resistance meol resistors

An integrated circuit structure includes: a semiconductor substrate; a shallow trench isolation (sti) region in the semiconductor substrate; one or more active devices formed on the semiconductor substrate; and a resistor array having a plurality of resistors disposed above the sti region; wherein the resistor array comprises a portion of one or more interconnect contact layers that are for interconnection to the one or more active devices.. . ... Xilinx Inc

01/05/17 / #20170005627

Moving mean and magnitude dual path digital predistortion

An apparatus relates generally to preconditioning an input signal. In this apparatus, a first digital predistortion module and a second digital predistortion module are for receiving the input signal for respectively providing a first predistorted signal and a second predistorted signal. ... Xilinx Inc

01/05/17 / #20170004031

Variable code rate solid-state drive

An apparatus, as well as a method therefor, relates generally to managing reliability of a solid state storage. In such an apparatus, there is a memory controller for providing a code rate. ... Xilinx Inc








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