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Zeno Semiconductor Inc patents


Recent patent applications related to Zeno Semiconductor Inc. Zeno Semiconductor Inc is listed as an Agent/Assignee. Note: Zeno Semiconductor Inc may have other listings under different names/spellings. We're not affiliated with Zeno Semiconductor Inc, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "Z" | Zeno Semiconductor Inc-related inventors


Compact semiconductor memory device having reduced number of contacts, methods of operating and methods of making

An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The link or string includes at least one contact configured to electrically connect the memory cells to at least one control line, and the number of contacts in the string or link is the same as or less than the number of memory cells in the string or link.. ... Zeno Semiconductor Inc

Mosfet and memory cell having improved drain current through back bias application

A semiconductor metal-oxide-semiconductor field effect transistor (mosfet) transistor with increased on-state current obtained through intrinsic bipolar junction transistor (bjt) of mosfet has been described. Methods of operating the mos transistor are provided.. ... Zeno Semiconductor Inc

Memory device having electrically floating body transistor

A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. ... Zeno Semiconductor Inc

Memory device comprising an electrically floating body transistor and methods of using

A semiconductor memory cell comprising an electrically floating body having two stable states is disclosed. A method of operating the memory cell is disclosed.. ... Zeno Semiconductor Inc

Memory device comprising an electrically floating body transistor

A memory cell comprising includes a silicon-on-insulator (soi) substrate, an electrically floating body transistor fabricated on the silicon-on-insulator (soi) substrate, and a charge injector region. The floating body transistor is configured to have more than one stable state through an application of a bias on the charge injector region.. ... Zeno Semiconductor Inc

Scalable floating body memory cell for memory compilers and method of using floating body memories with memory compilers

A floating body sram cell that is readily scalable for selection by a memory compiler for making memory arrays is provided. A method of selecting a floating body sram cell by a memory compiler for use in array design is provided.. ... Zeno Semiconductor Inc

Memory cells, memory cell arrays, methods of using and methods of making

A semiconductor memory cell and arrays of memory cells are provided in at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; a gate positioned between the first and second regions and above the top surface; and a nonvolatile memory configured to store data upon transfer from the body region.. . ... Zeno Semiconductor Inc

Memory device comprising electrically floating body transistor

A semiconductor memory cell comprising an electrically floating body. A method of operating the memory cell is provided.. ... Zeno Semiconductor Inc

Dual-port semiconductor memory and first in first out (fifo) memory having electrically floating body transistor

Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory cell. The multi-port semiconductor memory cells include a plurality of gates and conductive regions interfacing with said floating body region. ... Zeno Semiconductor Inc

Semiconductor memory having both volatile and non-volatile functionality including resistance change material and method of operating

Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating body under any one of a plurality of predetermined conditions. ... Zeno Semiconductor Inc

Method of maintaining the state of semiconductor memory having electrically floating body transistor

Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell.. . ... Zeno Semiconductor Inc

Memory device comprising electrically floating body transistor

A semiconductor memory instance is provided that includes an array of memory cells. The array includes a plurality of semiconductor memory cells arranged in at least one column and at least one row. ... Zeno Semiconductor Inc

Method of operating semiconductor memory device with floating body transistor using silicon controlled rectifier principle

Methods of operating semiconductor memory devices with floating body transistors, using a silicon controlled rectifier principle are provided, as are semiconductor memory devices for performing such operations. A method of maintaining the data state of a semiconductor dynamic random access memory cell is provided, wherein the memory cell comprises a substrate being made of a material having a first conductivity type selected from p-type conductivity type and n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type; a second region having the second conductivity type, the second region being spaced apart from the first region; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; and a gate positioned between the first and second regions and adjacent the body region. ... Zeno Semiconductor Inc

Semiconductor memory having both volatile and non-volatile functionality and method of operating

Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. ... Zeno Semiconductor Inc

10/12/17 / #20170294438

Nand string utilizing floating body memory cell

Nand string configurations and semiconductor memory arrays that include such nand string configurations are provided. Methods of making semiconductor memory cells used in nand string configurations are also described.. ... Zeno Semiconductor Inc

10/12/17 / #20170294230

Memory cells, memory cell arrays, methods of using and methods of making

A semiconductor memory cell and arrays of memory cells are provided in at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; a gate positioned between the first and second regions and above the top surface; and a nonvolatile memory configured to store data upon transfer from the body region.. . ... Zeno Semiconductor Inc

09/28/17 / #20170278846

Semiconductor memory device having an electrically floating body transistor

An ic may include an array of memory cells formed in a semiconductor, including memory cells arranged in rows and columns, each memory cell may include a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; a buried region located within the memory cell and located adjacent to the floating body region, wherein the buried region has a second conductivity type, wherein the floating body region is bounded on a first side by a first insulating region having a first thickness and on a second side by a second insulating region having a second thickness, and a gate region above the floating body region and the second insulating region and is insulated from the floating body region by an insulating layer; and control circuitry configured to provide electrical signals to said buried region.. . ... Zeno Semiconductor Inc

09/21/17 / #20170271339

Compact semiconductor memory device having reduced number of contacts, methods of operating and methods of making

An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The link or string includes at least one contact configured to electrically connect the memory cells to at least one control line, and the number of contacts in the string or link is the same as or less than the number of memory cells in the string or link.. ... Zeno Semiconductor Inc

08/10/17 / #20170229466

Memory cell comprising first and second transistors and methods of operating

Semiconductor memory cells, array and methods of operating are disclosed. In one instance, a memory cell includes a bi-stable floating body transistor and an access device; wherein the bi-stable floating body transistor and the access device are electrically connected in series.. ... Zeno Semiconductor Inc

08/10/17 / #20170229178

A semiconductor memory having both volatile and non-volatile functionality comprising resistive change material and method of operating

A semiconductor memory cell including a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell, and a non-volatile memory comprising a bipolar resistive change element, and methods of operating.. . ... Zeno Semiconductor Inc

08/03/17 / #20170221900

Method of maintaining the state of semiconductor memory having electrically floating body transistor

Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell.. . ... Zeno Semiconductor Inc

07/27/17 / #20170213593

Semiconductor memory having volatile and multi-bit non-volatile functionality and method of operating

A semiconductor memory cell, semiconductor memory devices comprising a plurality of the semiconductor memory cells, and methods of using the semiconductor memory cell and devices are described. A semiconductor memory cell includes a substrate having a first conductivity type; a first region embedded in the substrate at a first location of the substrate and having a second conductivity type; a second region embedded in the substrate at a second location of the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory; a trapping layer positioned in between the :first and second locations and above a surface of the substrate; the trapping layer comprising first and second storage locations being configured to store data as nonvolatile memory independently of one another; and a control gate positioned above the trapping layer.. ... Zeno Semiconductor Inc

06/15/17 / #20170169887

Semiconductor device having electrically floating body transistor, semiconductor device having both volatile and non-volatile functionality and method of operating

A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a gate positioned between said first and second regions. The cell may be a multi-level cell. ... Zeno Semiconductor Inc

06/01/17 / #20170154888

Compact semiconductor memory device having reduced number of contacts, methods of operating and methods of making

An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The link or siring includes at least one contact configured to electrically connect the memory cells to at least one control line, and the number of contacts in the string or link is the same as or less than the number of memory cells in the string or link.. ... Zeno Semiconductor Inc

05/11/17 / #20170133382

Dual-port semiconductor memory and first in first out (fifo) memory having electrically floating body transistor

Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory cell. The multi-port semiconductor memory cells include a plurality of gates and conductive regions interfacing with said floating body region. ... Zeno Semiconductor Inc

05/11/17 / #20170133091

Memory cells, memory cell arrays, methods of using and methods of making

A semiconductor memory cell and arrays of memory cells are provided in at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; a gate positioned between the first and second regions and above the top surface; and a nonvolatile memory configured to store data upon transfer from the body region.. . ... Zeno Semiconductor Inc

05/04/17 / #20170125421

Memory device having electrically floating body transistor

A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. ... Zeno Semiconductor Inc

03/30/17 / #20170092648

Asymmetric semiconductor memory device having electrically floating body transistor

Asymmetric, semiconductor memory cells, arrays, devices and methods are described. Among these, an asymmetric, bi-stable semiconductor memory cell is described that includes: a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with the floating body region; a second region in electrical contact with the floating body region and spaced apart from the first region; and a gate positioned between the first and second regions, such that the first region is on a first side of the memory cell relative to the gate and the second region is on a second side of the memory cell relative to the gate; wherein performance characteristics of the first side are different from performance characteristics of the second side.. ... Zeno Semiconductor Inc

03/30/17 / #20170092359

Content addressable memory device having electrically floating body transistor

A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the second floating body transistor are electrically connected in series through a common node. ... Zeno Semiconductor Inc

03/30/17 / #20170092351

Memory device comprising an electrically floating body transistor

A memory cell comprising includes a silicon-on-insulator (soi) substrate, an electrically floating body transistor fabricated on the silicon-on-insulator (soi) substrate, and a charge injector region. The floating body transistor is configured to have more than one stable state through an application of a bias on the charge injector region.. ... Zeno Semiconductor Inc

03/16/17 / #20170076784

Systems and methods for reducing standby power in floating body memory devices

Methods, devices, arrays and systems for reducing standby power for a floating body memory array. One method includes counting bits of data before data enters the array, wherein the counting includes counting at least one of: a total number of bits at state 1 and a total number of all bits; a total number of bits at state 0 and the total number of all bits; or the total number of bits at state 1 and the total number of bits at state 0. ... Zeno Semiconductor Inc

02/23/17 / #20170053919

Method of maintaining the state of semiconductor memory having electrically floating body transistor

Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell.. . ... Zeno Semiconductor Inc

02/09/17 / #20170040326

Method of operating semiconductor memory device with floating body transistor using silicon controlled rectifier principle

Methods of operating semiconductor memory devices with floating body transistors, using a silicon controlled rectifier principle are provided, as are semiconductor memory devices for performing such operations. A method of maintaining the data state of a semiconductor dynamic random access memory cell is provided, wherein the memory cell comprises a substrate being made of a material having a first conductivity type selected from p-type conductivity type and n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type; a second region having the second conductivity type, the second region being spaced apart from the first region; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; and a gate positioned between the first and second regions and adjacent the body region. ... Zeno Semiconductor Inc

02/02/17 / #20170032842

Semiconductor memory having both volatile and non-volatile functionality including resistance change material and method of operating

Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating body under any one of a plurality of predetermined conditions. ... Zeno Semiconductor Inc

01/26/17 / #20170025534

Semiconductor memory having both volatile and non-volatile functionality and method of operating

Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. ... Zeno Semiconductor Inc

01/26/17 / #20170025164

Memory device comprising electrically floating body transistor

A semiconductor memory instance is provided that includes an array of memory cells. The array includes a plurality of semiconductor memory cells arranged in at least one column and at least one row. ... Zeno Semiconductor Inc








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