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Adesto Technologies Corporation patents


Recent patent applications related to Adesto Technologies Corporation. Adesto Technologies Corporation is listed as an Agent/Assignee. Note: Adesto Technologies Corporation may have other listings under different names/spellings. We're not affiliated with Adesto Technologies Corporation, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "A" | Adesto Technologies Corporation-related inventors


Concurrent read and reconfigured write operations in a memory device

A method of controlling a memory device can include: receiving, by an interface, a write command from a host; beginning execution of a write operation on a first array plane of a memory array in response to the write command, where the memory array includes a plurality of memory cells arranged in a plurality of array planes; receiving, by the interface, a read command from the host; reconfiguring the write operation in response to detection of the read command during execution of the write operation; beginning execution of a read operation on a second array plane in response to the read command; and restoring the configuration of the write operation after the read operation has at least partially been executed.. . ... Adesto Technologies Corporation

Ultra-deep power down mode control in a memory device

A method of controlling an ultra-deep power down (udpd) mode in a memory device, can include: receiving a write command from a host via an interface; beginning a write operation on the memory device to execute the write command; reading an auto-udpd (audpd) configuration bit from a status register; completing the write operation on the memory device; automatically entering the udpd mode upon completion of the write operation in response to the audpd configuration bit being set; and entering a standby mode upon completion of the write operation in response to the audpd configuration bit being cleared.. . ... Adesto Technologies Corporation

Nonvolatile memory elements having conductive structures with semimetals and/or semiconductors

A memory element programmable between different impedance states, comprising: a first electrode layer comprising a semimetal or semiconductor (semimetal/semiconductor) and at least one other first electrode element; a second electrode; and a switch layer formed between the first and second electrodes and comprising an insulating material; wherein atoms of the semimetal/semiconductor provide a reversible change in conductivity of the switch layer by application of electric fields.. . ... Adesto Technologies Corporation

Read latency reduction in a memory device

A memory device can include: a memory array with memory cells arranged as data lines; an interface that receives a read command requesting bytes of data in a consecutively addressed order from an address of a starting byte; a first buffer that stores a first data line from the memory array that includes the starting byte; a second buffer that stores a second data line from the memory array, which is consecutively addressed with respect to the first data line; output circuitry configured to access data from the buffers, and to sequentially output each byte from the starting byte through a highest addressed byte of the first data line, and each byte from a lowest addressed byte of the second data line until the requested data bytes has been output; and a data strobe driver that clocks each byte of data output by a data strobe on the interface.. . ... Adesto Technologies Corporation

Memory device having multiple read buffers for read latency reduction

A memory device can include: a memory array arranged to store data lines; an interface that receives a first read command requesting bytes of data in a consecutively addressed order from a starting byte; a cache memory having a first buffer storing a first data line including the starting byte, and a second buffer storing a second data line, from the cache memory or the memory array; output circuitry that accesses data from the first buffer, and sequentially outputs each byte from the starting byte through a highest addressed byte of the first data line; and from the second buffer and sequentially outputs each byte from a lowest addressed byte of the second data line until the requested bytes of data have been output in order to execute the first read command, the contents of the first and second buffers being maintained in the cache memory.. . ... Adesto Technologies Corporation

Memory elements having conductive cap layers and methods therefor

A memory element can include a first electrode; at least one switching layer formed over the first electrode; a second electrode layer; and at least one conductive cap layer formed over the second electrode layer having substantially no grain boundaries extending through to the second electrode layer; wherein the at least one switching layer is programmable between different impedance states by application of electric fields via that first and second electrode. Methods of forming such memory elements are also disclosed.. ... Adesto Technologies Corporation

Read latency reduction in a memory device

A memory device can include: a memory array with memory cells arranged as data lines; an interface that receives a read command requesting bytes of data in a consecutively addressed order from an address of a starting byte; a first buffer that stores a first data line from the memory array that includes the starting byte; a second buffer that stores a second data line from the memory array, which is consecutively addressed with respect to the first data line; output circuitry configured to access data from the buffers, and to sequentially output each byte from the starting byte through a highest addressed byte of the first data line, and each byte from a lowest addressed byte of the second data line until the requested data bytes has been output; and a data strobe driver that clocks each byte of data output by a data strobe on the interface.. . ... Adesto Technologies Corporation

Memory device ultra-deep power-down mode exit control

A memory device operable in an ultra-deep power-down mode can include: a command user interface; a voltage regulator having an output that provides a supply voltage for a plurality of components of the memory device, where the plurality of components comprises the command user interface; a wake-up circuit that remains powered on even when the memory device is in the ultra-deep power-down mode; the memory device being operable to enter the ultra-deep power-down mode in response to receiving a first predetermined command that causes the output of the voltage regulator to be disabled to completely power down the plurality of components during the ultra-deep power-down mode; and the memory device being operable to exit the ultra-deep power-down mode in response to receiving one of a hardware reset command sequence, a reset pin assertion, a power supply cycling, and a second predetermined command.. . ... Adesto Technologies Corporation

Support for improved throughput in a memory device

A method of controlling a memory device can include: (i) receiving a first read command for a critical byte, where the critical byte resides in a first group of a memory array on the memory device; (ii) reading the critical byte from the memory array in response to the first read command, and providing the critical byte; (iii) reading a next byte in the first group; (iv) outputting the next byte from the first group when a clock pulse; (v) repeating the reading the next byte and the outputting the next byte for each byte in the first group; (vi) reading a first byte in a second group of the memory array, where the second group is sequential to the first group, and where each group is allocated to a cache line; and (vii) outputting the first byte from the second group when a clock pulse is received.. . ... Adesto Technologies Corporation

Memory devices and methods having instruction acknowledgement

A system can include memory circuits configured to execute memory access operations in response to commands, a serial interface circuit configured to receive commands, including at least a first type command, and a controller circuit configured to generate a command complete acknowledgement that is output at the interface circuit after an operation indicated by the first type command has been completed by the memory circuits.. . ... Adesto Technologies Corporation








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