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Advanced Micro Devices Inc patents (2015 archive)
Recent patent applications related to Advanced Micro Devices Inc. Advanced Micro Devices Inc is listed as an Agent/Assignee. Note: Advanced Micro Devices Inc may have other listings under different names/spellings. We're not affiliated with Advanced Micro Devices Inc, we're just tracking patents.
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Video and image compression based on position of the image generating device
An apparatus, computer readable medium, and method of compressing images generated on an image generating device, the method including responsive to a generated image and position and orientation data associated with an image generating device which generated the image, selecting a previously generated image having a similar position and a similar orientation as the generated image; and if a comparison between the selected previously generated image and the generated image indicates the difference between one of the previously generated images and the generated image is less than a threshold difference, then compressing the generated image using the previously generated image. The method may include generating the generated image from light incident to the image generating device, and generating the position and orientation associated with the image generating device.. ... Advanced Micro Devices Inc
Memory physical layer interface logic for generating dynamic random access memory (dram) commands with programmable delays
A plurality of registers implemented in association with a memory physical layer interface (phy) can be used to store one or more instruction words that indicate one or more commands and one or more delays. A training engine implemented in the memory phy can generate at-speed programmable sequences of commands for delivery to an external memory and to delay the commands based on the one or more delays. ... Advanced Micro Devices Inc
Integrated controller for training memory physical layer interface
A controller integrated in a memory physical layer interface (phy) can be used to control training used to configure the memory phy for communication with an associated external memory such as a dynamic random access memory (dram), thereby removing the need to provide training sequences over a data pipeline between a bios and the memory phy. For example, a controller integrated in the memory phy can control read training and write training of the memory phy for communication with the external memory based on a training algorithm. ... Advanced Micro Devices Inc
Calibrating a power supply using power supply monitors
A processing system includes one or more power supply monitors (psms) to measure one or more first voltages corresponding to one or more locations in the processing system. The measurements are performed concurrently with the processing system executing one or more code loops. ... Advanced Micro Devices Inc
Source synchronous bus clock gating system
Embodiments are described for a method of reducing power consumption in source synchronous bus systems by reducing signal transitions in the system. Instead of sending clock and data valid signals, only the start and end of valid data packets are marked by clock signal transitions, or only a number of clock pulses that corresponds to number of data words is sent, or only a number transitions on clock signals are sent. ... Advanced Micro Devices Inc
Dual-rail encoding
Embodiments may include a method, system and apparatus for providing for encoded dual-rail signal communications in asynchronous circuitry. A dual rail signal pair is received. ... Advanced Micro Devices Inc
Method and apparatus for bezel mitigation with head tracking
The present disclosure presents methods and apparatuses for operating a multi-display device to mitigate the effects of image interruption due to bezels between individual display devices. For example, a method of operating a video device includes generating a bezel-corrected image which spans a plurality of display devices, the bezel-corrected image including masked image pixels, wherein the masked image pixels are associated with a bezel of at least one of the plurality of display devices. ... Advanced Micro Devices Inc
Decoupled entry and exit prediction for power gating
Power gating logic detects a transition of a component of a processing device into an idle state. In response to detecting the transition, the entry/exit power gating logic selectively implements one or more entry prediction techniques for power gating the component based on estimates of reliability of the entry prediction techniques. ... Advanced Micro Devices Inc
Sidecar sram for high granularity in floor plan aspect ratio
A system and method for floorplanning a memory. A computing system includes a processing unit which generates memory access requests and a memory. ... Advanced Micro Devices Inc
Wavefront resource virtualization
A processor comprising hardware logic configured to execute of a first wavefront in a hardware resource and stop execution of the first wavefront before the first wavefront completes. The processor schedules a second wavefront for execution in the hardware resource.. ... Advanced Micro Devices Inc
Memory controller power management based on latency
A processor monitors, directly or indirectly, the amount of time it takes for the memory controller to respond to one or more memory access requests. When this memory access latency indicates that a memory latency tolerance of a program thread has been exceeded, the processor can apportion additional power to the memory controller, thereby increasing the speed with which the memory controller can process memory access requests.. ... Advanced Micro Devices Inc
Die-stacked device with partitioned multi-hop network
An electronic assembly includes horizontally-stacked die disposed at an interposer, and may also include vertically-stacked die. The stacked die are interconnected via a multi-hop communication network that is partitioned into a link partition and a router partition. ... Advanced Micro Devices Inc
Translation lookaside buffer
The described embodiments include a translation lookaside buffer (“tlb”) that is used for performing virtual address to physical address translations when making memory accesses in a memory in a computing device. In the described embodiments, the tlb includes a hierarchy of tables that are each used for performing virtual address to physical address translations based on the arrangement of pages of memory in corresponding regions of the memory. ... Advanced Micro Devices Inc
Resizable and relocatable queue
The described embodiments include a computing device with a queue stored in a memory of the computing device. In the described embodiments, the queue may be relocated and/or resized in the memory using a queue address, a queue size, a head pointer, and/or a tail pointer associated with the queue. ... Advanced Micro Devices Inc
Power management across heterogeneous processing units
A method includes controlling active frequency states of a plurality of heterogeneous processing units based on frequency sensitivity metrics indicating performance coupling between different types of processing units in the plurality of heterogeneous processing units. A processor includes a plurality of heterogeneous processing units and a performance controller to control active frequency states of the plurality of heterogeneous processing units based on frequency sensitivity metrics indicating performance coupling between different types of processing units in the plurality of heterogeneous processing units. ... Advanced Micro Devices Inc
Floating point multiply accumulator multi-precision mantissa aligner
A processing device is provided that includes a first, second and third precision operation circuit. The processing device further includes a shared, bit-shifting circuit that is communicatively coupled to the first, second and third precision operation circuits. ... Advanced Micro Devices Inc
Locally asynchronous logic circuit and method therefor
A locally asynchronous logic circuit includes an input latch; a synchronous-to-asynchronous control circuit having an input for receiving a first clock signal, a first output coupled to the latch enable input of the input latch, and a second output for providing a start signal; a predetermined number of stages coupled between the output of the input latch and an output of the locally asynchronous logic circuit, each stage having an asynchronous functional circuit and an associated completion circuit having an input for receiving a corresponding start signal and an output for providing a corresponding done signal; and an asynchronous-to-synchronous control circuit having a first input for receiving a done signal of a preceding stage, and an output for providing a valid signal. The asynchronous-to-synchronous control circuit activates said first valid signal to indicate said output of the locally asynchronous logic circuit is valid.. ... Advanced Micro Devices Inc
Channel rotating error correction code
A write or read method for use in a computer having multiple channels of memory includes writing or reading data to or from one channel in the memory, and simultaneously in parallel writing or reading an error correction code corresponding to the data to or from a different channel in the memory.. . ... Advanced Micro Devices Inc
Bimodal cooling in modular server system
A server system includes a plurality of stacked modular computing structures. Each modular computing structure includes a circuit board comprising a computing resource, an air-fluid heat exchange structure comprising a first set of pipe segments, and a cold plate structure attached to a second set of pipe segments of the modular computing structure. ... Advanced Micro Devices Inc
Apparatus to facilitate orthogonal coupling of a server sled with a server backplane
An orthogonal coupling mechanism includes a threaded rod, a pair of travelers engaging the threaded rod, and an actuator. The actuator is disposed on the threaded rod, such that the actuator translates a first axial force along the axis of the threaded rod into a rotational movement of the threaded rod about its axis. ... Advanced Micro Devices Inc
Route mapping at individual nodes of a cluster server
Each compute node of a cluster compute server generates and maintains route information for routing messages to other nodes of the server. Each compute node identifies the other nodes connected to a fabric interconnect and generates, based on a set of routing constraints, routes to each of the other nodes. ... Advanced Micro Devices Inc
Centralized distribution of configuration parameters for a cluster server
A management node of a server maintains a database of configuration parameters that stores the individual configuration parameters for each compute node. In response to a boot request at a compute node, a configuration parameter control module at the node intercepts locally targeted requests to load configuration parameters. ... Advanced Micro Devices Inc
Configuration of a cluster server using cellular automata
A cluster computer server is configured after a system reset or other configuration event. Each node of a fabric of the cluster compute server is employed, for purposes of configuration, as a cell in a cellular automaton, thereby obviating the need for a special configuration network to communicate configuration information from a central management unit. ... Advanced Micro Devices Inc
Redundancy method and apparatus for shader column repair
Methods, systems and non-transitory computer readable media are described. A system includes a shader pipe array, a redundant shader pipe array, a sequencer and a redundant shader switch. ... Advanced Micro Devices Inc
Thin provisioning architecture for high seek-time devices
A compute server accomplishes physical address to virtual address translation to optimize physical storage capacity via thin provisioning techniques. The thin provisioning techniques can minimize disk seeks during command functions by utilizing a translation table and free list stored to both one or more physical storage devices as well as to a cache. ... Advanced Micro Devices Inc
Hybrid system and method for determining performance levels based on thermal conditions within a processor
A system and method for efficient management of operating modes within an integrated circuit (ic) for optimal power and performance targets. A semiconductor chip includes one or more processing units each of which operates with respective operating parameters. ... Advanced Micro Devices Inc
System and method for memory allocation in a multiclass memory system
A system for memory allocation in a multiclass memory system includes a processor coupleable to a plurality of memories sharing a unified memory address space, and a library store to store a library of software functions. The processor identifies a type of a data structure in response to a memory allocation function call to the library for allocating memory to the data structure. ... Advanced Micro Devices Inc
Memory array test logic
A test circuit for a static random access memory (sram) array includes a plurality of stages coupled in a ring. Each stage includes a plurality of bit cells to store information, a bit line and a complementary bit line coupled to the plurality of bit cells, and a plurality of word lines coupled to the plurality of bit cells. ... Advanced Micro Devices Inc
Switching a computer system from a high performance mode to a low power mode
A computer system includes a first processor, a second processor, and a common memory connected to the second processor. The computer system is switched from a high performance mode, in which at least a portion of the first processor and at least a portion of components on the second processor are active, to a low power mode, in which at least a portion of the first processor is active and the components on the second processor are inactive. ... Advanced Micro Devices Inc
Memory access monitor
For each access request received at a shared cache of the data processing device, a memory access pattern (map) monitor predicts which of the memory banks, and corresponding row buffers, would be accessed by the access request if the requesting thread were the only thread executing at the data processing device. By recording predicted accesses over time for a number of access requests, the map monitor develops a pattern of predicted memory accesses by executing threads. ... Advanced Micro Devices Inc
Processor management based on application performance data
Application performance data that indicates a level of service provided in executing one or more applications is determined in software running on one or more processor cores in a computing system that executes the one or more applications. The application performance data is provided to a controller in the computing system that is distinct from the one or more processor cores.. ... Advanced Micro Devices Inc
Methods and systems for mitigating memory drift
A memory cell is read by measuring a parameter associated with the memory cell with a first resolution to determine a value stored in the memory cell. The parameter is also measured with a second resolution that is finer than the first resolution. ... Advanced Micro Devices Inc
Stacked semiconductor chips packaging
Various methods and apparatus for joining stacked substrates to a circuit board are disclosed. In one aspect, a method of manufacturing is provided that includes coupling plural substrates to form a stack. ... Advanced Micro Devices Inc
Method and apparatus for encoding erroneous data in an error correction code protected memory
A method and device are described for encoding erroneous data in an error correction code (ecc) protected memory. In one embodiment, incoming data including a plurality of data symbols and a data integrity marker is received. ... Advanced Micro Devices Inc
Dynamic power allocation based on phy power estimation
A system has a plurality of electronic components including a memory, a phy coupled to the memory, and one or more other electronic components. Power consumed by the phy is estimated during operation of the system. ... Advanced Micro Devices Inc
Chip debug during power gating events
A system, method, and tangible computer readable medium for chip debug is disclosed. For example, the system can include a plurality of functional blocks, a debug path, and a debug bus steering module. ... Advanced Micro Devices Inc
Energy-aware boosting of processor operating points for limited duration workloads
The operating point of a processing unit is controlled based on the power consumption (i.e., the rate of energy consumption) associated with a workload, wherein low power consumption may indicate short-duration workloads with idle phases and high power consumption may indicate long, sustained workloads. Energy credits are accumulated while a drain rate of a battery is lower than a threshold drain rate and the energy credits are consumed while the drain rate is higher than the threshold drain rate. ... Advanced Micro Devices Inc
Using temperature margin to balance performance with power allocation
A method and apparatus using temperature margin to balance performance with power allocation. Nominal, middle and high power levels are determined for compute elements. ... Advanced Micro Devices Inc
Address-partitioned multi-class physical memory system
A multilevel memory system includes a plurality of memories and a processor having a memory controller. The memory controller classifies each memory in accordance with a plurality of memory classes based on its level, its type, or both. ... Advanced Micro Devices Inc
Handling pointers in program code in a system that supports multiple address spaces
Some embodiments include a processing subsystem that compiles program code to generate compiled program code. In these embodiments, while compiling the program code, the processing subsystem first identifies a pointer in the program code that points to an unspecified address space. ... Advanced Micro Devices Inc
Memory interface supporting both ecc and per-byte data masking
A memory and a method of storing data in a memory are provided. The memory comprises a memory block comprising data bits and additional bits. ... Advanced Micro Devices Inc
Mechanisms to save user/kernel copy for cross device communications
Central processing units (cpus) in computing systems manage graphics processing units (gpus), network processors, security co-processors, and other data heavy devices as buffered peripherals using device drivers. Unfortunately, as a result of large and latency-sensitive data transfers between cpus and these external devices, and memory partitioned into kernel-access and user-access spaces, these schemes to manage peripherals may introduce latency and memory use inefficiencies. ... Advanced Micro Devices Inc
Cryptographic protection of information in a processing system
A processor employs a hardware encryption module in the processor's memory access path to cryptographically isolate secure information. In some embodiments, the encryption module is located at a memory controller (e.g. ... Advanced Micro Devices Inc
Adaptive voltage scaling
Some embodiments of a processing device include one or more power supply monitors to provide one or more counts representative of one or more operating frequencies of one or more circuit blocks based on a voltage supplied to the circuit block(s). Some embodiments of the processing device also include a system management unit to determine an initial voltage supplied to the circuit block(s) based on a target count and to reduce the voltage supplied to the circuit block(s) from the initial voltage in response to the count(s) generated by the power supply monitor(s) exceeding the target count.. ... Advanced Micro Devices Inc
Control of performance levels of different types of processors via a user interface
An apparatus and a method for controlling power consumption associated with a computing device having first and second processors configured to perform different types of operations includes providing a user interface that allows, during normal operation of the computing device, at least one of: (i) a user selection of desired performance levels of the first and second processors relative to one another, such that higher desired performance levels of one processor correspond to lower desired performance levels of the other processor, and (ii) a user selection of a desired performance level of the first processor and a user selection of a desired performance level of the second processor, the two user selections being made independently of one another. The apparatus and method control, during normal operation of the computing device, performance levels of the processors in response to the one or more user selections of the desired performance levels.. ... Advanced Micro Devices Inc
Thermally-aware process scheduling
A scheduler is presented that can adjust, responsive to a thermal condition at the processing device, a scheduling of process threads for compute units of the processing device so as to increase resource contentions between the process threads.. . ... Advanced Micro Devices Inc
Method and apparatus of adaptive application performance
A method and apparatus of adaptive application performance includes a determination of at least one criteria for implementing adaptive application performance measures. Based upon the determination, adaptive application performance measures are implemented.. ... Advanced Micro Devices Inc
Self-adjusting clock doubler and integrated circuit clock distribution system using same
In one form, a clock doubler includes a switched inverter, an exclusive logic circuit, and a control signal generation circuit. The switched inverter has first and second control inputs for respectively receiving first and second control signals, a signal input for receiving a clock input signal, and an output. ... Advanced Micro Devices Inc
Memory and memory controller for high reliability operation and method
In one form, a memory includes a memory bank, a page buffer, and an access circuit. The memory bank has a plurality of rows and a plurality of columns with volatile memory cells at intersections of the plurality of row and the plurality of columns. ... Advanced Micro Devices Inc
Region-based image decompression
A method and a non-transitory computer readable medium for decompressing an image including one or more regions are presented. A region of the image is selected to be decoded. ... Advanced Micro Devices Inc
Mode-dependent access to embedded memory elements
A system has a plurality of functional modules including a first functional module and one or more other functional modules. The first functional module includes an embedded memory element and is configurable in a plurality of modes including a first mode and a second mode. ... Advanced Micro Devices Inc
Connector adaptor to facilitate coupling of a mating card edge with a female card-edge connector
A connector adaptor facilitates coupling of a mating card edge with a corresponding female card-edge connector disposed on a circuit board. A gathering bevel at the face of the connector adaptor guides the mating card edge from the face of the connector adaptor to the slot at the connection surface of the female card-edge connector, thereby reducing the risk of damage to the female card-edge connector or the mating card edge during a blind mating attempt. ... Advanced Micro Devices Inc
Relocating infrequently-accessed dynamic random access memory (dram) data to non-volatile storage
A method includes emptying a first region of a dynamic random access memory of data by moving data from the first region to a non-volatile memory and reducing a refresh rate of the dynamic random access memory responsive to emptying the first region of data. A system includes a memory controller to refresh a dynamic random access memory based on a configurable refresh rate, the dynamic random access memory having a plurality of regions, each region having an associated minimum refresh rate, and a processing unit to empty a first region of the plurality of regions of the dynamic random access memory by moving data from the first region to a non-volatile memory and to reduce the configurable refresh rate responsive to emptying the first region.. ... Advanced Micro Devices Inc
Handling reads following transactional writes during transactions in a computing device
The described embodiments include a computing device that handles cache blocks during a transaction. In the described embodiments, after an entity has written to a cache block in a cache during the transaction, the computing device responds to a read request for the cache block from another entity with a copy of the cache block in a pre-transactional state. ... Advanced Micro Devices Inc
Low insertion delay clock doubler and integrated circuit clock distribution system using same
A clock doubler includes a first nand gate having a first input for receiving a clock input signal and a second input, a second nand gate having a first input and a second input for receiving a complement of the clock input signal, an output nand gate having a first and second inputs coupled to outputs of the first and second nand gates, respectively, and an output for providing a clock output signal, an inverter chain having an input for receiving the clock input signal and responsive to first and second control signals to selectively provide a first true output to the first input of the second nand gate, and a second complementary output to the second input of the first nand gate, and a control signal generation circuit providing the first and second control signals in response to the outputs of the first and second nand gates.. . ... Advanced Micro Devices Inc
Performing logical operations in a memory
The described embodiments include a memory with a memory array and logic circuits. In these embodiments, logical operations are performed on data from the memory array by reading the data from the memory array, performing a logical operation on the data in the logic circuits, and writing the data back to the memory array. ... Advanced Micro Devices Inc
Page migration in a 3d stacked hybrid memory
A die-stacked hybrid memory device implements a first set of one or more memory dies implementing first memory cell circuitry of a first memory architecture type and a second set of one or more memory dies implementing second memory cell circuitry of a second memory architecture type different than the first memory architecture type. The die-stacked hybrid memory device further includes a set of one or more logic dies electrically coupled to the first and second sets of one or more memory dies, the set of one or more logic dies comprising a memory interface and a page migration manager, the memory interface coupleable to a device external to the die-stacked hybrid memory device, and the page migration manager to transfer memory pages between the first set of one or more memory dies and the second set of one or more memory dies.. ... Advanced Micro Devices Inc
Predicting power management state durations on a per-process basis
Durations of power management states are predicted on a per-process basis. Some embodiments include storing, in one or more data structures associated with one or more processes, information indicating previous durations of a power management state associated with the process(es). ... Advanced Micro Devices Inc
Lever mechanism to facilitate edge coupling of circuit board
A lever mechanism facilitates coupling of a sliding board and a connector. A sliding board is partially enclosed by a sliding board enclosure, such that the sliding board is slidable relative to the enclosure. ... Advanced Micro Devices Inc
Boosting the operating point of a processing device for new user activities
A processing system detects user activities on one or more processing units. In response, an operating point (operating frequency or an operating voltage) of the processing unit handing the user activity is increased at the processing unit. ... Advanced Micro Devices Inc
Dedicated interface for coupling flash memory and dynamic random access memory
The present application describes embodiments of an interface for coupling flash memory and dynamic random access memory (dram) in a processing system. Some embodiments include a dedicated interface between a flash memory and dram. ... Advanced Micro Devices Inc
Methods and systems of synchronizer selection
A circuit includes a plurality of synchronizers to adapt a signal from a first clock domain to a second clock domain. Each synchronizer of the plurality of synchronizers includes a synchronizer input to receive the signal from the first clock domain and a synchronizer output to provide the signal as adapted to the second clock domain. ... Advanced Micro Devices Inc
Semiconductor device having high-k gate dielectric above an sti region
By forming a trench isolation structure after providing a high-k dielectric layer stack, direct contact of oxygen-containing insulating material of a top surface of the trench isolation structure with the high-k dielectric material in shared polylines may be avoided. This technique is self-aligned, thereby enabling further device scaling without requiring very tight lithography tolerances. ... Advanced Micro Devices Inc
Circuit and data processor with headroom monitoring and method therefor
A circuit with headroom monitoring includes a memory array having memory cells, a replica array, and a built-in self test circuit. The replica array has a plurality of word lines, a plurality of bit line pairs, and memory cells located at intersections of the plurality of word lines and the plurality of bit line pairs. ... Advanced Micro Devices Inc
Extensible i/o activity logs
A method of managing peripherals is performed in a device coupled to a processor in a computer system. In the method, information associated with i/o activity for one or more peripherals is recorded in a first segment of a log. ... Advanced Micro Devices Inc
Configuring processor policies based on predicted durations of active performance states
Durations of active performance states of components of a processing system can be predicted based on one or more previous durations of an active state of the components. One or more entities in the processing system such as processor cores or caches can be configured based on the predicted durations of the active state of the components. ... Advanced Micro Devices Inc
Partitionable memory interfaces
A memory device receives a plurality of read commands and/or write commands in parallel. The memory device transmits data corresponding to respective read commands on respective portions of a data bus and receives data corresponding to respective write commands on respective portions of the data bus. ... Advanced Micro Devices Inc
Power gating based on cache dirtiness
Power gating decisions can be made based on measures of cache dirtiness. Analyzer logic can selectively power gate a component of a processor system based on a cache dirtiness of one or more caches associated with the component. ... Advanced Micro Devices Inc
Multiple-candidate motion estimation with advanced spatial filtering of differential motion vectors
A system and method of performing motion estimation in a video encoder is enclosed. The system and method include calculating one or more candidate motion vectors for each macroblock of a video image to form a list of candidate motion vectors, calculating a second one or more candidate motion vectors using a sub-region of at least one macroblock of the video image to include in the list of candidate motion vectors, and comparing the calculated candidate motion vectors of a first macroblock with the calculated candidate motion vectors of at least one sub-region of the first macroblock to provide the estimated contribution to the candidate motion vector of the macroblock. ... Advanced Micro Devices Inc
Die-die stacking structure and method for making the same
The present invention relates to die-die stacking structure and the method for making the same. The die-die stacking structure comprises a top die having a bottom surface, a first insulation layer covering the bottom surface of the top die, a bottom die having a top surface, a second insulation layer covering the top surface of the bottom die, a plurality of connection members between the top die and the bottom die and a protection material between the first insulation layer and the second insulation layer. ... Advanced Micro Devices Inc
Voltage droop mitigation in 3d chip system
The present invention relates to a multichip system and a method for scheduling threads in 3d stacked chip. The multichip system comprises a plurality of dies stacked vertically and electrically coupled together; each of the plurality of dies comprising one or more cores, each of the plurality of dies further comprising: at least one voltage violation sensing unit, the at least one voltage violation sensing unit being connected with the one or more cores of each die, the at least one voltage sensing unit being configured to independently sense voltage violation in each core of each die; and at least one frequency tuning unit, the at least one frequency tuning unit being configured to tune the frequency of each core of each die, the at least one frequency tuning unit being connected with the at least one voltage violation sensing unit. ... Advanced Micro Devices Inc
Die-stacked memory device with reconfigurable logic
A die-stacked memory device incorporates a reconfigurable logic device to provide implementation flexibility in performing various data manipulation operations and other memory operations that use data stored in the die-stacked memory device or that result in data that is to be stored in the die-stacked memory device. One or more configuration files representing corresponding logic configurations for the reconfigurable logic device can be stored in a configuration store at the die-stacked memory device, and a configuration controller can program a reconfigurable logic fabric of the reconfigurable logic device using a selected one of the configuration files. ... Advanced Micro Devices Inc
System and method for security processor control over cpu power states
The present disclosure presents methods and apparatuses for controlling a power state, which may include a c-state, of one or more processing cores of a processor. In an aspect, an example method of securing a power state change of a processor is presented, the method including the steps of receiving a power state change request from the processor, the processor having a plurality of potential power states each including an operating power profile; determining a power state change request mode associated with the processor; forwarding the power state change request to a security processor where the power state change request mode is a one-time request mode; receiving a power state change request response from the security processor in response to the request; and adjusting the current power state of the processor to the target power state where the power state change request response comprises a power state change approval.. ... Advanced Micro Devices Inc
System and method for monitoring and controlling a performance state change
The present disclosure relates to a method and system for securing a performance state change of one or more processors. A disclosed method includes detecting a request to change a current performance state of a processor to a target performance state, and adjusting an operating level tolerance range of the current performance state to include operating levels associated with a transition from the current performance state to the target performance state. ... Advanced Micro Devices Inc
Methods and apparatus for software chaining of co-processor commands before submission to a command queue
Methods and apparatus of interleaving two or more workloads are presented herein. The methods and apparatus may comprise a schedule controller and a coprocessor. ... Advanced Micro Devices Inc
Dynamic and adaptive sleep state management
An approach is described herein that includes a method for power management of a device. In one example, the method includes sampling duration characteristics for a plurality of past idle events for a predetermined interval of time and determining whether to transition a device to a powered-down state based on the sampled duration characteristics. ... Advanced Micro Devices Inc
Using an idle duration history to configure an idle state of an entity in a computing device
The described embodiments include a computing device with an entity (a processor, a processor core, etc.) and a controller. In these embodiments, the controller, using an idle duration history, predicts a duration of a next idle period for the entity. ... Advanced Micro Devices Inc
Platform secure boot
A system and method for securing a boot process on the electronic device using a hardware-based secure processor are provided. The hardware-based secure processor receives a boot instruction. ... Advanced Micro Devices Inc
Bandwidth increase in branch prediction unit and level 1 instruction cache
A processor, a device, and a non-transitory computer readable medium for performing branch prediction in a processor are presented. The processor includes a front end unit. ... Advanced Micro Devices Inc
Ordering and bandwidth improvements for load and store unit and data cache
The present invention provides a method and apparatus for supporting embodiments of an out-of-order load to load queue structure. One embodiment of the apparatus includes a load queue for storing memory operations adapted to be executed out-of-order with respect to other memory operations. ... Advanced Micro Devices Inc
Processor and methods for immediate handling and flag handling
Described herein are methods and processors for flag renaming in groups to eliminate dependencies of instructions. Decoder and execution units in the processor may be configured to rename flags into groups that allow each group to be treated separately as appropriate. ... Advanced Micro Devices Inc
Processor and methods for floating point register aliasing
Methods, devices, and systems for accessing packed registers are presented. A state of the packed registers may be tracked and it may be determined whether the register is directly accessible based on the state. ... Advanced Micro Devices Inc
Method and apparatus for providing dedicated entries in a content addressable memory to facilitate real-time clients
A device and method for partitioning a cache that is expected to operate with at least two classes of clients (such as real-time clients and non-real-time clients). A first portion of the cache is dedicated to real-time clients such that non-real-time clients are prevented from utilizing said first portion.. ... Advanced Micro Devices Inc
Unified store queue
Embodiments herein provide for improved store-to-load-forwarding (stlf) logic and linear aliasing effect reduction logic. In one embodiment, a load instruction to be executed is selected. ... Advanced Micro Devices Inc
Method and apparatus for reformatting page table entries for cache storage
A device for and method of storing page table entries in a first cache. A first page table entry is received having a fragment field that contains address information for a requested first page and at least a second page logically adjacent to the first page. ... Advanced Micro Devices Inc
Input/output memory map unit and northbridge
The present invention provides for page table access and dirty bit management in hardware via a new atomic test[0] and or and mask. The present invention also provides for a gasket that enables ace to cci translations. ... Advanced Micro Devices Inc
Method and apparatus for performing a bus lock and translation lookaside buffer invalidation
A method and apparatus for performing a bus lock and a translation lookaside buffer invalidate transaction includes receiving, by a lock master, a lock request from a first processor in a system. The lock master sends a quiesce request to all processors in the system, and upon receipt of the quiesce request from the lock master, all processors cease issuing any new transactions and issue a quiesce granted transaction. ... Advanced Micro Devices Inc
Method and apparatus for providing performance data over a debug bus
A device and method for providing performance information about a processing device. A stream of performance data is generated by one or more devices whose performance is reflected in the performance data. ... Advanced Micro Devices Inc
Predictive periodic synchronization using phase-locked loop digital ratio updates
Embodiments are described for a method and system of enabling updates from a clock controller to be sent directly to a predictive synchronizer to manage instant changes in frequency between transmit and receive clock domains, comprising receiving receive and transmit reference frequencies from a phase-locked loop circuit, receiving receive and transmit constant codes from a controller coupled to the phase-locked loop circuit, obtaining a time delay factor to accommodate phase detection between the transmit and receive clock domains, and calculating new detection interval and frequency information using the time delay factor, the reference frequencies, and the constant codes.. . ... Advanced Micro Devices Inc
Virtualized aes computational engine
A computational engine may include an input configured to receive a first data packet and a second data packet, a context memory configured to store one or more contexts, and a set of computational elements coupled with the input and coupled with the context memory. The set of computational elements may be configured to generate a first output data packet by executing a first sequence of cryptographic operations on the first data packet, and generate a second output data packet by executing a second sequence of cryptographic operations on the second data packet and on a selected context of the one of the one or more contexts. ... Advanced Micro Devices Inc
Unified key schedule engine
A key generator may comprise a first set of word registers each configured to store at least one word of a prior key, a set of computational elements coupled with the first set of word registers, one or more path selection elements coupled with the set of computational elements, wherein the one or more path selection elements are configured to select as a selected computational pathway a first computational pathway including a first subset of computational elements when a mode selection signal indicates a first mode, and select as the selected computational pathway a second computational pathway including a second subset of computational elements when the mode selection signal indicates a second mode, and a second set of word registers coupled with the set of computational elements, wherein each of the second set of word registers is configured to store at least one word of a new key generated by the selected computational pathway.. . ... Advanced Micro Devices Inc
Virtualized sha computational engine
A computational engine may comprise a working memory configured to receive a first input message and a second input message, a context memory coupled with the working memory, wherein the context memory is configured to simultaneously store a first context corresponding to the first input message and a second context corresponding to the second input message, and a set of computational elements coupled with the working memory and coupled with the context memory, wherein the set of computational elements is configured to finish generating a first output digest based on the first input message and a first context after starting generation of a second output digest based the second input message and a second context and before finishing the generation of the second output digest.. . ... Advanced Micro Devices Inc
Efficient deflate decompression
A decompression engine may include an input configured to receive an input code comprises one or more bits from a bitstream of encoded data, a symbol decoder coupled with the input, where the symbol decoder is configured to calculate, based on the input code, a plurality of candidate addresses each corresponding to a code group. The symbol decoder may further include a group identifier module coupled with the symbol decoder, wherein the group identifier module is configured to identify one of the plurality of code groups corresponding to the input code, and a multiplexer coupled with the group identifier module, wherein the multiplexer is configured to select as a final address one of the plurality of candidate addresses corresponding to the identified code group.. ... Advanced Micro Devices Inc
Continuous frequency measurement for predictive periodic synchronization
Embodiments are described for a method of continuously measuring the ratio of frequencies between the transmit and receive clock domains of a heterochronous system using an array of digital frequency measurement circuits that provide overlapping frequency and detection interval measurements within single counter periods required for a single frequency measurement circuit to complete a frequency measurement. Embodiments may be used in a predictive synchronizer to provide low latency, continuous frequency measurements for system-on-chip (soc) devices that employ frequency drift or ramping to reduce power consumption and overheating conditions.. ... Advanced Micro Devices Inc
System-level testing of non-singulated integrated circuit die on a wafer
Structures and methods for system-level testing of integrated circuit dies at wafer sort is disclosed. This concept combines a system-level test (which is traditionally a “socketed” test performed on a packaged ic in a test socket) with the ability to contact an integrated circuit die on a wafer using a probe card. ... Advanced Micro Devices Inc
Leveraging a peripheral device to execute a machine instruction
A method includes executing microcode in a processing unit of a processor to implement a machine instruction, wherein the microcode is to manipulate the processing unit to access a peripheral device on a public communication bus at a private address not visible to other devices on the public communication bus and not specified in the machine instruction. A processor includes a public communication bus, a peripheral device coupled to the public communication bus, and a processing unit. ... Advanced Micro Devices Inc
Performance state boost for multi-core integrated circuit
An integrated circuit includes a multiple number of processor cores and a system management unit. The multiple number of processor cores each operate at one of a multiple number of performance states. ... Advanced Micro Devices Inc
Randomly branching using performance counters
A system and method for efficiently performing program instrumentation. A processor processes instructions stored in a memory. ... Advanced Micro Devices Inc
Randomly branching using hardware watchpoints
A system and method for efficiently performing program instrumentation. A processor processes instructions stored in a memory. ... Advanced Micro Devices Inc
Data remapping for heterogeneous processor
A processor remaps stored data and the corresponding memory addresses of the data for different processing units of a heterogeneous processor. The processor includes a data remap engine that changes the format of the data (that is, how the data is physically arranged in segments of memory) in response to a transfer of the data from system memory to a local memory hierarchy of an accelerated processing module (apm) of the processor. ... Advanced Micro Devices Inc
Performing processing operations for memory circuits using a hierarchical arrangement of processing circuits
The described embodiments include a computing device that comprises at least one memory die having memory circuits and memory die processing circuits, and a logic die coupled to the at least one memory die, the logic die having logic die processing circuits. In the described embodiments, the memory die processing circuits are configured to perform memory die processing operations on data retrieved from or destined for the memory circuits and the logic die processing circuits are configured to perform logic die processing operations on data retrieved from or destined for the memory circuits.. ... Advanced Micro Devices Inc
Programmable bandgap reference voltage
Embodiments may include a method, system and apparatus for providing a reference voltage supply. A series resistor is provided between a power supply and a bandgap circuit coupled to an amplifier. ... Advanced Micro Devices Inc
Detecting and correcting hard errors in a memory array
Hard errors in the memory array can be detected and corrected in real-time using reusable entries in an error status buffer. Data may be rewritten to a portion of a memory array and a register in response to a first error in data read from the portion of the memory array. ... Advanced Micro Devices Inc
Back-off mechanism for a peripheral page request log
A system and method of managing requests from peripherals in a computer system are provided. In the system and method, an input/output memory management unit (iommu) receives a peripheral page request (ppr) from a peripheral. ... Advanced Micro Devices Inc
Data processor and method of lane realignment
A data processor includes a register file divided into at least a first portion and a second portion for storing data. A single instruction, multiple data (simd) unit is also divided into at least a first lane and a second lane. ... Advanced Micro Devices Inc
Enhancing lifetime of non-volatile cache by injecting random replacement policy
A method, a system and a computer-readable medium for writing to a non-volatile cache memory are provided. The method maintains a write count associated with a set of memory locations. ... Advanced Micro Devices Inc
Enhancing lifetime of non-volatile cache by reducing intra-block write variation
A method, a system and a computer-readable medium for writing to a cache memory are provided. The method comprises maintaining a write count associated with a set, the set containing a memory block associated with a physical block address. ... Advanced Micro Devices Inc
Data processor with memory controller for high reliability operation and method
A data processor includes a memory accessing agent and a memory controller. The memory accessing agent generates a plurality of accesses to a memory. ... Advanced Micro Devices Inc
Methods and systems for moving and resizing i/o activity logs
A method of managing peripherals is performed in a device coupled to a processor in a computer system. For example, the method is performed in an input/output memory management unit (iommu) or a peripheral. ... Advanced Micro Devices Inc
Latency-aware memory control
A system, method and computer-readable storage device for accessing heterogeneous memory system, are provided. A memory controller schedules access of a command to a memory region in a set of memory regions based on an access priority associated with the command and where the set of memory regions have corresponding access latencies. ... Advanced Micro Devices Inc
Storing non-temporal cache data
Embodiments herein provide for using one or more cache memory to facilitate non-temporal transaction. A request to store data into a cache associated with a processor is received. ... Advanced Micro Devices Inc
Exploiting camera depth information for video encoding
The present disclosure is directed a system and method for exploiting camera and depth information associated with rendered video frames, such as those rendered by a server operating as part of a cloud gaming service, to more efficiently encode the rendered video frames for transmission over a network. The method and system of the present disclosure can be used in a server operating in a cloud gaming service to improve, for example, the amount of latency, downstream bandwidth, and/or computational processing power associated with playing a video game over its service. ... Advanced Micro Devices Inc
Nested channel address interleaving
A system and method for mapping an address space to a non-power-of-two number of memory channels. Addresses are translated and interleaved to the memory channels such that each memory channel has an equal amount of mapped address space. ... Advanced Micro Devices Inc
Debug apparatus and methods for dynamically switching power domains
Methods and apparatus are provided that facilitate debugging operations for components in dynamic power domains. In an embodiment, an integrated circuit includes hardware sectors associated with observability circuits served by a debug data bus of a debug circuit. ... Advanced Micro Devices Inc
Debug apparatus and methods for dynamically switching power domains
Methods and apparatus are provided that facilitate debugging operations for components that may include different power domains. In an embodiment, an integrated circuit (ic) includes a plurality of hardware sectors, each hardware sector associated with a debug observability circuit that is served by a debug data bus of a debug circuit. ... Advanced Micro Devices Inc
Method and apparatus for storing a processor architectural state in cache memory
A method includes storing architectural state data associated with a processing unit in a cache memory using an allocate without fill mode. A system includes a processing unit, a cache memory, and a cache controller. ... Advanced Micro Devices Inc
Ddr 2d vref training
A method is provided for performing memory operations in response to instructions to perform a double data rate (ddr) memory reference voltage training in the voltage domain by a processing device and determining a ddr memory reference voltage and a ddr memory delay time based upon the memory operation. Computer readable storage media are also provided. ... Advanced Micro Devices Inc
Apparatus and method for hash table access
A system and method for accessing a hash table are provided. A hash table includes buckets where each bucket includes multiple chains. ... Advanced Micro Devices Inc
Internal bus architecture and method in multi-processor systems
An internal bus architecture and method is described. Embodiments include a system with multiple bus endpoints coupled to a bus. ... Advanced Micro Devices Inc
Estimating leakage currents based on rates of temperature overages or power overages
An operating point of one or more components in a processing device may be set using a leakage current estimated based on at least one of a rate of temperature overages or a rate of power overages. In some embodiments, a power management controller may be used to set an operating point of one or more components in the processing device based on at least one of a rate of temperature overages or a rate of power overages for the component(s).. ... Advanced Micro Devices Inc
Programmable substitutions for microcode
The apparatuses, systems, and methods in accordance with the embodiments disclosed herein may facilitate modifying post silicon instruction behavior. Embodiments herein may provide registers in predetermined locations in an integrated circuit. ... Advanced Micro Devices Inc
Prediction for power gating
The present application describes embodiments of methods for tournament prediction of power gating in processing devices. Some embodiments of the method include selecting one of a plurality of predictions of a duration of a time to a power state transition of a component in a processing device. ... Advanced Micro Devices Inc
Power manager for multi-threaded data processor
A data processing system includes a plurality of processor resources, a manager, and a power distributor. Each of the plurality of data processor cores is operable at a selected one of a plurality of performance states. ... Advanced Micro Devices Inc
Specialized memory disambiguation mechanisms for different memory read access types
A system and method for efficient predicting and processing of memory access dependencies. A computing system includes control logic that marks a detected load instruction as a first type responsive to predicting the load instruction has high locality and is a candidate for store-to-load (stl) data forwarding. ... Advanced Micro Devices Inc
Using redundant transactions to verify the correctness of program code execution
In the described embodiments, a processor core (e.g., a gpu core) receives a section of program code to be executed in a transaction from another entity in a computing device. The processor core sends the section of program code to one or more compute units in the processor core to be executed in a first transaction and concurrently executed in a second transaction, thereby creating a “redundant transaction pair.” when the first transaction and the second transaction are completed, the processor core compares a read-set of the first transaction to a read-set of the second transaction and compares a write-set of the first transaction to a write-set of the second transaction. ... Advanced Micro Devices Inc
Early write-back of modified data in a cache memory
A level of cache memory receives modified data from a higher level of cache memory. A set of cache lines with an index associated with the modified data is identified. ... Advanced Micro Devices Inc
Method and apparatus for memory management
In some embodiments, a method of managing cache memory includes identifying a group of cache lines in a cache memory, based on a correlation between the cache lines. The method also includes tracking evictions of cache lines in the group from the cache memory and, in response to a determination that a criterion regarding eviction of cache lines in the group from the cache memory is satisfied, selecting one or more (e.g., all) remaining cache lines in the group for eviction.. ... Advanced Micro Devices Inc
Method and circuit for detecting usb 3.0 lfps signal
A system and method for efficient detection of low frequency periodic signaling (lfps) input signals. A receiver receives two input differential signals that are lfps input signals. ... Advanced Micro Devices Inc
Efficient duplicate elimination
Methods and systems for identifying unique values in an input list are provided. A method in a processor is provided. ... Advanced Micro Devices Inc
Phase locked loop with bandwidth control
A phase locked loop (pll) includes a first loop, a second loop, and a lock detector. The first loop locks a feedback signal having a frequency equal to a fraction of a frequency of an output signal to a reference signal in phase. ... Advanced Micro Devices Inc
Precharge disable using predecoded address
A memory can be a sum addressed memory (sam) that receives, for each read access, two address values (e.g. A base address and an offset) having a sum that indicates the entry of the memory to be read (the read entry). ... Advanced Micro Devices Inc
Hierarchical write-combining cache coherence
A method, computer program product, and system is described that enforces a release consistency with special accesses sequentially consistent (rcsc) memory model and executes release synchronization instructions such as a strel event without tracking an outstanding store event through a memory hierarchy, while efficiently using bandwidth resources. What is also described is the decoupling of a store event from an ordering of the store event with respect to a rcsc memory model. ... Advanced Micro Devices Inc
Write combining cache microarchitecture for synchronization events
A method, computer program product, and system is described that enforces a release consistency with special accesses sequentially consistent (rcsc) memory model and executes release synchronization instructions such as a strel event without tracking an outstanding store event through a memory hierarchy, while efficiently using bandwidth resources. What is also described is the decoupling of a store event from an ordering of the store event with respect to a rcsc memory model. ... Advanced Micro Devices Inc
Methods and apparatus related to data processors and caches incorporated in data processors
A cache includes a cache array and a cache controller. The cache array has a multiple number of entries. ... Advanced Micro Devices Inc
Management of caches
A system and method for efficiently powering down banks in a cache memory for reducing power consumption. A computing system includes a cache array and a corresponding cache controller. ... Advanced Micro Devices Inc
Pass-through routing at input/output nodes of a cluster server
Node locations in the topology of a cluster computer server are designated as input/output (i/o) nodes that provide input and output for the cluster computer server. Examples of i/o nodes include network nodes that provide an interface for the cluster computer server to an external network, and storage nodes that provide access to storage devices for the cluster compute server. ... Advanced Micro Devices Inc
Slot design for flexible and expandable system architecture
An apparatus includes a printed circuit board including a connector footprint comprising a first footprint portion operative to receive a first connector portion and a second footprint portion operative to receive a second connector portion. The first footprint portion is compliant with a first communications link type and the first and second footprint portions are jointly compliant with a second communications link type. ... Advanced Micro Devices Inc
Canary circuit with passgate transistor variation
A canary circuit with passgate transistor variation is described herein. The canary circuit includes a memory canary circuit that has a plurality of bitcells. ... Advanced Micro Devices Inc
Dependent instruction suppression in a load-operation instruction
A method includes suppressing execution of an operation portion of a load-operation instruction in a processor responsive to an invalid status of a load portion of load-operation instruction. A processor includes an instruction pipeline including an execution unit operable to execute instructions and a scheduler unit. ... Advanced Micro Devices Inc
Dependent instruction suppression
A method includes suppressing execution of at least one dependent instruction of a first instruction by a processor responsive to an invalid status of an ancestor load instruction associated with the first instruction. A processor includes an instruction pipeline having an execution unit to execute instructions, a load store unit for retrieving data from a memory hierarchy, and a scheduler unit. ... Advanced Micro Devices Inc
Method and apparatus for providing clock signals for a scan chain
An integrated circuit device includes a plurality of flip flops configured into a scan chain. The plurality of flip flops includes at least flip flop of a first type and at least one flip flop of a second type. ... Advanced Micro Devices Inc
Power supply monitor for detecting faults during scan testing
Some embodiments of a power supply monitor include a measurement circuit to measure a voltage provided to the power supply monitor, a comparator to compare the voltage to a predetermined voltage threshold, and an interface to provide, during a scan test of a processing device including the power supply monitor, a fault signal in response to the voltage being below the voltage threshold. Some embodiments of a method include providing a first test pattern to one or more power supply monitors associated with one or more circuit blocks in the processing device and capturing a first result generated by the power supply monitor(s) based on the first test pattern. ... Advanced Micro Devices Inc
Partitionable data bus
A method and a system are provided for partitioning a system data bus. The method can include partitioning off a portion of a system data bus that includes one or more faulty bits to form a partitioned data bus. ... Advanced Micro Devices Inc
Method and apparatus for differential checkpointing
A processor core stores information that maps a physical register to an architectural register in response to an instruction modifying the architectural register. The processor recovers a checkpointed state of a set of architectural registers prior to modification of the architectural register by the instruction by modifying a reference mapping of physical registers to the set of architectural registers using the stored information.. ... Advanced Micro Devices Inc
Hybrid tag scheduler
The present invention provides a method and apparatus for scheduling based on tags of different types. Some embodiments of the method include broadcasting a first tag to entries in a queue of a scheduler. ... Advanced Micro Devices Inc
Stride prefetching across memory pages
A prefetcher maintains the state of stored prefetch information, such as a prefetch confidence level, when a prefetch would cross a memory page boundary. The maintained prefetch information can be used both to identify whether the stride pattern for a particular sequence of demand requests persists after the memory page boundary has been crossed, and to continue to issue prefetch requests according to the identified pattern. ... Advanced Micro Devices Inc
Size adjusting caches based on processor power mode
As a processor enters selected low-power modes, a cache is flushed of data by writing data stored at the cache to other levels of a memory hierarchy. The flushing of the cache allows the size of the cache to be reduced without suffering an additional performance penalty of writing the data at the reduced cache locations to the memory hierarchy. ... Advanced Micro Devices Inc
Size adjusting caches by way
A size of a cache of a processing system is adjusted by ways, such that each set of the cache has the same number of ways. The cache is a set-associative cache, whereby each set includes a number of ways. ... Advanced Micro Devices Inc
Variable series resistance termination for wireline serial link transistor
A variable series resistance termination circuit for wireline serial link transceivers is provided. Some embodiments include a pad for coupling to a wireline serial link and a termination circuit. ... Advanced Micro Devices Inc
Techniques and circuits for testing a virtual power supply at an integrated circuit device
A power grid provides power to one or more modules of an integrated circuit device via a virtual power supply signal. A test module is configured to respond to assertion of a test signal so that, when the power grid is working properly and is not power gated, an output of the test module matches the virtual power supply. ... Advanced Micro Devices Inc
Memory hierarchy using page-based compression
A system includes a device coupleable to a first memory. The device includes a second memory to cache data from the first memory. ... Advanced Micro Devices Inc
Method and apparatus related to cache memory
A cache includes a cache array and a cache controller. The cache array has a plurality of entries. ... Advanced Micro Devices Inc
Memory hierarchy using row-based compression
A system includes a first memory and a device coupleable to the first memory. The device includes a second memory to cache data from the first memory. ... Advanced Micro Devices Inc
Virtual interrupt filter
A system for processing interrupts in a virtualized computing environment includes a virtual interrupt controller to provide virtual interrupts from peripherals to virtual machines. The system also includes a virtual interrupt filter that has an estimator circuit to provide an estimate of what proportion of interrupts from one or more of the peripherals are virtual interrupts. ... Advanced Micro Devices Inc
Query operations for stacked-die memory device
An integrated circuit (ic) package includes a stacked-die memory device. The stacked-die memory device includes a set of one or more stacked memory dies implementing memory cell circuitry. ... Advanced Micro Devices Inc
System and method for secure control over performance state
The present disclosure relates to a method and system for securing a performance state change of one or more processors. A disclosed method includes intercepting a request for a change of a performance state of the processor and determining whether to execute the request based on a security condition of the processor. ... Advanced Micro Devices Inc
Allocating power to compute units based on energy efficiency
A method is provided for allocating power to compute units based on energy efficiency. Some embodiments of the method include allocating portions of a power budget of a system-on-a-chip (soc) to a plurality of compute units implemented on the soc based on ratios of a performance level for each compute unit to a power consumed by the compute unit operating at the performance level. ... Advanced Micro Devices Inc
Selection of an operating point of a memory physical layer interface and a memory controller based on memory bandwidth utilization
The present application describes embodiments of a method that includes modifying an operating point of at least one of a memory physical layer interface or a memory controller in response to changes in bandwidth utilization of the memory physical layer interface. The present application also describes embodiments of an apparatus that includes a memory controller, a memory physical layer interface, and a power management controller to modify an operating point of at least one of the memory physical layer interface or the memory controller in response to changes in bandwidth utilization of the memory physical layer interface.. ... Advanced Micro Devices Inc
Register file with read ports clustered by entry
A register file includes a substrate, a plurality of entries, and a plurality of read ports. Each entry includes a corresponding subset of a plurality of memory cells defined on the substrate. ... Advanced Micro Devices Inc
Switching a computer system from a high performance mode to a low power mode
A computer system includes a first processor, a second processor, and a common memory connected to the second processor. The computer system is switched from a high performance mode, in which at least a portion of the first processor and at least a portion of components on the second processor are active, to a low power mode, in which at least a portion of the first processor is active and the components on the second processor are inactive. ... Advanced Micro Devices Inc
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