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Advanced Micro Devices Inc patents (2016 archive)


Recent patent applications related to Advanced Micro Devices Inc. Advanced Micro Devices Inc is listed as an Agent/Assignee. Note: Advanced Micro Devices Inc may have other listings under different names/spellings. We're not affiliated with Advanced Micro Devices Inc, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "A" | Advanced Micro Devices Inc-related inventors


Mechanism of identifying available memory resources in a network of multi-level memory modules

A method of managing memory in a network of nodes includes identifying memory resources for each of the plurality of nodes connected to the network, storing memory resource information describing the memory resources, and based on the stored memory resource information, allocating a portion of the memory resources for execution of instructions in a workload, where at least a first node of the plurality of nodes is configured to execute the workload using the allocated portion of the memory resources.. . ... Advanced Micro Devices Inc

Computer architecture using rapidly reconfigurable circuits and high-bandwidth memory interfaces

A programmable device comprises one or more programming regions, each comprising a plurality of configurable logic blocks, where each of the plurality of configurable logic blocks is selectively connectable to any other configurable logic block via a programmable interconnect fabric. The programmable device further comprises configuration logic configured to, in response to an instruction in an instruction stream, reconfigure hardware in one or more of the configurable logic blocks in a programming region independently from any of the other programming regions.. ... Advanced Micro Devices Inc

Semiconductor area optimization

Systems, apparatuses, and methods for reducing the area of a semiconductor structure. A spacing violation may be detected for a gap width used to separate first and second regions of a layer of semiconductor material. ... Advanced Micro Devices Inc

Reducing the load on the bitlines of a rom bitcell array

Systems, apparatuses, and methods for reducing the load on the bitlines of a rom bitcell array are described. The connections between nets of a rom bitcell array may be assigned based on their programmed values using a traditional approach. ... Advanced Micro Devices Inc

Method and apparatus for performing a search operation on heterogeneous computing systems

A method and apparatus for performing a top-down breadth-first search (bfs) includes performing a first determination whether to convert to a bottom-up bfs. A second determination is performed whether to convert to the bottom-up bfs, based upon the first determination being positive. ... Advanced Micro Devices Inc

Shared virtual address space for heterogeneous processors

A processor uses the same virtual address space for heterogeneous processing units of the processor. The processor employs different sets of page tables for different types of processing units, such as a cpu and a gpu, wherein a memory management unit uses each set of page tables to translate virtual addresses of the virtual address space to corresponding physical addresses of memory modules associated with the processor. ... Advanced Micro Devices Inc

Memory module with embedded access metadata

A memory module stores memory access metadata reflecting information about memory accesses to the memory module. The memory access metadata can indicate the number of times a particular unit of data (e.g., a row of data, a unit of data corresponding to a cache line, and the like) has been read, written, had one or more of its bits flipped, and the like. ... Advanced Micro Devices Inc

Independent between-module prefetching for processor memory modules

A processor employs multiple prefetchers at a processor to identify patterns in memory accesses to different memory modules. The memory accesses can include transfers between the memory modules, and the prefetchers can prefetch data directly from one memory module to another based on patterns in the transfers. ... Advanced Micro Devices Inc

Hot page selection in multi-level memory hierarchies

Systems, apparatuses, and methods for sorting memory pages in a multi-level heterogeneous memory architecture. The system may classify pages into a first “hot” category or a second “cold” category. ... Advanced Micro Devices Inc

Scriptable dynamic load balancing in computer systems

The described embodiments include a system for executing a load using a first processor and a second processor in a computer system. During operation, a load balancer executing on the first processor obtains one or more attributes of a load to be executed on the computer system. ... Advanced Micro Devices Inc

Method and apparatus for regulating processing core load imbalance

Briefly, methods and apparatus to rebalance workloads among processing cores utilizing a hybrid work donation and work stealing technique are disclosed that improve workload imbalances within processing devices such as, for example, gpus. In one example, the methods and apparatus allow for workload distribution between a first processing core and a second processing core by providing queue elements from one or more workgroup queues associated with workgroups executing on the first processing core to a first donation queue that may also be associated with the workgroups executing on the first processing core. ... Advanced Micro Devices Inc

Protecting state information for virtual machines

A processing system includes a processor that implements registers to define a state of a virtual machine (vm) running on the processor. The processor detects exit conditions of the vm. ... Advanced Micro Devices Inc

Dynamic power management optimization

Systems, apparatuses, and methods for managing power usage of integrated circuits. One or more processor cores may be powered down when the system is idle. ... Advanced Micro Devices Inc

Memory speculation for multiple memories

A plurality of memory modules, which may be used to form a heterogeneous memory system, are connected to a plurality of prefetchers. Each prefetcher is independently configured to prefetch information from a corresponding one of the plurality of memory modules in response to feedback from the corresponding one of the plurality of memory modules.. ... Advanced Micro Devices Inc

12/22/16 / #20160371116

Heterogeneous enqueuing and dequeuing mechanism for task scheduling

Methods, systems and computer-readable mediums for task scheduling on an accelerated processing device (apd) are provided. In an embodiment, a method comprises: enqueuing one or more tasks in a memory storage module based on the apd; using a software-based enqueuing module; and dequeuing the one or more tasks from the memory storage module using a hardware-based command processor, wherein the command processor forwards the one or more tasks to the shader cote.. ... Advanced Micro Devices Inc

12/22/16 / #20160371082

Instruction context switching

A processing device includes a first memory that includes a context buffer. The processing device also includes a processor core to execute threads based on context information stored in registers of the processor core and a memory controller to selectively move a subset of the context information between the context buffer and the registers based on one or more latencies of the threads.. ... Advanced Micro Devices Inc

12/22/16 / #20160371014

Ordering memory commands in a computer system

The disclosed embodiments provide a system for processing a memory command on a computer system. During operation, a command scheduler executing on a memory controller of the computer system obtains a predicted latency of the memory command based on a memory address to be accessed by the memory command. ... Advanced Micro Devices Inc

12/08/16 / #20160359973

Source-side resource request network admission control

A technique for source-side memory request network admission control includes adjusting, by a first node, a rate of injection of memory requests by the first node into a network coupled to a memory system. The adjusting is based on an injection policy for the first node and memory request efficiency indicators. ... Advanced Micro Devices Inc

12/08/16 / #20160357580

Per-block sort for performance enhancement of parallel processors

A method of enhancing performance of an application executing in a parallel processor and a system for executing the method are disclosed. A block size for input to the application is determined. ... Advanced Micro Devices Inc

12/08/16 / #20160357551

Conditional atomic operations at a processor

A conditional fetch-and-phi operation tests a memory location to determine if the memory locations stores a specified value and, if so, modifies the value at the memory location. The conditional fetch-and-phi operation can be implemented so that it can be concurrently executed by a plurality of concurrently executing threads, such as the threads of wavefront at a gpu. ... Advanced Micro Devices Inc

12/01/16 / #20160352598

Message aggregation, combining and compression for efficient data communications in gpu-based clusters

A system and method for efficient management of network traffic management of highly data parallel computing. A processing node includes one or more processors capable of generating network messages. ... Advanced Micro Devices Inc

12/01/16 / #20160352509

Method and system for constant time cryptography using a co-processor

The present disclosure presents methods, apparatuses, and systems to bolster communication security, and more particularly to utilize a constant time cryptographic co-processor engine for such communication security. For example, the disclosure includes a method for secure communication, comprising receiving encrypted data at a receiving device; obtaining a randomization for at least one bit of the encrypted data; modifying an execution of a cryptographic algorithm on the at least one bit to obtain a randomized cryptographic algorithm based on the randomization; and executing the randomized cryptographic algorithm on the at least one bit of encrypted data to recover original data associated with the encrypted data.. ... Advanced Micro Devices Inc

11/24/16 / #20160343343

Two-phase hybrid vertex classification

. . A processor performs vertex coloring for a graph based at least in part on the degree of each vertex of the graph and based at least in part with another coloring approach, such as comparison of random values assigned to the vertices. For each vertex in the graph, a processor determines whether the degree of the vertex is a local maximum; that is, whether the degree of the vertex is greater than the degree of each of its connected vertices. ... Advanced Micro Devices Inc

11/24/16 / #20160342185

Droop detection and regulation for processor tiles

A processor system includes first and second regulators for regulating an adjusted supply voltage. The first and second regulators generate a plurality of control signals to regulate an adjusted power supply voltage and that generate a charge when a droop level falls below a droop threshold value by implementing first and second control loops. ... Advanced Micro Devices Inc

11/24/16 / #20160342166

Droop detection for low-dropout regulator

A processor system includes first and second regulators for regulating an adjusted supply voltage. In one embodiment, the regulator system comprises a digital low-dropout (dldo) control system comprising first and second regulators that generate a plurality of control signals to regulate an adjusted power supply voltage and that generate a charge when a droop level falls below a droop threshold value. ... Advanced Micro Devices Inc

11/24/16 / #20160341793

Scan flip-flop circuit with dedicated clocks

In one form, a scan flip-flop includes a clock gating cell and a dedicated clock flip-flop. The clock gating cell provides an input clock input signal as a scan clock signal when a scan shift enable signal is active, and provides the input clock signal as a data clock signal when the scan shift enable signal is inactive. ... Advanced Micro Devices Inc

11/24/16 / #20160341604

Thermal oscillator

A temperature dependent oscillator charges a capacitance from a voltage source through a switch. The switch is opened and the capacitance discharges through a transistor having a temperature dependent resistance. ... Advanced Micro Devices Inc

11/17/16 / #20160338230

Control of thermal energy transfer for phase change material in data center

A cooling system controller for a set of computing resources of a data center includes a first interface to couple to a first flow controller that controls a rate of thermal energy transfer to a pcm store from the set of computing resources, a second interface to couple to a second flow controller that controls a rate of thermal energy transfer from the pcm store to a cooling system, and a controller to determine a current set of operational parameters for the data center and to manipulate the first and second flow controllers and via the first and second interfaces to control a net thermal energy transfer to and from the pcm store based on the current set of parameters.. . ... Advanced Micro Devices Inc

11/17/16 / #20160335143

System and method for determining concurrency factors for dispatch size of parallel processor kernels

Disclosed is a method of determining concurrency factors for an application running on a parallel processor. Also disclosed is a system for implementing the method. ... Advanced Micro Devices Inc

11/17/16 / #20160335064

Infrastructure to support accelerator computation models for active storage

A method, a system, and a non-transitory computer readable medium for generating application code to be executed on an active storage device are presented. The parts of an application that can be executed on the active storage device are determined. ... Advanced Micro Devices Inc

11/10/16 / #20160330469

Methods and apparatus for optical blur modeling for improved video encoding

Methods and apparatus of generating a refined reference frame for inter-frame encoding by applying blur parameters to allow encoding of image frames having blurred regions are presented herein. The methods and apparatus may identify a blurred region of an image frame by comparing the image frame with a reference frame, generate a refined reference frame by applying the blur parameter indicative of the blurred region to the reference frame, determine whether to use one of the reference frame and refined reference frame to encode the image frame, and encode the image frame using the refined reference frame when determined to use the refined reference frame.. ... Advanced Micro Devices Inc

11/03/16 / #20160321183

Early cache prefetching in preparation for exit from idle mode

A system includes a functional unit, at least one cache coupled to the functional unit, and a power management unit coupled to the functional unit and the at least one cache, the power management unit configured to trigger the functional unit to initiate prefetching of data to repopulate the at least one cache prior to a predicted exit of the functional unit from an idle mode to an active mode. The system further may include a prediction unit to predict the exit from the idle mode for the functional unit as occurring a predetermined duration from an entry into the idle mode. ... Advanced Micro Devices Inc

10/13/16 / #20160300320

Real time on-chip texture decompression using shader processors

A processing unit, method, and medium for decompressing or generating textures within a graphics processing unit (gpu). The textures are compressed with a variable-rate compression scheme such as jpeg. ... Advanced Micro Devices Inc

10/06/16 / #20160291678

Power reduction in bus interconnects

In one form, power consumed in transmitting data over a bus interconnect is reduced. The power is reduced by configuring a buffer that is used to store data to be transmitted over the bus interconnect as a two-dimensional (2d) buffer array having a plurality of rows and columns. ... Advanced Micro Devices Inc

09/29/16 / #20160285437

Integrated differential clock gater

A technique implements differential digital logic circuits with a differential clock distribution network using standard cell differential clock gater circuits to reduce area, delay, power consumption in integrated circuits. An apparatus includes a first terminal configured to receive a clock signal, a second terminal configured to receive a complementary clock signal, and a third terminal configured to receive a clock control signal. ... Advanced Micro Devices Inc

09/15/16 / #20160266629

Changing power limits based on device state

A method includes adjusting a maximum skin temperature threshold of a device based on a device state, adjusting a power limit for the device based on the adjusted maximum skin temperature threshold, and operating the device based on the adjusted power limit. A processor includes a processing unit and a power management controller to adjust a maximum skin temperature threshold based on a device state and adjust a power limit for the processing unit based on the adjusted maximum skin temperature threshold.. ... Advanced Micro Devices Inc

09/15/16 / #20160266628

Power management to change power limits based on device skin temperature

A method includes controlling a power limit of a computing system based on a determined skin temperature of at least one location on an outer surface of a device housing the computing system. A processor includes a processing unit and a power management controller to control a power limit of the processing unit based on a determined skin temperature of at least one location on an outer surface of a device housing the processor.. ... Advanced Micro Devices Inc

09/08/16 / #20160261869

Content-adaptive b-picture pattern video encoding

A method of video encoding is disclosed which is content adaptive. The encoding method is automatically adjusted to optimize the encoding, the adjusting depending on the content of the pictures being encoded. ... Advanced Micro Devices Inc

09/08/16 / #20160261399

Efficient asynchronous communication protocol

A more efficient asynchronous protocol transmits data from a transmitter circuit at a first time to a receiver circuit and transmits a next data from the transmitter circuit to the receiver circuit at a second time so that the next data arrives at the receiver circuit at approximately the same time an acknowledge signal of the first data from the receiver circuit arrives at the transmitting circuit. The propagation delay may be measured at the beginning of a transfer to help determine when to send data.. ... Advanced Micro Devices Inc

09/08/16 / #20160260246

Providing asynchronous display shader functionality on a shared shader core

A method, a non-transitory computer readable medium, and a processor for performing display shading for computer graphics are presented. Frame data is received by a display shader, the frame data including at least a portion of a rendered frame. ... Advanced Micro Devices Inc

09/08/16 / #20160260192

Redundancy method and apparatus for shader column repair

Methods, systems and non-transitory computer readable media are described. A system includes a shader pipe array, a redundant shader pipe array, a sequencer and a redundant shader switch. ... Advanced Micro Devices Inc

09/08/16 / #20160259667

Hardware and runtime coordinated load balancing for parallel applications

A method of balancing execution rates for a plurality of parallel program loops being executed concurrently by a processor may include estimating a completion time for each program loop of the plurality of program loops, determining a difference between the estimated completion time of a first program loop of the plurality of program loops and the estimated completion time of a second program loop of the plurality of program loops, and decreasing the difference by adjusting an execution rate of the first program loop.. . ... Advanced Micro Devices Inc

09/01/16 / #20160253774

Method and apparatus for directing application requests for rendering

A method and system for directing image rendering, implemented in a computer system including a plurality of processors includes determining one or more processors in the system on which to execute one or more commands. A graphics processing unit (gpu) control application program interface (api) determines one or more processors in the system on which to execute one or more commands. ... Advanced Micro Devices Inc

08/25/16 / #20160248405

Flip-flop circuit with latch bypass

In one form, a flip-flop comprises a master latch, a slave latch, and a multiplexer. The master latch has an input for receiving a data input signal, and an output, and operates in transparent and latching modes during respective first and second phases of a clock signal. ... Advanced Micro Devices Inc

08/25/16 / #20160246715

Memory module with volatile and non-volatile storage arrays

A memory module is responsive to control signaling for a random access memory (ram) module, and performs translation of received memory addresses so that it can map a relatively small address space of an operating system to a larger physical address space of its storage arrays. The memory module can therefore be employed in systems requiring a large amount of memory, such as systems using many processors, without requiring specialized operating systems for addressing the larger physical address space.. ... Advanced Micro Devices Inc

08/25/16 / #20160246601

Technique for translating dependent instructions

In response to determining an operation is a dependent operation, a mapper of a processor determines the source registers of the operation from which the dependent operation depends. The mapper translates the dependent operation to a new operation that uses as its source operands at least one of the determined source registers and a source register of the dependent operation. ... Advanced Micro Devices Inc

08/25/16 / #20160246540

Scheduling of data migration

In one form, scheduling data migration comprises determining whether the data is likely to be used by an input/output (i/o) device, the data being at a location remote to the i/o device; and scheduling the data for migration from the remote location to a location local to the i/o device in response to determining that the data is likely to be used by the i/o device.. . ... Advanced Micro Devices Inc

08/25/16 / #20160246360

Pruning of low power state information for a processor

A processor prunes state information based on information provided by software, thereby reducing the amount of state information to be stored prior to the processor entering a low-power state. The software, such as an operating system or application program executing at the processor, indicates one or more registers of the processor as storing data that is no longer useful. ... Advanced Micro Devices Inc

08/18/16 / #20160239302

Dynamic wavefront creation for processing units using a hybrid compactor

A method, a non-transitory computer readable medium, and a processor for repacking dynamic wavefronts during program code execution on a processing unit, each dynamic wavefront including multiple threads are presented. If a branch instruction is detected, a determination is made whether all wavefronts following a same control path in the program code have reached a compaction point, which is the branch instruction. ... Advanced Micro Devices Inc

08/18/16 / #20160239278

Generating a schedule of instructions based on a processor memory tree

A processor employs a memory tree and a code generation and scheduling framework (cgsf) to generate instructions to access data at memory modules associated with the processor. The memory tree is a data structure having a plurality of nodes, with each node corresponding to a different memory module, memory cluster, or other portion of memory. ... Advanced Micro Devices Inc

08/18/16 / #20160239265

Bit remapping mechanism to enhance lossy compression in floating-point applications

Methods and systems of reducing power transmitted over a memory to cache bus having a plurality of cache lines by identifying floating point numbers transmitted over a cache line, rounding bits in least significant bit (lsb) positions of identified floating point (fp) numbers to a uniform binary value string, mapping the rounded bits from the lsb positions to most significant bit (msb) positions of each fp number to increase a chance of matching bit patterns between pairs of the fp numbers, and compressing the floating point numbers by replacing matched bit patterns with smaller data elements using a defined data compression process. A decompressor decompresses the compressed fp numbers using a defined decompression process corresponding to the defined compression process; and the mapping component applies a reverse mapping function to map the rounded bits back to original lsb positions from the msb positions to recover the original floating point numbers.. ... Advanced Micro Devices Inc

08/11/16 / #20160232097

Query operations for stacked-die memory device

An integrated circuit (ic) package includes a stacked-die memory device. The stacked-die memory device includes a set of one or more stacked memory dies implementing memory cell circuitry. ... Advanced Micro Devices Inc

08/11/16 / #20160231935

Memory configuration operations for a computing device

In the described embodiments, a computing device executes firmware to perform a startup initialization operation, wherein performing the startup initialization operation comprises setting an operating state of a memory in the computing device to a default low performance memory operating state. After completing the startup initialization operation, the computing device executes an operating system, wherein executing the operating system comprises performing a memory test to determine a high performance memory operating state. ... Advanced Micro Devices Inc

08/11/16 / #20160231933

Memory page access detection

A processor maintains a count of accesses to each memory page. When the accesses to a memory page exceed a threshold amount for that memory page, the processor sets an indicator for the page. ... Advanced Micro Devices Inc

08/04/16 / #20160224397

Exploiting limited context streams

In one form, a data processing system includes volatile and non-volatile memory, a central processing unit, and at least one peripheral device. The central processing unit executes a selected one of a plurality of software applications as directed by an operating system by transferring the selected software application from the non-volatile memory to the volatile memory and executing instructions associated with the selected software application from the volatile memory. ... Advanced Micro Devices Inc

07/07/16 / #20160197729

Location aware cryptography

A method of decrypting encrypted data in a device may include generating a first key based on location information indicating a present location of the device, combining the first key with at least a second key to generate a combined key, and decrypting the encrypted data based on the combined key.. . ... Advanced Micro Devices Inc

06/16/16 / #20160173896

Methods and apparatus for decoding video using re-ordered motion vector buffer

Methods and apparatus for decoding video are presented herein. The methods and apparatus may comprise a host processor, such as a central processing unit (cpu), programmed to execute a software driver that causes the host processor to generate a motion compensation command for a plurality of cores of a massively parallel processor, such as a graphics processing unit (gpu), to provide motion compensation for encoded video. ... Advanced Micro Devices Inc

06/16/16 / #20160173589

Storage location assignment at a cluster compute server

A cluster compute server stores different types of data at different storage volumes in order to reduce data duplication at the storage volumes. The storage volumes are categorized into two classes: common storage volumes and dedicated storage volumes, wherein the common storage volumes store data to be accessed and used by multiple compute nodes (or multiple virtual servers) of the cluster compute server. ... Advanced Micro Devices Inc

06/16/16 / #20160172013

Address and control signal training

In one form, an apparatus comprises a delay circuit and a controller. The delay circuit delays a plurality of command and address signals according to a first delay signal and provides a delayed command and address signal to memory interface. ... Advanced Micro Devices Inc

06/16/16 / #20160170919

Traffic rate control for inter-class data migration in a multiclass memory system

A system includes a plurality of memory classes and a set of one or more processing units coupled to the plurality of memory classes. The system further includes a data migration controller to select a traffic rate as a maximum traffic rate for transferring data between the plurality of memory classes based on a net benefit metric associated with the traffic rate, and to enforce the maximum traffic rate for transferring data between the plurality of memory classes.. ... Advanced Micro Devices Inc

06/16/16 / #20160170887

Batching modified blocks to the same dram page

To efficiently transfer of data from a cache to a memory, it is desirable that more data corresponding to the same page in the memory be loaded in a line buffer. Writing data to a memory page that is not currently loaded in a row buffer requires closing an old page and opening a new page. ... Advanced Micro Devices Inc

06/09/16 / #20160163015

Shader pipelines and hierarchical shader resources

Shader resources may be specified for input to a shader using a hierarchical data structure which may be referred to as a descriptor set. The descriptor set may be bound to a bind point of the shader and may contain slots with pointers to memory containing shader resources. ... Advanced Micro Devices Inc

06/09/16 / #20160162190

Memory management in graphics and compute application programming interfaces

Methods are provided for creating objects in a way that permits an api client to explicitly participate in memory management for an object created using the api. Methods for managing data object memory include requesting memory requirements for an object using an api and expressly allocating a memory location for the object based on the memory requirements. ... Advanced Micro Devices Inc

06/02/16 / #20160155491

Memory persistence management control

A memory retention controller may include a data structure configured to store a memory refresh interval corresponding to a memory region in a memory subsystem and control logic coupled with the data structure. The control logic is configured to perform a first refresh of the memory region prior to a power off transition of a host processor coupled with the memory subsystem, and to perform a second refresh of the memory region after the power off transition of the host processor, based on the memory refresh interval corresponding to the memory region, and in response to an elapsed time since the first refresh of the memory region.. ... Advanced Micro Devices Inc

05/26/16 / #20160149697

Method and apparatus for securing access to an integrated circuit

A method and apparatus are described securely testing an integrated circuit (ic). When the ic is powered on, a first bit stream including unencrypted data bits and encrypted data bits is received by the ic, a second bit stream is generated based on a pseudorandom pattern, a third bit stream is generated by convolving the first bit stream with the second bit stream, the third bit stream is fed to at least one selected test data register (tdr), (i.e., a shift register), in the ic, a fourth bit stream is generated by delaying the second bit stream, and a fifth bit stream is generated by convolving a sixth bit stream output by the at least one selected tdr with the fourth bit stream. ... Advanced Micro Devices Inc

05/26/16 / #20160147467

Reliable wear-leveling for non-volatile memory and method therefor

In one form, a data processor comprises a memory accessing agent and a memory controller. The memory accessing agent selectively initiates read accesses to and write accesses from a memory. ... Advanced Micro Devices Inc

05/19/16 / #20160140084

Efficient sparse matrix-vector multiplication on parallel processors

A method of multiplication of a sparse matrix and a vector to obtain a new vector and a system for implementing the method are claimed. Embodiments of the method are intended to optimize the performance of sparse matrix-vector multiplication in highly parallel processors, such as gpus. ... Advanced Micro Devices Inc

05/19/16 / #20160139624

Processor and methods for remote scoped synchronization

Described herein is an apparatus and method for remote scoped synchronization, which is a new semantic that allows a work-item to order memory accesses with a scope instance outside of its scope hierarchy. More precisely, remote synchronization expands visibility at a particular scope to all scope-instances encompassed by that scope. ... Advanced Micro Devices Inc

05/05/16 / #20160124873

Memory system with region-specific memory access scheduling

An integrated circuit device includes a memory controller coupleable to a memory. The memory controller to schedule memory accesses to regions of the memory based on memory timing parameters specific to the regions. ... Advanced Micro Devices Inc

05/05/16 / #20160124871

External data processing for a display device

A method, a device, and a non-transitory computer readable medium for performing external processing on a display device are presented. An application is executed on the display device. ... Advanced Micro Devices Inc

05/05/16 / #20160124852

Memory management for graphics processing unit workloads

A method, a device, and a non-transitory computer readable medium for performing memory management in a graphics processing unit are presented. Hints about the memory usage of an application are provided to a page manager. ... Advanced Micro Devices Inc

04/28/16 / #20160117248

Coherency probe with link or domain indicator

A processor includes a set of processing modules, each of the processing modules including a cache and a coherency manager that keeps track of the memory addresses of data stored at the caches of other processing modules. In response to its local cache requesting access to a particular memory address or other triggering event, the coherency manager generates a coherency probe. ... Advanced Micro Devices Inc

04/28/16 / #20160117247

Coherency probe response accumulation

A processor accumulating coherency probe responses, thereby reducing the impact of coherency messages on the bandwidth of the processor's communication fabric. A probe response accumulator is connected to a processing module of the processor, the processing module having multiple processor cores and associated caches. ... Advanced Micro Devices Inc

04/28/16 / #20160117206

Method and system for block scheduling control in a processor by remapping

A method and a system for block scheduling are disclosed. The method includes retrieving an original block id, determining a corresponding new block id from a mapping, executing a new block corresponding to the new block id, and repeating the retrieving, determining, and executing for each original block id. ... Advanced Micro Devices Inc

04/28/16 / #20160117179

Command replacement for communication at a processor

A command replacement module at a coherency manager of a processor receives commands to be communicated over the communication fabric. For each received command of a specified type, the command replacement module compares a data payload of the command to a stored set of data patterns and, in response to a match, replaces the command with a replacement command, wherein the replacement command implies the contents of the data payload. ... Advanced Micro Devices Inc

04/28/16 / #20160116970

Power management

Processor power may be managed by executing state storage and power gating instructions after receiving an idle indication. The idle indication may be received while the processor is executing instructions in a first mode, and the processor may execute the state storage and power gating instructions in a second mode. ... Advanced Micro Devices Inc

04/07/16 / #20160098275

Thermal-aware compiler for parallel instruction execution in processors

Embodiments are described for a method for compiling instruction code for execution in a processor having a number of functional units by determining a thermal constraint of the processor, and defining instruction words comprising both real instructions and one or more no operation (nop) instructions to be executed by the functional units within a single clock cycle, wherein a number of nop instructions executed over a number of consecutive clock cycles is configured to prevent exceeding the thermal constraint during execution of the instruction code.. . ... Advanced Micro Devices Inc

03/31/16 / #20160092181

Automatic source code generation for accelerated function calls

A programming model for a processor accelerator allows accelerated functions to be called from a main program directly without a management api for the accelerator. A compiler automatically generates wrapper source code for each accelerator function called by the application source code. ... Advanced Micro Devices Inc

03/24/16 / #20160086654

Thermal aware data placement and compute dispatch in a memory system

A method of managing thermal levels in a memory system may include determining an expected thermal level associated with each of a plurality of locations in a memory structure, and for each operation of a plurality of operations addressed to the memory structure, assigning the operation to a target location of the plurality of physical locations in the memory structure based on a thermal penalty associated with the operation and the expected thermal level associated with the target location.. . ... Advanced Micro Devices Inc

03/24/16 / #20160085976

Method for privileged mode based secure input mechanism

A system and method are disclosed for securely receiving data from an input device coupled to a computing system. The system includes an interface configured to receive data from an input device, a coprocessor, and a host computer, wherein the host computer includes an input handler and a host processor. ... Advanced Micro Devices Inc

03/24/16 / #20160085677

System and method for repurposing dead cache blocks

A processing system having a multilevel cache hierarchy employs techniques for repurposing dead cache blocks so as to use otherwise wasted space in a cache hierarchy employing a write-back scheme. For a cache line containing invalid data with a valid tag, the valid tag is maintained for cache coherence purposes or otherwise, resulting in a valid tag for a dead cache block. ... Advanced Micro Devices Inc

03/24/16 / #20160085551

Heterogeneous function unit dispatch in a graphics processing unit

A compute unit configured to execute multiple threads in parallel is presented. The compute unit includes one or more single instruction multiple data (simd) units and a fetch and decode logic. ... Advanced Micro Devices Inc

03/24/16 / #20160085219

Scheduling applications in processing devices based on predicted thermal impact

A processing device includes a plurality of components and a system management unit to selectively schedule an application phase to one of the plurality of components based on one or more comparisons of predictions of a plurality of thermal impacts of executing the application phase on each of the plurality of components. The predictions may be generated based on a thermal history associated with the application phase, thermal sensitivities of the plurality of components, or a layout of the plurality of components in the processing device.. ... Advanced Micro Devices Inc

03/17/16 / #20160077981

Method and apparatus for efficient user-level io in a virtualized system

In a virtualized computer system without an iommu, all application io requests must be processed by the guest operating system and by the hypervisor so that addresses are translated (twice) and validated (twice) properly. In a virtualized computer system with an iommu containing one “stage” of translation, the peripheral can safely be assigned directly to a guest os because the iommu can be programmed to translate and check addresses issued by the device. ... Advanced Micro Devices Inc

03/17/16 / #20160077871

Predictive management of heterogeneous processing systems

A heterogeneous processing device includes one or more relatively large processing units and one or more relatively small processing units. The heterogeneous processing device selectively activates a large processing unit or a small processing unit to run a process thread based on a predicted duration of an active state of the process thread.. ... Advanced Micro Devices Inc

03/17/16 / #20160077575

Interface to expose interrupt times to hardware

A power management controller is used to control power management states of a processing device. A register stores a timer tick value accessible to the power management controller. ... Advanced Micro Devices Inc

03/17/16 / #20160077565

Frequency configuration of asynchronous timing domains under power constraints

A processing device includes one or more queues to convey data between a producing processor unit in a first timing domain and a consuming processor unit in a second timing domain that is asynchronous with the first timing domain. A system management unit configures a first operating frequency of the producing processor unit and a second operating frequency of the consuming processor unit based on a power constraint for the processing device and a target size of the one or more queues.. ... Advanced Micro Devices Inc

03/17/16 / #20160077545

Power and performance management of asynchronous timing domains in a processing device

A processing device includes a producing processor unit in a first timing domain and a consuming processor unit in a second timing domain that is asynchronous with the first timing domain. A queue is used to convey data between the producing processor unit and the consuming processor unit. ... Advanced Micro Devices Inc

03/10/16 / #20160070659

Concurrently executing critical sections in program code in a processor

In the described embodiments, entities in a computing device selectively write specified values to a lock variable in a local cache and one or more lower levels of a memory hierarchy to enable multiple entities to enable the concurrent execution of corresponding critical sections of program code that are protected by a same lock.. . ... Advanced Micro Devices Inc

03/03/16 / #20160062803

Selecting a resource from a set of resources for performing an operation

The described embodiments comprise a selection mechanism that selects a resource from a set of resources in a computing device for performing an operation. In some embodiments, the selection mechanism performs a lookup in a table selected from a set of tables to identify a resource from the set of resources. ... Advanced Micro Devices Inc

02/25/16 / #20160055609

Graphics processing method, system, and apparatus

A graphics processing apparatus, system, and method is provided. The graphics processing method includes separating a graphics context and graphics object from a packet; calculating a magic number of the graphics context; comparing the magic number of the graphics context with magic numbers stored in a context table, wherein each of the magic numbers corresponds to a specific graphics context; and, if the magic number of the graphics context is not found among the magic numbers in the context table, adding the graphics context to a graphics context slot of a graphics context storage, adding the graphics object to a graphics object list separate from the graphics context storage, and associating the graphics context slot with the listed graphics object.. ... Advanced Micro Devices Inc

02/25/16 / #20160055100

System and method for reverse inclusion in multilevel cache hierarchy

A processing system having multilevel cache employs techniques for identifying and selecting valid candidate cache lines for eviction from a lower level cache of an inclusive cache hierarchy, so as to reduce invalidations resulting from an eviction of a cache line in a lower level cache that also resides in a higher level cache. In response to an eviction trigger for a lower level cache, a cache controller identifies candidate cache lines for eviction from the cache lines residing in the lower level cache based on the replacement policy. ... Advanced Micro Devices Inc

02/25/16 / #20160055086

Dynamic cache partitioning apparatus and method

A dynamic cache partitioning apparatus and method is described, which may be used in a multi-core system having a plurality of cores. The apparatus includes at least one multi-core processor and at least one shared cache shared by a plurality of processing cores, the shared cache including a plurality of cache lines and being partitioned into a plurality of sub-caches including at least one private sub-cache for each single processing core and at least one public sub-cache being shared by all of the processing cores; means for detecting shared cache hit information for each respective processing core of the plurality of processing cores; and means for determining whether a cache line should be allocated to public sub-cache or to a private sub-cache associated with one of the plurality of processing cores.. ... Advanced Micro Devices Inc

02/25/16 / #20160055033

Runtime for automatically load-balancing and synchronizing heterogeneous computer systems with scoped synchronization

Sharing tasks among compute units in a processor can increase the efficiency of the processor. When a compute unit does not have a task in its task memory to perform, donating tasks from other compute units can prevent the compute unit from being idle while there is task in other parts of the processor. ... Advanced Micro Devices Inc

02/25/16 / #20160055005

System and method for page-conscious gpu instruction

Embodiments disclose a system and method for reducing virtual address translation latency in a wide execution engine that implements virtual memory. One example method describes a method comprising receiving a wavefront, classifying the wavefront into a subset based on classification criteria selected to reduce virtual address translation latency associated with a memory support structure, and scheduling the wavefront for processing based on the classifying.. ... Advanced Micro Devices Inc

02/18/16 / #20160049181

Virtual memory mapping for improved dram page locality

Embodiments are described for methods and systems for mapping virtual memory pages to physical memory pages by analyzing a sequence of memory-bound accesses to the virtual memory pages, determining a degree of contiguity between the accessed virtual memory pages, and mapping sets of the accessed virtual memory pages to respective single physical memory pages. Embodiments are also described for a method for increasing locality of memory accesses to dram in virtual memory systems by analyzing a pattern of virtual memory accesses to identify contiguity of accessed virtual memory pages, predicting contiguity of the accessed virtual memory pages based on the pattern, and mapping the identified and predicted contiguous virtual memory pages to respective single physical memory pages.. ... Advanced Micro Devices Inc

02/18/16 / #20160048376

Portable binary image format (pbif) for pre-compiled kernels

Embodiments include methods, systems, and computer-readable medium directed to a compiler for compiling a portable binary image. The compiler compiles a program source code into a first executable specific to a first instruction set architecture (isa). ... Advanced Micro Devices Inc

02/18/16 / #20160048327

Data distribution among multiple managed memories

A system and method are disclosed for managing memory interleaving patterns in a system with multiple memory devices. The system includes a processor configured to access multiple memory devices. ... Advanced Micro Devices Inc

02/11/16 / #20160042488

Method and system for frame pacing

A frame pacing method, computer program product, and computing system are provided for graphics processing.. . ... Advanced Micro Devices Inc

02/11/16 / #20160041914

Cache bypassing policy based on prefetch streams

Embodiments include methods, systems, and computer readable medium directed to cache bypassing based on prefetch streams. A first cache receives a memory access request. ... Advanced Micro Devices Inc

02/11/16 / #20160041909

Moving data between caches in a heterogeneous processor system

Apparatus, computer readable medium, integrated circuit, and method of moving a plurality of data items to a first cache or a second cache are presented. The method includes receiving an indication that the first cache requested the plurality of data items. ... Advanced Micro Devices Inc

02/11/16 / #20160041853

Tracking source availability for instructions in a scheduler instruction queue

A processor includes an execution unit to execute instructions and a scheduler unit to store a queue of instructions for execution by the execution unit. The scheduler unit includes a wake array including a plurality of source slots to store source identifiers for sources associated with the instructions, a picker to schedule a particular instruction for execution in the execution unit, broadcast a destination identifier associated with the particular instruction to a first subset of the source slots, and a delay element to receive the destination identifier broadcast by the picker and communicate a delayed version of the destination identifier to a second subset of the source slots different from the first subset.. ... Advanced Micro Devices Inc

02/04/16 / #20160034304

Dependence tracking by skipping in user mode queues

A system and methods embodying some aspects of the present embodiments for maintaining compact in-order queues are provided. The queue management method includes requesting a work pointer from a primary queue, wherein the work pointer points to a work assignment comprising an indirect queue and a dependency list; responsive to the dependency list not being cleared, invalidating the work pointer in the primary queue and adding a new pointer to the end of the primary queue, the new pointer configured to point to the work assignment; and responsive to the dependency list being clear, removing the work pointer from the primary queue and performing work in the indirect queue.. ... Advanced Micro Devices Inc

02/04/16 / #20160034023

Dynamic cache prefetching based on power gating and prefetching policies

A system may determine that a processor has powered up. The system may determine a first prefetching policy based on determining that the processor has powered up. ... Advanced Micro Devices Inc

01/28/16 / #20160028387

Measuring delay between signal edges of different signals using an undersampling clock

A system may measure a first sample, of a first signal, using an undersampling signal. The system may measure a second sample, of a second signal, using the undersampling signal. ... Advanced Micro Devices Inc

01/28/16 / #20160026577

Technique to improve performance of memory copies and stores

A system and method for efficiently relocating and initializing a block of memory of the computer system. For data initialization and data relocation, multiple registers in a processor are used for intermediate storage of data to be written into the memory. ... Advanced Micro Devices Inc

01/21/16 / #20160018870

Controlling energy consumption of an electronic device in response to availability of an energy source

An apparatus and methods for controlling energy consumption of an electronic device determine an availability of an energy source to provide energy to the electronic device. The apparatus and methods control, by power management control logic of the electronic device, energy consumption of the electronic device in response to determining the availability of the energy source.. ... Advanced Micro Devices Inc

01/14/16 / #20160011652

Method and apparatis for processor standby

A method of and device for removing a processor from a low power mode. The method includes and the device provides for performing multiple processor start-up tasks in parallel. ... Advanced Micro Devices Inc

01/07/16 / #20160004445

Devices and methods for interconnecting server nodes

Described are aggregation devices and methods for interconnecting server nodes. The aggregation device can include an input region, an output region, and a memory switch. ... Advanced Micro Devices Inc








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