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Advanced Micro Devices Inc patents (2017 archive)


Recent patent applications related to Advanced Micro Devices Inc. Advanced Micro Devices Inc is listed as an Agent/Assignee. Note: Advanced Micro Devices Inc may have other listings under different names/spellings. We're not affiliated with Advanced Micro Devices Inc, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "A" | Advanced Micro Devices Inc-related inventors


Achieving balanced execution through runtime detection of performance variation

Systems, apparatuses, and methods for achieving balanced execution in a multi-node cluster through runtime detection of performance variation are described. During a training phase, performance counters and an amount of time spent waiting for synchronization is monitored for a plurality of tasks for each node of the multi-node cluster. ... Advanced Micro Devices Inc

Culling objects from a 3-d graphics pipeline using hierarchical z buffers

A shader in a graphics pipeline accesses an object that represents a portion of a model of a scene in object space and one or more far-z values that indicate a furthest distance of a previously rendered portion of one or more tiles from a viewpoint used to render the scene on a screen. The one or more tiles overlap a bounding box of the object in a plane of the screen. ... Advanced Micro Devices Inc

Method and apparatus for reducing tlb shootdown overheads in accelerator-based systems

A method and apparatus for reducing tlb shootdown operation overheads in accelerator-based computing systems is described. The disclosed method and apparatus may also be used in the areas of near-memory and in-memory computing, where near-memory or in-memory compute units may need to share a host cpu's virtual address space. ... Advanced Micro Devices Inc

Contended lock request elision scheme

A system and method for network traffic management between multiple nodes are described. A computing system includes multiple nodes connected to one another. ... Advanced Micro Devices Inc

Shadow tag memory to monitor state of cachelines at different cache level

A processing system includes a plurality of processor cores and a plurality of private caches. Each private cache is associated with a corresponding processor core of the plurality of processor cores and includes a corresponding first set of cachelines. ... Advanced Micro Devices Inc

Targeted per-line operations for remote scope promotion

A processing system includes one or more first caches and one or more first lock tables associated with the one or more first caches. The processing system also includes one or more processing units that each include a plurality of compute units for concurrently executing work-groups of work items, a plurality of second caches associated with the plurality of compute units and configured in a hierarchy with the one or more first caches, and a plurality of second lock tables associated with the plurality of second caches. ... Advanced Micro Devices Inc

Real-time performance tracking using dynamic compilation

Systems, apparatuses, and methods for performing real-time tracking of performance targets using dynamic compilation. A performance target is specified in a service level agreement. ... Advanced Micro Devices Inc

System and method for protecting gpu memory instructions against faults

A system and method for protecting memory instructions against faults are described. The system and method include converting the slave instructions to dummy operations, modifying memory arbiter to issue up to n master and n slave global/shared memory instructions per cycle, sending master memory requests to memory system, using slave requests for error checking, entering master requests to the gm/lm fifo, storing slave requests in a register, and comparing the entered master requests with the stored slave requests.. ... Advanced Micro Devices Inc

Multi-processor apparatus and method of detection and acceleration of lagging tasks

A method and processing apparatus for accelerating program processing is provided that includes a plurality of processors configured to process a plurality of tasks of a program and a controller. The controller is configured to determine, from the plurality of tasks being processed by the plurality of processors, a task being processed on a first processor to be a lagging task causing a delay in execution of one or more other tasks of the plurality of tasks. ... Advanced Micro Devices Inc

Temperature-aware task scheduling and proactive power management

Systems, apparatuses, and methods for performing temperature-aware task scheduling and proactive power management. A soc includes a plurality of processing units and a task queue storing pending tasks. ... Advanced Micro Devices Inc

Virtualization of a graphics processing unit for network applications

An accelerated processing unit includes a first processing unit configured to implement one or more virtual machines and a second processing unit configured to implement one or more acceleration modules. The one or more virtual machines are configured to provide information identifying a task or data to the one or more acceleration modules via first queues. ... Advanced Micro Devices Inc

System and method for processing data in a computing system

Systems, apparatuses, and methods for adjusting group sizes to match a processor lane width are described. In early iterations of an algorithm, a processor partitions a dataset into groups of data points which are integer multiples of the processing lane width of the processor. ... Advanced Micro Devices Inc

System and method for scheduling instructions in a multithread simd architecture with a fixed number of registers

A method and apparatus for scheduling instructions of a shader program for a graphics processing unit (gpu) with a fixed number of registers. The method and apparatus include computing, via a processing unit (pu), a liveness-based register usage across all basic blocks in the shader program, computing, via the pu, the range of numbers of waves of a plurality of registers for the shader program, assessing the impact of available post-register allocation optimizations, computing, via the pu, the scoring data based on number of waves of the plurality of registers, and computing, via the pu, the number of waves for execution for the plurality of registers.. ... Advanced Micro Devices Inc

Method and apparatus for memory efficiency improvement by providing burst memory access control

Methods and apparatus monitor memory access activities of non-real-time processing engines to determine time intervals when the memory access activities are low. When such time intervals are found, the methods and apparatus perform burst memory access control for real-time processing engines by bursting data from a memory to a burst memory buffer, or from the burst memory buffer to the memory, to allow fast data access by the real-time processing engines.. ... Advanced Micro Devices Inc

12/28/17 / #20170371386

Control system and architecture for incorporating microelectromechanical (mem) switches in fluid-based cooling of 3d integrated circuits

A cooling system is provided for a 3d integrated circuit (ic) to deliver fluid in x, y, and z dimensions to interior regions of the ic as a means to regulate heat. An ic includes a microfluidic network of channels, at least one sensor and at least one microelectromechanical system (mems)-based device that is disposed within the network of channels and that is configured to regulate a flow of fluid within the network of channels. ... Advanced Micro Devices Inc

12/21/17 / #20170366412

Managing cluster-level performance variability without a centralized controller

Systems, apparatuses, and methods for managing cluster-level performance variability without a centralized controller are described. Each node of a multi-node cluster tracks a maximum and minimum progress across the plurality of nodes for a workload executed by the cluster. ... Advanced Micro Devices Inc

12/21/17 / #20170364332

Fingerprinting of redundant threads using compiler-inserted transformation code

A first processing element is configured to execute a first thread and one or more second processing elements are configured to execute one or more second threads that are redundant to the first thread. The first thread and the one or more second threads are to selectively bypass one or more comparisons of results of operations performed by the first thread and the one or more second threads depending on whether an event trigger for the comparison has occurred a configurable number of times since a previous comparison of previously encoded values of the results. ... Advanced Micro Devices Inc

12/21/17 / #20170364262

Write buffer design for high-latency memories

A memory system includes a write buffer, a main memory having a higher latency than the write buffer, and a memory controller. In response to a write request indicating first data for storing at a write address in the main memory, the memory controller adds a new write entry in the write buffer, where the new write entry includes the write address and the first data, and updates a pointer of a previous write entry in the write buffer to point to the new write entry. ... Advanced Micro Devices Inc

12/14/17 / #20170357596

Dynamically adjustable inclusion bias for inclusive caches

A first cache that includes a plurality of cache lines and is inclusive of a second cache. The plurality of cache lines are associated with a plurality of n-bit values. ... Advanced Micro Devices Inc

12/14/17 / #20170357588

Scaled set dueling for cache replacement policies

A processing system includes a cache that includes a cache lines that are partitioned into a first subset of the cache lines and a second subsets of the cache lines. The processing system also includes one or more counters that are associated with the second subsets of the cache lines. ... Advanced Micro Devices Inc

12/14/17 / #20170357587

Up/down prefetcher

In a processing system comprising a cache, a method includes monitoring demand cache accesses for a thread to maintain a first running count of a number of times demand cache accesses for the thread are directed to cachelines that are adjacent in a first direction to cachelines that are targets of a set of sampled cache accesses for the thread. In response to determining the first running count has exceeded a first threshold, the method further includes enabling a first prefetching mode in which a received demand cache access for the thread triggers a prefetch request for a cacheline adjacent in the first direction to a cacheline targeted by the received demand cache access.. ... Advanced Micro Devices Inc

12/14/17 / #20170357585

Setting cache entry age based on hints from another cache level

A processor replaces data at a first cache based on hints from a second cache, wherein the hints indicate information about the data that is not available to the first cache directly. When data at an entry is transferred from the first cache to the second cache, the first cache can provide an age hint to the second cache to indicate that the data should be assigned a higher or lower initial age relative to a nominal initial age. ... Advanced Micro Devices Inc

12/14/17 / #20170357583

Asynchronous cache flushing

Proactive flush logic in a computing system is configured to perform a proactive flush operation to flush data from a first memory in a first computing device to a second memory in response to execution of a non-blocking flush instruction. Reactive flush logic in the computing system is configured to, in response to a memory request issued prior to completion of the proactive flush operation, interrupt the proactive flush operation and perform a reactive flush operation to flush requested data from the first memory to the second memory.. ... Advanced Micro Devices Inc

12/14/17 / #20170357509

Power management of instruction processors in a system-on-a-chip

A system-on-a-chip includes a plurality of instruction processors and a hardware block such as a system management unit. The hardware block accesses values of performance counters associated with the plurality of instruction processors and modifies one or more operating points of one or more of the plurality of instruction processors based on comparisons of the instruction arrival rates and the instruction service rates to achieve optimized system metrics.. ... Advanced Micro Devices Inc

12/14/17 / #20170357446

Cache entry replacement based on availability of entries at another cache

A processing system selects entries for eviction at one cache based at least in part on the validity status of corresponding entries at a different cache. The processing system includes a memory hierarchy having at least two caches, a higher level cache and a lower level cache. ... Advanced Micro Devices Inc

12/07/17 / #20170353397

Offloading execution of an application by a network connected device

A client device detects one or more servers to which an application can be offloaded. The client device receives information from the servers regarding their graphics processing unit (gpu) compute resources. ... Advanced Micro Devices Inc

12/07/17 / #20170351450

Self refresh state machine mop array

In one form, a memory controller includes a controller and a memory operation array. The controller has an input for receiving a power state change request signal and an output for providing memory operations. ... Advanced Micro Devices Inc

11/30/17 / #20170347498

Multi-compartment computing device with shared cooling device

Various computing devices, thermal solutions and enclosures are disclosed. In one aspect, a computing device enclosure is provided that includes a first compartment that has a first upper side and is adapted to house the computing device and a liquid cooling device. ... Advanced Micro Devices Inc

11/30/17 / #20170345512

Wear-limiting non-volatile memory

A non-volatile memory device having at least one non-volatile flash memory formatted with physical addresses to read and write data that is organized into blocks of data, wherein the blocks of data are organized into pages of data, and wherein the pages of data are organized into cells of data. The non-volatile memory device includes a non-volatile memory controller to direct read and write requests to the non-volatile flash memory for the storage and retrieval of data. ... Advanced Micro Devices Inc

11/30/17 / #20170345482

Fine granularity refresh

A data processing system includes a memory channel and a data processor coupled to the memory channel. The data processor is adapted to access at least one rank and has refresh logic. ... Advanced Micro Devices Inc

11/30/17 / #20170344490

Using multiple memory elements in an input-output memory management unit for performing virtual address to physical address translations

The described embodiments include an input-output memory management unit (iommu) with two or more memory elements and a controller. The controller is configured to select, based on one or more factors, one or more selected memory elements from among the two or more memory elements for performing virtual address to physical address translations in the iommu. ... Advanced Micro Devices Inc

11/30/17 / #20170344479

Cache coherence for processing in memory

A cache coherence bridge protocol provides an interface between a cache coherence protocol of a host processor and a cache coherence protocol of a processor-in-memory, thereby decoupling coherence mechanisms of the host processor and the processor-in-memory. The cache coherence bridge protocol requires limited change to existing host processor cache coherence protocols. ... Advanced Micro Devices Inc

11/30/17 / #20170344421

Integral post package repair

A post-package repair system includes a memory channel controller, a first error counter, a scrubber, and a data processor. The memory channel controller converts data access requests to corresponding memory accesses, and provides returned data to the host interface in response to responses received from a memory interface, wherein the responses comprise returned data and a plurality of error correcting code (ecc) bits. ... Advanced Micro Devices Inc

11/30/17 / #20170344309

Low power memory throttling

In one form, a data processing system includes a memory channel having a plurality of ranks, and a data processor. The data processor is coupled to the memory channel and is adapted to access each of the plurality of ranks. ... Advanced Micro Devices Inc

11/23/17 / #20170337136

Managing cache coherence using information in a page table

The described embodiments include a computing device with two or more types of processors and a memory that is shared between the two or more types of processors. The computing device performs operations for handling cache coherency between the two or more types of processors. ... Advanced Micro Devices Inc

10/26/17 / #20170308297

Object tagged memory monitoring method and processing apparatus

Described are a method and processing apparatus to tag and track objects related to memory allocation calls. An application or software adds a tag to a memory allocation call to enable object level tracking. ... Advanced Micro Devices Inc

10/12/17 / #20170295111

Methods and apparatus for processing in a network on chip (noc)

Methods and apparatus of delegating instructions or data from a cu to an noc node in a network on chip (noc) is disclosed. The noc node executes the delegated instructions or processes the delegated data. ... Advanced Micro Devices Inc

10/12/17 / #20170293560

Method and apparatus for performing memory prefetching

A method and apparatus for performing memory prefetching includes determining whether to initiate prefetching. Upon a determination to initiate prefetching, a first memory row is determined as a suitable prefetch candidate, and it is determined whether a particular set of one or more cachelines of the first memory row is to be prefetched.. ... Advanced Micro Devices Inc

10/12/17 / #20170293499

Message handler compiling and scheduling in heterogeneous system architectures

A receiving node in a computer system that includes a plurality of types of execution units receives an active message from a sending node. The receiving node compiles an intermediate language message handler corresponding to the active message into a machine instruction set architecture (isa) message handler and the receiver executes the isa message handler on a selected one of the execution units. ... Advanced Micro Devices Inc

10/12/17 / #20170293487

Flexible framework to support memory synchronization operations

A method of performing memory synchronization operations is provided that includes receiving, at a programmable cache controller in communication with one or more caches, an instruction in a first language to perform a memory synchronization operation of synchronizing a plurality of instruction sequences executing on a processor, mapping the received instruction in the first language to one or more selected cache operations in a second language executable by the cache controller and executing the one or more cache operations to perform the memory synchronization operation. The method further comprises receiving a second mapping that provides mapping instructions to map the received instruction to one or more other cache operations, mapping the received instruction to one or more other cache operations and executing the one or more other cache operations to perform the memory synchronization operation.. ... Advanced Micro Devices Inc

10/05/17 / #20170289078

Systems and methods of supporting parallel processor message-based communications

A method of message-based communication is provided which includes executing, on one or more accelerated processing units, a plurality of groups of work items, receiving a first message from a first group of work items of the plurality of groups of work items executing on the one or more accelerated processing units and storing the first message at a first segment of memory allocated to a second group of work items of the plurality of groups of work items executing on the accelerated processing unit.. . ... Advanced Micro Devices Inc

10/05/17 / #20170289057

Self-timed router with virtual channel control

Systems, apparatuses, and methods for implementing an asynchronous router with virtual channel (vc) control. The asynchronous router may support multiple vcs for connections to other routers. ... Advanced Micro Devices Inc

09/28/17 / #20170279703

Managing variations among nodes in parallel system frameworks

Systems, apparatuses, and methods for managing variations among nodes in parallel system frameworks. Sensor and performance data associated with the nodes of a multi-node cluster may be monitored to detect variations among the nodes. ... Advanced Micro Devices Inc

09/28/17 / #20170278213

Hierarchical register file at a graphics processing unit

A processor employs a hierarchical register file for a graphics processing unit (gpu). A top level of the hierarchical register file is stored at a local memory of the gpu (e.g., a memory on the same integrated circuit die as the gpu). ... Advanced Micro Devices Inc

09/28/17 / #20170277898

Key management for secure memory address spaces

A processor employs a security module to manage authentication and encryption keys for the processor. The security module can authenticate itself to other processing systems, such as processing systems providing software to be executed at the processor, can generate keys for encrypting address spaces for the provided software, and can securely import and export information at the encrypted address spaces to and from the processing system. ... Advanced Micro Devices Inc

09/28/17 / #20170277639

Adaptive extension of leases for entries in a translation lookaside buffer

The described embodiments include a computing device with two or more translation lookaside buffers (tlb). During operation, the computing device updates an entry in the tlb based on a virtual address to physical address translation and metadata from a page table entry that were acquired during a page table walk. ... Advanced Micro Devices Inc

09/28/17 / #20170277634

Using leases for entries in a translation lookaside buffer

The described embodiments include a computing device with two or more translation lookaside buffers (tlb) that performs operations for handling entries in the tlbs. During operation, the computing device maintains lease values for entries in the tlbs, the lease values representing times until leases for the entries expire, wherein a given entry in the tlb is invalid when the associated lease has expired. ... Advanced Micro Devices Inc

09/28/17 / #20170277441

Performance-aware and reliability-aware data placement for n-level heterogeneous memory systems

Techniques for selecting one of a plurality of heterogeneous memory units for placement of blocks of data (e.g., memory pages), based on both reliability and performance, are disclosed. A “cost” for each data block/memory unit combination is determined, based on the frequency of access of the data block, the latency of the memory unit, and, optionally, an architectural vulnerability factor (which represents the level of exposure of a particular memory data value to memory faults such as bit flips). ... Advanced Micro Devices Inc

09/21/17 / #20170269651

Method and apparatus for managing power in a thermal couple aware system

A method and apparatus for managing power in a thermal couple aware system includes determining a candidate configuration mapping based upon one or more criteria, the candidate configuration mapping being a mapping of performance for a candidate configuration of processor sockets in the thermal couple aware system. The candidate configuration mapping is evaluated by comparing the candidate configuration mapping to a stored configuration. ... Advanced Micro Devices Inc

09/14/17 / #20170262289

Method and system for yield operation supporting thread-like behavior

A method, system, and computer program product synchronize a group of workitems executing an instruction stream on a processor. The processor is yielded by a first workitem responsive to a synchronization instruction in the instruction stream. ... Advanced Micro Devices Inc

09/07/17 / #20170255397

Efficient implementation of queues and other data structures using processing near memory

Systems, apparatuses, and methods for implementing efficient queues and other data structures. A queue may be shared among multiple processors and/or threads without using explicit software atomic instructions to coordinate access to the queue. ... Advanced Micro Devices Inc

08/17/17 / #20170237658

Assigning variable length address identifiers to packets in a processing system

A controller assigns variable length addresses to addressable elements that are connected to a network. The variable length addresses are determined based on probabilities that packets are addressed to the corresponding addressable element. ... Advanced Micro Devices Inc

08/17/17 / #20170235700

Peripheral component

Embodiments of a peripheral component are described herein. Embodiments provide alternatives to the use of an external bridge integrated circuit (ic) architecture. ... Advanced Micro Devices Inc

08/10/17 / #20170228321

Pinning objects in multi-level memory hierarchies

The described embodiments include a computer system having a multi-level memory hierarchy with two or more levels of memory, each level being one of two or more types of memory. The computer system handles storing objects in the multi-level memory hierarchy. ... Advanced Micro Devices Inc

08/10/17 / #20170228164

User-level instruction for memory locality determination

Systems and methods for efficiently processing data in a non-uniform memory access (numa) computing system are disclosed. A computing system includes multiple nodes connected in a numa configuration. ... Advanced Micro Devices Inc

08/03/17 / #20170220369

Hypervisor post-write notification of control and debug register updates

Systems, apparatuses, and methods for implementing hypervisor post-write notification of processor state register modifications. A write to a state register of the processor may be detected during guest execution. ... Advanced Micro Devices Inc

08/03/17 / #20170220346

Method and apparatus for inter-lane thread migration

Briefly, methods and apparatus to migrate a software thread from one wavefront executing on one execution unit to another wavefront executing on another execution unit whereby both execution units are associated with a compute unit of a processing device such as, for example, a gpu. The methods and apparatus may execute compiled dynamic thread migration swizzle buffer instructions that when executed allow access to a dynamic thread migration swizzle buffer that allows for the migration of register context information when migrating software threads. ... Advanced Micro Devices Inc

08/03/17 / #20170220022

Determining thermal time constants of processing systems

A processing system includes one or more processing units to perform operations and one or more sensors to measure a temperature concurrently with the one or more processing units performing the operations. The processing system also includes a controller to receive feedback indicating the temperature and to determine a peak temperature and a thermal time constant for heating of the processing system based on a comparison of the measured temperature to a first temperature that is predicted based on the peak temperature and a previously determined thermal time constant for heating. ... Advanced Micro Devices Inc

07/27/17 / #20170212851

Using processor types for processing interrupts in a computing device

The described embodiments include a computing device with multiple interrupt processors for processing interrupts. In the described embodiments, each of the multiple processors is classified as one or more processor types based on factors such as features and functionality of the processor, an operating environment of the processor, the characteristics of some or all of the available interrupts, etc. ... Advanced Micro Devices Inc

07/27/17 / #20170212845

Region migration cache

A memory access profiling and region migration technique makes allocation and replacement decisions for periodic migration of most frequently accessed regions of main memory to least frequently accessed regions of a region migration cache, in background operations. The technique improves performance in sparsely-used memory systems by migrating regions of main memory corresponding to the working footprint of main memory to the region migration cache. ... Advanced Micro Devices Inc

07/27/17 / #20170212837

Adaptive value range profiling for enhanced system performance

Enhanced adaptive profiling of ranges of values in a stream of events includes identifying a set of contiguous ranges of the values and corresponding access frequencies in the stream of events. The enhanced adaptive profiling uses a merge threshold value and a split threshold value. ... Advanced Micro Devices Inc

07/27/17 / #20170212757

Simd processing unit with local data share and access to a global data share of a gpu

A graphics processing unit is disclosed, the graphics processing unit having a processor having one or more simd processing units, and a local data share corresponding to one of the one or more simd processing units, the local data share comprising one or more low latency accessible memory regions for each group of threads assigned to one or more execution wavefronts, and a global data share comprising one or more low latency memory regions for each group of threads. W. ... Advanced Micro Devices Inc

07/20/17 / #20170206638

Hybrid anti-aliasing

Systems, apparatuses, and methods for performing hybrid anti-aliasing operations are disclosed. The hybrid anti-aliasing resolve operation combines multi-sampling anti-aliasing (msaa) and post-processing anti-aliasing to generate higher-quality images in a computationally efficient manner. ... Advanced Micro Devices Inc

07/20/17 / #20170206626

Techniques for sampling sub-pixels of an image

Systems, apparatuses, and methods for generating and utilizing sub-pixel sampling patterns on a processor are disclosed. In one embodiment, a processor includes at least multiple execution units and a memory. ... Advanced Micro Devices Inc

07/20/17 / #20170206625

Method and apparatus to accelerate rendering of graphics images

Described is a method and apparatus to accelerate rendering of 3d graphics images. When rendering, the transformation matrix (or equivalent) used for projecting primitives is modified so that a resulting image is smaller and/or warped compared to a regular unmodified rendering. ... Advanced Micro Devices Inc

07/13/17 / #20170201503

Memory operation encryption

A processing system includes a processing module having a first interface coupleable to an interconnect. The first interface includes a first cryptologic engine to encrypt a representation of store data of a store operation and a memory address using a first key and a first feedback-based cryptologic process to generate first encrypted data and an encrypted memory address. ... Advanced Micro Devices Inc

07/13/17 / #20170200672

Interposer having a pattern of sites for mounting chiplets

The described embodiments include an interposer with signal routes located therein. The interposer includes a set of sites arranged in a pattern, each site including a set of connection points. ... Advanced Micro Devices Inc

07/06/17 / #20170195683

Texture compression techniques

A texture compression method is described. The method comprises splitting an original texture having a plurality of pixels into original blocks of pixels. ... Advanced Micro Devices Inc

07/06/17 / #20170193697

Method and apparatus for performing high throughput tessellation

A method, a system, and a computer-readable storage medium directed to performing high-speed parallel tessellation of 3d surface patches are disclosed. The method includes generating a plurality of primitives in parallel. ... Advanced Micro Devices Inc

06/29/17 / #20170185514

Caching policies for processing units on multiple sockets

A processing system includes a first socket, a second socket, and an interface between the first socket and the second socket. A first memory is associated with the first socket and a second memory is associated with the second socket. ... Advanced Micro Devices Inc

06/29/17 / #20170185409

Hardware accuracy counters for application precision and quality feedback

Methods, devices, and systems for capturing an accuracy of an instruction executing on a processor. An instruction may be executed on the processor, and the accuracy of the instruction may be captured using a hardware counter circuit. ... Advanced Micro Devices Inc

06/22/17 / #20170178397

Texel shading in texture space

A graphics processing unit is configured to map pixels of a first frame of a video stream to texels, select a subset of the texels for shading based on previously cached texels that were shaded for a second frame, and shade the subset of the texels. The graphics processing unit is also configured to cache the shaded subset of the texels with the previously cached texels and determine values for the pixels of the first frame based on the cached texels.. ... Advanced Micro Devices Inc

06/22/17 / #20170178275

Method and system for using solid state device as eviction pad for graphics processing unit

Described is a method and system for using a solid state device (ssd) as an eviction pad for graphics processing units (gpus). The method for eviction processing includes a processor that determines when a dedicated memory associated with a gpu and a host memory associated with the processor are congested. ... Advanced Micro Devices Inc

06/22/17 / #20170177498

Centrally managed unified shared virtual address space

Systems, apparatuses, and methods for managing a unified shared virtual address space. A host may execute system software and manage a plurality of nodes coupled to the host. ... Advanced Micro Devices Inc

06/22/17 / #20170177492

Hybrid cache

Systems, apparatuses, and methods for implementing a hybrid cache. A processor may include a hybrid l2/l3 cache which allows the processor to dynamically adjust a size of the l2 cache and a size of the l3 cache. ... Advanced Micro Devices Inc

06/22/17 / #20170177484

Region probe filter for distributed memory system

A probe filter determines whether to issue a probe to at least one other processing node in response to a memory access request, and includes a region probe filter directory, a line probe filter directory, and a controller. The region probe filter directory identifies regions of memory for which at least one cache line may be cached in a data processing system and a state of each region, wherein a size of each region corresponds to a plurality of cache lines. ... Advanced Micro Devices Inc

06/15/17 / #20170168546

Method and apparatus for performing inter-lane power management

A method and apparatus for performing inter-lane power management includes de-energizing one or more execution lanes upon a determination that the one or more execution lanes are to be predicated. Energy from the predicated execution lanes is redistributed to one or more active execution lanes.. ... Advanced Micro Devices Inc

06/08/17 / #20170163282

Reducing power needed to send signals over wires

Methods and apparatus are described. A method, implemented in a decoder, includes receiving two or more signals from an encoder over two or more respective wires. ... Advanced Micro Devices Inc

06/08/17 / #20170161212

System and method for application migration

Described is a method and apparatus for application migration between a dockable device and a docking station in a seamless manner. The dockable device includes a processor and the docking station includes a high-performance processor. ... Advanced Micro Devices Inc

06/08/17 / #20170161194

Page-based prefetching triggered by tlb activity

A method of prefetching data includes issuing to a translation lookaside buffer (tlb) an address translation request for a virtual memory address, detecting a tlb miss generated in response to the address translation request, and in response to the tlb miss, selecting the data for prefetching from memory based on the memory address causing the tlb miss and prefetching the selected data to a cache.. . ... Advanced Micro Devices Inc

06/08/17 / #20170161114

Method and apparatus for time-based scheduling of tasks

A computing device is disclosed. The computing device includes an accelerated processing unit (apu) including at least a first heterogeneous system architecture (hsa) computing device and at least a second hsa computing device, the second computing device being a different type than the first computing device, and an hsa memory management unit (hmmu) allowing the apu to communicate with at least one memory. ... Advanced Micro Devices Inc

06/08/17 / #20170160955

Page migration in a 3d stacked hybrid memory

A die-stacked hybrid memory device implements a first set of one or more memory dies implementing first memory cell circuitry of a first memory architecture type and a second set of one or more memory dies implementing second memory cell circuitry of a second memory architecture type different than the first memory architecture type. The die-stacked hybrid memory device further includes a set of one or more logic dies electrically coupled to the first and second sets of one or more memory dies, the set of one or more logic dies comprising a memory interface and a page migration manager, the memory interface coupleable to a device external to the die-stacked hybrid memory device, and the page migration manager to transfer memory pages between the first set of one or more memory dies and the second set of one or more memory dies.. ... Advanced Micro Devices Inc

06/08/17 / #20170160781

Balancing computation and communication power in power constrained clusters

Systems, apparatuses, and methods for balancing computation and communication power in power constrained environments. A data processing cluster with a plurality of compute nodes may perform parallel processing of a workload in a power constrained environment. ... Advanced Micro Devices Inc

06/01/17 / #20170153916

Voltage droop mitigation in 3d chip system

The present invention relates to a multichip system and a method for scheduling threads in 3d stacked chip. The multichip system comprises a plurality of dies stacked vertically and electrically coupled together; each of the plurality of dies comprising one or more cores, each of the plurality of dies further comprising: at least one voltage violation sensing unit, the at least one voltage violation sensing unit being connected with the one or more cores of each die, the at least one voltage sensing unit being configured to independently sense voltage violation in each core of each die; and at least one frequency tuning unit, the at least one frequency tuning unit being configured to tune the frequency of each core of each die, the at least one frequency tuning unit being connected with the at least one voltage violation sensing unit. ... Advanced Micro Devices Inc

06/01/17 / #20170153815

Dedicated interface for coupling flash memory and dynamic random access memory

The present application describes embodiments of an interface for coupling flash memory and dynamic random access memory (dram) in a processing system. Some embodiments include a dedicated interface between a flash memory and dram. ... Advanced Micro Devices Inc

05/18/17 / #20170139748

Efficient processor load balancing using predication

A system and methods embodying some aspects of the present embodiments for efficient load balancing using predication flags are provided. The load balancing system includes a first processing unit, a second processing unit, and a shared queue. ... Advanced Micro Devices Inc

05/18/17 / #20170139635

Interconnect architecture for three-dimensional processing systems

A processing system includes a plurality of processor cores formed in a first layer of an integrated circuit device and a plurality of partitions of memory formed in one or more second layers of the integrated circuit device. The one or more second layers are deployed in a stacked configuration with the first layer. ... Advanced Micro Devices Inc

05/11/17 / #20170132147

Cache with address space mapping to slice subsets

A processing device includes a cache implementing a set of at least three cache slices. Each cache slice is to store a corresponding set of cache lines. ... Advanced Micro Devices Inc

05/04/17 / #20170123987

In-memory interconnect protocol configuration registers

Systems, apparatuses, and methods for moving the interconnect protocol configuration registers into the main memory space of a node. The region of memory used for storing the interconnect protocol configuration registers may also be made cacheable to reduce the latency of accesses to the interconnect protocol configuration registers. ... Advanced Micro Devices Inc

05/04/17 / #20170123693

Relocatable and resizable tables in a computing device

The described embodiments include a computing device that performs operations for at least one of resizing or relocating a table in a memory in the computing device. In the described embodiments, the computing device includes at least one register storing a table base address indicating an original location of an original table in the memory and a table size indicating an original size of the original table in the memory. ... Advanced Micro Devices Inc

05/04/17 / #20170123670

Method and systems of controlling memory-to-memory copy operations

A memory-to-memory copy operation control system includes a processor configured to receive an instruction to perform a memory-to-memory copy operation and a memory module network in communication with the processor. The memory module network has a plurality of memory modules that include a proximal memory module in direct communication with the processor and one or more additional memory modules in communication with the processor via the proximal memory module. ... Advanced Micro Devices Inc

04/27/17 / #20170115970

Estimation of bit widths of variables based on liveness

A compiler generates transfer functions for blocks of a program during compilation of the program. The transfer functions estimate bit widths of variables in the blocks based on numbers of bits needed to carry out at least one instruction in the blocks and whether the variables are live in the blocks. ... Advanced Micro Devices Inc

04/13/17 / #20170102971

Method and apparatus for workload placement on heterogeneous systems

The methods and apparatus can assign processing core workloads to processing cores from a heterogeneous instruction set architectures (isa) pool of available processing cores based on processing core metric results. For example, the method and apparatus can obtain processing core metric results for one or more processing cores, such as processing cores within general purpose processors, from a heterogeneous isa pool of available processing cores. ... Advanced Micro Devices Inc

04/13/17 / #20170102886

Minimizing latency from peripheral devices to compute engines

Methods, systems, and computer program products are provided for minimizing latency in a implementation where a peripheral device is used as a capture device and a compute device such as a gpu processes the captured data in a computing environment. In embodiments, a peripheral device and gpu are tightly integrated and communicate at a hardware/firmware level. ... Advanced Micro Devices Inc

04/06/17 / #20170097774

Mode-dependent access to embedded memory elements

A system has a plurality of functional modules including a first functional module and one or more other functional modules. The first functional module includes an embedded memory element and is configurable in a plurality of modes including a first mode and a second mode. ... Advanced Micro Devices Inc

03/23/17 / #20170085472

Multi-protocol header generation system

A communication device includes a data source that generates data for transmission over a bus, and a data encoder that receives and encodes outgoing data. An encoder system receives outgoing data from a data source and stores the outgoing data in a first queue. ... Advanced Micro Devices Inc

03/23/17 / #20170083474

Distributed memory controller

A plurality of first controllers operate according to a plurality of access protocols to control a plurality of memory modules. A second controller receives access requests that target the plurality of memory modules and selectively provides the access requests and control information to the plurality of first controllers based on physical addresses in the access requests. ... Advanced Micro Devices Inc

03/23/17 / #20170083444

Configuring fast memory as cache for slow memory

A cache controller to configure a portion of a first memory as cache for a second memory responsive to an indicator of locality of memory access requests to the second memory. The indicator of locality determines a probability that a location of a memory access request to the second memory is predictable based upon at least one previous memory access request. ... Advanced Micro Devices Inc

03/23/17 / #20170083435

Dynamic multithreaded cache allocation

Apparatus and method embodiments for dynamically allocating cache space in a multi-threaded execution environment are disclosed. In some embodiments, a processor includes a cache shared by each of a plurality of processor cores and/or each of a plurality of threads executing on the processor. ... Advanced Micro Devices Inc

03/23/17 / #20170083382

Power-aware work stealing

First and second processor cores are configured to concurrently execute tasks. A scheduler is configured to schedule tasks for execution by the first and second processor cores. ... Advanced Micro Devices Inc

03/23/17 / #20170083077

Power management for heterogeneous computing systems

A computing system includes a set of computing resources and a datastore to store information representing a corresponding idle power consumption metric and a corresponding peak power consumption metric for each computing resource of the set. The computing system further includes a controller coupled to the set of computing resources and the datastore. ... Advanced Micro Devices Inc

03/23/17 / #20170083074

Power management of interactive workloads driven by direct and indirect user feedback

A method of managing power state transitions for an interactive workload includes storing one or more parameters, each representing an electrical operating characteristic that controls power consumption of the processing unit, receiving a first user input requesting execution of a task by the processing unit, in response to receiving a second user input, modifying at least one of the one or more parameters, and executing the task in the processing unit while operating the processing unit according to the at least one modified parameter.. . ... Advanced Micro Devices Inc

03/23/17 / #20170083065

Thermally-aware throttling in a three-dimensional processor stack

A three-dimensional (3-d) processor stack includes a plurality of processor cores implemented in a plurality of layers. A controller is to selectively throttle one or more of a plurality of processor cores in response to detecting a thermal event. ... Advanced Micro Devices Inc

03/16/17 / #20170076421

Preemptive context switching of processes on an accelerated processing device (apd) based on time quanta

Methods and apparatus are described. A method includes an accelerated processing device running a process. ... Advanced Micro Devices Inc

03/02/17 / #20170061670

Graphics library extensions

Methods for enabling graphics features in processors are described herein. Methods are provided to enable trinary built-in functions in the shader, allow separation of the graphics processor's address space from the requirement that all textures must be physically backed, enable use of a sparse buffer allocated in virtual memory, allow a reference value used for stencil test to be generated and exported from a fragment shader, provide support for use specific operations in the stencil buffers, allow capture of multiple transform feedback streams, allow any combination of streams for rasterization, allow a same set of primitives to be used with multiple transform feedback streams as with a single stream, allow rendering to be directed to layered framebuffer attachments with only a vertex and fragment shader present, and allow geometry to be directed to one of an array of several independent viewport rectangles without a geometry shader.. ... Advanced Micro Devices Inc

03/02/17 / #20170060450

Programmable memory command sequencer

Systems, apparatuses, and methods for utilizing a programmable memory command sequencer to generate multiple commands from a single memory request. A sequencer receives requests from a host processor and utilizes any of a plurality of programmable routines in response to determining that a given request meets specific criteria. ... Advanced Micro Devices Inc

02/23/17 / #20170053377

Priority-based command execution

A method of processing commands is provided. The method includes holding commands in queues and executing the commands in an order based on their respective priority. ... Advanced Micro Devices Inc

02/16/17 / #20170048358

Register files for i/o packet compression

Systems, apparatuses, and methods for reducing inter-node bandwidth are contemplated. A computer system includes requesting nodes sending transactions to target nodes. ... Advanced Micro Devices Inc

02/16/17 / #20170048320

Distributed gather/scatter operations across a network of memory nodes

Devices, methods, and systems for distributed gather and scatter operations in a network of memory nodes. A responding memory node includes a memory; a communications interface having circuitry configured to communicate with at least one other memory node; and a controller. ... Advanced Micro Devices Inc

02/16/17 / #20170046272

Logical memory address regions

Systems, apparatuses, and methods for implementing logical memory address regions in a computing system. The physical memory address space of a computing system may be partitioned into a plurality of logical memory address regions. ... Advanced Micro Devices Inc

02/16/17 / #20170046042

Media system having three dimensional navigation via dynamic carousel

A system and method are set forth which combine an ability to view a motion video with an ability to simultaneously access computer programs. In certain embodiments, the media system provides access to movies, music and photos in a visually appealing three dimensional environment. ... Advanced Micro Devices Inc

02/02/17 / #20170031853

Communication device with selective encoding

A communication device includes a data source that generates data for transmission over a bus, and that further includes a data encoder coupled to receive and encode outgoing data. The encoder further includes a coupling toggle rate (ctr) calculator configured to calculate a ctr for the outgoing data, a threshold calculator configured to determine an expected value of the ctr as a threshold value, a comparator configured to compare the calculated ctr to the threshold value wherein the comparison is used to determine whether to perform an encoding step by an encoding block configured to selectively encode said data. ... Advanced Micro Devices Inc

02/02/17 / #20170031719

Mechanism for resource utilization metering in a computer system

Systems, apparatuses, and methods for tracking system resource utilization of guest virtual machines (vms). Counters may be maintained to track resource utilization of different system resources by different guest vms executing on the system. ... Advanced Micro Devices Inc

01/19/17 / #20170018053

Split storage of anti-aliased samples

Embodiments of the present invention are directed to improving the performance of anti-aliased image rendering. One embodiment is a method of rendering a pixel from an anti-aliased image. ... Advanced Micro Devices Inc

01/05/17 / #20170004080

System performance management using prioritized compute units

Methods, devices, and systems for managing performance of a processor having multiple compute units. An effective number of the multiple compute units may be determined to designate as having priority. ... Advanced Micro Devices Inc








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