Real Time Touch



new TOP 200 Companies filing patents this week

new Companies with the Most Patent Filings (2010+)




Real Time Touch

Altera Corporation patents


Recent patent applications related to Altera Corporation. Altera Corporation is listed as an Agent/Assignee. Note: Altera Corporation may have other listings under different names/spellings. We're not affiliated with Altera Corporation, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "A" | Altera Corporation-related inventors


 new patent  Modular offloading for computationally intensive tasks

Systems and methods are provided for configuring a programmable integrated circuit device. A hard processor region of the programmable integrated circuit device includes a processor that identifies one or more tasks for assigning to an offload region of the programmable integrated circuit. ... Altera Corporation

Backchannel transmission adaptation

Receiver circuitry for receiving a data signal includes summation node circuitry that predicts an error value of the received data signal. The receiver circuitry also includes adaptation engine circuitry coupled to the summation node circuitry. ... Altera Corporation

Method and apparatus for automatic hierarchical design partitioning

A method for designing a system on a target device is disclosed. The system is synthesized. ... Altera Corporation

Herbal composition for treatment of back pain

The present invention encompasses compositions and methods for reducing back pain in a subject.. . ... Altera Corporation

Network processor fpga (npfpga): multi-die-fpga chip for scalable multi-gigabit network processing

Systems and methods are provided for reducing power consumption of a multi-die device, such as a network processor fpga (npfpga). The multi-die device may include hardware resources such as fpga dies, which may be coupled to nic dies and/or memory dies. ... Altera Corporation

Application-based dynamic heterogeneous many-core systems and methods

A method for dynamically configuring multiple processors based on needs of applications includes receiving, from an application, an acceleration request message including a task to be accelerated. The method further includes determining a type of the task and searching a database of available accelerators to dynamically select a first accelerator based on the type of the task. ... Altera Corporation

Methods for memory interface calibration

Integrated circuits with memory interface circuitry may be provided. Prior to calibration, a number of samples may be determined by computing probability density function curves as a function of timing window edge asymmetry for different degrees of oversampling. ... Altera Corporation

Systems and methods for preventing data remanence in memory systems

Methods, circuits, and systems for preventing data remanence in memory systems are provided. Original data is stored in a first memory, which may be a static random access memory (sram). ... Altera Corporation

Denormalization in multi-precision floating-point arithmetic circuitry

The present embodiments relate to integrated circuits with floating-point arithmetic circuitry that handles normalized and denormalized floating-point numbers. The floating-point arithmetic circuitry may include a normalization circuit and a rounding circuit, and the floating-point arithmetic circuitry may generate a first result in form of a normalized, unrounded floating-point number and a second result in form of a normalized, rounded floating-point number. ... Altera Corporation

Techniques for handling high voltage circuitry in an integrated circuit

An integrated circuit formed using a semiconductor substrate may include a logic circuit and a switch circuit, whereby the logic circuit operates at a first power supply voltage and the switch circuit operates at a second power supply voltage that is greater than the first power supply voltage. The logic circuit may be formed within a first triple well structure within the semiconductor substrate and is supplied with a first bias voltage. ... Altera Corporation

Methods and apparatus for managing application-specific power gating on multichip packages

A multichip package is provided that includes multiple integrated circuit (ic) dies mounted on a shared interposer. The ic dies may communicate with one another via corresponding input-output (io) elements on the dies. ... Altera Corporation

Methods and apparatus for dynamically configuring soft processors on an integrated circuit

An offloading engine integrated circuit that includes soft processors may be implemented using an aggregated profiler and a soft processor system generation tool. In particular, the aggregated profiler may generate a suggested configuration for soft processors within the integrated circuit. ... Altera Corporation

Circuitry for reducing leakage current in configuration memory

Integrated circuits may include dual mode memory cells. Dual mode memory cells may be operated in a lookup-table mode or a memory mode. ... Altera Corporation

Methods and apparatus for automated adaptation of transmitter equalizer tap settings

One embodiment relates to a method of automated adaptation of a transmitter equalizer. A multi-dimensional search space of tap settings for the transmitter equalizer is divided into multiple single-dimensional search spaces, each single-dimensional search space being associated with a single tap of the transmitter equalizer. ... Altera Corporation

03/29/18 / #20180091154

Methods and devices for reducing clock skew in bidirectional clock trees

The present disclosure provides systems and methods for improving operation of integrated circuit device including a logic region, which includes a plurality of logic gates that operate based at least in part on a clock signal to facilitate providing a target function, and a clock tree, which includes a clock switch block that receives a source clock signal from a clock source and a branch communicatively coupled between the clock switch block and the logic region, in which the branch operates to provide the clock signal to the logic region based at least in part on the source clock signal and the branch includes a tunable delay buffer that operates to apply a delay to the clock signal based at least in part on a clock skew expected to be introduced by the branch.. . ... Altera Corporation

03/29/18 / #20180091128

Zero-offset sampling for clock duty cycle correction

Duty cycle sampling circuitry is disclosed that may generate offsets that cancel each other out, thereby improving the accuracy of duty cycle sampling of input clock signals based on sampling clock signals. The input clock input signals may be swapped, or the sampling clock signals may be swapped, or both may be swapped, at various times. ... Altera Corporation

03/29/18 / #20180090474

Interconnection of an embedded die

Devices and methods related to an integrated circuit device are provided. The integrated circuit device includes a mother die and a daughter die, in which the daughter die embedded is in a substrate of the integrated circuit device. ... Altera Corporation

03/29/18 / #20180090417

Fluid routing devices and methods for cooling integrated circuit packages

A fluid routing device includes a fluid inlet, first vertical channels, a horizontal channel, a second vertical channel, and a fluid outlet. The first vertical channels are open to the fluid inlet. ... Altera Corporation

03/29/18 / #20180089355

Reset sequencing for reducing noise on a power distribution network

A computer-implemented method includes receiving a first circuit design for an integrated circuit device, determining when multiple power-drawing events are to occur at substantially the same time via one or more circuitry components of the integrated circuit device, which would have a disruptive effect on a power distribution network of the integrated circuit device, based on the first circuit design, and generating logic that schedules the more than one event so that the more than one event do not occur simultaneously. The logic is included in an event sequencer. ... Altera Corporation

03/29/18 / #20180089352

Smart diagnosis of integrated circuits including ip cores with encrypted simulation models

The present embodiments relate to methods for simulating the behavior of an ip core that has an encrypted simulation model. The encrypted simulation model of the ip core may include a plurality of probes, which a debug option may activate selectively, if desired. ... Altera Corporation

03/29/18 / #20180089139

Hybrid programmable many-core device with on-chip interconnect

The present invention provides a hybrid programmable logic device which includes a programmable field programmable gate array logic fabric and a many-core distributed processing subsystem. The device integrates both a fabric of programmable logic elements and processors in the same device, i.e., the same chip. ... Altera Corporation

03/29/18 / #20180088906

Integrated circuits with specialized processing blocks for performing floating-point fast fourier transforms and complex multiplication

Integrated circuits with specialized processing blocks are provided. A specialized processing block may include one real addition stage and one real multiplier stage. ... Altera Corporation

03/29/18 / #20180088622

Adaptive rate-matching first-in first-out (fifo) system

A control system controls first-in first-out (fifo) settings of a receiving system. The control system includes a fifo settings controller that receives a first signal indicative of a first frequency of data received by the receiving system. ... Altera Corporation

03/22/18 / #20180083765

Multi-rate transceiver circuitry

Techniques to operate circuitry in an integrated circuit are provided. The circuitry may include a receiver circuit and one of the provided techniques includes receiving a data stream at the receiver circuit. ... Altera Corporation

03/22/18 / #20180083626

Techniques for power control of circuit blocks

An integrated circuit includes a circuit block, a storage circuit that stores a static power gating control signal, a logic gate circuit that receives a dynamic power gating control signal and the static power gating control signal from the storage circuit, and a transistor coupled between the circuit block and a supply node at a supply voltage. A conductive state of the transistor is determined by an output signal of the logic gate circuit. ... Altera Corporation

03/22/18 / #20180083091

On-die capacitor (odc) structure

An on-die-capacitor structure includes a first capacitor and a second capacitor. The first capacitor may have first and second terminals. ... Altera Corporation

03/22/18 / #20180082720

Pipelined interconnect circuitry having reset values holding capabilities

An integrated circuit may have pipelined interconnects that includes reset control circuitry, which provide desirable reset values to combinational logic. The pipelined interconnects may include multiple parallel input data paths coupled to the combinational logic. ... Altera Corporation

03/22/18 / #20180081840

Methods and apparatus for performing partial reconfiguration in a pipeline-based network topology

A programmable integrated circuit that can support partial reconfiguration is provided. The programmable integrated circuit may include multiple processing nodes that serve as accelerator blocks for an associated host processor that is communicating with the integrated circuit. ... Altera Corporation

03/22/18 / #20180081696

Integrated circuits having expandable processor memory

Integrated circuits may have programmable logic circuitry and hard-coded circuitry. The hard-coded circuitry may include data circuitry, a processor, and memory. ... Altera Corporation

03/22/18 / #20180081633

Variable precision floating-point adder and subtractor

An integrated circuit may include a floating-point adder that supports variable precisions. The floating-point adder may receive first and second inputs to be added, where the first and second inputs each have a mantissa and an exponent. ... Altera Corporation

03/22/18 / #20180081632

Reduced floating-point precision arithmetic circuitry

The present embodiments relate to performing reduced-precision floating-point arithmetic operations using specialized processing blocks with higher-precision floating-point arithmetic circuitry. A specialized processing block may receive four floating-point numbers that represent two single-precision floating-point numbers, each separated into an lsb portion and an msb portion, or four half-precision floating-point numbers. ... Altera Corporation

03/22/18 / #20180081631

Distributed double-precision floating-point multiplication

The present embodiments relate to circuitry that efficiently performs double-precision floating-point multiplication operations, single-precision floating-point multiplication operations, and fixed-point multiplication operations. Such circuitry may be implemented in specialized processing blocks. ... Altera Corporation

03/15/18 / #20180076814

Programmable logic device virtualization

A device includes a programmable logic fabric. The programmable logic fabric includes a first area, wherein a first persona is configured to be programmed in the first area. ... Altera Corporation

03/15/18 / #20180074996

Dot product based processing elements

Systems and methods for calculating a dot product using digital signal processing units that are organized into a dot product processing unit for dot product processing using multipliers and adders of the digital signal processing units.. . ... Altera Corporation

03/15/18 / #20180074787

Fast filtering

Devices and methods for filtering data include calculating intermediate input values from input elements using a transformation function. The transformation function is based at least in part on a size of the filter and a number of filter outputs. ... Altera Corporation

03/15/18 / #20180074704

Memory controller architecture with improved memory scheduling efficiency

Integrated circuits that include memory interface and controller circuitry for communicating with external memory are provided. The memory interface and controller circuitry may include a user logic interface, a memory controller, and a physical layer input-output interface. ... Altera Corporation

03/08/18 / #20180069551

Scalable 2.5d interface architecture

Systems and methods for interface block. The interface block includes input/output modules distributed along the interface block and a mid-stack module interspersed within the input/output modules. ... Altera Corporation

03/08/18 / #20180069533

Systems and methods for a low hold-time sequential input stage

Systems and methods for a low hold-time sequential input stage provide circuitry that includes a first latch element receiving a first input. The first latch element is connected to a first two-input multiplexer. ... Altera Corporation

03/08/18 / #20180068136

Systems and methods for detecting and mitigating of programmable logic device tampering

Systems and methods are disclosed for preventing tampering of a programmable integrated circuit device. Generally, programmable devices, such as fpgas, have two stages of operation; a configuration stage and a user mode stage. ... Altera Corporation

03/01/18 / #20180060561

Systems and methods for authenticating firmware stored on an integrated circuit

The invention discloses a method of authenticating data stored in an integrated circuit. The method includes storing randomized data in the integrated circuit such that the randomized data occupies each address space of the memory circuit that is not occupied by the stored data. ... Altera Corporation

02/22/18 / #20180054110

Voltage regulator with jitter control

A voltage regulator package includes a voltage regulator module that outputs a voltage signal of a particular voltage level through an output terminal is provided. The voltage regulator module may be switched on according to a periodic signal having a periodic signal frequency as a variable. ... Altera Corporation

02/22/18 / #20180052661

Variable precision floating-point multiplier

Integrated circuits with specialized processing blocks are provided. The specialized processing blocks may include floating-point multiplier circuits that can be configured to support variable precision. ... Altera Corporation

02/08/18 / #20180041328

Dynamic clock-data phase alignment in a source synchronous interface circuit

The present embodiments relate to clock-data phase alignment circuitry in source-synchronous interface circuits. Source-synchronous interface standards require the transmission and reception of a clock signal that is transmitted separately from the data signal. ... Altera Corporation

02/08/18 / #20180041201

Techniques for generating pulse-width modulation data

An integrated circuit includes a control circuit, a first-in first-out circuit, and a serializer circuit. The control circuit generates parallel pulse-width modulation data in first parallel pulse-width modulation signals. ... Altera Corporation

02/08/18 / #20180039724

Method and apparatus for verifying structural correctness in retimed circuits

A method for designing a system on a target device includes performing register retiming on an original design for the system to generate a retimed design. Whether the retimed design is structurally correct is verified by performing register retiming on the retimed design.. ... Altera Corporation

02/01/18 / #20180034748

Multi-function, multi-protocol fifo for high-speed communication

Systems and methods are disclosed for buffering data using a multi-function, multi-protocol first-in-first-out (fifo) circuit. For example, a data buffering apparatus is provided that includes a mode selection input and a fifo circuit that is operative to buffer a data signal between a fifo circuit input and a fifo circuit output, wherein the fifo circuit is configured in an operating mode responsive to the mode selection signal.. ... Altera Corporation

01/25/18 / #20180026642

Feedback control systems with pulse density signal processing capabilities

A feedback control system may include a feedback controller for controlling a plant using pulse density signals. The feedback controller may include a pulse density signal generator and a controller logic circuit. ... Altera Corporation

01/25/18 / #20180026638

Apparatus for configurable interface and associated methods

An field programmable gate array (fpga) includes a circuit implemented using the fpga fabric. The fpga further includes another circuit implemented as hardened circuitry. ... Altera Corporation

01/25/18 / #20180025100

Method and apparatus for improving system operation by replacing components for performing division during design compilation

A method for designing a system on a target device includes identifying components in a netlist that perform a division operation. The netlist is modified during synthesis to utilize other components to compute a result of the division operation by performing a multiplication operation.. ... Altera Corporation

01/04/18 / #20180006664

Methods and apparatus for performing reed-solomon encoding by lagrangian polynomial fitting

An integrated circuit for implementing a reed-solomon encoder circuit is provided. The encoder circuit may include partial syndrome calculation circuitry and matrix multiplication circuitry. ... Altera Corporation

01/04/18 / #20180006653

Integrated circuits with hybrid fixed/configurable clock networks

An integrated circuit with a clock distribution network is provided. The clock distribution network may include configurable clock routing paths linking a clock source to one or more clock tree roots and may also include fixed clock routing paths linking the clock tree roots to corresponding leaf nodes. ... Altera Corporation

01/04/18 / #20180004878

Circuit design instrumentation for state visualization

An integrated circuit includes user storage circuits, a local control circuit, and scan storage circuits arranged in a scan chain. At least a portion of a design-under-test is implemented in a subset of the integrated circuit that comprises the user storage circuits. ... Altera Corporation

12/28/17 / #20170373690

Apparatus and methods for on-die temperature sensing to improve fpga performance

A field programmable gate array (fpga) includes a temperature sensor array. The fpga also includes a supply voltage modulation circuit. ... Altera Corporation

12/28/17 / #20170373675

Method and apparatus for phase-aligned 2x frequency clock generation

One embodiment relates to a multiple-channel serializer circuit that includes a plurality of one-channel serializers. A one-channel serializer of the plurality of one-channel serializes includes a local 2× frequency clock generator with a non-divider structure. ... Altera Corporation

12/28/17 / #20170371836

Methods for specifying processor architectures for programmable integrated circuits

A programmable integrated circuit may include soft and hard logic for implementing a reduced instruction set computing (risc) processor. Processor generator tools implemented on specialized computing equipment may be used to specify desired parameters for the processor architecture, including the data word size of one or more data paths, the instruction word size, and a set of instruction formats. ... Altera Corporation

12/28/17 / #20170371818

Method and apparatus for data detection and event capture

One embodiment relates to a data detection and event capture circuit. Data comparator logic receives a monitored data word from a parallel data bus and generates a plurality of pattern detected signals. ... Altera Corporation

12/28/17 / #20170371594

Methods and apparatus for smart memory interface

One embodiment relates to a memory structure that includes a bank group and a port emulation circuit module. The bank group includes a plurality of memory banks, each memory bank having one read port and one write port. ... Altera Corporation

12/21/17 / #20170366190

Phase-locked loops with electrical overstress protection circuitry

An integrated circuit with a phase-locked loop (pll) is provided. The pll may include a phase frequency detector, a charge pump, a source follower circuit, a variable oscillator, a frequency divider, and a control block. ... Altera Corporation

12/21/17 / #20170366186

Selectively disabled output

Circuits, methods, and apparatus are directed to an integrated circuit having a disabling element that can disable a reading of data from the circuit. Once the disabling element is set to not allow a reading of the data, the disabling element cannot be changed to allow a reading of the data. ... Altera Corporation

12/21/17 / #20170366174

Techniques for detecting and correcting errors on a ring oscillator

A circuit may include a ring oscillator circuit and monitoring circuitry. The ring oscillator circuit has a group of inverters in a loop, whereby the group of inverters includes first, second, and third output nodes. ... Altera Corporation

12/21/17 / #20170365643

Parallel configured resistive memory elements

The present invention discloses a memory cell that includes at least two non-volatile resistive memory elements coupled in parallel. The non-volatile resistive memory elements are capable of existing in different resistive states such that each of the different resistive state represents a different data state. ... Altera Corporation

12/14/17 / #20170359073

Supporting pseudo open drain input/output standards in a programmable logic device

Techniques and mechanisms allow a programmable logic device (pld) to support a pseudo open drain (pod) input/output (i/o) standard used in interface protocols such as fourth generation double data rate (ddr4). An or gate with inputs including data and an inverted output enable from a user's design may be inserted into programmable logic. ... Altera Corporation

12/14/17 / #20170357606

Configuration via high speed serial link

Mechanisms and techniques for configuring a configurable slave device using a high speed serial link where a different number of lanes of the high speed serial link are used to send data between the slave device and a master device, depending on whether the slave device is in configuration mode or in normal operations mode, are provided.. . ... Altera Corporation

12/07/17 / #20170353335

Low-skew channel bonding using phase-measuring fifo buffer

Circuits and methods are disclosed for low-skew bonding of a plurality of data channels into a multi-lane data channel. In one embodiment, phase-measuring first-in first-out buffer circuits buffer pre-buffer parallel data signals and generate phase-measurement signals. ... Altera Corporation

12/07/17 / #20170352393

Emulated multiport memory element circuitry with exclusive-or based control circuitry

Integrated circuits may include memory element circuitry. The memory element circuitry may include multiple dual-port memory elements that are controlled to effectively form a multi-port memory element having multiple read and write ports. ... Altera Corporation

12/07/17 / #20170350937

Integrated circuit calibration system using general purpose processors

In one embodiment, an integrated circuit is disclosed. The integrated includes a general purpose processor, an interface circuit, and a calibration adapter circuit. ... Altera Corporation

11/23/17 / #20170339116

Method and apparatus for secure provisioning of an integrated circuit device

A method of operating an integrated circuit may include generating a session key with a random number generator circuit. The session key may then be used to establish a secure communications channel between the integrated circuit and a remote server. ... Altera Corporation

11/23/17 / #20170337318

Method and apparatus for implementing soft constraints in tools used for designing programmable logic devices

A method for designing a system on a target device utilizing programmable logic devices (plds) includes generating options for utilizing resources on the plds in response to user specified constraints. The options for utilizing the resources on the plds are refined independent of the user specified constraints.. ... Altera Corporation

11/16/17 / #20170331363

Current limited power converter circuits and methods

. . A power converter circuit regulates an output voltage of a power train circuit and controls the current in the power train circuit. A current sensor circuit measures a current in the power train circuit. ... Altera Corporation

11/09/17 / #20170322813

Pipelined cascaded digital signal processing structures and methods

Circuitry operating under a floating-point mode or a fixed-point mode includes a first circuit accepting a first data input and generating a first data output. The first circuit includes a first arithmetic element accepting the first data input, a plurality of pipeline registers disposed in connection with the first arithmetic element, and a cascade register that outputs the first data output. ... Altera Corporation

11/09/17 / #20170322775

Structures for lut-based arithmetic in plds

A programmable logic device (pld) includes a plurality of logic array blocks (lab's) connected by a pld routing architecture. At least one lab includes a logic element (le) configurable to arithmetically combine a plurality of binary input signals in a plurality of stages. ... Altera Corporation

11/09/17 / #20170322769

Fixed-point and floating-point arithmetic operator circuits in specialized processing blocks

The present embodiments relate to circuitry that efficiently performs floating-point arithmetic operations and fixed-point arithmetic operations. Such circuitry may be implemented in specialized processing blocks. ... Altera Corporation

10/26/17 / #20170310340

Serial memory interface circuitry for programmable integrated circuits

A programmable integrated circuit may be provided with a memory interface for communicating with an external memory over a serial communications path. To accommodate a variety of different memory interface protocols while satisfying low-latency performance criteria, part of the memory interface may be formed from programmable logic and part of the memory interface may be formed from hardwired circuitry. ... Altera Corporation

10/26/17 / #20170308721

Setting security features of programmable logic devices

Systems and methods are disclosed for allowing security features to be selectively enabled during device configuration. For example, a programmable integrated circuit device is provided that receives configuration data and security requirement data. ... Altera Corporation

10/12/17 / #20170294914

Power gated lookup table circuitry

. . A programmable integrated circuit with lookup table circuitry is provided. The lookup table (lut) circuitry may be formed using multiplexers. ... Altera Corporation

10/12/17 / #20170294913

Method apparatus for high-level programs with general control flow

A method of configuring a programmable integrated circuit device to implement control flow at a current basic block. A branch selector node within the current basic block is configured to receive at least one control signal, where each of the at least one control signal is associated with a respective previous basic block. ... Altera Corporation

10/12/17 / #20170293703

Safety features for high level design

Aspects of this disclosure relate generally to electronic design automation, and more specifically, to electronic design automation using high level synthesis techniques to generate circuit designs that include safety features. Some innovative aspects can be implemented in computer-readable media, systems and methods capable of accessing an algorithmic description representation of a circuit design. ... Altera Corporation

10/05/17 / #20170288671

Pipelined interconnect circuitry with double data rate interconnections

An integrated circuit may have pipelined interconnects that are configurable to operate in registered single data rate mode, registered double data rate mode, or in combinational mode. The pipelined interconnect may include routing multiplexers for selecting incoming signals, circuitry for serialization and de-serialization, and memory elements that are configurable to store one or two signals per clock period. ... Altera Corporation

10/05/17 / #20170288648

Pulse-width modulation voltage identification interface

Systems, methods, and devices for voltage identification using a pulse-width modulation signal are provided. Such an integrated circuit device may include an input/output (i/o) interface and voltage identification (vid) circuitry. ... Altera Corporation

10/05/17 / #20170287872

Bumpless wafer level fan-out package

An integrated circuit package may include a first conductive pad on an interposer substrate, and a second conductive pad formed on a front surface of an integrated circuit die. The second conductive pad may directly contact the first conductive pad on the interposer substrate. ... Altera Corporation

10/05/17 / #20170287543

Adaptive refresh scheduling for memory

The present disclosure provides for adaptive scheduling of memory refreshes. One embodiment relates to a method of adapting an initial refresh sequence. ... Altera Corporation

10/05/17 / #20170286590

Method and apparatus for performing register retiming in the presence of timing analysis exceptions

A method for designing a system on a target device includes identifying a timing exception for a portion of a signal path. An area on the target device that includes components affected by the timing exception. ... Altera Corporation

10/05/17 / #20170286582

Efficient integrated circuits configuration data mangement

Circuitry for efficient configuration data management is presented. The circuitry may include an encoding circuit that compares the configuration data of a circuit design with the base configuration data of a base circuit design. ... Altera Corporation

09/21/17 / #20170272073

Dynamic parameter operation of an fpga

Methods and systems for operating a programmable logic fabric including a dynamic parameter scaling controller that tracks an operating parameter that functions at multiple operating conditions by maintaining the operating parameter while cycling through a multiple operating conditions during a calibration mode using the calibration configuration for the programmable logic fabric. The dynamic parameter scaling controller also stores one or more functional values for the operating parameter in a calibration table. ... Altera Corporation

09/21/17 / #20170270995

Circuits and methods for dqs autogating

In one aspect, a method includes receiving a differential strobe signal including first and second components; buffering, by a first buffer, both the first and second components; and buffering, by a second buffer, the first component. The method includes receiving, by a control logic block, the output of the second buffer. ... Altera Corporation

09/14/17 / #20170264283

Techniques for enabling and disabling transistor legs in an output driver circuit

An output driver circuit includes a control circuit and first and second transistor legs that are coupled to an output pad. Each of the first and second transistor legs includes a pull-up transistor and a pull-down transistor. ... Altera Corporation

09/14/17 / #20170262563

State visibility and manipulation in integrated circuits

In a first mode, a control circuit may implement a circuit design with storage circuits in an integrated circuit by programming configuration memory bits via configuration resources. The storage circuits may be accessed for read and write operations during the execution of the circuit design implementation with the integrated circuit. ... Altera Corporation

09/07/17 / #20170257369

Flexible feature enabling integrated circuit and methods to operate the integrated circuit

A method for enabling a circuit feature on an integrated circuit device having inactive circuit features includes a step to receive an encrypted message and a signed digital signature from a server using an input/output (i/o) terminal within the integrated circuit device. The method also includes a step to decrypt the encrypted message using a public key to obtain a decrypted message using a data decryption block within the integrated circuit device. ... Altera Corporation

09/07/17 / #20170257222

Techniques for protecting security features of integrated circuits

An integrated circuit includes a control circuit, a one-time programmable circuit, and a security feature. The control circuit determines if the one-time programmable circuit is programmed in response to a request by a user of the integrated circuit to access the security feature. ... Altera Corporation

08/31/17 / #20170250713

Methods and apparatus for performing reed-solomon encoding

The present embodiments relate to reed-solomon encoding, and to circuitry for performing such encoding, particularly in an integrated circuit. A reed-solomon encoder circuit may receive a message with data symbols and compute a partial syndrome vector by multiplying the data symbols with a first matrix. ... Altera Corporation

08/31/17 / #20170250681

Techniques for detecting and correcting errors on a ring oscillator

A circuit may include a ring oscillator circuit and monitoring circuitry. The ring oscillator circuit has a group of inverters in a loop, whereby the group of inverters includes first, second, and third output nodes. ... Altera Corporation

08/31/17 / #20170250155

Multi-access memory system and a method to manufacture the system

A multiple memory access system is disclosed. The system includes a first die disposed on a package substrate. ... Altera Corporation

08/31/17 / #20170249409

Emulation of synchronous pipeline registers in integrated circuits with asynchronous interconnection resources

Integrated circuits may include synchronous nodes and asynchronous routing elements coupled between the synchronous nodes. A synchronous design implemented in such an integrated circuit may identify a register chain having a source register, a destination register, and intermediate registers. ... Altera Corporation

08/24/17 / #20170244413

Hybrid architecture for signal processing and signal processing accelerator

Systems and methods for configuring circuitry for use with a field programmable gate array (fpga) are disclosed. The circuitry includes an array of signal processing accelerators (spas) and an array of network nodes. ... Altera Corporation

08/24/17 / #20170244411

Apparatus for flexible electronic interfaces and associated methods

A semiconductor die includes at least one flexible interface block. The flexible interface block includes at least one interconnect, and at least one buffer coupled to the at least one interconnect. ... Altera Corporation

08/17/17 / #20170237433

Circuits and methods for impedance calibration

A driver circuit drives data to an output based on an input data signal in a transmission mode. The driver circuit includes transistors. ... Altera Corporation

08/10/17 / #20170230209

High-speed serial data signal receiver circuitry

Circuitry for receiving a high-speed serial data signal (e.g., having a bit rate in the range of about 10 gbps and higher) includes a two-stage, continuous-time, linear equalizer having only two serially connected stages. Phase detector circuitry may be provided for receiving the serial output of the equalizer and for converting successive pairs of bits in that output to successive parallel-form bit pairs. ... Altera Corporation

08/03/17 / #20170222651

Transformable logic and routing structures for datapath optimization

Integrated circuits such as programmable integrated circuits may include programmable logic regions that can be configured to perform custom user functions. The programmable logic regions may include lookup table (lut) circuitry driven using vectored multiplexing circuits. ... Altera Corporation

08/03/17 / #20170221537

High speed fpga boot-up through concurrent multi-frame configuration scheme

Systems and methods are provided herein for implementing a programmable integrated circuit device that enables high-speed fpga boot-up through a significant reduction of configuration time. By enabling high-speed fpga boot-up, the programmable integrated circuit device will be able to accommodate applications that require faster boot-up time than conventional programmable integrated circuit devices are able to accommodate. ... Altera Corporation

07/27/17 / #20170214557

Digital equalizer adaptation using on-die instrument

Systems and methods are provided for adjusting gain of a receiver. Adaptation circuitry is operable to identify, based on a matrix representation of a receiver's output generated from horizontal and vertical sweeps of the receiver's output, an eye opening of the receiver's output. ... Altera Corporation

07/20/17 / #20170206176

Integrated circuit device with embedded programmable logic

Systems and methods are provided to enhance the functionality of an integrated circuit. Such an integrated circuit may include a primary circuitry and an embedded programmable logic programmable to adjust the functionality of the primary circuitry. ... Altera Corporation

07/20/17 / #20170203304

Electrostatic collector

An electrostatic collector including: a collection chamber delimited by a tubular wall oriented along a first axis; a collection electrode configured to be disposed inside the collection chamber against the wall; a discharge electrode, of elongate form, that extends along the first axis and includes an end, in a shape of a tip, the end being disposed opposite the collection electrode; a first part of a first diameter, emerging on the tip-shaped end, a second part of a second diameter, the second diameter being greater than or equal to twice the first diameter, the second diameter for example being between 2 and 6 times the first diameter; and a sudden widening, extending between the first part and the second part.. . ... Altera Corporation

07/13/17 / #20170201256

Power gated lookup table circuitry

A programmable integrated circuit with lookup table circuitry is provided. The lookup table (lut) circuitry may be formed using multiplexers. ... Altera Corporation

07/13/17 / #20170200484

Programmable integrated circuits with in-operation reconfiguration capability

Integrated circuits may include partial reconfiguration (pr) circuitry for reconfiguring only a portion of a memory array. In some applications, partial reconfiguration may be performed during user mode. ... Altera Corporation

07/06/17 / #20170194964

Programmable routing performance, power, and area by recovering aging in routing pass gates

Transistors degrade when subjected to voltage stress. Methods are described for reducing this aging problem by applying a reverse voltage to the gates of the circuit on an intermittent or periodic basis. ... Altera Corporation

06/01/17 / #20170155529

Clock data recovery circuitry associated with programmable logic device circuitry

A programmable logic device (“pld”) is augmented with programmable clock data recover (“cdr”) circuitry to allow the pld to communicate via any of a large number of cdr signaling protocols. The cdr circuitry may be integrated with the pld, or it may be wholly or partly on a separate integrated circuit. ... Altera Corporation

06/01/17 / #20170154951

Scalable fixed-footprint capacitor structure

In one embodiment, a capacitor structure includes a substrate, a dielectric stack, a first conductor segment, a second conductor segment and a shielding conductor segment. The dielectric stack is formed on the substrate. ... Altera Corporation

05/11/17 / #20170133329

2.5d electronic package

A 2.5d electronic package is provided in which at least one integrated circuit is mounted on an interposer that is mounted on a package substrate. To reduce warpage, the interconnection array of the integrated circuit does not include a thick metallization layer; and at least part of the power distribution function that would otherwise have been performed by the thick metallization layer is performed by one or more metallization layers that are added to the interposer. ... Altera Corporation

05/11/17 / #20170133298

Integrated circuit package with enhanced cooling structure

An integrated circuit package may include an integrated circuit die having first and second circuit regions and a surface. The first circuit region of the integrated circuit package has an operating temperature that is different than that of the second circuit region. ... Altera Corporation

04/27/17 / #20170117899

Systems and methods for configuring an sopc without a need to use an external memory

Systems and techniques for configuration of a system on a programmable chip (sopc) are described. By configuring the sopc, during power-up, with a voltage input instead of with a flash memory or another non-volatile memory, the systems and techniques may save cost and board space.. ... Altera Corporation

04/27/17 / #20170117250

Integrated circuit packages with detachable interconnect structures

An integrated circuit package may include a first integrated circuit die having a first bump structure, a second integrated circuit die having a second bump structure, and a detachable interconnect structure having first and second conductive structures that is positioned between the first and second integrated circuit dies. In order to establish electrical communication between the first and second integrated circuit dies, the first conductive structure of the detachable interconnect structure is connected to the first bump structure of the first integrated circuit die, and the second conductive structure of the detachable interconnect structure is connected to the second bump structure of the second integrated circuit die. ... Altera Corporation

04/27/17 / #20170115958

Methods and apparatus for performing product series operations in multiplier accumulator blocks

A specialized processing block on an integrated circuit includes a first and second arithmetic operator stage, an output coupled to another specialized processing block, and configurable interconnect circuitry which may be configured to route signals throughout the specialized processing block, including in and out of the first and second arithmetic operator stages. The configurable interconnect circuitry may further include multiplexer circuitry to route selected signals. ... Altera Corporation

04/13/17 / #20170103299

Method and apparatus for implementing layers on a convolutional neural network accelerator

A method for implementing a convolutional neural network (cnn) accelerator on a target includes utilizing one or more processing elements to implement a standard convolution layer. A configuration of the cnn accelerator is modified to change a data flow between components on the cnn accelerator. ... Altera Corporation

04/13/17 / #20170103298

Method and apparatus for designing and implementing a convolution neural net accelerator

A method for implementing a convolutional neural network (cnn) accelerator on a target includes identifying characteristics and parameters for the cnn accelerator. Resources on the target are identified. ... Altera Corporation

04/13/17 / #20170103157

State visibility and manipulation in integrated circuits

In a first mode, a control circuit generates a circuit design implementation with storage circuits in an integrated circuit by programming configuration memory bits via configuration resources. The storage circuits can be accessed for read and write operations during the execution of the circuit design implementation with the integrated circuit. ... Altera Corporation

04/06/17 / #20170099053

Programmable logic device virtualization

A device includes a programmable logic fabric. The programmable logic fabric includes a first area, wherein a first persona is configured to be programmed in the first area. ... Altera Corporation

04/06/17 / #20170098026

Control block size reduction through ip migration in an integrated circuit device

Methods for control block size reduction of a controller of an integrated circuit (ic) device through intellectual property (ip) migration in the ic device are disclosed. A disclosed method includes receiving configuration data for the ic device and determining whether ip construction data is defined in the configuration data. ... Altera Corporation

04/06/17 / #20170097840

Efficient virtual i/o address translation

A method includes using a network interface controller to monitor a transmit ring, wherein the transmit ring comprises a circular ring data structure that stores descriptors, wherein a descriptor describes data and comprises a guest bus address that provides a virtual memory location of the data. The method also includes using the network interface controller to determine that a descriptor has been written to the transmit ring. ... Altera Corporation

04/06/17 / #20170097810

Methods and apparatus for sequencing multiply-accumulate operations

An integrated circuit may have specialized processing blocks that are configurable to operate as arithmetic operators that may implement, amongst other functions, multiplication and multiply-accumulation operations in a first mode. In a second mode, a sequencer circuit may provide data signals and control signals to the specialized processing blocks such that the specialized processing block operates as a signal processing device that handles signals in a given sequence. ... Altera Corporation

03/30/17 / #20170092586

Multi-level signaling for on-package chip-to-chip interconnect through silicon bridge

One embodiment relates to an apparatus for data communication between at least two in-package semiconductor dies. On the first semiconductor die in a package, a digital-to-analog converter (dac) converts a plurality of binary signals to an analog signal. ... Altera Corporation

03/23/17 / #20170084553

Tranmission line bridge interconnects

In one embodiment, an integrated circuit package includes a package substrate, a printed circuit board, an interposer structure and a transmission line bridge interconnect within the interposer. The interposer structure, which includes multiple interposer layers, may be formed on a top surface of the package substrate. ... Altera Corporation

03/23/17 / #20170082689

Systems and methods for particle detection and error correction in an integrated circuit

An integrated circuit for detecting and correcting error events associated with atomic particles includes error detection circuitry connected to monitoring circuitry. The error detection circuitry may include a particle sensing circuit (e.g., a diode circuit) embedded below a substrate surface of the integrated circuit, and a particle validation circuit (e.g., a sense amplifier) coupled to the particle sensing circuit through a conductive via. ... Altera Corporation

03/16/17 / #20170077814

Asymmetric power flow controller for a power converter and method of operating the same

A controller for a power converter formed with a plurality of converter stages, and method of operating the same. In one embodiment, the controller includes a power system controller configured to determine an unequal current allocation among the plurality of converter stages based on an operation of the power converter. ... Altera Corporation

03/09/17 / #20170068768

Method and apparatus for performing parallel routing using a multi-threaded routing procedure

A method for designing a system to be implemented on a target device includes generating bounding boxes on the target device for nets in the system where a bounding box identifies routing resources available for routing its corresponding net. The nets in the system are assigned to a plurality of threads to be routed. ... Altera Corporation

03/09/17 / #20170068765

Incremental register retiming of an integrated circuit design

A first circuit design description may have registers and combinational gates. Circuit design computing equipment may perform register retiming on the first circuit design description, whereby registers are moved across combinational gates during a first circuit design implementation. ... Altera Corporation

03/09/17 / #20170068638

Distributed multi-die protocol application interface

Systems and methods are provided for supporting wide-protocol interface across a multi-die interconnect interface. Data signals of a wide-protocol interface are split into a plurality of data streams. ... Altera Corporation

03/02/17 / #20170061162

Systems and methods for multiport to multiport cryptography

Systems and methods are discussed herein for reusing hardware for encryption and authentication, where the hardware has a fixed input bandwidth, and where the hardware has the same bandwidth for a different input bandwidth. In order to accomplish this mechanism, systems and methods are provided herein for processing invalid data that appears within streams of valid data. ... Altera Corporation

03/02/17 / #20170061055

Efficient integrated circuits configuration data management

Circuitry for efficient configuration data management is presented. The circuitry may include an encoding circuit that compares the configuration data of a circuit design with the base configuration data of a base circuit design. ... Altera Corporation

02/16/17 / #20170046455

Method and apparatus for implementing a system-level design tool for design planning and architecture exploration

A method for designing a system on a target device includes mapping a high-level description of the system onto a model of a target device prior to generating a register transfer level description of the system. A visual representation of the mapping is generated.. ... Altera Corporation

02/16/17 / #20170046179

Application-based dynamic heterogeneous many-core systems and methods

A method for dynamically configuring multiple processors based on needs of applications includes receiving, from an application, an acceleration request message including a task to be accelerated. The method further includes determining a type of the task and searching a database of available accelerators to dynamically select a first accelerator based on the type of the task. ... Altera Corporation

02/09/17 / #20170041249

Programmable logic device with integrated network-on-chip

Systems and methods for providing a network-on-chip (noc) structure on an integrated circuit for high-speed data passing. In some aspects, the noc structure includes multiple noc stations with a hard-ip interface having a bidirectional connection to local components of the integrated circuit. ... Altera Corporation

01/26/17 / #20170024355

Hybrid programmable many-core device with on-chip interconnect

The present invention provides a hybrid programmable logic device which includes a programmable field programmable gate array logic fabric and a many-core distributed processing subsystem. The device integrates both a fabric of programmable logic elements and processors in the same device, i.e., the same chip. ... Altera Corporation

01/05/17 / #20170005662

Programmable high-speed i/o interface

Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. ... Altera Corporation

01/05/17 / #20170005661

Programmable high-speed i/o interface

Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. ... Altera Corporation








ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009



###

This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. Freshpatents.com is not affiliated or associated with Altera Corporation in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Altera Corporation with additional patents listed. Browse our Agent directory for other possible listings. Page by FreshPatents.com

###