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Applied Micro Circuits Corporation patents


Recent patent applications related to Applied Micro Circuits Corporation. Applied Micro Circuits Corporation is listed as an Agent/Assignee. Note: Applied Micro Circuits Corporation may have other listings under different names/spellings. We're not affiliated with Applied Micro Circuits Corporation, we're just tracking patents.

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Power optimization mechanisms for framers by serializing frame alignment processes for multiple lanes

System and method of frame alignment at a receiver with power optimization mechanisms. A framer at the receiver is configured to process data streams from multiple physical lanes and/or multiple channels serially. ... Applied Micro Circuits Corporation

Power optimization mechanisms for framers by using serial comparison in frame alignment process

System and method of frame alignment at a receiver with power optimization mechanisms. A framer uses one or more comparators to search for the faw in the incoming data, with each comparator configured to serially compare multiple windows of a parallel m-bit block (as provided from a parallel data bus) with the faw. ... Applied Micro Circuits Corporation

Power optimization mechanisms for framers by selectively deactivating frame alignment process

System and method of frame alignment at a receiver with power optimization mechanisms. A framer is configured to perform a frame alignment process on a data stream and enter an inactive state after frame alignment is achieved. ... Applied Micro Circuits Corporation

Mitigating interaction between adaptive equalization and timing recovery

System and method of timing recovery for recovering a clock signal with reduced interference with clock phase correction by an adaptive equalizer. The equalizer in the timing recovery loop is dynamically adapted to the current channel characteristics that vary over time. ... Applied Micro Circuits Corporation

Resolving interaction between channel estimation and timing recovery

System and method of timing recovery for recovering a clock signal with reduced interaction between an adaptive channel estimator and the overall timing loop for correcting clock phase. The channel response estimation in the timing recovery loop is dynamically adapted to the current channel response that varies over time. ... Applied Micro Circuits Corporation

Timing recovery with adaptive channel response estimation

System and method of timing recovery for recovering a clock signal by using adaptive channel response estimation. The channel response estimation in the timing recovery loop is dynamically adapted to the current channel response that varies over time. ... Applied Micro Circuits Corporation

High speed serializer using quadrature clocks

Techniques efficiently serialize multiple data streams using quadrature clocks. Serializer employs first, second, third, and fourth clock signals. ... Applied Micro Circuits Corporation

Self-referenced on-die voltage droop detector

A self-referenced on-die voltage droop detector generates a reference voltage from the supply voltage of an integrated circuit's power distribution network, and compares this reference voltage to the transient supply voltage in order to detect voltage droops. The detector responds to detected occurrences of voltage droop with low latency by virtue of being located on-die. ... Applied Micro Circuits Corporation

High speed add-compare-select for viterbi decoder

System and method of comparing-selecting state metric values for high speed. Viterbi decoding. ... Applied Micro Circuits Corporation

Virtual appliance on a chip

Various embodiments provide for a system that integrates 64 bit arm cores and a switch on a single chip. The risc style processors use highly optimized sets of instructions rather than the specialized set of instructions found in other architectures (e.g., x86). ... Applied Micro Circuits Corporation

Package programmable decoupling capacitor array

A semiconductor chip allows for a selected amount of on-die decoupling capacitance to be connected to a very-large-scale integrated circuit (vlsi) system after the circuit design is complete. The semiconductor chip comprises an integrated circuit disposed on a packaging substrate, and a power distribution network that is electrically connectable to the integrated circuit via a programmable connectivity array via the packaging substrate.. ... Applied Micro Circuits Corporation

Systems and methods facilitating reduced latency via stashing in system on chips

Systems and methods that facilitate reduced latency via stashing in multi-level cache memory architectures of systems on chips (socs) are provided. One method involves stashing, by a device includes a plurality of multi-processor central processing unit cores, first data into a first cache memory of a plurality of cache memories, the plurality of cache memories being associated with a multi-level cache memory architecture. ... Applied Micro Circuits Corporation








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