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Arm Limited patents


Recent patent applications related to Arm Limited. Arm Limited is listed as an Agent/Assignee. Note: Arm Limited may have other listings under different names/spellings. We're not affiliated with Arm Limited, we're just tracking patents.

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An apparatus and method for processing a received input signal containing a sequence of data blocks

An apparatus and method are provided for processing a received input signal comprising a sequence of data blocks. Counter circuitry within the apparatus is arranged to receive a digital representation of the input signal, and for each data block generates a count value indicative of occurrences of a property of the digital representation (for example a rising edge or a falling edge) during an associated data block transmission period. ... Arm Limited

Providing output surface data to a display in data processing systems

A method of operating a data processing system is disclosed for a data processing system that comprises a display and a display controller operable to provide to the display data in respect of output surfaces to be displayed. The method comprises, when an output surface is to be displayed, the display controller providing to the display data in respect of the output surface in the form of image data and image modification data, and the display using the image data and the image modification data when producing an output surface for display.. ... Arm Limited

Graphics processing

A data processing system replicates the operation of a target graphics processor using a graphics processor of the data processing system. A driver for the target graphics processor converts higher level commands and program expressions intended for the target graphics processor into lower level control data and instructions suitable for use by the target graphics processor. ... Arm Limited

Trace data representation

Trace circuitry 22, 6 forms trace objects 34 representing a sequence of executed program instructions and comprising a start address indicator indicating a start address of a sequence of executed program instructions, a branch outcome indicator indicating a sequence of branch outcomes within the sequence of executed program instructions starting from the start address and a count indicator indicating a count of times the sequence of branch outcomes was detected. The trace circuitry may be on-chip 22 or off-chip 6. ... Arm Limited

Hardware thread scheduling

An apparatus has processing circuitry to execute instructions from multiple threads and hardware registers to store context data for the multiple threads concurrently. At a given time a certain number of software-scheduled threads may be scheduled for execution by software executed by the processing circuitry. ... Arm Limited

Data processing

Data processing circuitry comprises out-of-order instruction execution circuitry to execute program instructions in an instruction execution order; a data store, to store information on a set of instructions for which execution has been initiated, the data store providing ordering information indicating the relative position of each instruction in the set of instructions with respect to a program code order; commit circuitry to commit the results of instructions executed by the instruction execution circuitry; one or more cumulative status registers configured to be set in response to a respective condition generated by execution of an instruction and then to remain set until an unset instruction is executed; and an identifier store, to store for at least those of the one or more cumulative status registers which are not currently set, an identifier of an instruction which is earliest in the program code order in the set of instructions and which generated a condition to set that cumulative status register.. . ... Arm Limited

Video data processing system

An apparatus for encoding frames of a sequence of source frames of video image data to be encoded. The apparatus includes encoding circuitry configured to encode the source frames using reference frames. ... Arm Limited

System, device, and method of secure entry and handling of passwords

Devices, system, and methods of secure entry and handling of passwords and personal identification numbers (pins), as well as for secure local storage, secure user authentication, and secure payment via mobile devices and via payment terminals. A computing device includes: a secure storage unit to securely store a confidential data item; a non-secure execution environment to execute program code, the program code to transport to a remote server a message; a secure execution environment (see) to securely execute code, the see including: a rewriter module to securely obtain the confidential data item from the secure storage, and to securely write the confidential data item into one or more fields in said message prior to its encrypted transport to the remote server.. ... Arm Limited

Skewed corner tracking for memory write operations

A memory device includes a bitcell array having a plurality of bitcells, a dummy wordline, a dummy row cell pulldown, and a write tracker coupling the dummy wordline to the dummy row cell pulldown. The write tracker is configured as a transmission gate during a read operation on the bitcell array, and is configured as having only one or more active nmosfets during a write operation on the bitcell array.. ... Arm Limited

Memory circuit

A circuit comprises an array of programmable memory elements fabricated on a substrate, each memory element having one or more processable regions which, when processed by an external process in which a material is applied to at least partially cover one or more of the regions, are configured to program that memory element to one of multiple states;a first set of control lines connected to the array of memory elements, by which the contents of each individual memory element are capable of being accessed by control signals applied to a respective combination of at least two control lines in the first set of control lines;and an array of second circuit elements, different to the memory elements, each connected to a control line of the first set of control lines and to another control line of a second set of control lines, different to the first set of control lines, so as to provide access to second circuit elements in the array.. . ... Arm Limited

Targeted recovery process

An apparatus comprises at least three processing circuits to perform redundant processing of common program instructions. Error detection circuitry coupled to a plurality of signal nodes of each of said at least three processing circuits comprises comparison circuitry to detect a mismatch between signals on corresponding signal nodes in said at least three processing circuits, the plurality of signal nodes forming a first group of signal nodes and a second group of signal nodes. ... Arm Limited

Handling stalling event for multiple thread pipeline, and triggering action based on information access delay

A processing pipeline for processing instructions with instructions from multiple threads in flight concurrently may have control circuitry to detect a stalling event associated with a given thread. In response, at least one instruction of the given thread may be flushed from the pipeline, and the control circuitry may trigger fetch circuitry to reduce a fraction of the fetched instructions which are fetched from the given thread. ... Arm Limited

Move prefix instruction

An apparatus 2 has instruction fusing circuitry 50 for fusing two or more instructions fetched from a data store to generate a fused instruction to be processed by processing circuitry 14. A move prefix instruction is provided which indicates to the instruction fusing circuitry 50 that the move prefix instruction can be fused with an immediately following data processing instruction without needing to compare registers specified by the move prefix instruction and the immediately following instruction. ... Arm Limited

Memory access monitoring

An apparatus has a monitoring data store for storing monitoring data indicating regions of a memory address space to be monitored for changes, which can include at least two non-contiguous regions. Processing circuitry updates the monitoring data in response to an update monitor instruction. ... Arm Limited

09/06/18 / #20180253523

Technique for generating the layout of a circuit block of an integrated circuit

A computer implemented method is described for generating a layout of a circuit block of an integrated circuit. The method comprises receiving input data defining a logical operation of the circuit block, and accessing a cell library providing a plurality of cells that define circuit elements, in order to determine with reference to the input data the cells to be used to implement the circuit block. ... Arm Limited

09/06/18 / #20180253387

Cache storage

A data processing apparatus is provided that includes a plurality of storage elements. Receiving circuitry receives a plurality of incoming data beats from cache circuitry and stores the incoming data beats in the storage elements. ... Arm Limited

09/06/18 / #20180253310

Vector load instruction

First and second types of vector load instruction are provided. For the first type, a response action is performed when an exceptional condition is detected for a load operation performed for a first active data element of at least one vector register, but when the exceptional condition is detected for an active data element other than the first active data element, the response action is suppressed and element identifying information is stored identifying the element which caused the exceptional condition. ... Arm Limited

09/06/18 / #20180253309

Vector data transfer instruction

A vector data transfer instruction is provided for triggering a data transfer between storage locations corresponding to a contiguous block of addresses and multiple data elements of at least one vector register. The instruction specifies a start address of the contiguous block using a base register and an immediate offset value specifies as a multiple of the size of the contiguous block of addresses. ... Arm Limited

09/06/18 / #20180253299

Defer buffer

An apparatus comprises processing circuitry for executing instructions of two or more threads of processing, hardware registers to store context data for the two or more threads concurrently, and commit circuitry to commit results of executed instructions of the threads, where for each thread the commit circuitry commits the instructions of that thread in program order. At least one defer buffer is provided to buffer at least one blocked instruction for which execution by the processing circuitry is complete but execution of an earlier instruction of the same thread in the program order is incomplete. ... Arm Limited

08/23/18 / #20180239992

Processing artificial neural network weights

A data processing apparatus processes a set of weight values for an artificial neural network by representing the set of weight values in the form of an array of weight values and by using an image compression scheme to provide compressed weight data for the artificial neural network. The data processing apparatus uses an image decompression scheme to derive decompressed weight values from the compressed weight data and applies the decompressed weight values when producing a result from an input to the artificial neural network. ... Arm Limited

08/23/18 / #20180239714

Technique for efficient utilisation of an address translation cache

An apparatus and method are provided for making efficient use of address translation cache resources. The apparatus has an address translation cache having a plurality of entries, where each entry is used to store address translation data used when converting a virtual address into a corresponding physical address of a memory system. ... Arm Limited

08/23/18 / #20180239607

Exception handling

A data processing system (2) includes exception handling circuitry (26) to detect attempted execution of an exception-triggering processing operation which includes transfer of a data value with a given register of a register bank (20). Upon detection of such an exception-triggering processing operation, syndrome data is stored within a syndrome register (32) characterising the exception-triggering processing operation with that syndrome data including the data value. ... Arm Limited

08/16/18 / #20180233194

Storage bitcell

A storage bitcell comprising a first inverter cross-coupled with a second inverter, both the first and second inverter being in a path between a first potential and a second potential; wherein a first isolator is connected in the path between the first inverter and the first potential. The storage bitcell has particular application as static random-access memory (sram) circuitry.. ... Arm Limited

08/16/18 / #20180233193

Process variation detector

Various implementations described herein are directed to an integrated circuit having a memory cell array disposed in a first area of the integrated circuit. The memory cell array may include memory cells with first transistors of multiple types. ... Arm Limited

08/16/18 / #20180232935

Graphics processing

A graphics processing system groups plural initial pilot shader programs into a set of initial pilot shader programs and associates the set of initial pilot shader programs with a set of indexes. The initial pilot shader programs each contain constant program expressions to be executed on behalf of an original shader program. ... Arm Limited

08/16/18 / #20180232313

Cache sector usage prediction

A system cache and method of operating a system cache are provided. The system cache provides data caching in response to data access requests from plural system components. ... Arm Limited

08/16/18 / #20180232168

Parameter storage management

An apparatus for processing data 2 contains multiple power domains which may be in a non-retaining power state or a retaining power state. If a power domain is in a non-retaining power state in which it is not able to retain a copy of a stored parameter value and it is switched into a retaining power state in which it requires a copy of that parameter value, then it fetches the parameter value from a store within another power domain. ... Arm Limited

08/16/18 / #20180232148

Data processing systems

Operating a data processing system including producing data in the form of plural blocks of data, where each block of data represents a particular region of an output data array, storing the data in a memory of the data processing system, and reading the data from the memory in the form of lines. Storing the data in the memory comprises storing each block of data of a first row of blocks of data in the memory at one or more memory addresses of a first set of memory addresses of a sequence of memory addresses for the memory, and storing each block of data of a second row of blocks of data in the memory at one or more memory addresses of a second set of different memory addresses of the sequence of memory addresses for the memory.. ... Arm Limited

08/09/18 / #20180227382

Forwarding responses to snoop requests

A data processing apparatus is provided, which includes receiving circuitry to receive a snoop request in respect of requested data on behalf of a requesting node. The snoop request includes an indication as to whether forwarding is to occur. ... Arm Limited

08/09/18 / #20180225232

Data processing

A memory controller comprises memory access circuitry configured to initiate a data access of data stored in a memory in response to a data access hint message received from another node in data communication with the memory controller; to access data stored in the memory in response to a data access request received from another node in data communication with the memory controller and to provide the accessed data as a data access response to the data access request.. . ... Arm Limited

08/09/18 / #20180225219

Cache bypass

A data processing apparatus is provided including a memory hierarchy having a plurality of cache levels including a forwarding cache level, at least one bypassed cache level, and a receiver cache level. The forwarding cache level forwards a data access request relating to a given data value to the receiver cache level, inhibiting the at least one bypassed cache level from responding to the data access request. ... Arm Limited

08/09/18 / #20180225216

Data processing

Data processing apparatus comprises a data access requesting node; data access circuitry to receive a data access request from the data access requesting node and to route the data access request for fulfilment by one or more data storage nodes selected from a group of two or more data storage nodes; and indication circuitry to provide a source indication to the data access requesting node, to indicate an attribute of the one or more data storage nodes which fulfilled the data access request; the data access requesting node being configured to vary its operation in response to the source indication.. . ... Arm Limited

08/09/18 / #20180225214

Cache content management

Apparatus and a corresponding method of operating a hub device, and a target device, in a coherent interconnect system are presented. A cache pre-population request of a set of coherency protocol transactions in the system is received from a requesting master device specifying at least one data item and the hub device responds by cause a cache pre-population trigger of the set of coherency protocol transactions specifying the at least one data item to be transmitted to a target device. ... Arm Limited

08/09/18 / #20180225210

Responding to snoop requests

A data processing apparatus includes receiving circuitry to receive a snoop request sent by a source node in respect of requested data and transmitting circuitry. Cache circuitry caches at least one data value. ... Arm Limited

08/09/18 / #20180225209

Read-with overridable-invalidate transaction

A system comprises a number of master devices and an interconnect for managing coherency between the master devices. In response to a read-with-overridable-invalidate transaction received by the interconnect from a requesting master device requesting that target data associated with a target address is provided to the requesting master device, when target data associated with the target address is stored by a cache, the interconnect issues a snoop request to said cache triggering invalidation of the target data from the cache except when the interconnect or cache determines to override the invalidation and retain the target data in the cache. ... Arm Limited

08/09/18 / #20180225206

Read transaction tracker lifetimes in a coherent interconnect system

Apparatus and a corresponding method of operating the apparatus, in a coherent interconnect system comprising a requesting master device and a data-storing slave device, are provided. The apparatus maintains records of coherency protocol transactions received from the requesting master device whilst completion of the coherency protocol transactions are pending and is responsive to reception of a read transaction from the requesting master device for a data item stored in the data-storing slave device to issue a direct memory transfer request to the data-storing slave device. ... Arm Limited

08/09/18 / #20180225168

Responding to unresponsive processing circuitry

A data processing apparatus is provided comprising first processing circuitry. Interrupt generating circuitry generates an outgoing interrupt in response to the first processing circuitry becoming unresponsive. ... Arm Limited

08/09/18 / #20180225120

An apparatus and method for controlling instruction execution behaviour

An apparatus and method are provided for controlling instruction execution behaviour. The apparatus includes a set of data registers for storing data values, and a set of bounded pointer storage elements, where each bounded pointer storage element stores a pointer having associated range information indicative of an allowable range of addresses when using that pointer. ... Arm Limited

08/09/18 / #20180225047

Compare-and-swap transaction

A compare and swap transaction can be issued by a master device to request a processing unit to select whether to write a swap data value to a storage location corresponding to a target address in dependence on whether a compare data value matches a target data value read from the storage location. The compare and swap data values are transported within a data field of the compare and swap transaction. ... Arm Limited

08/02/18 / #20180219647

Adaptive wait in data communications

A machine-implemented method for controlling retry of unicast data packet transmission from a transmitter node to a receiver node comprises selecting a receiver node from a set of receiver nodes having different processing delays; transmitting a first unicast data packet to the receiver node; establishing a delay, at the transmitter node, for an expected acknowledgement wait duration; receiving, at the transmitter node, an acknowledgement packet from the receiver node; responsive to an actual acknowledgement wait duration being less than the expected duration, setting the expected duration to a new expected duration comprising at least the actual wait duration; transmitting a second unicast data packet to the receiver node; establishing a delay, at the transmitter node, for the new expected duration; and responsive to expiry of the new expected duration without receipt of an acknowledgement packet from the receiver node, retrying transmitting the second unicast data packet.. . ... Arm Limited

08/02/18 / #20180219549

Digital forward body biasing in cmos circuits

Embodiments are described for digital forward body biasing cmos circuits. In an embodiment, a power management unit limits the amount of time for which digital forward body biasing may be implemented. ... Arm Limited

08/02/18 / #20180218108

Sleep signal stitching technique

Various implementations described herein are directed to an apparatus having a receiver module that receives a floorplan of an integrated circuit having power gates, an obstruction, and a control pin for providing a sleep signal. The apparatus may include an identifier module that identifies where the obstruction interrupts a sequence of the power gates, organizes the sequence of the power gates into a column, and divides the column into segments in which a first segment lies below the obstruction, a second segment lies above the obstruction, and a third segment is offset from the first and second segments. ... Arm Limited

08/02/18 / #20180218107

Power grid healing techniques

Various implementations described herein are directed to an apparatus. The apparatus may include a region identifier module that receives a floorplan of an integrated circuit, identifies a standard cell region between already placed functional blocks of the floorplan, and sub-divides the standard cell region into multiple sub-regions. ... Arm Limited

08/02/18 / #20180218106

Power grid insertion technique

Various implementations described herein are directed to an apparatus. The apparatus may include a region identifier module that receives user defined parameters for modifying a power grid layout and identifies a region of the power grid layout for strap insertion based on the user defined parameters. ... Arm Limited

08/02/18 / #20180217934

Data processing systems

When a data processing operation requires data that is stored in a first cache and the fetching of the data into the first cache is dependent upon data stored in another cache, and an attempt to read the data from the first cache “misses”, the data processing operation is added to a record of data processing operations that have missed in the first cache and the data that is required for the data processing operation is fetched into the first cache by reading the data that is required to fetch the data into the first cache from the another cache and then using that data from the another cache to fetch the required data into the first cache. When the data that is required for the data processing operation has been fetched into the first cache, the data processing operation is performed using the fetched data.. ... Arm Limited

08/02/18 / #20180217932

Data processing apparatus with snoop request address alignment and snoop response time alignment

A home node of a data processing apparatus that includes a number of devices coupled via an interconnect system is configured to provide efficient transfer of data to a first device from a second device. The home node is configured dependent upon data bus widths of the first and second devices and the data bus width of the interconnect system. ... Arm Limited

08/02/18 / #20180217840

An apparatus and method for transferring a plurality of data structures between memory and one or more vectors of data elements stored in a register bank

An apparatus and method are provided for transferring a plurality of data structures from memory into one or more vectors of data elements stored in a register bank. The apparatus has first interface circuitry to receive data structures retrieved from memory, where each data structure has an associated identifier and comprises n data elements. ... Arm Limited

08/02/18 / #20180217815

Apparatus and method for processing input operand values

An apparatus and method are provided for processing input operand values. The apparatus has a set of vector data storage elements, each vector data storage element providing a plurality of sections for storing data values. ... Arm Limited

08/02/18 / #20180217648

No-operation power state command

A system comprises a first domain 4 and second domain 6 which communicate via an interface 8. The first domain 4 transmits power state commands to the second domain 6 for controlling transitions of power states at the second domain 6. ... Arm Limited

07/26/18 / #20180213040

Enabling communications between devices

A method of establishing a communications path between devices comprising: receiving, at a first device, data, the data comprising: a first resource having a first identifier for a second device remote from the first device; a second resource having a second identifier for the second device; addressing the second device with the first identifier; generating, at the first device, first connection data based on the second identifier; transmitting, from the first device to the second device, the first connection data; receiving, at the first device, second connection data; validating, at the first device, the second connection data; establishing the communications path between the first device and second device responsive to valid second connection data.. . ... Arm Limited

07/26/18 / #20180212582

Electronic filter circuit

Many kinds of filters are found in electronic circuits and provide a range of signal processing applications. Such filters can be passive, active, analogue or digital and work across a range of frequencies. ... Arm Limited

07/26/18 / #20180211914

Power distribution

An apparatus, a method, and a method of manufacturing an integrated circuit having a metal layer, metal wires within the metal layer being configured such that they have a regular pattern.. . ... Arm Limited

07/26/18 / #20180211436

Data processing systems

A programmable execution unit (42) of a graphics processor includes a functional unit (50) that is operable to execute instructions (51). The output of the functional unit (50) can both be written to a register file (46) and fed back directly as an input to the functional unit by means of a feedback circuit (52). ... Arm Limited

07/26/18 / #20180210845

Information switching

An information switch comprises a plurality of input circuits and a plurality of output circuits, the information switch being configured to communicate information units between the input circuits and the output circuits in successive transmission cycles; each input circuit being configured, in dependence upon a queue of one or more information units for transmission via that input circuit and in dependence upon hint data received in respect of a current transmission cycle, to send an information unit transmission request to one or more of the output circuits; and each output circuit being configured, in response to one or more information unit transmission requests received from respective input circuits, to select an input circuit for information unit transmission to that output circuit in a current transmission cycle and to provide hint data indicating a provisional selection, by that output circuit, of an input circuit at a next transmission cycle.. . ... Arm Limited

07/26/18 / #20180210805

Apparatus and method for generating and processing a trace stream indicative of execution of predicated vector memory access instructions by processing circuitry

An apparatus and method are provided for generating and processing a trace stream indicative of execution of predicated vector memory access instructions by processing circuitry. An apparatus has an input interface to receive execution information from the processing circuitry indicative of operations performed by that processing circuitry when executing a sequence of instructions. ... Arm Limited

07/26/18 / #20180210733

An apparatus and method for performing a splice operation

An apparatus and a method are provided for performing a splice operation, the apparatus having a set of vector registers and one or more control registers. Processing circuitry is arranged to execute a sequence of instructions including a splice instruction that identifies at least a first vector register and at least one control register. ... Arm Limited

07/26/18 / #20180210731

Data processing

Data processing apparatus comprises processing circuitry to selectively apply a vector processing operation to data items at positions within data vectors according to the states of a set of respective predicate flags associated with the positions, the data vectors having a data vector processing order, each data vector comprising a plurality of data items having a data item order, the processing circuitry comprising: instruction decoder circuitry to decode program instructions; and instruction processing circuitry to execute instructions decoded by the instruction decoder circuitry; wherein the instruction decoder circuitry is responsive to a propagation instruction to control the instruction processing circuitry to derive a set of predicate flags applicable to a current data vector in dependence upon a set of predicate flags applicable to a preceding data vector in the data vector processing order, wherein when one or more last-most predicate flags of the set applicable to the preceding data vector are inactive, all of the derived predicate flags in the set applicable to the current data vector are inactive.. . ... Arm Limited

07/19/18 / #20180203807

Partitioning tlb or cache allocation

A request for data from a cache (tlb or data/instruction cache) specifies a partition identifier allocated to a software execution environment associated with the request. Allocation of data to the cache is controlled based on a set of configuration information selected based on the partition identifier specified by the request. ... Arm Limited

07/19/18 / #20180203802

Cache apparatus and a method of caching data

A cache apparatus is provided comprising a data storage structure providing n cache ways that each store data as a plurality of cache blocks. The data storage structure is organised as a plurality of sets, where each set comprises a cache block from each way, and further the data storage structure comprises a first data array and a second data array, where at least the second data array is set associative. ... Arm Limited

07/19/18 / #20180203798

Quality-of-service monitoring in a cache

A cache to provide data caching in response to data access requests from at least one system device, and a method operating such a cache, are provided. Allocation control circuitry of the cache is responsive to a cache miss to allocate an entry of the multiple entries in the data caching storage circuitry in dependence on a cache allocation policy. ... Arm Limited

07/19/18 / #20180203756

Contingent load suppression

A data processing system (2) supports non-speculative execution of vector load instructions that perform at least one contingent load of a data value. Fault detection circuitry (26) serves to detect whether a contingent load is fault-generating contingent load or a fault-free contingent load. ... Arm Limited

07/19/18 / #20180203723

Memory partitioning

An apparatus is provided comprising processing circuitry to perform data processing in response to instructions of one of a plurality of software execution environments. At least one memory system component handles memory transactions for accessing data, with each memory transaction specifying a partition identifier allocated to a software execution environment associated with the memory transaction. ... Arm Limited

07/19/18 / #20180203699

Vector operand bitsize control

A data processing system (2) includes processing circuitry (18) and decoder circuitry (14) for decoding program instructions and controlling the processor circuitry. The decoder circuitry is responsive to a vector operand bit size dependant instruction executed within a selected exception level state of a hierarchy of exception level states to control the processing circuitry to perform processing with a vector operand bit size governed by a limiting value of the vector operand bit size associated with the currently selected exception level state, any programmable limit value set for an exception level state closer to a top exception level state within the hierarchy and the implemented limit.. ... Arm Limited

07/19/18 / #20180203692

Vector arithmetic instruction

A data processing system (2) supports vector processing operations performed upon vector operands comprising a plurality of vector operand elements. The data processing system includes a processor (4) having an instruction decoder (14) which decodes mixed-element-sized vector arithmetic instructions to generate control signals (16) which control processing circuitry (18) to perform arithmetic operations upon a first vector of first source operand elements ai of a first bit size a, and a second vector of second source operand elements bj of a second bit size b. ... Arm Limited

07/19/18 / #20180203669

Digit recurrence division

A data processing apparatus is provided to perform a digit-recurrence division operation to determine a quotient as a result of dividing a dividend by a divisor. Scaling circuitry scales the dividend and the divisor by a factor to produce a scaled dividend and a scaled divisor. ... Arm Limited

07/19/18 / #20180203638

Partitioning of memory system resources or performance monitoring

An apparatus comprises partition identifier storage storing an instruction partition identifier and a data partition identifier. When issuing a memory transaction for accessing data, the transaction is issued specifying a partition identifier depending on the data partition identifier, while when the memory transaction is for accessing an instruction, the transaction specifies a partition identifier depending on the instruction partition identifier. ... Arm Limited

07/19/18 / #20180203610

Partitioning of memory system resources or performance monitoring

An apparatus comprises two or more partition identifier registers, each corresponding to a respective operating state of processing circuitry and specifying a partition identifier for that operating state. The processing circuitry issues a memory transaction specifying a partition identifier depending on the partition identifier stored in a partition identifier register selected based on the current operating state. ... Arm Limited

07/19/18 / #20180203609

Partitioning of memory system resources or performance monitoring

Memory transactions are issued to a memory system component specifying a partition identifier allocated to a software execution environment associated with said memory transaction. The memory system component selects one of a plurality of sets of memory system component parameters in dependence on the partition identifier specified by a memory transaction to be handled. ... Arm Limited

07/12/18 / #20180197326

Graphics processing system

When rendering a scene that includes a complex object made up of many individual primitives, rather than processing each primitive making up the object in turn, a bounding volume which surrounds the complex object is generated and the scene is then processed using the bounding volume in place of the actual primitives making up the complex object. If it is determined that the bounding volume representation of the object will be completely occluded in the scene (e.g. ... Arm Limited

07/12/18 / #20180197268

Graphics processing

A graphics processing apparatus performs an intermediate processing pass in which region lists that indicate geometry for respective regions of an intermediate projection surface are generated and stored. A subsequent processing pass is then performed in which a region of the intermediate projection surface is selected using a vector for a fragment, and geometry data for shading the fragment is obtained with reference to the region list that was stored for the selected region in the intermediate processing pass. ... Arm Limited

07/12/18 / #20180196746

Apparatus and method for executing instruction using range information associated with a pointer

An apparatus (2) comprises one or more bounded pointer storage element (60s) each to store a pointer (62) having associated range information (64) indicating an allowable range of addresses for the pointer (62). Processing circuitry (4) performs, in response to a first type of instruction (70) identifying a given bounded pointer storage element, a predetermined operation for a target range of addresses determined at least in part on the basis of the range information (64) associated with the pointer stored in the given bounded pointer storage element (60).. ... Arm Limited

07/12/18 / #20180196673

Vector length querying instruction

A data processing system 2 supporting vector processing operations uses scaling vector length querying instructions. The scaling vector length querying instructions return a result which is dependent upon a number of elements in a vector for a variable vector element size specified by the instruction and multiplied by a scaling value specified by the instruction. ... Arm Limited

07/05/18 / #20180189097

Data processing

Data processing apparatus comprises one or more transaction issuing devices configured to issue data processing transactions to be handled by a downstream device and to receive a completion acknowledgement in respect of each completed transaction; each transaction issuing device having associated transaction regulator circuitry configured to allow that transaction issuing device to issue transactions subject to a limit on a maximum number of outstanding transactions, an outstanding transaction being a transaction which has been issued but for which a completion acknowledgement has not yet been received; in which the downstream device is configured to issue an indication to a transaction issuing device, to authorise a change by the transaction regulator circuitry of the limit applicable to outstanding transactions by that transaction issuing device.. . ... Arm Limited

06/28/18 / #20180181478

Performing diagnostic operations upon a target apparatus

Diagnostic operations upon a target apparatus 2 having a target transaction master 8 which initiates memory transactions with one or more target transaction slaves 12, 14, 16 are provided by halting operation of the target transaction master 8 while permitting continued operation within the target apparatus 2 of at least some of the target transaction slaves 12, 14, 16. Opening state data representing an operating state of the target transaction master 8 is transferred to a model transaction master 32. ... Arm Limited

06/28/18 / #20180181347

Data processing apparatus and method for controlling vector memory accesses

An apparatus and method are provided for controlling vector memory accesses. The apparatus comprises a set of vector registers, and flag setting circuitry that is responsive to a determination that a vector generated for storage in one of the vector registers comprises a plurality of elements that meet specified contiguousness criteria, to generate flag information associated with that vector register. ... Arm Limited

06/21/18 / #20180176590

Video processing systems

A video processing system includes a host processor, a video encoder and a memory. The host processor sends a configuration message to the video encoder that indicates to the video encoder how to encode a video frame and that includes information indicating the location of encoding configuration data that is stored in the memory. ... Arm Limited

06/21/18 / #20180175615

Power clamp with correlated electron material device

A circuit is provided for limiting an applied voltage applied between a power line and an electrical ground. The circuit includes a transistive element connected between the power line and the electrical ground to provide a channel, where current flow through the channel is controlled by a control voltage provided to a control terminal of the transistive element. ... Arm Limited

06/21/18 / #20180173899

Logic encryption using on-chip memory cells

A protected circuit includes a logic circuit having one or more input nodes and one or more output nodes. The logic circuit has a network of logic elements and one or more logic encryption elements. ... Arm Limited

06/21/18 / #20180173834

Pin-based noise characterization for silicon compiler

A silicon compiler, such as a memory compiler, provides for pin-based noise characterization in a computationally efficient manner. For a given user-provided option set, a silicon compiler provides a noise database for the set of all available memory instances by performing pin-based noise characterization on only a subset of the set of available memory instances.. ... Arm Limited

06/21/18 / #20180173822

Corner database generator

Various implementations described herein are directed to a computing device. The computing device may include a mapper module that receives a user configuration input of a destination corner for building a destination corner database. ... Arm Limited

06/21/18 / #20180173660

Data processing

A data processing system comprises a master node to initiate data transmissions; one or more slave nodes to receive the data transmissions; and a home node to control coherency amongst data stored by the data processing system; in which at least one data transmission from the master node to one of the one or more slave nodes bypasses the home node.. . ... Arm Limited

06/21/18 / #20180173645

Secure initialisation

A data processing system for processing data using a memory having a plurality of memory regions, a given memory region within said plurality of memory regions having an associated owning process having exclusive rights to control access to said given memory region, said system comprising: a security controller to: receive a request to initialise a guest execution environment; claim one or more regions of memory to be owned by said security controller; store executable program code of said guest execution environment within said one or more regions of memory; and transfer ownership of said one or more regions to said guest execution environment.. . ... Arm Limited

06/21/18 / #20180173641

Address translation

A data processing apparatus (20) comprises address translation circuitry (40) to translate a first address into a physical address directly identifying a corresponding location in a data store, and a table (50) comprising one or more entries indexed by the physical address, wherein at least one of the entries specifies the first address from which the corresponding physical address was translated by the address translation circuitry (40).. . ... Arm Limited

06/21/18 / #20180173546

System and method for translating a guest instruction of a guest architecture into at least one host instruction of a host architecture

A system and method are provided for translating a guest instruction of a guest architecture into at least one host instruction of a host architecture. The method comprises providing multiple representation states, each representation state providing a representation in the host architecture for at least one item of state from the guest architecture. ... Arm Limited

06/21/18 / #20180173535

Determining a predicted behaviour for processing of instructions

An apparatus comprises prediction circuitry (40, 100, 80) for determining, based on current prediction policy information (43, 82, 104), a predicted behaviour to be used for processing instructions. The current prediction policy information is updated based on an outcome of processing of instructions. ... Arm Limited

06/21/18 / #20180173498

Arithmetic operation input-output equality detection

Apparatus and corresponding methods are disclosed relating to circuitry to perform an arithmetic operation on one or more input operands, where the circuitry is responsive to an equivalence of a result value of the arithmetic operation with at least one of the one or more input operands, when the one or more input operands are not an identity element for the arithmetic operation, to generate a signal indicative of the equivalence. Idempotency (between at least one input operand and the result value) is thus identified.. ... Arm Limited

06/21/18 / #20180173497

An apparatus and method for processing floating point values

An apparatus and method are provided for processing floating point values using an intermediate representation which has significand, exponent and shadow sections. A less significant portion of the exponent of the floating point value defines a range of positions within the significand section where the representation of the significand is to be held. ... Arm Limited

06/21/18 / #20180173271

Clock signal distribution and signal value storage

An integrated circuit includes multiple blocks of circuitry (4, 6, 8) communicating signals via an interface 10 controlled by a clock signal. A clock mesh (20, 22) is used on at least one side of the interface driven by one or more clock drivers (24, 26) that drive the clock mesh with the clock signal communicated with a further block of circuitry. ... Arm Limited

06/21/18 / #20180172764

Method, system and apparatus for tuning an integrated embedded subsystem

A method, apparatus and system are provided for the tuning of embedded subsystems of a device under test (dut) that have analog characteristics. In response to a tester invoking one or more test procedures via a command channel between the tester and a target embedded subsystem of the dut, test firmware of the invoked tests is loaded into the target embedded subsystem. ... Arm Limited

06/14/18 / #20180165962

Method of detecting and providing parking space information and/or road obstacle information to vehicles

Vehicles which are provided with at least one sensor and a location system, such as a global positioning system (gps) detect parking spaces and/or road obstacles when driving along a road. The detected parking space and/or road obstacle data is transferred to a remote processing module. ... Arm Limited

06/14/18 / #20180165218

Memory management

Apparatus comprises input circuitry to receive a translation request defining an input memory address within an input memory address space; and address translation circuitry comprising: permission circuitry to detect whether memory access is permitted for the input memory address with reference to permission data populated from address translation tables and stored in a permission data store for each of a set of respective regions of the input memory address space, there being a dedicated entry in the permission data store for each of the regions so that the input memory address maps to a single respective entry; and output circuitry to provide an output memory address in response to the translation request, in which when the permission circuitry indicates that access is permitted to a region of the input memory address space including the input memory address, the output circuitry is configured to provide the output memory address as a predetermined function of the input memory address.. . ... Arm Limited

06/14/18 / #20180165064

Partial square root calculation

A data processing apparatus is provided, to calculate an at least partial square root of a floating point number having an exponent and significand. Recurrence circuitry performs one or more iterations of an iterative square root operation, each of the one or more iterations receiving an input at least partial square root and an input remainder to produce the at least partial square root and a remainder of performing the iterative square root operation. ... Arm Limited

06/14/18 / #20180164375

Adapting the usage configuration of integrated circuit input-output pads

Techniques for implementing a self-test procedure of an integrated circuit are provided, where the self-test procedure comprises testing for an electrical connection between first and second input-output pads of the integrated circuit. A control device is capable of adapting a functional configuration of usage of the first and second input-output pads in dependence on presence of the electrical connection. ... Arm Limited

06/07/18 / #20180157601

Apparatus and method for avoiding conflicting entries in a storage structure

An apparatus and method are provided for avoiding conflicting entries in a storage structure. The apparatus comprises a storage structure having a plurality of entries for storing data, and allocation circuitry, responsive to a trigger event for allocating new data into the storage structure, to determine a victim entry into which the new data is to be stored, and to allocate the new data into the victim entry upon determining that the new data is available. ... Arm Limited

06/07/18 / #20180157590

Filtering coherency protocol transactions

A filter unit comprises interface circuitry, to intercept coherency protocol transactions exchanged between a master device comprising a first cache and an interconnect for managing coherency between the first cache and at least one other cache or other master device. The filter unit has filtering circuitry for filtering the coherency protocol transactions in dependence on memory access permission data defining which regions of an address space the master device is allowed to access.. ... Arm Limited

06/07/18 / #20180157490

Variable-length-instruction processing modes

A data processing apparatus (2) operates in a first mode of operation having a first set of processing circuitry (8, 12, 18, 20, 22) ready to perform processing operations and in a second mode of operation having a second set of processing circuitry (8, 12, 14, 18, 20, 22, 24) ready to perform processing operations. A first proper subset (32) of program instructions within the instruction set supported are processed by the processor using a selectable one of the first mode and the second mode. ... Arm Limited

06/07/18 / #20180157464

Apparatus and method for performing arithmetic operations to accumulate floating-point numbers

An apparatus and method are provided for performing arithmetic operations to accumulate floating-point numbers. The apparatus comprises execution circuitry to perform arithmetic operations, and decoder circuitry to decode a sequence of instructions in order to generate control signals to control the arithmetic operations performed by the execution circuitry. ... Arm Limited

06/07/18 / #20180157463

Leading zero anticipation

A data processing apparatus is provided. Intermediate value generation circuitry generates an intermediate value from a first floating point number and a second floating point number. ... Arm Limited

06/07/18 / #20180157437

Apparatus and method for transferring data between address ranges in memory

An apparatus and method are provided for transferring data between address ranges in memory. The apparatus comprises a data transfer controller, that is responsive to a data transfer request received by the apparatus from a processing element, to perform a transfer operation to transfer data from at least one source address range in memory to at least one destination address range in the memory. ... Arm Limited

06/07/18 / #20180156866

Scan cell for dual port memory applications

Various implementations described herein are directed to a scan cell. The scan cell may include an input phase having multiple multiplexers and a latch arranged to receive a scan input signal, a first address signal, and a second address signal and provide the scan input signal, the first address signal, or the second address signal based on a scan enable signal, a first clock signal, and a selection enable signal. ... Arm Limited

05/31/18 / #20180152252

Communications device and method

A device comprises a coupling configured to couple signals to and from a communications path including at least a part of a human or animal body; a data transmitter coupled to the coupling and configured to transmit, from time to time, a data signal of at least a predetermined temporal duration via the communications path; and a data receiver coupled to the coupling and configured to detect the presence of a signal on the communications path at sets of one or more successive detection instances disposed between successive transmissions of the data signal by the data transmitter, the data receiver being configured so that the successive detection instances of a set are temporally separated by no more than the predetermined temporal duration; the device being configured to initiate a processing operation in response to a detection by the data receiver of the presence of a signal on the communications path.. . ... Arm Limited

05/31/18 / #20180151800

Cem switching device

Subject matter herein disclosed relates to an improved cem switching device and methods for its manufacture. In this device, a conductive substrate and/or conductive overlay comprises a primary layer of a conductive material and a secondary layer of a conductive material. ... Arm Limited

05/31/18 / #20180150413

Protected exception handling

A data processing system for processing data comprising: ownership circuitry to enforce ownership rights of memory regions, a given more privileged state memory region having a given owning process specified from among a plurality of processes, said given owning process having exclusive rights to control access to said given memory region; and context switching circuitry responsive to receipt of an interrupt to trigger a context switch from a first active process to a second active process whereby one or more items of state for use in restarting said first process is saved to one or more context data memory regions owned by said first process and one or more items of state accessible to said second process and dependent upon processing by said first process is overwritten prior to commencing execution of said second process.. . ... Arm Limited

05/31/18 / #20180150389

Method and apparatus for memory wear leveling

A method and apparatus is provided for wear leveling of a storage medium in an electronic device. Wear leveling is achieved by mapping each logical memory address to a corresponding physical memory address. ... Arm Limited

05/31/18 / #20180150322

Data processing

Data processing apparatus comprises one or more interconnected processing elements each configured to execute processing instructions of a program task; coherent memory circuitry storing one or more copies of data accessible by each of the processing elements, so that data written to a memory address in the coherent memory circuitry by one processing element is consistent with data read from that memory address in the coherent memory circuitry by another of the processing elements; the coherent memory circuitry comprising a memory region to store data, accessible by the processing elements, defining one or more attributes of a program task and context data associated with a most recent instance of execution of that program task; the apparatus comprising scheduling circuitry to schedule execution of a task by a processing element in response to the one or more attributes defined by data stored in the memory region corresponding to that task; and each processing element which executes a program task is configured to modify one or more of the attributes corresponding to that program task in response to execution of that program task.. . ... Arm Limited

05/31/18 / #20180150321

Data processing

Data processing apparatus comprises a group of two or more processing elements configured to execute processing instructions of a program task; the processing elements being configured to provide context data relating to a program task following execution of that program task by that processing element; and to receive context data, provided by that processing element or another processing element, at resumption of execution of a program task; in which a next processing element of the group to execute a program task is configured to receive a first subset of the context data from a previous processing element to execute that program task and to start to execute the program task using the first subset of the context data; and in which the next processing element is configured to receive one or more items of a second, remaining, subset of the context data during execution of the program task by that processing element.. . ... Arm Limited

05/31/18 / #20180150315

Data processing

Data processing apparatus comprises one or more interconnected processing elements; each processing element being configured to execute processing instructions of program tasks; each processing element being configured to save context data relating to a program task following execution of that program task by that processing element; and to load context data, previously saved by that processing element or another of the processing elements, at resumption of execution of a program task; each processing element having respective associated format definition data to define one or more sets of data items for inclusion in the context data; the apparatus comprising format selection circuitry to communicate the format definition data of each of the processing elements with others of the processing elements and to determine, in response to the format definition data for each of the processing elements, a common set of data items for inclusion in the context data.. . ... Arm Limited

05/31/18 / #20180150297

Processing pipeline with first and second processing modes having different performance or energy consumption characteristics

An apparatus (2) has a processing pipeline (4) supporting at least a first processing mode and a second processing mode with different energy consumption or performance characteristics. A storage structure (22, 30, 36, 50, 40, 64, 44) is accessible in both the first and second processing modes. ... Arm Limited

05/31/18 / #20180150251

Shared pages

A data processing system comprising: ownership circuitry to enforce ownership rights of memory regions within a physical memory address space, a given memory region having a given owning process specified from among a plurality of processes and independently of privilege level, said given owning process having exclusive rights to control access to said given memory region, wherein said given owning process designates said given memory region as one of: private to said given owning process; and shared between said given owning process and at least one further source of memory access requests.. . ... Arm Limited

05/31/18 / #20180150243

Data movement engine

A memory system of a data processing system includes one or more storage devices and a data rearrangement engine for moving data between memory regions of the plurality of memory regions. The data rearrangement engine is configured to rearrange data stored at non-contiguous addresses in a source memory region into contiguous address in a destination region responsive to a rearrangement specified by a host processing unit of the data processing system. ... Arm Limited

05/31/18 / #20180150120

Monitoring circuit and method

Broadly speaking, embodiments of the present techniques provide a voltage monitoring circuit for low power minimum-energy sensor nodes. The circuit comprises sensing circuitry to sense a monitored signal having a plurality of operating signal states; a first comparator having a first input for receiving an upper threshold signal; and a second comparator having a first input for receiving a lower threshold signal, the upper and lower threshold signals defining a range which includes at least one signal state of the plurality of operating states of the monitored signal, wherein the first and second comparators have a bias input for receiving a bias configuration setting, the bias configuration setting being selectable according to an operating signal state of the monitored signal.. ... Arm Limited

05/24/18 / #20180146158

De-interlacing data arrays in data processing systems

A data processing system includes a scaler 18 operable to scale a received input data array to provide a scaled output version of the input data array. When it is desired to produce a de-interlaced and scaled output version of an input data array 21, 22, the input data array 21, 22 is provided to the scaler 18, and the scaler 18 scales the input data array 21, 22 so as to simultaneously de-interlace and scale the input data array and to produce a de-interlaced and scaled output version of the input data array.. ... Arm Limited

05/24/18 / #20180144780

Tracking wordline behavior

Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a memory bank having an array of memory cells that are accessible via a selected wordline and a pair of complementary bitlines. ... Arm Limited

05/24/18 / #20180144437

Graphics processing systems

In a graphics processing system, an application executing on a host processor can request graphics processing operations that are to be performed by only subsets of the set of stages of a graphics processing pipeline implemented by a graphics processor. In response to such a request, the driver for the graphics processor causes the graphics processing operation that is to be performed using only a subset of the set of stages of the graphics processing pipeline to be performed. ... Arm Limited

05/24/18 / #20180143831

Check instruction for verifying correct code execution context

A data processing apparatus and method of data processing are provided which make use of a processor state check instruction to determine if the data processing apparatus is currently operating in a processor state, defined by at least one runtime processor state configuration value, which matches a processor state check value defined by the processor state check instruction. Dependent on the required runtime processor state configuration value(s) matching the processor state check value, the processor state check instruction is treated as an ineffective instruction. ... Arm Limited

05/24/18 / #20180143771

Managing persistent storage writes in electronic systems

The apparatus operable to communicate with a memory comprises a persistent write tracker component operable to track frequency of persistent writes to at least one memory location during a time window; a threshold-exceeded detector component responsive to the tracker component and operable to detect excessive persistent writes to the at least one memory location during the time window; and a selective throttle component operable in response to a threshold-exceeded outcome from the detector component to cause selective throttling of persistent writes to the at least one memory location.. . ... Arm Limited

05/24/18 / #20180143679

Multiple heterogeneous energy stores

There is provided an apparatus comprising a requirement determination unit to determine an energy requirement for a system component. A status determination unit determines status information relating to a plurality of heterogeneous energy stores and actuating system control unit controls an activity of the system component in dependence on the status information relating to the plurality of heterogeneous energy stores and the energy requirement.. ... Arm Limited

05/17/18 / #20180138900

Transition detection circuitry and method of detecting a transition of a signal occurring within a timing window

A transition detection circuit (20) and method of operation of such a circuit are provided, the transition detection circuit (20) having pulse generation circuitry (25) to receive an input signal (10) and to generate a pulse signal in response to a transition in the input signal, and pulse detection circuitry (30) to assert an error signal on detection of the pulse signal generated by the pulse generation circuitry. The pulse generation circuitry has pulse control circuitry (35) to control a property of the pulse signal dependent on a timing window indication signal (40). ... Arm Limited

05/17/18 / #20180136984

Apparatus and methods for load balancing across a network of nodes

A system provided at nodes within a network of nodes enabling the nodes to migrate activities to other nodes within its communication range to provide load balancing across the network. The other nodes having power and processing capabilities and capacity enabling them to undertake the migrated activities.. ... Arm Limited

05/10/18 / #20180129611

Data processing apparatus and method with ownership table

A data processing apparatus (20) comprises processing circuitry (24, 25, 28) to execute a plurality of processes. An ownership table (50) comprises one or more entries (52) each indicating, for a corresponding block of physical addresses, which of the processes is an owner process that has exclusive control of access to the corresponding block of physical addresses.. ... Arm Limited

05/10/18 / #20180129573

Error detection

An apparatus 2 comprises at least three processing circuits 4 to perform redundant processing of a common thread of program instructions. Error detection circuitry 16 is provided comprising a number of comparators 22 for detecting a mismatch between signals on corresponding signal nodes 20 in the processing circuits 4. ... Arm Limited

05/10/18 / #20180129499

Data processing systems

A program is analysed to identify instructions that will load external data and to determine whether such instructions are followed by a sequence of instructions that will produce the same result for each thread in a thread group if the data loaded by the load instruction is the same for each thread in the thread group. Each time there is an external load instruction, it is determined whether the data loaded by the external load instruction is the same for all threads of the thread group, and whether the external load instruction was indicated as being followed by a sequence of instructions that produce the same result if the external load instruction loads the same data value for each thread of a thread group. ... Arm Limited

05/10/18 / #20180129437

Computer architecture

A tagged memory organized is into memory chunks. Each memory chunk has a data field, a type field and an owner address field. ... Arm Limited

05/10/18 / #20180129419

Updating data stored in a memory

A process of updating data for a block of an array of data elements stored in an allocated memory region for the block comprises reading in data for a first group of the data elements, updating the data for the first group, and then writing back the updated data to memory. The process can avoid overwriting data for a second group of the data elements that is yet to be read in from the memory region by writing back the updated data for the first group starting at a selected memory address, for example other than the start address of the memory region. ... Arm Limited

05/03/18 / #20180121203

Shortcut path for a branch target buffer

An apparatus comprises a branch target buffer (btb) to store predicted target addresses of branch instructions. In response to a fetch block address identifying a fetch block comprising two or more program instructions, the btb performs a lookup to identify whether it stores one or more predicted target addresses for one or more branch instructions in the fetch block. ... Arm Limited

05/03/18 / #20180120926

Controlling transitions of devices between normal state and quiescent state

A data processing apparatus has a number of devices having a normal state and a quiescent state in which the device is ready for being placed in a power saving state. Each device provides at least one preference indication indicative of a preference to operate in the normal state or the quiescent state. ... Arm Limited

04/19/18 / #20180108167

Graphics processing systems

A graphics processing pipeline (30) includes a programmable fragment shader (40) that is operable to, in response to a “test” instruction included in a fragment shader program that it is executing, trigger, if appropriate, the performance of an alpha-to-coverage operation (41), a late stencil test (42), and a late depth test (43) for a fragment being processed, and to then return updated coverage information to the fragment shader (40). This allows alpha-to-coverage and late stencil and depth test operations to be triggered and performed during shader execution, rather than having to wait until shader execution has been completed before performing those operations.. ... Arm Limited

04/19/18 / #20180107606

Eviction control for an address translation cache

A data processing system 2 includes an address translation cache 12 to store a plurality of address translation entries. Eviction control circuitry 10 selects a victim entry for eviction from address translation cache 12 using an eviction control parameter. ... Arm Limited

04/19/18 / #20180107604

Apparatus and method for maintaining address translation data within an address translation cache

An apparatus and method are provided for maintaining address translation data within an address translation cache. The address translation cache has a plurality of entries, where each entry is used to store address translation data used when converting a virtual address into a corresponding physical address of a memory system. ... Arm Limited

04/12/18 / #20180101928

Display controllers

In a display controller of a data processing system, when composing two or more input surfaces to generate a composited surface comprising the two or more input surfaces, data indicating a border between different input surfaces in the composited surface is associated with the composited surface. The data indicative of the border between two input surfaces in the composited surface is then used to control subsequent processing, such as compression and/or filtering, of the composited surface.. ... Arm Limited

04/12/18 / #20180101489

Controlling transitions of devices between normal state and quiescent state

A data processing apparatus (2) has a number of devices (4) having a normal state and a quiescent state. Transition sequencing circuitry (70) controls a sequential state transition process for transitioning each of the devices (4) in turn between the normal state and the quiescent state. ... Arm Limited

04/12/18 / #20180101480

Apparatus and method for maintaining address translation data within an address translation cache

An apparatus and method are provided for maintaining address translation data within an address translation cache. Each entry of the address translation cache is arranged to store address translation data used when converting a virtual address into a corresponding physical address of a memory system. ... Arm Limited

04/05/18 / #20180098078

Selecting encoding options

A set of encoding options to use when encoding an array of data elements is selected based on a bit count value and a distortion value for that set of encoding options. The distortion value is determined from a set of error values that represents the difference between a set of frequency domain coefficients and a set of de-quantised coefficients. ... Arm Limited

04/05/18 / #20180096715

Integrated circuit using shaping and timing circuitries

Various implementations described herein may refer to and may be directed to an integrated circuit using shaping and timing circuitries. In one implementation, an integrated circuit may include memory that is accessed based on a voltage level on a first control line, and may include a control driver circuitry coupled to the first and a second control line that drives a first and a second control signal toward first or second voltage levels. ... Arm Limited

04/05/18 / #20180095893

Queuing memory access requests

A data processing apparatus is provided including queue circuitry to respond to control signals each associated with a memory access instruction, and to queue a plurality of requests for data, each associated with a reference to a storage location. Resolution circuitry acquires a request for data, and issues the request for data, the resolution circuitry having a resolution circuitry limit. ... Arm Limited

04/05/18 / #20180095752

Instruction predecoding

An apparatus comprises processing circuitry, an instruction cache, decoding circuitry to decode program instructions fetched from the cache to generate macro-operations to be processed by the processing circuitry, and predecoding circuitry to perform a predecoding operation on a block of program instructions fetched from a data store to generate predecode information to be stored to the cache with the block of instructions. In one example the predecoding operation comprises generating information on how many macro-operations are to generated by the decoding circuitry for a group of one or more program instructions. ... Arm Limited

04/05/18 / #20180095677

Display controllers

In a display controller, output surface data from a composition processing stage 22 is received by and stored in a local latency hiding buffer 40 of a memory write subsystem 31 before being written out to an external memory. The local buffer 40 of the memory write subsystem 31 signals when it is “full”, and in response thereto the inputting of output surface data to the local buffer 40 is stopped until the current line of the output surface has been finished, and then started again when the next line of the output surface begins. ... Arm Limited

03/29/18 / #20180091818

Methods of and apparatus for encoding data arrays

To perform motion estimation for a video frame block to be encoded, a difference measure is determined for each of a plurality of reference frame block positions at a first, coarser resolution. The determined difference measures are then used estimate difference measures for reference frame blocks at positions at a second resolution that is finer than the first resolution. ... Arm Limited

03/29/18 / #20180091407

Error detection in communication networks

Broadly speaking, embodiments of the present techniques provide apparatus and methods to identify and correct communication errors in a network formed of a plurality of nodes. In particular, the apparatus and methods identify synchronisation errors in a network which result in delayed propagation of messages through the network.. ... Arm Limited

03/29/18 / #20180089079

Apparatus, memory controller, memory module and method for controlling data transfer

An apparatus, memory controller, memory module and method are provided for controlling data transfer in memory. The apparatus comprises a memory controller and a plurality of memory modules. ... Arm Limited

03/29/18 / #20180088951

Instruction issue according to in-order or out-of-order execution modes

Apparatus for processing data (2) includes issue circuitry (22) for issuing program instructions (processing operations) to execute either within real time execution circuitry (32) or non real time execution circuitry (24, 26, 28, 30). Registers within a register file (18) are marked as non real time dependent registers if they are allocated to store a data value which is to be written by an uncompleted program instruction issued to the non real time execution circuitry and not yet completed. ... Arm Limited

03/22/18 / #20180083631

Receiver circuitry and method for converting an input signal from a source voltage domain into an output signal for a destination voltage domain

The present invention provides a receiver circuit and method for receiving an input signal from a source voltage domain and converting the input signal into an output signal for a destination voltage domain. The source voltage domain operates from a supply voltage that exceeds a stressing threshold of components within the receiver circuitry, and the receiver circuitry is configured to operate from the supply voltage of the source voltage domain. ... Arm Limited

03/22/18 / #20180081624

Data item order restoration

An apparatus and a corresponding method for processing a sequence of received data items are disclosed. The processing is performed by multiple processing elements. ... Arm Limited

03/15/18 / #20180076388

Cem switching device

Subject matter herein disclosed relates to a method for the manufacture of a cem switching device providing that the cem layer comprises a doped metal compound substantially free from metal wherein ions of the same metal element are present in different oxidation states. The method may provide a cem layer which is born on and capable of switching with operating voltages below 2.0v.. ... Arm Limited

03/15/18 / #20180076386

Cem switching device

Subject matter herein disclosed relates to a method for the manufacture of a switching device comprising a silicon-containing correlated electron material. In embodiments, processes are described for forming the silicon-containing correlated electron material. ... Arm Limited

03/15/18 / #20180074954

Comparator and memory region detection circuitry and methods

Comparator circuitry comprises carry-save-addition (csa) circuitry to generate a set of partial sum bits and a set of carry bits in respect of corresponding bit positions in a first input value, a second input value, a carry-in value associated with the first and second input values, and a third input value, the csa circuitry comprising inverter circuitry to provide a relative inversion between the third input value and the group consisting of the first and second input values; and combiner circuitry to combine the set of partial sum bits, the set of carry bits offset by a predetermined number of bits in a more significant bit direction, the carry-in value and 1, to generate at least a carry output bit; in which the carry output bit is indicative of whether the third input value is greater than the sum of the first and second input values.. . ... Arm Limited

03/15/18 / #20180074933

Management of log data in electronic systems

The disclosed method comprises receiving operating environment data, such as resource availability data, from connected computing devices and services, analysing the data to create one or more policies governing log data storage and upload parameters, and sending the policies to the connected devices to enable them to limit resource consumption in the management of log data.. . ... Arm Limited

03/15/18 / #20180074736

Providing data in a shared memory

A data processing apparatus is provided, comprising controller circuitry. The controller circuitry includes processing circuitry that executes a stream of instructions. ... Arm Limited

03/15/18 / #20180074116

Critical path architect

Various implementations described herein are directed to a system and methods for implementing a critical path architect. In one implementation, the critical path architect may be implemented with a system having a processor and memory including instructions stored thereon that, when executed by the processor, cause the processor to analyze timing data of an integrated circuit. ... Arm Limited

03/08/18 / #20180067749

Tracing processing activity

Data processing apparatus comprises a processing element having an instruction pipeline to execute instructions; and trace circuitry to generate items of trace data indicative of processing activities of the processing element; the trace circuitry being configured to generate items of event trace data in response to events initiated by execution of instructions by the instruction pipeline and to generate items of waypoint trace data in response to instructions, in a set of waypoint instructions, reaching a predetermined stage relative to the instruction pipeline; and the trace circuitry being configured to generate position data, indicating a relative position with respect to execution of the corresponding instructions by the instruction pipeline, of one or more items of event trace data and one or more items of waypoint trace data.. . ... Arm Limited








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