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Arm Limited patents


Recent patent applications related to Arm Limited. Arm Limited is listed as an Agent/Assignee. Note: Arm Limited may have other listings under different names/spellings. We're not affiliated with Arm Limited, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "A" | Arm Limited-related inventors


Graphics processing system

When rendering a scene that includes a complex object made up of many individual primitives, rather than processing each primitive making up the object in turn, a bounding volume which surrounds the complex object is generated and the scene is then processed using the bounding volume in place of the actual primitives making up the complex object. If it is determined that the bounding volume representation of the object will be completely occluded in the scene (e.g. ... Arm Limited

Graphics processing

A graphics processing apparatus performs an intermediate processing pass in which region lists that indicate geometry for respective regions of an intermediate projection surface are generated and stored. A subsequent processing pass is then performed in which a region of the intermediate projection surface is selected using a vector for a fragment, and geometry data for shading the fragment is obtained with reference to the region list that was stored for the selected region in the intermediate processing pass. ... Arm Limited

Apparatus and method for executing instruction using range information associated with a pointer

An apparatus (2) comprises one or more bounded pointer storage element (60s) each to store a pointer (62) having associated range information (64) indicating an allowable range of addresses for the pointer (62). Processing circuitry (4) performs, in response to a first type of instruction (70) identifying a given bounded pointer storage element, a predetermined operation for a target range of addresses determined at least in part on the basis of the range information (64) associated with the pointer stored in the given bounded pointer storage element (60).. ... Arm Limited

Vector length querying instruction

A data processing system 2 supporting vector processing operations uses scaling vector length querying instructions. The scaling vector length querying instructions return a result which is dependent upon a number of elements in a vector for a variable vector element size specified by the instruction and multiplied by a scaling value specified by the instruction. ... Arm Limited

Data processing

Data processing apparatus comprises one or more transaction issuing devices configured to issue data processing transactions to be handled by a downstream device and to receive a completion acknowledgement in respect of each completed transaction; each transaction issuing device having associated transaction regulator circuitry configured to allow that transaction issuing device to issue transactions subject to a limit on a maximum number of outstanding transactions, an outstanding transaction being a transaction which has been issued but for which a completion acknowledgement has not yet been received; in which the downstream device is configured to issue an indication to a transaction issuing device, to authorise a change by the transaction regulator circuitry of the limit applicable to outstanding transactions by that transaction issuing device.. . ... Arm Limited

Performing diagnostic operations upon a target apparatus

Diagnostic operations upon a target apparatus 2 having a target transaction master 8 which initiates memory transactions with one or more target transaction slaves 12, 14, 16 are provided by halting operation of the target transaction master 8 while permitting continued operation within the target apparatus 2 of at least some of the target transaction slaves 12, 14, 16. Opening state data representing an operating state of the target transaction master 8 is transferred to a model transaction master 32. ... Arm Limited

Data processing apparatus and method for controlling vector memory accesses

An apparatus and method are provided for controlling vector memory accesses. The apparatus comprises a set of vector registers, and flag setting circuitry that is responsive to a determination that a vector generated for storage in one of the vector registers comprises a plurality of elements that meet specified contiguousness criteria, to generate flag information associated with that vector register. ... Arm Limited

Video processing systems

A video processing system includes a host processor, a video encoder and a memory. The host processor sends a configuration message to the video encoder that indicates to the video encoder how to encode a video frame and that includes information indicating the location of encoding configuration data that is stored in the memory. ... Arm Limited

Power clamp with correlated electron material device

A circuit is provided for limiting an applied voltage applied between a power line and an electrical ground. The circuit includes a transistive element connected between the power line and the electrical ground to provide a channel, where current flow through the channel is controlled by a control voltage provided to a control terminal of the transistive element. ... Arm Limited

Logic encryption using on-chip memory cells

A protected circuit includes a logic circuit having one or more input nodes and one or more output nodes. The logic circuit has a network of logic elements and one or more logic encryption elements. ... Arm Limited

Pin-based noise characterization for silicon compiler

A silicon compiler, such as a memory compiler, provides for pin-based noise characterization in a computationally efficient manner. For a given user-provided option set, a silicon compiler provides a noise database for the set of all available memory instances by performing pin-based noise characterization on only a subset of the set of available memory instances.. ... Arm Limited

Corner database generator

Various implementations described herein are directed to a computing device. The computing device may include a mapper module that receives a user configuration input of a destination corner for building a destination corner database. ... Arm Limited

Data processing

A data processing system comprises a master node to initiate data transmissions; one or more slave nodes to receive the data transmissions; and a home node to control coherency amongst data stored by the data processing system; in which at least one data transmission from the master node to one of the one or more slave nodes bypasses the home node.. . ... Arm Limited

Secure initialisation

A data processing system for processing data using a memory having a plurality of memory regions, a given memory region within said plurality of memory regions having an associated owning process having exclusive rights to control access to said given memory region, said system comprising: a security controller to: receive a request to initialise a guest execution environment; claim one or more regions of memory to be owned by said security controller; store executable program code of said guest execution environment within said one or more regions of memory; and transfer ownership of said one or more regions to said guest execution environment.. . ... Arm Limited

06/21/18 / #20180173641

Address translation

A data processing apparatus (20) comprises address translation circuitry (40) to translate a first address into a physical address directly identifying a corresponding location in a data store, and a table (50) comprising one or more entries indexed by the physical address, wherein at least one of the entries specifies the first address from which the corresponding physical address was translated by the address translation circuitry (40).. . ... Arm Limited

06/21/18 / #20180173546

System and method for translating a guest instruction of a guest architecture into at least one host instruction of a host architecture

A system and method are provided for translating a guest instruction of a guest architecture into at least one host instruction of a host architecture. The method comprises providing multiple representation states, each representation state providing a representation in the host architecture for at least one item of state from the guest architecture. ... Arm Limited

06/21/18 / #20180173535

Determining a predicted behaviour for processing of instructions

An apparatus comprises prediction circuitry (40, 100, 80) for determining, based on current prediction policy information (43, 82, 104), a predicted behaviour to be used for processing instructions. The current prediction policy information is updated based on an outcome of processing of instructions. ... Arm Limited

06/21/18 / #20180173498

Arithmetic operation input-output equality detection

Apparatus and corresponding methods are disclosed relating to circuitry to perform an arithmetic operation on one or more input operands, where the circuitry is responsive to an equivalence of a result value of the arithmetic operation with at least one of the one or more input operands, when the one or more input operands are not an identity element for the arithmetic operation, to generate a signal indicative of the equivalence. Idempotency (between at least one input operand and the result value) is thus identified.. ... Arm Limited

06/21/18 / #20180173497

An apparatus and method for processing floating point values

An apparatus and method are provided for processing floating point values using an intermediate representation which has significand, exponent and shadow sections. A less significant portion of the exponent of the floating point value defines a range of positions within the significand section where the representation of the significand is to be held. ... Arm Limited

06/21/18 / #20180173271

Clock signal distribution and signal value storage

An integrated circuit includes multiple blocks of circuitry (4, 6, 8) communicating signals via an interface 10 controlled by a clock signal. A clock mesh (20, 22) is used on at least one side of the interface driven by one or more clock drivers (24, 26) that drive the clock mesh with the clock signal communicated with a further block of circuitry. ... Arm Limited

06/21/18 / #20180172764

Method, system and apparatus for tuning an integrated embedded subsystem

A method, apparatus and system are provided for the tuning of embedded subsystems of a device under test (dut) that have analog characteristics. In response to a tester invoking one or more test procedures via a command channel between the tester and a target embedded subsystem of the dut, test firmware of the invoked tests is loaded into the target embedded subsystem. ... Arm Limited

06/14/18 / #20180165962

Method of detecting and providing parking space information and/or road obstacle information to vehicles

Vehicles which are provided with at least one sensor and a location system, such as a global positioning system (gps) detect parking spaces and/or road obstacles when driving along a road. The detected parking space and/or road obstacle data is transferred to a remote processing module. ... Arm Limited

06/14/18 / #20180165218

Memory management

Apparatus comprises input circuitry to receive a translation request defining an input memory address within an input memory address space; and address translation circuitry comprising: permission circuitry to detect whether memory access is permitted for the input memory address with reference to permission data populated from address translation tables and stored in a permission data store for each of a set of respective regions of the input memory address space, there being a dedicated entry in the permission data store for each of the regions so that the input memory address maps to a single respective entry; and output circuitry to provide an output memory address in response to the translation request, in which when the permission circuitry indicates that access is permitted to a region of the input memory address space including the input memory address, the output circuitry is configured to provide the output memory address as a predetermined function of the input memory address.. . ... Arm Limited

06/14/18 / #20180165064

Partial square root calculation

A data processing apparatus is provided, to calculate an at least partial square root of a floating point number having an exponent and significand. Recurrence circuitry performs one or more iterations of an iterative square root operation, each of the one or more iterations receiving an input at least partial square root and an input remainder to produce the at least partial square root and a remainder of performing the iterative square root operation. ... Arm Limited

06/14/18 / #20180164375

Adapting the usage configuration of integrated circuit input-output pads

Techniques for implementing a self-test procedure of an integrated circuit are provided, where the self-test procedure comprises testing for an electrical connection between first and second input-output pads of the integrated circuit. A control device is capable of adapting a functional configuration of usage of the first and second input-output pads in dependence on presence of the electrical connection. ... Arm Limited

06/07/18 / #20180157601

Apparatus and method for avoiding conflicting entries in a storage structure

An apparatus and method are provided for avoiding conflicting entries in a storage structure. The apparatus comprises a storage structure having a plurality of entries for storing data, and allocation circuitry, responsive to a trigger event for allocating new data into the storage structure, to determine a victim entry into which the new data is to be stored, and to allocate the new data into the victim entry upon determining that the new data is available. ... Arm Limited

06/07/18 / #20180157590

Filtering coherency protocol transactions

A filter unit comprises interface circuitry, to intercept coherency protocol transactions exchanged between a master device comprising a first cache and an interconnect for managing coherency between the first cache and at least one other cache or other master device. The filter unit has filtering circuitry for filtering the coherency protocol transactions in dependence on memory access permission data defining which regions of an address space the master device is allowed to access.. ... Arm Limited

06/07/18 / #20180157490

Variable-length-instruction processing modes

A data processing apparatus (2) operates in a first mode of operation having a first set of processing circuitry (8, 12, 18, 20, 22) ready to perform processing operations and in a second mode of operation having a second set of processing circuitry (8, 12, 14, 18, 20, 22, 24) ready to perform processing operations. A first proper subset (32) of program instructions within the instruction set supported are processed by the processor using a selectable one of the first mode and the second mode. ... Arm Limited

06/07/18 / #20180157464

Apparatus and method for performing arithmetic operations to accumulate floating-point numbers

An apparatus and method are provided for performing arithmetic operations to accumulate floating-point numbers. The apparatus comprises execution circuitry to perform arithmetic operations, and decoder circuitry to decode a sequence of instructions in order to generate control signals to control the arithmetic operations performed by the execution circuitry. ... Arm Limited

06/07/18 / #20180157463

Leading zero anticipation

A data processing apparatus is provided. Intermediate value generation circuitry generates an intermediate value from a first floating point number and a second floating point number. ... Arm Limited

06/07/18 / #20180157437

Apparatus and method for transferring data between address ranges in memory

An apparatus and method are provided for transferring data between address ranges in memory. The apparatus comprises a data transfer controller, that is responsive to a data transfer request received by the apparatus from a processing element, to perform a transfer operation to transfer data from at least one source address range in memory to at least one destination address range in the memory. ... Arm Limited

06/07/18 / #20180156866

Scan cell for dual port memory applications

Various implementations described herein are directed to a scan cell. The scan cell may include an input phase having multiple multiplexers and a latch arranged to receive a scan input signal, a first address signal, and a second address signal and provide the scan input signal, the first address signal, or the second address signal based on a scan enable signal, a first clock signal, and a selection enable signal. ... Arm Limited

05/31/18 / #20180152252

Communications device and method

A device comprises a coupling configured to couple signals to and from a communications path including at least a part of a human or animal body; a data transmitter coupled to the coupling and configured to transmit, from time to time, a data signal of at least a predetermined temporal duration via the communications path; and a data receiver coupled to the coupling and configured to detect the presence of a signal on the communications path at sets of one or more successive detection instances disposed between successive transmissions of the data signal by the data transmitter, the data receiver being configured so that the successive detection instances of a set are temporally separated by no more than the predetermined temporal duration; the device being configured to initiate a processing operation in response to a detection by the data receiver of the presence of a signal on the communications path.. . ... Arm Limited

05/31/18 / #20180151800

Cem switching device

Subject matter herein disclosed relates to an improved cem switching device and methods for its manufacture. In this device, a conductive substrate and/or conductive overlay comprises a primary layer of a conductive material and a secondary layer of a conductive material. ... Arm Limited

05/31/18 / #20180150413

Protected exception handling

A data processing system for processing data comprising: ownership circuitry to enforce ownership rights of memory regions, a given more privileged state memory region having a given owning process specified from among a plurality of processes, said given owning process having exclusive rights to control access to said given memory region; and context switching circuitry responsive to receipt of an interrupt to trigger a context switch from a first active process to a second active process whereby one or more items of state for use in restarting said first process is saved to one or more context data memory regions owned by said first process and one or more items of state accessible to said second process and dependent upon processing by said first process is overwritten prior to commencing execution of said second process.. . ... Arm Limited

05/31/18 / #20180150389

Method and apparatus for memory wear leveling

A method and apparatus is provided for wear leveling of a storage medium in an electronic device. Wear leveling is achieved by mapping each logical memory address to a corresponding physical memory address. ... Arm Limited

05/31/18 / #20180150322

Data processing

Data processing apparatus comprises one or more interconnected processing elements each configured to execute processing instructions of a program task; coherent memory circuitry storing one or more copies of data accessible by each of the processing elements, so that data written to a memory address in the coherent memory circuitry by one processing element is consistent with data read from that memory address in the coherent memory circuitry by another of the processing elements; the coherent memory circuitry comprising a memory region to store data, accessible by the processing elements, defining one or more attributes of a program task and context data associated with a most recent instance of execution of that program task; the apparatus comprising scheduling circuitry to schedule execution of a task by a processing element in response to the one or more attributes defined by data stored in the memory region corresponding to that task; and each processing element which executes a program task is configured to modify one or more of the attributes corresponding to that program task in response to execution of that program task.. . ... Arm Limited

05/31/18 / #20180150321

Data processing

Data processing apparatus comprises a group of two or more processing elements configured to execute processing instructions of a program task; the processing elements being configured to provide context data relating to a program task following execution of that program task by that processing element; and to receive context data, provided by that processing element or another processing element, at resumption of execution of a program task; in which a next processing element of the group to execute a program task is configured to receive a first subset of the context data from a previous processing element to execute that program task and to start to execute the program task using the first subset of the context data; and in which the next processing element is configured to receive one or more items of a second, remaining, subset of the context data during execution of the program task by that processing element.. . ... Arm Limited

05/31/18 / #20180150315

Data processing

Data processing apparatus comprises one or more interconnected processing elements; each processing element being configured to execute processing instructions of program tasks; each processing element being configured to save context data relating to a program task following execution of that program task by that processing element; and to load context data, previously saved by that processing element or another of the processing elements, at resumption of execution of a program task; each processing element having respective associated format definition data to define one or more sets of data items for inclusion in the context data; the apparatus comprising format selection circuitry to communicate the format definition data of each of the processing elements with others of the processing elements and to determine, in response to the format definition data for each of the processing elements, a common set of data items for inclusion in the context data.. . ... Arm Limited

05/31/18 / #20180150297

Processing pipeline with first and second processing modes having different performance or energy consumption characteristics

An apparatus (2) has a processing pipeline (4) supporting at least a first processing mode and a second processing mode with different energy consumption or performance characteristics. A storage structure (22, 30, 36, 50, 40, 64, 44) is accessible in both the first and second processing modes. ... Arm Limited

05/31/18 / #20180150251

Shared pages

A data processing system comprising: ownership circuitry to enforce ownership rights of memory regions within a physical memory address space, a given memory region having a given owning process specified from among a plurality of processes and independently of privilege level, said given owning process having exclusive rights to control access to said given memory region, wherein said given owning process designates said given memory region as one of: private to said given owning process; and shared between said given owning process and at least one further source of memory access requests.. . ... Arm Limited

05/31/18 / #20180150243

Data movement engine

A memory system of a data processing system includes one or more storage devices and a data rearrangement engine for moving data between memory regions of the plurality of memory regions. The data rearrangement engine is configured to rearrange data stored at non-contiguous addresses in a source memory region into contiguous address in a destination region responsive to a rearrangement specified by a host processing unit of the data processing system. ... Arm Limited

05/31/18 / #20180150120

Monitoring circuit and method

Broadly speaking, embodiments of the present techniques provide a voltage monitoring circuit for low power minimum-energy sensor nodes. The circuit comprises sensing circuitry to sense a monitored signal having a plurality of operating signal states; a first comparator having a first input for receiving an upper threshold signal; and a second comparator having a first input for receiving a lower threshold signal, the upper and lower threshold signals defining a range which includes at least one signal state of the plurality of operating states of the monitored signal, wherein the first and second comparators have a bias input for receiving a bias configuration setting, the bias configuration setting being selectable according to an operating signal state of the monitored signal.. ... Arm Limited

05/24/18 / #20180146158

De-interlacing data arrays in data processing systems

A data processing system includes a scaler 18 operable to scale a received input data array to provide a scaled output version of the input data array. When it is desired to produce a de-interlaced and scaled output version of an input data array 21, 22, the input data array 21, 22 is provided to the scaler 18, and the scaler 18 scales the input data array 21, 22 so as to simultaneously de-interlace and scale the input data array and to produce a de-interlaced and scaled output version of the input data array.. ... Arm Limited

05/24/18 / #20180144780

Tracking wordline behavior

Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a memory bank having an array of memory cells that are accessible via a selected wordline and a pair of complementary bitlines. ... Arm Limited

05/24/18 / #20180144437

Graphics processing systems

In a graphics processing system, an application executing on a host processor can request graphics processing operations that are to be performed by only subsets of the set of stages of a graphics processing pipeline implemented by a graphics processor. In response to such a request, the driver for the graphics processor causes the graphics processing operation that is to be performed using only a subset of the set of stages of the graphics processing pipeline to be performed. ... Arm Limited

05/24/18 / #20180143831

Check instruction for verifying correct code execution context

A data processing apparatus and method of data processing are provided which make use of a processor state check instruction to determine if the data processing apparatus is currently operating in a processor state, defined by at least one runtime processor state configuration value, which matches a processor state check value defined by the processor state check instruction. Dependent on the required runtime processor state configuration value(s) matching the processor state check value, the processor state check instruction is treated as an ineffective instruction. ... Arm Limited

05/24/18 / #20180143771

Managing persistent storage writes in electronic systems

The apparatus operable to communicate with a memory comprises a persistent write tracker component operable to track frequency of persistent writes to at least one memory location during a time window; a threshold-exceeded detector component responsive to the tracker component and operable to detect excessive persistent writes to the at least one memory location during the time window; and a selective throttle component operable in response to a threshold-exceeded outcome from the detector component to cause selective throttling of persistent writes to the at least one memory location.. . ... Arm Limited

05/24/18 / #20180143679

Multiple heterogeneous energy stores

There is provided an apparatus comprising a requirement determination unit to determine an energy requirement for a system component. A status determination unit determines status information relating to a plurality of heterogeneous energy stores and actuating system control unit controls an activity of the system component in dependence on the status information relating to the plurality of heterogeneous energy stores and the energy requirement.. ... Arm Limited

05/17/18 / #20180138900

Transition detection circuitry and method of detecting a transition of a signal occurring within a timing window

A transition detection circuit (20) and method of operation of such a circuit are provided, the transition detection circuit (20) having pulse generation circuitry (25) to receive an input signal (10) and to generate a pulse signal in response to a transition in the input signal, and pulse detection circuitry (30) to assert an error signal on detection of the pulse signal generated by the pulse generation circuitry. The pulse generation circuitry has pulse control circuitry (35) to control a property of the pulse signal dependent on a timing window indication signal (40). ... Arm Limited

05/17/18 / #20180136984

Apparatus and methods for load balancing across a network of nodes

A system provided at nodes within a network of nodes enabling the nodes to migrate activities to other nodes within its communication range to provide load balancing across the network. The other nodes having power and processing capabilities and capacity enabling them to undertake the migrated activities.. ... Arm Limited

05/10/18 / #20180129611

Data processing apparatus and method with ownership table

A data processing apparatus (20) comprises processing circuitry (24, 25, 28) to execute a plurality of processes. An ownership table (50) comprises one or more entries (52) each indicating, for a corresponding block of physical addresses, which of the processes is an owner process that has exclusive control of access to the corresponding block of physical addresses.. ... Arm Limited

05/10/18 / #20180129573

Error detection

An apparatus 2 comprises at least three processing circuits 4 to perform redundant processing of a common thread of program instructions. Error detection circuitry 16 is provided comprising a number of comparators 22 for detecting a mismatch between signals on corresponding signal nodes 20 in the processing circuits 4. ... Arm Limited

05/10/18 / #20180129499

Data processing systems

A program is analysed to identify instructions that will load external data and to determine whether such instructions are followed by a sequence of instructions that will produce the same result for each thread in a thread group if the data loaded by the load instruction is the same for each thread in the thread group. Each time there is an external load instruction, it is determined whether the data loaded by the external load instruction is the same for all threads of the thread group, and whether the external load instruction was indicated as being followed by a sequence of instructions that produce the same result if the external load instruction loads the same data value for each thread of a thread group. ... Arm Limited

05/10/18 / #20180129437

Computer architecture

A tagged memory organized is into memory chunks. Each memory chunk has a data field, a type field and an owner address field. ... Arm Limited

05/10/18 / #20180129419

Updating data stored in a memory

A process of updating data for a block of an array of data elements stored in an allocated memory region for the block comprises reading in data for a first group of the data elements, updating the data for the first group, and then writing back the updated data to memory. The process can avoid overwriting data for a second group of the data elements that is yet to be read in from the memory region by writing back the updated data for the first group starting at a selected memory address, for example other than the start address of the memory region. ... Arm Limited

05/03/18 / #20180121203

Shortcut path for a branch target buffer

An apparatus comprises a branch target buffer (btb) to store predicted target addresses of branch instructions. In response to a fetch block address identifying a fetch block comprising two or more program instructions, the btb performs a lookup to identify whether it stores one or more predicted target addresses for one or more branch instructions in the fetch block. ... Arm Limited

05/03/18 / #20180120926

Controlling transitions of devices between normal state and quiescent state

A data processing apparatus has a number of devices having a normal state and a quiescent state in which the device is ready for being placed in a power saving state. Each device provides at least one preference indication indicative of a preference to operate in the normal state or the quiescent state. ... Arm Limited

04/19/18 / #20180108167

Graphics processing systems

A graphics processing pipeline (30) includes a programmable fragment shader (40) that is operable to, in response to a “test” instruction included in a fragment shader program that it is executing, trigger, if appropriate, the performance of an alpha-to-coverage operation (41), a late stencil test (42), and a late depth test (43) for a fragment being processed, and to then return updated coverage information to the fragment shader (40). This allows alpha-to-coverage and late stencil and depth test operations to be triggered and performed during shader execution, rather than having to wait until shader execution has been completed before performing those operations.. ... Arm Limited

04/19/18 / #20180107606

Eviction control for an address translation cache

A data processing system 2 includes an address translation cache 12 to store a plurality of address translation entries. Eviction control circuitry 10 selects a victim entry for eviction from address translation cache 12 using an eviction control parameter. ... Arm Limited

04/19/18 / #20180107604

Apparatus and method for maintaining address translation data within an address translation cache

An apparatus and method are provided for maintaining address translation data within an address translation cache. The address translation cache has a plurality of entries, where each entry is used to store address translation data used when converting a virtual address into a corresponding physical address of a memory system. ... Arm Limited

04/12/18 / #20180101928

Display controllers

In a display controller of a data processing system, when composing two or more input surfaces to generate a composited surface comprising the two or more input surfaces, data indicating a border between different input surfaces in the composited surface is associated with the composited surface. The data indicative of the border between two input surfaces in the composited surface is then used to control subsequent processing, such as compression and/or filtering, of the composited surface.. ... Arm Limited

04/12/18 / #20180101489

Controlling transitions of devices between normal state and quiescent state

A data processing apparatus (2) has a number of devices (4) having a normal state and a quiescent state. Transition sequencing circuitry (70) controls a sequential state transition process for transitioning each of the devices (4) in turn between the normal state and the quiescent state. ... Arm Limited

04/12/18 / #20180101480

Apparatus and method for maintaining address translation data within an address translation cache

An apparatus and method are provided for maintaining address translation data within an address translation cache. Each entry of the address translation cache is arranged to store address translation data used when converting a virtual address into a corresponding physical address of a memory system. ... Arm Limited

04/05/18 / #20180098078

Selecting encoding options

A set of encoding options to use when encoding an array of data elements is selected based on a bit count value and a distortion value for that set of encoding options. The distortion value is determined from a set of error values that represents the difference between a set of frequency domain coefficients and a set of de-quantised coefficients. ... Arm Limited

04/05/18 / #20180096715

Integrated circuit using shaping and timing circuitries

Various implementations described herein may refer to and may be directed to an integrated circuit using shaping and timing circuitries. In one implementation, an integrated circuit may include memory that is accessed based on a voltage level on a first control line, and may include a control driver circuitry coupled to the first and a second control line that drives a first and a second control signal toward first or second voltage levels. ... Arm Limited

04/05/18 / #20180095893

Queuing memory access requests

A data processing apparatus is provided including queue circuitry to respond to control signals each associated with a memory access instruction, and to queue a plurality of requests for data, each associated with a reference to a storage location. Resolution circuitry acquires a request for data, and issues the request for data, the resolution circuitry having a resolution circuitry limit. ... Arm Limited

04/05/18 / #20180095752

Instruction predecoding

An apparatus comprises processing circuitry, an instruction cache, decoding circuitry to decode program instructions fetched from the cache to generate macro-operations to be processed by the processing circuitry, and predecoding circuitry to perform a predecoding operation on a block of program instructions fetched from a data store to generate predecode information to be stored to the cache with the block of instructions. In one example the predecoding operation comprises generating information on how many macro-operations are to generated by the decoding circuitry for a group of one or more program instructions. ... Arm Limited

04/05/18 / #20180095677

Display controllers

In a display controller, output surface data from a composition processing stage 22 is received by and stored in a local latency hiding buffer 40 of a memory write subsystem 31 before being written out to an external memory. The local buffer 40 of the memory write subsystem 31 signals when it is “full”, and in response thereto the inputting of output surface data to the local buffer 40 is stopped until the current line of the output surface has been finished, and then started again when the next line of the output surface begins. ... Arm Limited

03/29/18 / #20180091818

Methods of and apparatus for encoding data arrays

To perform motion estimation for a video frame block to be encoded, a difference measure is determined for each of a plurality of reference frame block positions at a first, coarser resolution. The determined difference measures are then used estimate difference measures for reference frame blocks at positions at a second resolution that is finer than the first resolution. ... Arm Limited

03/29/18 / #20180091407

Error detection in communication networks

Broadly speaking, embodiments of the present techniques provide apparatus and methods to identify and correct communication errors in a network formed of a plurality of nodes. In particular, the apparatus and methods identify synchronisation errors in a network which result in delayed propagation of messages through the network.. ... Arm Limited

03/29/18 / #20180089079

Apparatus, memory controller, memory module and method for controlling data transfer

An apparatus, memory controller, memory module and method are provided for controlling data transfer in memory. The apparatus comprises a memory controller and a plurality of memory modules. ... Arm Limited

03/29/18 / #20180088951

Instruction issue according to in-order or out-of-order execution modes

Apparatus for processing data (2) includes issue circuitry (22) for issuing program instructions (processing operations) to execute either within real time execution circuitry (32) or non real time execution circuitry (24, 26, 28, 30). Registers within a register file (18) are marked as non real time dependent registers if they are allocated to store a data value which is to be written by an uncompleted program instruction issued to the non real time execution circuitry and not yet completed. ... Arm Limited

03/22/18 / #20180083631

Receiver circuitry and method for converting an input signal from a source voltage domain into an output signal for a destination voltage domain

The present invention provides a receiver circuit and method for receiving an input signal from a source voltage domain and converting the input signal into an output signal for a destination voltage domain. The source voltage domain operates from a supply voltage that exceeds a stressing threshold of components within the receiver circuitry, and the receiver circuitry is configured to operate from the supply voltage of the source voltage domain. ... Arm Limited

03/22/18 / #20180081624

Data item order restoration

An apparatus and a corresponding method for processing a sequence of received data items are disclosed. The processing is performed by multiple processing elements. ... Arm Limited

03/15/18 / #20180076388

Cem switching device

Subject matter herein disclosed relates to a method for the manufacture of a cem switching device providing that the cem layer comprises a doped metal compound substantially free from metal wherein ions of the same metal element are present in different oxidation states. The method may provide a cem layer which is born on and capable of switching with operating voltages below 2.0v.. ... Arm Limited

03/15/18 / #20180076386

Cem switching device

Subject matter herein disclosed relates to a method for the manufacture of a switching device comprising a silicon-containing correlated electron material. In embodiments, processes are described for forming the silicon-containing correlated electron material. ... Arm Limited

03/15/18 / #20180074954

Comparator and memory region detection circuitry and methods

Comparator circuitry comprises carry-save-addition (csa) circuitry to generate a set of partial sum bits and a set of carry bits in respect of corresponding bit positions in a first input value, a second input value, a carry-in value associated with the first and second input values, and a third input value, the csa circuitry comprising inverter circuitry to provide a relative inversion between the third input value and the group consisting of the first and second input values; and combiner circuitry to combine the set of partial sum bits, the set of carry bits offset by a predetermined number of bits in a more significant bit direction, the carry-in value and 1, to generate at least a carry output bit; in which the carry output bit is indicative of whether the third input value is greater than the sum of the first and second input values.. . ... Arm Limited

03/15/18 / #20180074933

Management of log data in electronic systems

The disclosed method comprises receiving operating environment data, such as resource availability data, from connected computing devices and services, analysing the data to create one or more policies governing log data storage and upload parameters, and sending the policies to the connected devices to enable them to limit resource consumption in the management of log data.. . ... Arm Limited

03/15/18 / #20180074736

Providing data in a shared memory

A data processing apparatus is provided, comprising controller circuitry. The controller circuitry includes processing circuitry that executes a stream of instructions. ... Arm Limited

03/15/18 / #20180074116

Critical path architect

Various implementations described herein are directed to a system and methods for implementing a critical path architect. In one implementation, the critical path architect may be implemented with a system having a processor and memory including instructions stored thereon that, when executed by the processor, cause the processor to analyze timing data of an integrated circuit. ... Arm Limited

03/08/18 / #20180067749

Tracing processing activity

Data processing apparatus comprises a processing element having an instruction pipeline to execute instructions; and trace circuitry to generate items of trace data indicative of processing activities of the processing element; the trace circuitry being configured to generate items of event trace data in response to events initiated by execution of instructions by the instruction pipeline and to generate items of waypoint trace data in response to instructions, in a set of waypoint instructions, reaching a predetermined stage relative to the instruction pipeline; and the trace circuitry being configured to generate position data, indicating a relative position with respect to execution of the corresponding instructions by the instruction pipeline, of one or more items of event trace data and one or more items of waypoint trace data.. . ... Arm Limited

03/08/18 / #20180067721

Floating point addition with early shifting

A floating point adder includes leading zero anticipation circuitry 18 to determine a number of leading zeros within a result significand value of a sum of a first floating point operand and a second floating point operand. This number of leading zeros is used to generate a mask which in turn selects input bits from a non-normalized significand produced by adding the first significand value and the second significand value. ... Arm Limited

03/08/18 / #20180067165

Serial communication control

An apparatus 2 for performing serial data communication with a target device 4, such as an integrated circuit, utilizes serial transfer circuitry 16 to perform a serial transfer of data to a communication register 26 in the target device 4 and serial retrieval circuitry 18 to retrieve an acknowledge signal 32 indicating whether or not the target device is ready to perform further processing following such a transfer. Delay control circuitry 20 serves to apply a predetermined delay period following the transfer of the serial data via the serial transfer circuitry before initiating the retrieval of the acknowledge signal. ... Arm Limited

03/01/18 / #20180060475

Method for generating three-dimensional integrated circuit design

A method for generating a design for a 3d integrated circuit (3dic) comprises extracting at least one design characteristic from a first data representation of a design for a integrated circuit (2dic) generated according to the design criteria required for the 3dic. Components of the 3dic are partitioned into groups (each representing one tier of the 3dic) based on the extracted design characteristic. ... Arm Limited

02/22/18 / #20180052790

Interconnect circuitry and a method of operating such interconnect circuitry

An interconnect circuit, and method of operation of such an interconnect circuit, are provided. The interconnect circuitry has a first interface for coupling to a master device and a second interface for coupling to a slave device. ... Arm Limited

02/22/18 / #20180052691

Memory dependence prediction

A data processing apparatus executes a stream of instructions. Memory access circuitry accesses a memory in response to control signals associated with a memory access instruction that is executed in the stream of instructions. ... Arm Limited

02/22/18 / #20180052660

Apparatus and method for fixed point to floating point conversion and negative power of two detector

A data processing system 2 supports conversion of fixed point numbers to floating point numbers. The result floating point numbers may be subnormal. ... Arm Limited

02/15/18 / #20180046460

Data processing

Data processing apparatus comprises: processing circuitry to selectively apply vector processing operations to one or more data items of one or more data vectors each comprising a plurality of data items at respective vector positions in the data vector, according to the state of respective predicate indicators associated with the vector positions; a predicate store; and predicate generation circuitry to apply a processing operation to generate a set of predicate indicators, each associated with a respective one of the vector positions, to generate a count value indicative of the number of predicate indicators in the set having a given state, and to store the generated set of predicate indicators and the count value in the predicate store.. . ... Arm Limited

02/15/18 / #20180046459

Data processing

Data processing apparatus comprises processing circuitry to selectively apply vector processing operations to one or more data items of one or more data vectors each comprising an ordered plurality of data items at respective vector positions in the data vector, according to the state of respective predicate indicators associated with the vector positions; predicate generation circuitry to apply a processing operation to generate an ordered set of predicate indicators, each associated with a respective one of the vector positions, the ordered set of predicate indicators being associated with an ordered set of active indicators each having an active or an inactive state; and a detector to detect a status flag indicative of whether a predicate indicator at a position, in the ordered set of predicate indicators, corresponding to the position of an outermost active indicator having the active state, has a given state; in which the detector comprises: first and second circuitry to combine the ordered set of predicate indicators and the ordered set of active indicators using first and second respective logical bit-wise combinations to generate first and second ordered sets of intermediate data; and arithmetic circuitry to combine the first and second ordered sets of intermediate data using an arithmetic combination generating a carry bit, the detector generating the status flag in dependence upon the carry bit.. . ... Arm Limited

02/08/18 / #20180039323

Power supply control

A data processing apparatus 2 includes processing circuitry 4 performing processing operations which move the processing circuitry 4 between logical states. Monitoring circuitry 18 monitors logical state variables of the processing circuitry and these are supplied to prediction circuitry 30 which detects predetermined patterns within the logical states which are indicative (previously correlated with) of a future potential temporary insufficiency in the supply power to the processing circuitry 4. ... Arm Limited

02/01/18 / #20180033191

Graphics processing systems

In a graphics processing system, a bounding volume (20) representative of the volume of all or part of a scene to be rendered is defined. Then, when rendering an at least partially transparent object (21) that is within the bounding volume (20) in the scene, a rendering pass for part or all of the object (21) is performed in which the object (21) is rendered as if it were an opaque object. ... Arm Limited

02/01/18 / #20180032455

Interface device for a data processing system

An interface device for a data processing system is provided. The interface device comprises first interface circuitry to receive incoming data and second interface circuitry to transmit processed data to a data store for storage. ... Arm Limited

02/01/18 / #20180032435

Cache maintenance instruction

An apparatus (2) comprises processing circuitry (4) for performing data processing in response to instructions. The processing circuitry (4) supports a cache maintenance instruction (50) specifying a virtual page address (52) identifying a virtual page of a virtual address space. ... Arm Limited

01/25/18 / #20180026799

A method of establishing trust between a device and an apparatus

There is disclosed a method of establishing trust between an agent device and a verification apparatus, the method comprising: obtaining, at the agent device, a trust credential, wherein the trust credential relates to an aspect of the agent device and comprises authentication information for identifying at least one party trusted by the verification apparatus and/or device data relating to the agent device; transmitting, from the agent device to the verification apparatus, the trust credential; obtaining, at the verification apparatus, the trust credential; analysing, at the verification apparatus, the trust credential; determining, at the verification apparatus, whether the agent device is trusted based on the analysis; and responsive to determining the agent device is trusted, establishing trust between the agent device and the verification apparatus.. . ... Arm Limited

01/18/18 / #20180019951

Data item replay protection

Apparatus and a corresponding method for processing a received data item comprising a received sequence number are provided. A set of sequence number entries are stored as an array and data item processing circuitry performs an access to only a selected entry in the array in dependence on the received sequence number. ... Arm Limited

01/18/18 / #20180018420

System and method for perforating redundant metal in self-aligned multiple patterning

A method for modifying metal portions of a layout data file associated with a self-aligned multiple patterning (samp) process. The method comprises receiving the layout data file that includes one or more active metal portions and layout information associated with an integrated circuit. ... Arm Limited

01/18/18 / #20180018359

Datagram reassembly

Apparatus and a corresponding method for processing received datagram fragments are provided. Fragments are considered in fragments lists, which comprise a linked list of fragments. ... Arm Limited

01/04/18 / #20180005351

Data processing systems

In a data processing system, an input data array to be downscaled is split into plural parts along its horizontal extent and the different parts of the input data array are then provided to respective scalers of the data processing system and are respectively downscaled by those scalers to provide a plurality of downscaled output parts. The plural downscaled output parts are then combined (merged) to provide the desired downscaled output data array.. ... Arm Limited

01/04/18 / #20180004704

Interface apparatus and method

An interface comprises routing circuitry configured to receive data items from a data source device and to route the received data items to a data sink device by either a first data path including a data buffer or a second data path, in response to an indication of a current state of a data sink device; the routing circuitry being configured to route the received data item by the first data path and to initiate a transition of the data sink device to a ready state in response to an indication that the data sink device is in a quiescent mode and currently not ready to receive the data item, the routing circuitry being configured to hold the data item at the buffer and to inhibit the data source device from sending further data items until the routing circuitry receives a subsequent indication that the data sink device is ready to receive the data item; and the routing circuitry being configured to route the received data item by the second data path in response to an indication that the data sink device is currently ready to receive the data item.. . ... Arm Limited

01/04/18 / #20180004678

Apparatus and method for performing address translation

An apparatus, system, and method for address translation are provided. Physical address information corresponding to virtual addresses is prefetched and stored, where at least some sequences of the virtual addresses are in a predefined order. ... Arm Limited

01/04/18 / #20180004663

Progressive fine to coarse grain snoop filter

A data processing system includes a snoop filter organized as a number of lines, each storing an address tag associated with the address of data stored in one or more caches of the system, a coherency state of the data, and presence data. A snoop controller sends snoop messages in response to data access requests. ... Arm Limited

01/04/18 / #20180004500

Systems and methods for short range wireless data transfer

Systems and methods for application level authentication are provided for use with the low energy bluetooth device and accessory. This includes receiving accessory credentials from a server, establishing a bluetooth low energy connection with the accessory, authenticating with the accessory, and lastly transferring data to the accessory. ... Arm Limited

01/04/18 / #20180004443

Accessing encoded blocks of data in memory

A method of storing encoded blocks of data in memory comprises generating headers for the encoded blocks of data. The headers are stored in memory according to a tiled layout based on tiles of plural adjacent blocks of data elements of the array of data elements. ... Arm Limited

01/04/18 / #20180004278

Power control circuitry for controlling power domains

A data processing apparatus 2 includes a plurality of power domains controlled by respective power control signals pcs. Power control circuitry 22 includes mapping circuitry which maps a plurality of power status signals pss indicative of the power status of respective power domains, and received from those power domains, to form the power control signals which are then supplied power domains. ... Arm Limited

12/28/17 / #20170371793

Cache with compressed data and tag

Cache line data and metadata are compressed and stored in first and, optionally, second memory regions, the metadata including an address tag when the compressed data fit entirely within a primary block in the first memory region, both data and metadata are retrieved in a single memory access. Otherwise, overflow data is stored in an overflow block in the second memory region. ... Arm Limited

12/28/17 / #20170371560

An apparatus for controlling access to a memory device, and a method of performing a maintenance operation within such an apparatus

A technique is described for performing a maintenance operation within an apparatus that is used to control access to a memory device. The apparatus has a storage device for storing access requests to be issued to the memory device, and maintenance circuitry for performing a maintenance operation on storage elements provided within the storage device. ... Arm Limited

12/21/17 / #20170365600

Using inter-tier vias in integrated circuits

Various implementations described herein may be directed to using inter-tier vias (ivs) in integrated circuits (ics). In one implementation, a three-dimensional (3d) ic may include a plurality of tiers disposed on a substrate layer, where the tiers may include a first tier having a first active device layer electrically coupled to first interconnect layers, and may also include a second tier having a second active device layer electrically coupled to a second interconnect layer, where the first interconnect layers include an uppermost layer that is least proximate to the first active device layer. ... Arm Limited

12/21/17 / #20170365331

Boost circuit for memory

Various implementations described herein are directed to a device having a memory cell coupled to complementary bitlines. The memory cell may store at least one data bit value associated with complementary bitline signals received via the complementary bitlines. ... Arm Limited

12/21/17 / #20170364817

Estimating a number of occupants in a region

A method for estimating a number of occupants in a region comprises receiving a time series of sensor values detected over a period of time by a motion sensor sensing motion in the region. A spread parameter indicative of the spread of the sensor values is determined. ... Arm Limited

12/21/17 / #20170364710

Apparatus and method for obfuscating power consumption of a processor

An apparatus for obfuscating power consumption associated with one or more operations of a logic circuitry of a processor. The apparatus comprises counterbalance circuitry configured to provide a second power consumption to directly counterbalance the power consumption associated with the one or more operations of the logic circuitry. ... Arm Limited

12/21/17 / #20170364461

Transferring data between memory system and buffer of a master device

A master device has a buffer for storing data transferred from, or to be transferred to, a memory system. Control circuitry issues from time to time a group of one or more transactions to request transfer of a block of data between the memory system and the buffer. ... Arm Limited

12/14/17 / #20170359589

Video data processing system

A system for encoding and decoding a sequence of frames of video data. The system includes encoding processing circuitry configured to encode a sequence of source video frames using other source frames as reference frames. ... Arm Limited

12/14/17 / #20170359338

Management of relationships between a device and a service provider

An authentication device is used to create a secure connection between an internet of things (iot) device and a service provider, so that the iot device is not limited to only the services of one specific provider or the specific services of the provider of the iot device. In addition, multiple iot devices purchased from several different providers can all be connected to the same service provider.. ... Arm Limited

12/14/17 / #20170357570

Storing arrays of data in data processing systems

In a data processing system that comprises a memory 8 comprising n memory banks 11, a memory controller is configured to store one or more n data unit×n data unit arrays of data in the memory 8 such that each data unit in each row of each n×n data unit array is stored in a different memory bank of the n memory banks 11, and such that each data unit in each column of each n×n data unit array is stored in a different memory bank of the n memory banks 11.. . ... Arm Limited

12/07/17 / #20170352165

Encoding and decoding arrays of data elements

A method of encoding a block of an array of data elements comprises selectively writing out an encoded version of the block either that is encoded using a first encoding scheme, which provides encoded blocks of non-fixed data size, or that is encoded using a second encoding scheme, which provides encoded blocks of fixed data size. The selection of which version of the encoded block to write out is based on the size of the encoded block when encoded using the first encoding scheme. ... Arm Limited

12/07/17 / #20170351517

Debugging data processing transactions

A data processing system supporting execution of transactions comprising one or more program instructions that execute to generate speculative updates is provided. The speculative updates are committed in normal operation if the transaction completes without a conflict. ... Arm Limited

12/07/17 / #20170351488

Arithmetic operation input-output equality detection

Apparatus and a corresponding method are disclosed relating to circuitry to perform an arithmetic operation on one or more input operands, where the circuitry is responsive to an equivalence of a result value of the arithmetic operation with at least one of the one or more input operands, when the one or more input operands are not an identity element for the arithmetic operation, to generate a signal indicative of the equivalence. Idempotency (between at least one input operand and the result value) is thus identified.. ... Arm Limited

12/07/17 / #20170351319

Delegating component power control

An apparatus and a corresponding method of operating the apparatus are disclosed. A component of the apparatus is capable of operating in one of at least two power modes and component power control circuitry which is communicatively coupled to the component causes the component to operate in a selected power mode of those power modes. ... Arm Limited

11/30/17 / #20170346504

Apparatus and method for generating an error code for a block comprising a plurality of data bits and a plurality of address bits

An apparatus and method are provided for generating an error code for a block comprising a plurality of data bits and a plurality of address bits. The apparatus has block generation circuitry to generate a block comprising a plurality of data bits and a plurality of address bits, and error code generation circuitry for receiving that block and a mask array comprising a plurality of mask rows, and for then applying an error code generation algorithm to generate an error code for the block. ... Arm Limited

11/30/17 / #20170344492

Address translation within a virtualised system background

A memory management unit 22, 34, 48 serves to use first stage of address translation and permission data s1 managed by a guest operating system and second stage of address translation and permission data s2 managed by a hypervisor. If there is a mismatch between the permissions (or other characteristics) provided by these different translation and permission data sets, then a speculative mismatch response is triggered. ... Arm Limited

11/30/17 / #20170344480

Method and apparatus for maintaining data coherence in a non-uniform compute device

A data processing apparatus includes one or more host processors with first processing units, one or more caches with second processing unit, a non-cache memory having a third processing unit and a reorder buffer operable to maintain data order during execution of a program of instructions. An instruction scheduler routes instructions to the processing units. ... Arm Limited

11/30/17 / #20170344367

Method and apparatus for reordering in a non-uniform compute device

A data processing apparatus includes a multi-level memory system, one or more first processing unit coupled to the memory system at a first level and one or more second processing units each coupled to the memory system at a second level. A first reorder buffer maintains data order during execution of instructions by the first and second processing units and a second reorder buffer maintains data order during execution of the instructions by an associated second processing unit. ... Arm Limited

11/30/17 / #20170344366

Method and apparatus for scheduling in a non-uniform compute device

A data processing apparatus, and method of operation thereof, for executing instructions. The apparatus includes one or more host processors, each having a first processing unit, and a multi-level memory system. ... Arm Limited

11/30/17 / #20170344342

Rounding circuitry and method

A data processing apparatus for performing rounding on an input value to produce a rounded form output value includes floor calculation circuitry that receives the input value in redundant-representation and generates two candidates of a floor of the input value in non-redundant representation. Ceiling calculation circuitry receives the input value in redundant-representation and generates two candidates of a ceiling of the input value in non-redundant representation. ... Arm Limited

11/23/17 / #20170338836

Logical interleaver

Various implementations described herein are directed to a memory device. The memory device may include a first interleaving circuit that receives data words and generates a first error correction code based on the received data words. ... Arm Limited

11/23/17 / #20170337133

Cache entry replacement

A data processing system 2 incorporates a cache system 4 having a cache memory 6 and a cache controller 10, 12, 14, 16, 18. The cache controller selects for cache entry eviction using a primary eviction policy. ... Arm Limited

11/23/17 / #20170337115

Instruction sampling within transactions

A data processing apparatus (4) includes processing circuitry (6) for executing program instructions that form part of a transaction which executes to generate speculative updates and to commit the speculative updates if the transaction completes without a conflict. Instruction sampling circuitry (44) captures instruction diagnostic data (idd) relating to execution of a sampled instruction. ... Arm Limited

11/16/17 / #20170331465

General purpose receiver

. . Various implementations described herein are directed to circuit. The circuit may include a first input stage having first devices and a first path for slow slew input detection. ... Arm Limited

11/16/17 / #20170330372

Graphics processing systems

A graphics processing pipeline comprises vertex shading circuitry that operates to vertex shade position attributes of vertices of a set of vertices to be processed by the graphics processing pipeline, to generate, inter alia, a separate vertex shaded position attribute value for each view of the plural different views. Tiling circuitry then determines for the vertices that have been subjected to the first vertex shading operation, whether the vertices should be processed further. ... Arm Limited

11/16/17 / #20170329627

Monitoring utilization of transactional processing resource

An apparatus (2) may have a processing element (4) for performing data access operations to access data from at least one storage device (10, 12, 14). The processing element may have at least one transactional processing resource (10, 18) supporting processing of a transaction in which data accesses are performed speculatively following a transaction start event and for which the speculative results are committed in response to a transaction end event. ... Arm Limited

11/16/17 / #20170329626

Apparatus with at least one resource having thread mode and transaction mode, and method

An apparatus (2) has processing circuitry (6) having access to a first processing resource (20-0) and a second processing resource (20-3). A first thread can be processed using the first processing resource. ... Arm Limited

11/16/17 / #20170329613

Method of and apparatus for providing an output surface in a data processing system

An apparatus for compositing an output surface (10) from a plurality of input surfaces (1, 2, 3, 4) includes processing circuitry and a composition processor. The processing circuitry is configured to determine whether two or more input surfaces of the plurality of input surfaces (1, 2, 3, 4) can be combined into a single secondary surface for provision to the composition processor. ... Arm Limited

11/16/17 / #20170329603

Conditional selection of data elements

An apparatus performs an operation on a register, and then conditionally selects either that register or a further register on which no operation has been performed. The apparatus includes a decoder that decodes a conditional select instruction that specifies a primary source register, a secondary source register, a destination register, a condition, and an operation to be performed on a data element from the secondary source register. ... Arm Limited

10/26/17 / #20170309027

Method and apparatus for processing graphics

A graphics processing system sorts graphics primitives for rendering into lists corresponding to different sub-regions of a render output to be generated, each list indicating primitives to be processed for the render output. A primitive list building unit divides a render target into various sub-regions, determines which sub-regions a primitive falls within and adds the primitive to the primitive lists corresponding to those sub-regions. ... Arm Limited

10/26/17 / #20170308491

Apparatus and method for combining trace data from a plurality of trace sources

An apparatus and method are provided for combining trace data from a plurality of trace sources. The apparatus has an input interface to receive trace data from the plurality of trace sources, and an output interface from which to issue a trace stream incorporating the trace data from each of those trace sources. ... Arm Limited

10/26/17 / #20170308478

Caching data from a non-volatile memory

A data processing system 2 includes interconnect circuitry 10 providing a plurality of memory transaction paths between one or more transaction masters, including a processor 4, debugging circuitry 6 and a dma unit 8, and one or more transaction slaves including a non-volatile memory 12, a dram memory 18 and an i/o interface 20. A cache memory 26 is provided between the interconnect circuitry 10 and the non-volatile memory 12. ... Arm Limited

10/12/17 / #20170294222

Storage bitcell with isolation

A storage bitcell comprising a first inverter cross-coupled with a second inverter, both the first and second inverter being in a path between a first potential and a second potential; wherein a first isolator is connected in the path between the first inverter and the first potential. The storage bitcell has particular application as static random-access memory (sram) circuitry.. ... Arm Limited

10/12/17 / #20170293567

Proxy identifier for data access operation

An apparatus comprises processing circuitry to process data access operations specifying a virtual address of data to be loaded from or stored to a data store, and proxy identifier determining circuitry to determine a proxy identifier for a data access operation to be processed by the data access circuitry, the proxy identifier having fewer bits than a physical address corresponding to the virtual address specified by the data access operation. The processing circuitry comprises at least one buffer to buffer information (including the proxy identifier) associated with one or more pending data access operations awaiting processing. ... Arm Limited

10/12/17 / #20170293541

Self-testing in a processor core

Apparatus and a method for processor core self-testing are disclosed. The apparatus comprises processor core circuitry to perform data processing operations by executing data processing instructions. ... Arm Limited

10/12/17 / #20170293467

Apparatus and method for supporting a conversion instruction

A data processing system 2 includes instruction decoder circuitry 12 responsive to a conversion instruction fcvtjs to convert a double precision floating point number into a 32-bit integer number. Right shifting circuitry 28 performs a right shift upon at least part of the input number and left shifting circuitry 32 performs a left shift of at least part of the input number. ... Arm Limited

10/05/17 / #20170287101

Graphics processing systems

. . A tile-based graphics processing pipeline includes rendering circuitry for rendering graphics fragments to generate rendered fragment data. Each graphics fragment has associated with it a set of sampling positions to be rendered. ... Arm Limited

10/05/17 / #20170286421

Indexing entries of a storage structure shared between multiple threads

An apparatus has processing circuitry for processing instructions from multiple threads. A storage structure is shared between the threads and has a number of entries. ... Arm Limited

10/05/17 / #20170286116

Instruction prefetching

A data processing apparatus has prefetch circuitry for prefetching instructions from a data store into an instruction queue. Branch prediction circuitry is provided for predicting outcomes of branch instructions and the prefetch circuitry may prefetch instructions subsequent to the branch based on the predicted outcome. ... Arm Limited

10/05/17 / #20170286107

Shared resources in a data processing apparatus for executing a plurality of threads

A data processing apparatus (100) executes threads and includes a general program counter (pc) (120) identifying an instruction to be executed for at least a subset of the threads. Each thread has a thread pc (184). ... Arm Limited

10/05/17 / #20170285725

Data processing

A data processing apparatus comprises processing circuitry configured to predict whether a region of output data to be generated by the apparatus for a current set of output data will be similar to a region of output data generated and stored in memory for a previous set of output data. When it is predicted that the new region of output data will be similar to the previous region of output data, the new region of output data is prevented from being generated and the previous region of output data is used for the current set of output data instead. ... Arm Limited

09/28/17 / #20170280307

Apparatus and method of tracking call paths

A data processing apparatus is provided. Call path storage circuitry stores an identifier of a call path and processing circuitry executes a current group of instructions from a plurality of groups of instructions. ... Arm Limited

09/28/17 / #20170277817

Computer implemented system and method for reducing failure in time soft errors of a circuit design

A computer implemented system and method is provided for reducing failure in time (fit) errors associated with one or more sequential devices of a circuit design for a process technology. The method comprises receiving an input data file that includes register transfer level (rtl) data of the circuit design. ... Arm Limited

09/28/17 / #20170277537

Processing mixed-scalar-vector instructions

Processing circuitry supports overlapped execution of vector instructions when at least one beat of a first vector instruction is performed in parallel with at least one beat of a second vector instruction. The processing circuitry also supports mixed-scalar-vector instructions for which one of a destination register and one or more source registers is a vector register and another is a scalar register. ... Arm Limited

09/21/17 / #20170272774

Video data processing system

An apparatus for decoding a sequence of frames of encoded video data includes parsing circuitry configured to parse the encoded video image data for a frame to derive encoding information for each block of the frame. The apparatus also includes feedback circuitry configured to feed back, to the parsing circuitry, encoding information for a frame for use when parsing the encoded video image data of the next frame. ... Arm Limited








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