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Cavium Inc patents


Recent patent applications related to Cavium Inc. Cavium Inc is listed as an Agent/Assignee. Note: Cavium Inc may have other listings under different names/spellings. We're not affiliated with Cavium Inc, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "C" | Cavium Inc-related inventors


Apparatus and method for scalable and flexible wildcard matching in a network switch

A network switch to support scalable and flexible wildcard matching (wcm) comprises a packet processing pipeline including a plurality of packet processing units each configured to generate a master key for a wcm request to a memory pool and process a packet based on looked up wcm rules. The memory pool includes a plurality of memory groups each configured to maintain a plurality of wcm tables to be searched in one or more sram memory tiles of the memory group, format the master key generated by the packet processing unit into a compact key based on a bitmap per user configuration, hash the formatted compact key and perform wildcard matching with the wcm tables stored in the one or more sram memory tiles of the memory group using the formatted compact key, process and provide the wcm rules from the wildcard matching to the requesting packet processing unit.. ... Cavium Inc

Apparatus and method for scalable and flexible access control list lookup in a network switch

A network switch to support scalable and flexible access control list (acl) lookup comprises a packet processing pipeline including a plurality of packet processing units each configured to generate a master key for an acl lookup request to a memory pool and process a received packet based on acl search results. The network switch further includes said memory pool including a plurality of memory groups each configured to maintain a plurality of acl tables to be searched in one or more sram memory tiles of the memory group, accept and format the master key generated by the packet processing unit into a compact key based on a bitmap per user configuration, hash the formatted compact key and search the acl tables stored in the one or more sram memory tiles using the formatted compact key, process and provide the acl search results to the requesting packet processing unit.. ... Cavium Inc

Method and system for reconfigurable parallel lookups using multiple shared memories

Embodiments of the present invention relate to multiple parallel lookups using a pool of shared memories by proper configuration of interconnection networks. The number of shared memories reserved for each lookup is reconfigurable based on the memory capacity needed by that lookup. ... Cavium Inc

Barrel compactor system, method and device

A packet processing system having a barrel compactor that extracts a desired data subset from an input dataset (e.g. An incoming packet). ... Cavium Inc

Instruction ordering for in-progress operations

Execution of the memory instructions is managed using memory management circuitry including a first cache that stores a plurality of the mappings in the page table, and a second cache that stores entries based on virtual addresses. The memory management circuitry executes operations from the one or more modules, including, in response to a first operation that invalidates at least a first virtual address, selectively ordering each of a plurality of in progress operations that were in progress when the first operation was received by the memory management circuitry, wherein a position in the ordering of a particular in progress operation depends on either or both of: (1) which of one or more modules initiated the particular in progress operation, or (2) whether or not the particular in progress operation provides results to the first cache or second cache.. ... Cavium Inc

Phantom queue link level load balancing system, method and device

A data processing system includes a phantom queue for each of a plurality of output ports each associated with an output link for outputting data. The phantom queues receive/monitor traffic on the respective ports and/or the associated links such that the congestion or traffic volume on the output ports/links is able to be determined by a congestion mapper coupled with the phantom queues. ... Cavium Inc

Hierarchical hardware linked list approach for multicast replication engine in a network asic

A multicast rule is represented in a hierarchical linked list with n tiers. Each tier or level in the hierarchical linked list corresponds to a network layer of a network stack that requires replication. ... Cavium Inc

Fast hardware switchover in a control path in a network asic

A multicast destination table contains a list of links. The list of links includes the main link that is currently in use and alternate links to reach the same destination. ... Cavium Inc

Systems and methods for secure machine for hardware security module (hsm) adapter

A new approach is proposed that contemplates systems and methods to support a secure machine environment on a hsm adapter, which enables an end user of the hsm adapter to run its own security sensitive applications securely via a secure machine within the hsm adapter and to gain access to its security measures. During operation, the secure machine receives commands from an application running on a host outside of the hsm adapter and executes a security sensitive application within the secure machine environment. ... Cavium Inc

Compiler architecture for programmable application specific integrated circuit based network devices

A processing network including a plurality of lookup and decision engines (ldes) each having one or more configuration registers and a plurality of on-chip routers forming a matrix for routing the data between the ldes, wherein each of the on-chip routers is communicatively coupled with one or more of the ldes. The processing network further including an lde compiler stored on a memory and communicatively coupled with each of the ldes, wherein the lde compiler is configured to generate values based on input source code that when programmed into the configuration registers of the ldes cause the ldes to implement the functionality defined by the input source code.. ... Cavium Inc

Systems and methods for perfect forward secrecy (pfs) traffic monitoring via a hardware security module

A new approach is proposed to support monitoring perfect forward secrecy (pfs) network traffic by utilizing a hardware security module (hsm) appliance. Here, the hsm appliance is a high-performance, federal information processing standards (fips) 140-compliant security hardware with embedded firmware, which can be used for management and sharing of ephemeral keys used in a secured pfs communication session between two parties. ... Cavium Inc

Protocol independent programmable switch (pips) for software defined data center networks

A software-defined network (sdn) system, device and method comprise one or more input ports, a programmable parser, a plurality of programmable lookup and decision engines (ldes), programmable lookup memories, programmable counters, a programmable rewrite block and one or more output ports. The programmability of the parser, ldes, lookup memories, counters and rewrite block enable a user to customize each microchip within the system to particular packet environments, data analysis needs, packet processing functions, and other functions as desired. ... Cavium Inc

Session based packet mirroring in a network asic

A forwarding pipeline of a forwarding engine includes a mirror bit mask vector with one bit per supported independent mirror session. Each bit in the mirror bit mask vector can be set at any point in the forwarding pipeline when the forwarding engine determines that conditions for a corresponding mirror session are met. ... Cavium Inc

Engine architecture for processing finite automata

An engine architecture for processing finite automata includes a hyper non-deterministic automata (hna) processor specialized for non-deterministic finite automata (nfa) processing. The hna processor includes a plurality of super-clusters and an hna scheduler. ... Cavium Inc

12/28/17 / #20170371799

Managing virtual-address caches for multiple memory page sizes

A translation lookaside buffer stores information indicating respective page sizes for different translations. A virtual-address cache module manages entries, where each entry stores a memory block in association with a virtual address and a code representing at least one page size of a memory page on which the memory block is located. ... Cavium Inc

12/21/17 / #20170364541

Method and apparatus for table aging in a network switch

Embodiments of the present invention relate to a centralized table aging module that efficiently and flexibly utilizes an embedded memory resource, and that enables and facilitates separate network controllers. The centralized table aging module performs aging of tables in parallel using the embedded memory resource. ... Cavium Inc

11/30/17 / #20170344880

Systems and methods for vectorized fft for multi-dimensional convolution operations

A new approach is proposed to support efficient convolution for deep learning by vectorizing multi-dimensional input data for multi-dimensional fast fourier transform (fft) and direct memory access (dma) for data transfer. Specifically, a deep learning processor (dlp) includes a plurality of tensor engines each configured to perform convolution operations by applying one or more kernels on multi-dimensional input data for pattern recognition and classification based on a neural network, wherein each tensor engine includes, among other components, one or more vector processing engines each configured to vectorize the multi-dimensional input data at each layer of the neural network to generate a plurality of vectors and to perform multi-dimensional fft on the generated vectors and/or the kernels to create output for the convolution operations. ... Cavium Inc

11/23/17 / #20170338822

Process-compensated level-up shifter circuit

A level-up shifter circuit is suitable for high speed and low power applications. The circuit dissipates almost no static power, or leakage current, compared to conventional designs and can preserve the signal's duty cycle even at high data rates. ... Cavium Inc

11/16/17 / #20170331664

Methods and apparatus for frequency offset estimation

Methods and apparatus for frequency offset estimation are disclosed. In an exemplary embodiment, a method includes determining a demodulation reference signal (dmrs) frequency offset estimate from dmrs symbols in a received signal, and determining a cyclic prefix (cp) frequency offset estimate from cyclic prefix values in the received signal. ... Cavium Inc

11/16/17 / #20170329731

Method and apparatus for efficient and flexible direct memory access

Method and system embodying the method for a direct memory access between a data storage and a data processing device via one or more direct memory access units, comprising transferring data between the data storage and a first direct memory access engine of a respective one or more direct memory access units and providing the data for a second direct memory access engine of the respective one or more direct memory access units; and transferring the data provided by the first direct memory access engine by a second direct memory access engine to the data processing device via the second direct memory access engine is disclosed.. . ... Cavium Inc

11/09/17 / #20170322886

Admission control for memory access requests

Managing memory access requests for a plurality of processor cores includes: storing admission control information for determining whether or not to admit a predetermined type of memory access request into a shared resource that is shared among the processor cores and includes one or more cache levels of a hierarchical cache system and at least one memory controller for accessing a main memory; determining whether or not a memory access request of the predetermined type made on behalf of a first processor core should be admitted into the shared resource based at least in part on the stored admission control information; and updating the admission control information based on a latency of a response to a particular memory access request admitted into the shared resource, where the updating depends on whether the response originated from a particular cache level included in the shared resource or from the main memory.. . ... Cavium Inc

11/09/17 / #20170322885

Managing memory access requests with prefetch for streams

Managing memory access requests to a cache system including one or more cache levels that are configured to store cache lines that correspond to memory blocks in a main memory includes: storing stream information identifying recognized streams that were recognized based on previously received memory access requests, where one or more of the recognized streams comprise strided streams that each have an associated strided prefetch result corresponding to a stride that is larger than or equal to a size of a single cache line; and determining whether or not a next cache line prefetch request corresponding to a particular memory access request will be made based at least in part on whether or not the particular memory access request matches a strided prefetch result for at least one strided stream, and a history of past next cache line prefetch requests.. . ... Cavium Inc

11/09/17 / #20170322828

Systems and methods for virtio based optimization of data packet paths between a virtual machine and a network device for live virtual machine migration

A new approach is proposed that contemplates systems and methods to support virtio-based data packet path optimization for live virtual machine (vm) migration for linux. Specifically, a data packet receiving (rx) path and a data packet transmitting (tx) path between a vm running on a host and a virtual function (vf) driver configured to interact with a physical network device of the host to receive and transmit communications dedicated to the vm are both optimized to implement a zero-copy solution to reduce overheads in packet processing. ... Cavium Inc

10/26/17 / #20170308408

Method and apparatus for dynamic virtual system on chip

A processor device comprises a plurality of virtual systems on chip, configured to utilize resources of a plurality of resources in accordance with a resource alignment between the plurality of virtual systems on chip and the plurality of resources. The processor device may further comprises a resource aligning unit configured to modify the resource alignment, dynamically, responsive to at least one event. ... Cavium Inc

10/05/17 / #20170286315

Managing translation invalidation

Managing translation invalidation includes: in response to determining that a first invalidation message (im) applies to a subset of virtual addresses (vas) consisting of fewer than all vas associated with a first set of translation context (tc) values, searching va-indexed structure(s) to find and invalidate any entries that correspond to a va in the subset; in response to determining that a second im applies to all vas associated with a second set of tc values and that no entry exists in invalidation-tracking structure(s) corresponding to the second set, bypassing searching any va-indexed structure(s); and in response to determining that a third im applies to all vas associated with a third set of tc values and that at least one entry exists in the invalidation-tracking structure(s) corresponding to the third set, storing invalidation information in the invalidation-tracking structure(s) to invalidate the third set and delaying searching any va-indexed structure(s).. . ... Cavium Inc

10/05/17 / #20170286296

Managing synonyms in virtual-address caches

A virtual-address cache module receives at least a portion of a virtual address and in response indicates a hit or a miss. A first cache structure stores only memory blocks with virtual addresses that are members of a set of multiple synonym virtual addresses that have all been previously received by the virtual-address cache module during the operating period, where each member of a particular set of multiple synonym virtual addresses translates to a common physical address, and a memory block with the common physical address is stored in at most a single storage location within the first cache structure. ... Cavium Inc

09/07/17 / #20170257327

Multiple ethernet ports and port types using a shared data path

In an embodiment an interface unit includes a transmit pipeline configured to transmit egress data, and a receive pipeline configured to receive ingress data. At least one of the transmit pipeline and the receive pipeline being may be configured to provide shared resources to a plurality of ports. ... Cavium Inc

09/07/17 / #20170255566

Method and system for compressing data for a translation look aside buffer (tlb)

An embodiment of the present disclosure includes a method for compressing data for a translation look aside buffer (tlb). The method includes: receiving an identifier at a content addressable memory (cam), the identifier having a first bit length; compressing the identifier based on a location within the cam the identifier is stored, the compressed identifier having a second bit length, the second bit length being smaller than the first bit length; and mapping at least the compressed identifier to a physical address in a buffer.. ... Cavium Inc

08/24/17 / #20170244816

Method of using bit vectors to allow expasion and collapse of header layers within packets for enabling flexible modifications and an apparatus thereof

Embodiments of the apparatus for modifying packet headers relate to a use of bit vectors to allow expansion and collapse of protocol headers within packets for enabling flexible modification. A rewrite engine expands each protocol header into a generic format and applies various commands to modify the generalized protocol header. ... Cavium Inc

08/24/17 / #20170242624

Apparatus and method for optimized n-write/1-read port memory design

An optimized design of n-write/1-read port memory comprises a memory unit including a plurality of memory banks each having one write port and one read port configured to write data to and read data from the memory banks, respectively. The memory further comprises a plurality of write interfaces configured to carry concurrent write requests to the memory unit for a write operation, wherein the first write request is always presented by its write interface directly to a crossbar, wherein the rest of the write requests are each fed through a set of temporary memory modules connected in a sequence before being presented to the crossbar. ... Cavium Inc

08/24/17 / #20170242619

Method and system for reconfigurable parallel lookups using multiple shared memories

Embodiments of the present invention relate to multiple parallel lookups using a pool of shared memories by proper configuration of interconnection networks. The number of shared memories reserved for each lookup is reconfigurable based on the memory capacity needed by that lookup. ... Cavium Inc

08/24/17 / #20170242618

Method and system for reconfigurable parallel lookups using multiple shared memories

Embodiments of the present invention relate to multiple parallel lookups using a pool of shared memories by proper configuration of interconnection networks. The number of shared memories reserved for each lookup is reconfigurable based on the memory capacity needed by that lookup. ... Cavium Inc

08/17/17 / #20170237691

Apparatus and method for supporting multiple virtual switch instances on a network switch

A network switch to support multiple virtual switch instances comprises a control cpu configured to run a plurality of network switch control stacks, wherein each of the network switch control stacks is configured to manage and control operations of one or more virtual switch instances of a switching logic circuitry of the network switch. The network switch further includes said switching logic circuitry partitioned into a plurality of said virtual switch instances, wherein each of the virtual switch instances is provisioned and controlled by one of the network switch control stacks and is dedicated to serve and route data packets for a specific client of the network switch.. ... Cavium Inc

08/10/17 / #20170228183

Method and apparatus for virtualization

A virtual system on chip (vsoc) is an implementation of a machine that allows for sharing of underlying physical machine resources between different virtual systems. A method or corresponding apparatus of the present invention relates to a device that includes a plurality of virtual systems on chip and a configuring unit. ... Cavium Inc

08/10/17 / #20170228007

Method and apparatus for managing global chip power on a multicore system on chip

According to at least one example embodiment, a method and corresponding apparatus for controlling power in a multi-core processor chip include: accumulating, at a controller within the multi-core processor chip, one or more power estimates associated with multiple core processors within the multi-core processor chip. A global power threshold is determined based on a cumulative power estimate, the cumulative power estimate being determined based at least in part on the one or more power estimates accumulated. ... Cavium Inc

08/03/17 / #20170220523

Methods and apparatus for providing an fft engine using a reconfigurable single delay feedback architecture

Methods and apparatus for providing an fft engine using a reconfigurable single delay feedback architecture. In one aspect, an apparatus includes a radix-2 (r2) single delay feedback (sdf) stage that generates a radix-2 output and a radix-3 (r3) sdf stage that generates a radix-3 output. ... Cavium Inc

08/03/17 / #20170220477

Method and apparatus for determining metric for selective caching

System and method determining metric for selective caching, comprising determining a result of an access to a cache for at least one tracked attribute; determining a count value for the at least one tracked attribute in a translation look-aside buffer entry corresponding to the access to the cache in accordance with the determined result; comparing the count value for the at least one tracked attribute with a threshold associated with the at least one tracked attribute; assigning the metric of sticky property to a cache line corresponding to the translation look-aside buffer entry when the count value for at least one of the at least one tracked attribute exceeds the threshold. Selective caching then assigns different protection status to the cache lines with and without sticky property; and evicting a cache line in accordance with a cache eviction policy starting with the cache lines with the lowest protection status.. ... Cavium Inc

07/27/17 / #20170212689

Packet processing system, method and device utilizing memory sharing

A packet processing system having a control path memory of a control path subsystem and a datapath memory of a datapath subsystem. The datapath subsystem stores packet data of incoming packets and the control path subsystem performs matches of a subset of packet data, or a hash of the packet data, against the contents of a the control path memory in order to process the packets. ... Cavium Inc

07/20/17 / #20170206171

Collapsed address translation with multiple page sizes

A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (gvas), which are translated to guest physical addresses (gpas). ... Cavium Inc

07/06/17 / #20170195900

Methods and apparatus for configuring a front end to process multiple sectors with multiple radio frequency frames

Methods and apparatus for configuring a front end to process multiple sectors with multiple radio frequency frames. In an exemplary embodiment, a method includes decoding instructions included in a job description list, and configuring one or more processing functions of a transceiver to process a radio signal associated with a selected sector based on the decoded instructions. ... Cavium Inc

07/06/17 / #20170195281

Methods and apparatus for twiddle factor generation for use with a programmable mixed-radix dft/idft processor

Twiddle factor generation for use with a programmable mix-radix vector processor (“pvp”) capable of calculating discrete fourier transform (“dft/idft”) values. In an exemplary embodiment, an apparatus includes look-up table logic that receives twiddle control factors and outputs a selected twiddle factor scaler value (tfsv), a base vector generator that generates a base vector values based on the selected tfsv, and a twiddle column generator that generates a twiddle vector from the base vector.. ... Cavium Inc

07/06/17 / #20170192936

Methods and apparatus for providing a programmable mixed-radix dft/idft processor using vector engines

A programmable vector processor (“pvp”) capable of calculating discrete fourier transform (“dft/idft”) values is disclosed. In an exemplary embodiment, an apparatus includes a memory bank and a vector data path pipeline coupled to the memory bank. ... Cavium Inc

07/06/17 / #20170192935

Methods and apparatus for a vector memory subsystem for use with a programmable mixed-radix dft/idft processor

A vector memory subsystem for use with a programmable mix-radix vector processor (“pvp”) capable of calculating discrete fourier transform (“dft/idft”) values. In an exemplary embodiment, an apparatus includes a vector memory bank and a vector memory system (vms) that generates input memory addresses that are used to store input data into the vector memory bank. ... Cavium Inc

06/29/17 / #20170187623

Method of identifying internal destinations of network packets and an apparatus thereof

Embodiments of the apparatus of identifying internal destinations of network packets relate to a network chip that allows flexibility in handling packets. The handling of packets can be a function of what the packet contents are or where the packets are from. ... Cavium Inc

06/15/17 / #20170171854

Methods and apparatus for providing soft and blind combining for pusch cqi processing

Methods and apparatuses for providing soft and blind combining for pusch cqi processing are disclosed. In an exemplary embodiment, a method includes generating a plurality of hypothetical rank indicator (ri) values associated with a user equipment (ue), and concurrently soft-combining channel quality information (cqi) and ri information associated with the ue that is contained in a received subframe of symbols. ... Cavium Inc

06/15/17 / #20170170930

Methods and apparatus for providing soft and blind combining for pusch acknowledgement (ack) processing

Methods and apparatus for providing soft and blind combining for pusch acknowledgement (ack) processing. In an exemplary embodiment, a method includes soft-combining acknowledgement (ack) bits received from a ue that are contained in a received sub-frame of symbols. ... Cavium Inc

06/08/17 / #20170161402

Systems and methods for dynamic regression test generation using coverage-based clustering

A new approach is proposed that contemplates systems and methods to support dynamic regression test generation for an ic design based upon coverage-based clustering of rtl modules in the design. First, coverage data for code coverage by a plurality of rtl modules in the ic design are collected and a plurality of clusters of related rtl modules of the ic design are generated based on statistical analysis of the collected coverage data and hierarchal information of the rtl modules. ... Cavium Inc

06/08/17 / #20170161215

Packet processing system, method and device utilizing a port client chain

A packet processing system having each of a plurality of hierarchical clients and a packet memory arbiter serially communicatively coupled together via a plurality of primary interfaces thereby forming a unidirectional client chain. This chain is then able to be utilized by all of the hierarchical clients to write the packet data to or read the packet data from the packet memory.. ... Cavium Inc

04/06/17 / #20170097895

Input output value prediction with physical or virtual addressing for virtual environment

Method and system embodying the method for input/output value determination at a processor core, comprising generating an i/o instruction comprising at least a physical or a virtual address; comparing the address with a relevant database of i/o devices addresses. When the comparing is successful determining the i/o device or a state on the i/o device to receive the i/o instruction in accordance with the address; setting a value of a first register to a value identifying the determined i/o device or the state on the i/o device; predicting a value to be set in a second register in accordance with the address; and setting a value of a third register. ... Cavium Inc

03/16/17 / #20170075845

Systems and methods for offloading link aggregation to a host bus adapter (hba) in single root i/o virtualization (sriov) mode

A new approach is proposed to offload of link aggregation from a host to a hba in sriov mode. The hba first creates one or more link aggregation offload engines each having one or more physical ports and to establish a first link between a vm running on the host and one of the link aggregation offload engines for network data transmission with the vm. ... Cavium Inc

03/16/17 / #20170075754

Apparatus and method for parallel crc units for variably-sized data frames

A cyclic redundancy check (crc) device configured to support parallel calculation of a crc value for a data frame comprises a plurality of crc processing units each configured to accept one of a plurality of data segments of the data frame of a variable size that can be unknown to the crc device beforehand and generate one of plurality of partial crc values in parallel with rest of the crc processing units over multiple clock cycles/iterations. The crc device further comprises an integration component configured to integrate the plurality of partial crc values from the plurality of crc processing units into one final crc value for the data frame, wherein the final crc value is attached to the data frame for error checking during storage or transmission of the data frame.. ... Cavium Inc

03/02/17 / #20170063959

Method and apparatus for providing a low latency transmission system using adjustable buffers

One aspect of the present invention discloses a network system capable of transmitting and processing audio video (“a/v”) data with enhanced quality of service (“qos”). The network system includes a transmitter, a transmission channel, an adjustable decoder buffer, and a decoder. ... Cavium Inc

03/02/17 / #20170063808

Systems and methods for offloading ipsec processing to an embedded networking device

A new approach is proposed that contemplates systems and methods to support a mechanism to offload ipsec/ike processing of virtual machines (vms) running on a host to an embedded networking device, which serves as a hardware accelerator for the vms that need to have secured communication with a remote device/server over a network. By utilizing a plurality of its software and hardware features, the embedded networking device is configured to perform all offloaded ipsec operations on data packets transferred between the host and the remote device over the network as required for the secured communication before the data packets can be transmitted over the network. ... Cavium Inc

03/02/17 / #20170063692

Method and apparatus for providing a low latency transmission system using adaptive buffering estimation

One aspect of the present invention discloses a network system capable of transmitting and processing audio video (“a/v”) data with enhanced quality of service (“qos”). The network system includes a transmitter, a transmission channel, an adjustable decoder buffer, and a decoder. ... Cavium Inc

01/26/17 / #20170024346

Apparatus and method for on-chip crossbar design in a network switch using benes network

An on-chip crossbar of a network switch comprising a central arbitration component configured to allocate packet data requests received from destination port groups to memory banks. The on-chip crossbar further comprises a benes routing network comprising a forward network having a plurality of pipelined forward routing stages and a reverse network, wherein the benes routing network retrieves the packet data from the memory banks coupled to input of the benes routing network and route the packet data to the port groups coupled to output of the benes routing network. ... Cavium Inc

01/26/17 / #20170024159

Method and apparatus for virtualization

A virtual system on chip (vsoc) is an implementation of a machine that allows for sharing of underlying physical machine resources between different virtual systems. A method or corresponding apparatus of the present invention relates to a device that includes a plurality of virtual systems on chip and a configuring unit. ... Cavium Inc

01/05/17 / #20170003905

Local instruction ordering

A method for managing an observed order of instructions in a computing system includes utilizing an overloaded memory barrier instruction to specify whether a global ordering constraint or a local ordering constraint is enforced.. . ... Cavium Inc








ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009



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