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Centipede Semi Ltd patents


Recent patent applications related to Centipede Semi Ltd. Centipede Semi Ltd is listed as an Agent/Assignee. Note: Centipede Semi Ltd may have other listings under different names/spellings. We're not affiliated with Centipede Semi Ltd, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "C" | Centipede Semi Ltd-related inventors


Memory access control for parallelized processing

A processor includes a hardware-implemented pipeline and parallelization circuitry. The pipeline processes program code. ... Centipede Semi Ltd

Run-time parallelization of code execution based on an approximate register-access specification

A method includes, in a processor (20) that processes instructions of program code, processing a first segment of the instructions. One or more destination registers are identified in the first segment using an approximate specification of register access by the instructions. ... Centipede Semi Ltd

Micro-op fusion for non-adjacent instructions

Method(s) for up/down fusion and/or pseudo-fusion of micro-operations are performed in a hardware processor configured to execute program code. A mergeable pair of micro-operations is identified in a sequence of micro-operations of the program code. ... Centipede Semi Ltd

Single-thread processing of multiple code regions

A method includes retrieving to a pipeline of a processor first instructions of program code from a first region in the program code. Before fully determining a flow-control path, which is to be traversed within the first region until exit from the first region, a beginning of a second region in the code that is to be processed following the first region is predicted, and second instructions begin to be retrieved to the pipeline from the second region. ... Centipede Semi Ltd

Micro-op fusion for non-adjacent instructions

Method(s) for up/down fusion and/or pseudo-fusion of micro-operations are performed in a hardware processor configured to execute program code. A mergeable pair of micro-operations is identified in a sequence of micro-operations of the program code. ... Centipede Semi Ltd

Flushing in a parallelized processor

A method includes, in a processor having a pipeline, fetching instructions of program code at run-time, in an order that is different from an order-of-appearance of the instructions in the program code. The instructions are divided into segments having segment identifiers (ids). ... Centipede Semi Ltd

Sequential monitoring and management of code segments for run-time parallelization

A processor includes an instruction pipeline and control circuitry. The instruction pipeline is configured to process instructions of program code. ... Centipede Semi Ltd

Processor with efficient reorder buffer (rob) management

A method includes, in a pipeline of a processor, writing instructions of a single software thread that are pending for execution into a reorder buffer (rob) in accordance with a single write position, and incrementing the single write position to point to a location in the rob for a next instruction to be written. The instructions, which were written in accordance with the single write position, are removed from first and second different locations in the rob, and the first and second locations are incremented.. ... Centipede Semi Ltd

Single-thread speculative multi-threading

A processor includes a pipeline and control circuitry. The pipeline is configured to process instructions of program code and includes one or more fetch units. ... Centipede Semi Ltd

Run-time code parallelization with monitoring of repetitive instruction sequences during branch mis-prediction

A processor includes an execution pipeline and monitoring circuity. The execution pipeline is configured to execute instructions of program code. ... Centipede Semi Ltd

Speculative multi-threading trace prediction

A method for trace prediction includes using trace prediction to predict a trace specifying branch decisions. When a branch misprediction is detected, trace prediction is terminated and prediction is continued using branch prediction.. ... Centipede Semi Ltd

Run-time code parallelization with independent speculative committing of instructions per segment

A method includes, in a processor that processes multiple segments of a sequence of instructions of program code, wherein each segment is defined as either speculative or non-speculative, dispatching the instructions of the segments into at least one instruction buffer. The instructions of the segments are executed, and, in each segment, at least some of the executed instructions of the segment are speculatively-committed from the at least one instruction buffer independently of any other segment. ... Centipede Semi Ltd

Hardware-based run-time mitigation of blocks having multiple conditional branches

A method includes, in a processor, processing a sequence of pre-compiled instructions by an instruction pipeline of the processor. A first block of instructions is identified in the instructions flowing via the pipeline. ... Centipede Semi Ltd

Hardware-based run-time mitigation of conditional branches

A method includes, in a processor, processing a sequence of pre-compiled instructions by an instruction pipeline of the processor. A first block of instructions is identified in the instructions flowing via the pipeline. ... Centipede Semi Ltd

01/12/17 / #20170010973

Processor with efficient processing of load-store instruction pairs

A method includes, in a processor, processing program code that includes memory-access instructions, wherein at least some of the memory-access instructions include symbolic expressions that specify memory addresses in an external memory in terms of one or more register names. At least a store instruction and a subsequent load instruction that access the same memory address in the external memory are identified, based on respective formats of the memory addresses specified in the symbolic expressions. ... Centipede Semi Ltd

01/12/17 / #20170010972

Processor with efficient processing of recurring load instructions

A method includes, in a processor, processing program code that includes memory-access instructions, wherein at least some of the memory-access instructions include symbolic expressions that specify memory addresses in an external memory in terms of one or more register names. At least first and second load instructions that access a same memory address in the external memory are identified in the program code, based on respective formats of the memory addresses specified in the symbolic expressions of the load instructions. ... Centipede Semi Ltd

01/12/17 / #20170010971

Processor with efficient processing of recurring load instructions from nearby memory addresses

A method includes, in a processor, processing program code that includes memory-access instructions, wherein at least some of the memory-access instructions include symbolic expressions that specify memory addresses in an external memory in terms of one or more register names. Based on respective formats of the memory addresses specified in the symbolic expressions, a sequence of load instructions that access a predictable pattern of memory addresses in the external memory is identified. ... Centipede Semi Ltd

01/12/17 / #20170010892

Processor with efficient memory access

A method includes, in a processor, processing program code that includes memory-access instructions, wherein at least some of the memory-access instructions include symbolic expressions that specify memory addresses in an external memory in terms of one or more register names. A relationship between the memory addresses accessed by two or more of the memory-access instructions is identified, based on respective formats of the memory addresses specified in the symbolic expressions. ... Centipede Semi Ltd








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