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Everspin Technologies Inc patents


Recent patent applications related to Everspin Technologies Inc. Everspin Technologies Inc is listed as an Agent/Assignee. Note: Everspin Technologies Inc may have other listings under different names/spellings. We're not affiliated with Everspin Technologies Inc, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "E" | Everspin Technologies Inc-related inventors


Magnetoresistive stack and method of fabricating same

A magnetoresistive element (e.g., a spin-torque magnetoresistive memory element) includes a fixed magnetic layer, a free magnetic layer, having a high-iron alloy interface region located along a surface of the free magnetic layer, wherein the high-iron alloy interface region has at least 50% iron by atomic composition, and a first dielectric, disposed between the fixed magnetic layer and the free magnetic layer. The magnetoresistive element further includes a second dielectric, having a first surface that is in contact with the surface of the free magnetic layer, and an electrode, disposed between the second dielectric and a conductor. ... Everspin Technologies Inc

Tuning magnetic anisotropy for spin-torque memory

Techniques for configuring the layers included in the free portion of a spin-torque magnetoresistive device are presented that allow for characteristics of the free portion to be tuned to meet the needs of various applications. In one embodiment, high data retention is achieved by balancing the perpendicular magnetic anisotropy of the ferromagnetic layers in the free portion. ... Everspin Technologies Inc

Preprogrammed data recovery

Techniques for recovering preprogrammed data from non-volatile memory are provided that include majority voting and/or use of one or more levels of ecc correction. Embodiments include storage of multiple copies of the data where ecc correction is performed before and after majority voting with respect to the multiple copies. ... Everspin Technologies Inc

Structures and methods for shielding magnetically sensitive components

Structures and methods are disclosed for shielding magnetically sensitive components. One structure includes a substrate, a bottom shield deposited on the substrate, a magnetoresistive semiconductor device having a first surface and a second surface opposing the first surface, the first surface of the magnetoresistive semiconductor device deposited on the bottom shield, a top shield deposited on the second surface of the magnetoresistive semiconductor device, the top shield having a window for accessing the magnetoresistive semiconductor device, and a plurality of interconnects that connect the magnetoresistive semiconductor device to a plurality of conductive elements.. ... Everspin Technologies Inc

Methods for fabricating semiconductor shielding structures

The present disclosure is drawn to, among other things, a method of forming a semiconductor shield from a stock material having a thickness. In some aspects the methods includes providing a first layer of material on a first surface of the stock material, wherein at least a portion of the first layer of material includes a first window that exposes a portion of the first surface; providing a second layer of material on a second surface of the stock material, wherein the second surface of the stock material is spaced from the first surface by the thickness of the stock material, and wherein at least portion of the second layer of material includes a second window that exposes a portion of the second surface; and selectively removing a portion of the stock material exposed at the first or second windows, wherein the portion removed includes less than an entirety of the thickness of the stock material.. ... Everspin Technologies Inc

Data storage in synthetic antiferromagnets included in magnetic tunnel junctions

A magnetoresistive memory device that stores data in the synthetic antiferromagnet (saf) included in each spin-torque memory cell provides for more robust data storage. In normal operation, the memory cells use the free portion of the memory cell for data storage. ... Everspin Technologies Inc

Magnetoresistive devices and methods therefor

The present disclosure is directed to exemplary methods of manufacturing a magnetoresistive device. In one aspect, a method may include forming one or more regions of a magnetoresistive stack on a substrate, wherein the substrate includes at least one electronic device. ... Everspin Technologies Inc

Magnetic field sensor with increased field linearity

A magnetic field sensor includes a plurality of transducer legs coupled together as a first circuit to sense a magnetic field, wherein each transducer leg comprises a plurality of magnetoresistance sense elements. The magnetic field sensor also includes a second circuit including a first plurality of current lines, wherein each current line of the first plurality of current lines is adjacent to a corresponding plurality of magnetoresistance sense elements of a transducer leg of the plurality of transducer legs. ... Everspin Technologies Inc

Magnetoresistive device and method of manufacturing same

A magnetoresistive-based device and method of manufacturing a magnetoresistive-based device using one or more hard masks. The process of manufacture, in one embodiment, includes patterning a mask, after patterning the mask, etching (a) through a first layer of electrically conductive material to form an electrically conductive electrode and (b) through a third layer of ferromagnetic material to provide sidewalls of the second synthetic antiferromagnetic structure. ... Everspin Technologies Inc

Method and apparatus for magnetic device alignment on an integrated circuit

Techniques are presented for ensuring alignment marks are available for use and patterning magnetoresistive devices following the deposition of layers used to form the magnetoresistive devices. In some cases, the plurality of layers corresponding to the magnetoresistive devices are selectively etched in order to expose the underlying alignment marks, whereas in other embodiments, the deposition of the plurality of layers is controlled by deposition tool tabs that prevent the materials from obscuring the underlying alignment marks.. ... Everspin Technologies Inc

Methods of manufacturing a magnetic field sensor

A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a “z” axis magnetic field onto sensors orientated in the xy plane.. ... Everspin Technologies Inc

Magnetoresistive structure having two dielectric layers, and method of manufacturing same

A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least one encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes. ... Everspin Technologies Inc

Short detection and inversion

In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells. For instance, the memory device may be configured to identify a shorted bit cell within a memory array and to store the data in the memory array, such that a state of the data bit stored in the shorted bit cell matches the state associated with the shorted bit cell.. ... Everspin Technologies Inc

Two bit error correction via a field programmable gate array

Apparatus, methods, and systems are disclosed for performing bit error correction on a data stream. In some aspects, the described systems and methods may include a plurality of memory devices, a first interface, and a field programmable gate array. ... Everspin Technologies Inc

02/01/18 / #20180033959

Magnetoresistive stack/structure and method of manufacturing same

A method of manufacturing a magnetoresistive stack/structure comprising (a) etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer, (b) depositing a first encapsulation layer on the sidewalls of the second magnetic region and over a surface of the dielectric layer, (c) thereafter: (i) etching the first encapsulation layer which is disposed over the dielectric layer using a first etch process, and (ii) etching re-deposited material using a second etch process, wherein, after such etching, a portion of the first encapsulation layer remains on the sidewalls of the second magnetic region, (d) etching (i) through the dielectric layer to form a tunnel barrier and provide sidewalls thereof and (ii) etching the first magnetic region to provide sidewalls thereof, and (e) depositing a second encapsulation layer on the sidewalls of the tunnel barrier and first magnetic region.. . ... Everspin Technologies Inc

01/25/18 / #20180026180

Methods of manufacturing magnetoresistive mtj stacks having an unpinned, fixed synthetic anti-ferromagnetic structure

A magnetoresistive magnetic tunnel junction (mtj) stack includes a free magnetic region, a fixed magnetic region, and a dielectric layer positioned between the free magnetic region and the fixed magnetic region. In one aspect, the fixed magnetic region consists essentially of an unpinned, fixed synthetic anti-ferromagnetic (saf) structure which comprises (i) a first layer of one or more ferromagnetic materials, including cobalt, (ii) a multi-layer region including a plurality of layers of ferromagnetic materials, wherein the plurality of layers of ferromagnetic materials include a layer of one or more ferromagnetic materials including cobalt, and (iii) an anti-ferromagnetic coupling layer disposed between the first layer and the multi-layer region. ... Everspin Technologies Inc

11/23/17 / #20170337959

Nonvolatile logic and security circuits

In some examples, a nonvolatile storage element may be configured to store a state or value during a low power or powered down period of a circuit. For example, the nonvolatile storage element may include a bridge of resistive elements that have a resistive state that may be configured by applying voltages to multiple drive paths. ... Everspin Technologies Inc

10/05/17 / #20170288136

Magnetoresistive device and method of manufacturing same

A magnetoresistive-based device and method of manufacturing a magnetoresistive-based device using one or more hard masks. The process of manufacture, in one embodiment, includes patterning a mask over a selected portion of the third layer of ferromagnetic material, wherein the mask is a metal hard mask. ... Everspin Technologies Inc

09/14/17 / #20170263300

Write verify programming of a memory device

A memory device is configured to identify a set of bit cells to be changed from a first state to a second state. In some examples, the memory device may apply a first voltage to the set of bit cells to change a least a first portion of the set of bit cells to the second state. ... Everspin Technologies Inc

06/29/17 / #20170184635

Sensing apparatus for sensing current through a conductor and methods therefor

A sensing apparatus for characterizing current flow through a conductor includes a plurality of magnetic sensors. In some embodiments, the sensors are grouped in pairs to achieve common mode rejection of signals generated in response to magnetic fields not resulting from current flow through the conductor. ... Everspin Technologies Inc

06/22/17 / #20170178709

Word line auto-booting in a spin-torque magnetic memory having local source lines

In a spin-torque magnetic random access memory (mram) that includes local source lines, auto-booting of the word line is used to reduce power consumption by reusing charge already present from driving a plurality of bit lines during writing operations. Auto-booting is accomplished by first driving the word line to a first word line voltage. ... Everspin Technologies Inc

06/15/17 / #20170170388

Magnetoresistive stack, seed region therefor and method of manufacturing same

A magnetoresistive stack/structure and method of manufacturing same comprising wherein the stack/structure includes a seed region, a fixed magnetic region disposed on and in contact with the seed region, a dielectric layer(s) disposed on the fixed magnetic region and a free magnetic region disposed on the dielectric layer(s). In one embodiment, the seed region comprises an alloy including nickel and chromium having (i) a thickness greater than or equal to 40 angstroms (+/−10%) and less than or equal to 60 angstroms (+/−10%), and (ii) a material composition or content of chromium within a range of 25-60 atomic percent (+/−10%) or 30-50 atomic percent (+/−10%).. ... Everspin Technologies Inc

05/11/17 / #20170133073

Redundant magnetic tunnel junctions in magnetoresistive memory

Memory cells in a spin-torque magnetic random access memory (mram) include at least two magnetic tunnel junctions within each memory cell, where each memory cell only stores a single data bit of information. Access circuitry coupled to the memory cells are able to read from and write to a memory cell even when one of the magnetic tunnel junctions within the memory cell is defective and is no longer functional. ... Everspin Technologies Inc

05/04/17 / #20170125670

Magnetoresistive stack and method of fabricating same

A magnetoresistive element (e.g., a spin-torque magnetoresistive memory element) includes a fixed magnetic layer, a free magnetic layer, having a high-iron alloy interface region located along a surface of the free magnetic layer, wherein the high-iron alloy interface region has at least 50% iron by atomic composition, and a first dielectric, disposed between the fixed magnetic layer and the free magnetic layer. The magnetoresistive element further includes a second dielectric, having a first surface that is in contact with the surface of the free magnetic layer, and an electrode, disposed between the second dielectric and a conductor. ... Everspin Technologies Inc

05/04/17 / #20170125663

Method of manufacturing a magnetoresistive stack/ structure using plurality of encapsulation layers

A method of manufacturing a magnetoresistive stack/structure comprising etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer; depositing a first encapsulation layer on the sidewalls of the second magnetic region and over the dielectric layer; etching the first encapsulation layer which is disposed over the exposed surface of the dielectric layer. The method further includes (a) depositing a second encapsulation layer: (i) on the first encapsulation layer disposed on the sidewalls of the second magnetic region and (ii) over the exposed surface of the dielectric layer and (b) depositing a third encapsulation layer: (i) on the second encapsulation layer which is on the first encapsulation layer and the exposed surface of the dielectric layer. ... Everspin Technologies Inc

05/04/17 / #20170125079

Memory device with shared read/write circuitry

In some examples, a memory device may be configured to use shared read circuitry to sample a voltage drop across both a bit cell and a resistive circuit in order to perform a comparison that produces an output corresponding to the bit stored in the bit cell. The shared read circuitry can include a shared sense amplifier as well as shared n-mos and p-mos followers used to apply read voltages across the bit cell and resistive circuit.. ... Everspin Technologies Inc

04/27/17 / #20170117462

Method of integration of a magnetoresistive structure

A method of manufacturing one or more interconnects to magnetoresistive structure comprising (i) depositing a first conductive material in a via; (2) etching the first conductive material wherein, after etching the first conductive material a portion of the first conductive material remains in the via, (3) partially filling the via by depositing a second conductive material in the via and directly on the first conductive material in the via; (4) depositing a first electrode material in the via and directly on the second conductive material in the via; (5) polishing a first surface of the first electrode material wherein, after polishing, the first electrode material is (i) on the second conductive material in the via and (ii) over the portion of the first conductive material remaining in the via; and (6) forming a magnetoresistive structure over the first electrode material.. . ... Everspin Technologies Inc

04/27/17 / #20170117461

Methods of manufacturing a magnetic field sensor

A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a “z” axis magnetic field onto sensors orientated in the xy plane.. ... Everspin Technologies Inc

04/27/17 / #20170117029

Bias configuration for write operations in memory

Techniques and circuits for testing and configuring bias voltage or bias current for write operations in memory devices are presented. Registers and nonvolatile storage is included on the memory devices for storing values used to control testing of the memory devices as well as for configuring parameters related to both testing and normal operation.. ... Everspin Technologies Inc

04/13/17 / #20170104498

Ecc word configuration for system-level ecc compatibility

In some examples, a memory device includes memory arrays configured to store pages of data organized into multiple ecc words. The memory device also includes at least one input/output pad for each ecc word associated with a page, such that a first level of error correction may be performed by the memory device on each of the ecc words associated with a page and a second level of error correction may be performed on the data output by each of the input/output pads during a particular period of time. ... Everspin Technologies Inc

04/13/17 / #20170104149

Packages for integrated circuits and methods of packaging integrated circuits

An integrated circuit package including an integrated circuit die including a first side and a second side opposite the first side, the first side including at least one magnetoresistive device formed thereon. The integrated circuit package also may include a first magnetic shield disposed on or adjacent the first side of the integrated circuit die, wherein the first magnetic shield is formed of a composite material.. ... Everspin Technologies Inc

03/30/17 / #20170092347

Circuit and method for controlling mram cell bias voltages

A cell bias control circuit maximizes the performance of devices in the read/write path of memory cells (magnetic tunnel junction device+transistor) without exceeding leakage current or reliability limits by automatically adjusting multiple control inputs of the read/write path at the memory array according to predefined profiles over supply voltage, temperature, and process corner variations by applying any specific reference parameter profiles to the memory array.. . ... Everspin Technologies Inc

03/23/17 / #20170084324

Memory device with timing overlap mode

In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in response to receiving the precharge command and a second series of events related to the activate command in response to receiving the activate command. ... Everspin Technologies Inc

03/23/17 / #20170084323

Non-destructive write/read leveling

In some examples, a memory device is configured with non-volatile memory array(s) having one or more associated volatile memory arrays. The memory device may include a non-destructive write mode configured to prevent access to the non-volatile memory array(s) during an initiation or calibration sequence performed by the memory device or an electronic device associated with the memory device to calibrate read and write access timing associated with the memory device.. ... Everspin Technologies Inc

03/16/17 / #20170074948

Bipolar chopping for 1/f noise and offset reduction in magnetic field sensors

A chopping technique, and associated structure, is implemented to cancel the magnetic 1/f noise contribution in a tunneling magnetoresistance (tmr) field sensor. The tmr field sensor comprises a first bridge circuit including multiple tmr elements to sense a magnetic field and a second circuit to apply a bipolar current pulse adjacent to each tmr element. ... Everspin Technologies Inc

03/09/17 / #20170069397

Short detection and inversion

In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells. For instance, the memory device may be configured to identify a shorted bit cell within a memory array and to store the data in the memory array, such that a state of the data bit stored in the shorted bit cell matches the state associated with the shorted bit cell.. ... Everspin Technologies Inc

03/02/17 / #20170060691

Memory device with page emulation mode

In some examples, a memory is configured to write multiple pages of an internal page size from a cache on the memory to a memory array on the memory in response to receiving a single precharge command when in a page emulation mode. When in the page emulation mode, the memory also reads multiple pages of the internal page size from the memory array and stores them in the cache in response to receiving a single activate command.. ... Everspin Technologies Inc

02/02/17 / #20170033058

Structures and methods for semiconductor packaging

A semiconductor package including a lead frame having a die pad and a plurality of leads arranged along at least a portion of a periphery of the semiconductor package, a semiconductor die secured to the die pad, wherein at least a portion of the semiconductor die extends beyond a periphery of the die pad, and a molding material encapsulating the semiconductor die and at least a portion of the die pad.. . ... Everspin Technologies Inc








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