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Freescale Semiconductor Inc patents


Recent patent applications related to Freescale Semiconductor Inc. Freescale Semiconductor Inc is listed as an Agent/Assignee. Note: Freescale Semiconductor Inc may have other listings under different names/spellings. We're not affiliated with Freescale Semiconductor Inc, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "F" | Freescale Semiconductor Inc-related inventors


Inertial sensor with motion limit structure

An inertial sensor includes a substrate, a movable mass, and a motion limit structure. The motion limit structure includes a rigid element interposed between first and second spring beams. ... Freescale Semiconductor Inc

Amplifier architecture reconfiguration

An amplifier includes first, second, and third inputs to receive an rf signal, first and second amplifiers, and an input phase adjustment circuit coupling the first, second, and third inputs to the first and second amplifiers, the input phase adjustment circuit having first and second outputs coupled to the first and second amplifiers, respectively. The input phase adjustment circuit includes a pair of inputs, where the pair of inputs includes the first and second inputs, for the first output and a pair of phase adjustment paths coupling the pair of inputs to the first output, respectively. ... Freescale Semiconductor Inc

Through substrate via (tsv) and method therefor

A through substrate via (tsv) and method of forming the same are provided. The method of making the tsv may include etching a via opening into the backside of semiconductor substrate, the via opening exposing a surface of a metal landing structure. ... Freescale Semiconductor Inc

Systems and methods for testing package assemblies

A method for stress testing a device under test (dut) having a plurality of pins includes generating a stress test pattern which independently stresses each pin of the plurality of pins, wherein the stress test pattern includes a plurality of test vector, and applying each test vector to the plurality of pins for a predetermined amount of time. The method further includes, after applying all the test vectors of the stress test pattern, applying a programmable load to each pin independently and after applying each programmable load, comparing an output voltage of each pin to a predetermined voltage range to form an output vector for each pin.. ... Freescale Semiconductor Inc

Microelectromechanical systems device test system and method

A system includes a rotary platform adapted to undergo oscillatory motion about a fixed point, a test fixture coupled to the rotary platform, the test fixture being adapted to receive a device-under-test, and an inertial sensor mounted to the rotary platform for providing a motion output signal indicative of the oscillatory motion. A controller is in communication with the rotary platform and inertial sensor. ... Freescale Semiconductor Inc

Feedback directed program stack optimization

A processing device includes an instruction memory to store executable applications that are executable by a target processor, and a compiler. The compiler includes a builder module and a call graph generator. ... Freescale Semiconductor Inc

Method for link adaptation and power amplifier voltage control and system therefor

A method includes determining a quality indicator designating a quality of packet reception at a wireless local area network transceiver. A modulation and coding scheme (mcs) index value is selected based on the quality indicator. ... Freescale Semiconductor Inc

Operation amplifiers with offset cancellation

A semiconductor device includes an operational transconductance amplifier (ota) with a matched pair of transistors including a first transistor and a second transistor, and configuration units that include a first set of switches, a second set of switches, and an input transistor. Gain adjustment circuitry is coupled to adjust gain of the ota. ... Freescale Semiconductor Inc

Distributed reservation based coherency protocol

A method of operating a cache-coherent computing system includes storing first state information corresponding to a first reservation for a first exclusive access to a first memory address requested by a first thread executing on a first processor of a first plurality of processors. The method includes transmitting an output atomic response transaction indicating a status of the first reservation to a coherency interconnection in response to issuance of the first exclusive access to the coherency interconnection. ... Freescale Semiconductor Inc

Calibrating inertial navigation data using tire pressure monitoring system signals

A system includes a tire pressure monitoring system (tpms) module coupled with a wheel on a vehicle and a vehicle navigation system of the vehicle. A method entails determining a movement signal at the tpms module and receiving the movement signal at the vehicle navigation system. ... Freescale Semiconductor Inc

Integrated circuit with protection from transient electrical stress events and method therefor

An integrated circuit for protecting against transient electrical stress events includes a rail clamp device, and a trigger circuit including a resistive-capacitive (rc) filter, a drive circuit including a first inverter stage receiving an input signal from the rc filter, the drive circuit is configured to enable the rail clamp device during a transient electrical stress event, and a stress event detection circuit coupled to the rc filter. The drive circuit includes a configurable activation voltage which is controlled by the stress event detection circuit, wherein the activation voltage is reduced when the transient electrical stress event is detected.. ... Freescale Semiconductor Inc

Integrated circuit with protection from transient electrical stress events and method therefor

An integrated circuit with protection against transient electrical stress events includes a trigger circuit having a first detection circuit coupled to a first supply voltage, a second detection circuit coupled to a second supply voltage, and a rail clamp device. During a first type of electrical stress event, the rail clamp device is activated in response to a first output signal provided by the first detection circuit. ... Freescale Semiconductor Inc

Air cavity packages and methods for the production thereof

Air cavity packages and methods for producing air cavity packages containing sintered bonded components, multipart window frames, and/or other unique structural features are disclosed. In one embodiment, a method for fabricating an air cavity package includes the step or process of forming a first metal particle-containing precursor layer between a base flange and a window frame positioned over the base flange. ... Freescale Semiconductor Inc

System and method for adjusting boot interface frequency

A system-on-chip includes a processing core and a memory controller connected between the core and an external memory. A clock divider receives an internal clock signal and outputs a divided clock signal. ... Freescale Semiconductor Inc

03/22/18 / #20180081412

Configuration of default voltage level for dual-voltage input/output pad cell via voltage rail ramp up timing

An integrated circuit (ic) package of an electronic device includes a first input coupled to a first voltage rail and a second input coupled to a second voltage rail. The ic package further includes a set of one or more input/output (io) pad cells and a power sequence detector coupled to the first and second voltage rails. ... Freescale Semiconductor Inc

03/15/18 / #20180075258

Systems and methods for dynamically assigning domain identifiers for access control

A master domain assignment controller includes a first plurality of registers corresponding to a first processor including a first register corresponding to a first set of process identifiers (pids) and a second register corresponding to a second set of pids, and comparison circuitry. The comparison circuitry is coupled to receive an input pid from the first processor and is configured to determine if the input pid is one of the first set or the second set of pids. ... Freescale Semiconductor Inc

03/15/18 / #20180074532

Reference voltage generator

A reference voltage generator includes first through sixth transistors and an operational amplifier. The first and second transistors provide first and second voltages to the operational amplifier, respectively. ... Freescale Semiconductor Inc

03/15/18 / #20180074122

Circuit and method for testing flip flop state retention

An integrated circuit includes a plurality of state retention power gating (srpg) flip-flops coupled in a first chain, wherein the first chain has a first scan input and a first scan output; a pseudo random pattern generator (prpg) configured to generate test patterns in response to seeds; a multiplexer (mux) coupled between the prpg and the first scan input and coupled to receive a select signal; and response compression logic coupled to the first scan output and configured to generate a test signature in response to an output pattern provided at the first scan output. The mux is configured to, when the select signal has a first value, couple a first output of the prpg to the first scan input, and, when the select signal has a second value, couple an inversion of the first output of the prpg to the first scan input.. ... Freescale Semiconductor Inc

03/08/18 / #20180068980

Multiple interconnections between die

Embodiments of a semiconductor packaged device and method of making thereof are provided, the device including a substrate; a first flip chip die mounted to a first major surface of the substrate; a second flip chip die mounted to the first major surface of the substrate, the second flip chip die laterally adjacent to the first flip chip die on the first major surface; and a wire bond formed between a first bond pad on the first flip chip die and a second bond pad on the second flip chip die.. . ... Freescale Semiconductor Inc

03/01/18 / #20180062241

Power amplifier system with integrated antenna

A system with an integrated antenna includes a housing having a first surface and a second surface. The second surface of the housing defines a recess. ... Freescale Semiconductor Inc

03/01/18 / #20180061780

Active tamper detection circuit with bypass detection and method therefor

An active tamper detection circuit with bypass detection is provided. A bypass detection circuit is coupled to an active mesh loop. ... Freescale Semiconductor Inc

03/01/18 / #20180060164

Integrated circuits and methods for dynamic allocation of one-time programmable memory

An integrated circuit includes a one-time programmable (otp) memory having a plurality of pages and address translation circuitry. A first line of each page is configured to store error policy bits. ... Freescale Semiconductor Inc

03/01/18 / #20180059756

Multiprocessing system with peripheral power consumption control

An integrated circuit device includes a peripheral control circuit configured to receive a low power intent signal from a first processor, and a first control register in the peripheral control circuit. The first control register includes a peripheral enable indicator for each processor that can use a first peripheral. ... Freescale Semiconductor Inc

03/01/18 / #20180059290

Aluminum nitride protection of silver apparatus, system and method

A semiconductor apparatus including a wafer base with a top side and a bottom side, a silver base with a top side and a bottom side, wherein the bottom side of the silver base is attached to the top side of the wafer base and wherein the silver base provides a reflective surface, and an aluminum nitride protective layer attached to the top side of the silver base, wherein the aluminum nitride protective layer shields the silver base from the environment.. . ... Freescale Semiconductor Inc

03/01/18 / #20180059177

Scan circuitry with iddq verification

An integrated circuitry includes a first logic block coupled between a first power supply terminal and a second power supply terminal. The first logic block includes a first scan chain and a configurable defect coupled to a scan output node of the first scan chain. ... Freescale Semiconductor Inc

03/01/18 / #20180059052

Methods and sensor devices for sensing fluid properties

An ion sensor for sensing ions in a fluid includes a metal-oxide semiconductor (mos) varactor formed in and on a semiconductor substrate having a gate dielectric over the semiconductor substrate, a gate over the gate dielectric, a well region in the substrate under the gate dielectric, and source/drain regions in the well region, wherein the well region and the source/drain regions are of a same conductivity type; and a sense electrode coupled to the mos varactor, wherein the capacitance of the gate dielectric of the varactor changes when the sense electrode interacts with ions in the fluid. Alternatively, resistance of the well region changes when the sense electrode interacts with ions in the fluid, affecting a change in a quality factor of an inductor.. ... Freescale Semiconductor Inc

03/01/18 / #20180058970

System, test chamber, and method for response time measurement of a pressure sensor

A test chamber is used within a system for testing microelectromechanical systems (mems) pressure sensors. The system includes a processor, two air tanks pressurized to different air pressures, a high speed switch mechanism, and the test chamber. ... Freescale Semiconductor Inc

02/22/18 / #20180053753

Stackable molded packages and methods of manufacture thereof

A stackable package assembly and method of manufacturing is provided. The method includes attaching a plurality of interconnect balls to a first surface of a substrate, and encapsulating the first surface of the substrate and the plurality of interconnect balls with an encapsulant. ... Freescale Semiconductor Inc

02/22/18 / #20180053698

System and method for characterizing critical parameters resulting from a semiconductor device fabrication process

A system includes three related structures. A first structure includes a first finger interposed between a first pair of sidewalls. ... Freescale Semiconductor Inc

02/22/18 / #20180052615

Soft error detection in a memory system

An integrated circuit (ic) device including a first memory device, a second memory device stacked with the first memory device, and one or more memory controllers configured to detect a first error in data stored in the first memory device at a first physical location in the ic device, and upon detecting the first error, determine whether there is a second error in data stored in the second memory device in a second physical location in the ic device near the first physical location.. . ... Freescale Semiconductor Inc

02/22/18 / #20180052185

Methods and systems for electrically calibrating transducers

Devices, systems and methods are provided for calibrating a transducer. One exemplary method involves determining a transfer function for the transducer based on a measured response of the transducer to an applied electrical signal, determining a set of values for a plurality of response parameters associated with the transducer based on the transfer function, determining a calibration coefficient value associated with the transducer based at least in part on the set of values and a correlation between physical sensitivity and the plurality of response parameters, and storing the calibration coefficient value in association with the transducer.. ... Freescale Semiconductor Inc

02/15/18 / #20180048320

Switching power converter

Aspects of various embodiments of the present disclosure are directed to applications utilizing voltage regulation. In certain embodiments, an oscillator circuit is configured to generate an oscillating signal having a frequency specified by a frequency control signal. ... Freescale Semiconductor Inc

02/15/18 / #20180046392

Method for performing data transaction and memory device therefor

A system for performing a data transaction between a memory and a master via a bus based on a strobe signal. The memory includes at least one memory bank having first and second cuts. ... Freescale Semiconductor Inc

02/08/18 / #20180039589

Communication system for transmitting and receiving control frames

A communication system for communicating control data between a processor and an interface includes configuration registers, a packet processor, an interrupt processor, a timing monitor, a configuration sampler, a control-frame processor, a mode selector, and a transceiver. The processor, timing monitor, and configuration sampler generate control data, a timing signal and frame structure data, respectively. ... Freescale Semiconductor Inc

02/08/18 / #20180039552

Distributed baseboard management controller for multiple devices on server boards

A server board includes first and second devices. A first service processor of the first device operates as a master baseboard management controller of the server board, and monitors a communication channel for alive messages from a plurality service processors. ... Freescale Semiconductor Inc

02/01/18 / #20180033716

Sintered multilayer heat sinks for microelectronic packages and methods for the production thereof

Methods for producing multilayer heat sinks utilizing low temperature sintering processes are provided. In one embodiment, the method includes forming a metal particle-containing precursor layer over a first principal surface of a first metal layer. ... Freescale Semiconductor Inc

02/01/18 / #20180033472

Adaptable sense circuitry and method for read-only memory

Apparatus and methods for operating a read-only memory (rom) are disclosed. The method for operating the rom includes sensing a dummy bit line with a dummy sense amplifier coupled to the dummy bit line to generate a keeper adjust signal. ... Freescale Semiconductor Inc

01/25/18 / #20180024951

Heterogeneous multi-processor device and method of enabling coherent data access within a heterogeneous multi-processor device

A heterogeneous multi-processor device having a first processor component arranged to issue a data access command request, a second processor component arranged to execute a set of threads, a task scheduling component arranged to schedule the execution of threads by the second processor component, and an internal memory component. In response to the data access command request being issued by the first processor component, the task scheduling component is arranged to wait for activities relating to the indicated subset of threads to finish, and when the activities relating to the indicated subset of threads have finished to load a command thread for execution by the second processor component, the command thread being arranged to cause the second processor component to read the indicated data from the at least one region of memory and make the read data available to the first processor component.. ... Freescale Semiconductor Inc

01/18/18 / #20180020468

Scheduler for layer mapped code words

An enode-b includes push mapping hardware for improved performance. A scheduler schedules first and second code words of first and second respective user devices. ... Freescale Semiconductor Inc

01/18/18 / #20180019735

Systems and methods for non-volatile flip flops

A non-volatile flip flop integrated circuit includes a master latch circuit, a slave latch circuit coupled to the master latch circuit, and a non-volatile memory array coupled to the slave latch circuit. The non-volatile memory array includes a first pair of memory cells coupled to the slave latch circuit, and a second pair of memory cells coupled to the slave latch circuit in parallel with the first pair of memory cells. ... Freescale Semiconductor Inc

01/18/18 / #20180019020

Sample-and-hold circuit

A sample-and-hold circuit, which includes a hold capacitor at its output terminal and at least one intermediate capacitor, intermittently receives an input voltage, and a first value of a switch enable signal causes the sample-and-hold circuit to sample the input voltage and to charge the at least one intermediate capacitor and the hold capacitor to the input voltage, and when it is not receiving the input voltage, a second value of the switch enable signal causes the sample-and-hold circuit to hold, at its output terminal, the input voltage until the hold capacitor discharges, which starts to discharge only after the at least one intermediate capacitor has substantially discharged.. . ... Freescale Semiconductor Inc

01/18/18 / #20180018131

Memory controller for performing write transaction

A memory controller receives first and second write transactions from a processor and stores write data in a memory. The memory controller includes an address comparison circuit, a buffer, a level control circuit, a command generator, and a control circuit. ... Freescale Semiconductor Inc

01/18/18 / #20180018125

Breach detection in integrated circuits

An apparatus embodiment includes an integrated circuit (ic) and breach-detection circuitry. The ic includes data storage circuitry, a power grid configured to distribute power to the data storage circuitry, and a plurality of nodes distributed over at least one sensitive region of the ic. ... Freescale Semiconductor Inc

01/11/18 / #20180011736

Hardware controlled instruction pre-fetching

A task control circuit maintains, in response to task event information, a task information queue that includes task information for a plurality of tasks. Based upon the task information in the task information queue, a future task switch condition is identified as corresponding to a task switch time for a particular task of the plurality of tasks. ... Freescale Semiconductor Inc

01/11/18 / #20180011735

Instruction pre-fetching

Pre-fetching instructions for tasks of an operating system (os) is provided by calling a task scheduler that determines a load start time for a set of instructions for a particular task corresponding to a task switch condition. The os calls, and in response to the load start time, a loader entity module that generates a pre-fetch request that loads the set of instructions for the particular task from a non-volatile memory circuit into a random access memory circuit. ... Freescale Semiconductor Inc

01/11/18 / #20180010913

Vibration and shock robust gyroscope

A mems device includes a movable mass having a central region overlying a sense electrode and an opening in which a suspension structure and spring system are located. The suspension structure includes an anchor coupled to a substrate and rigid links extending from opposing sides of the anchor. ... Freescale Semiconductor Inc

01/04/18 / #20180007746

Solid state microwave heating apparatus with dielectric resonator antenna array, and methods of operation and manufacture

An embodiment of a microwave heating apparatus includes a solid state microwave energy source, a chamber, a dielectric resonator antenna with an exciter dielectric resonator and a feed structure, and one or more additional dielectric resonators each positioned within a distance of the exciter resonator to form a dielectric resonator antenna array. The distance is selected so that each additional resonator is closely capacitively coupled with the exciter resonator. ... Freescale Semiconductor Inc

01/04/18 / #20180007745

Solid state microwave heating apparatus with stacked dielectric resonator antenna array, and methods of operation and manufacture

An embodiment of a microwave heating apparatus includes a solid state microwave energy source, a first dielectric resonator antenna that includes a first exciter dielectric resonator and a first feed structure in proximity to the first exciter dielectric resonator, one or more additional dielectric resonators stacked above the top surface of the first exciter dielectric resonator to form a vertically-stacked dielectric resonator antenna array. The first feed structure is electrically coupled to the microwave energy source to receive a first excitation signal, and the first exciter dielectric resonator is configured to produce a first electric field in response to the excitation signal provided to the first feed structure.. ... Freescale Semiconductor Inc

01/04/18 / #20180005957

Shielded package with integrated antenna

A semiconductor structure includes a packaged semiconductor device having at least one device, a conductive pillar, an encapsulant over the at least one device and surrounding the conductive pillar, wherein the conductive pillar extends from a first major surface to a second major surface of the encapsulant, and is exposed at the second major surface and the at least one device is exposed at the first major surface. The packaged device also includes a conductive shield layer on the second major surface of the encapsulant and on minor surfaces of the encapsulant and an isolation region at the second major surface of the encapsulant between the encapsulant and the conductive pillar such that the conductive shield layer is electrically isolated from the conductive pillar. ... Freescale Semiconductor Inc

01/04/18 / #20180005925

Packaged semiconductor device having a lead frame and inner and outer leads and method for forming

A method of making a packaged integrated circuit device includes forming a lead frame with leads that have an inner portion and an outer portion, the inner portion of the lead is between a periphery of a die pad and extends to one end of openings around the die pad. The outer portion of the leads are separated along their length almost up to an opposite end of the openings. ... Freescale Semiconductor Inc

01/04/18 / #20180004692

Direct memory access (dma) unit with address alignment

Systems and methods for operating a dma unit with address alignment are disclosed. These may include configuring a bandwidth control setting for a read job that includes a data transfer size corresponding to a first number of bytes. ... Freescale Semiconductor Inc

12/28/17 / #20170373053

Esd protection structure

An esd protection structure formed within a semiconductor substrate of an integrated circuit device. The esd protection structure comprises a thyristor structure being formed from a first p-doped section forming an anode of the thyristor structure, a first n-doped section forming a collector node of the thyristor structure, a second p-doped section, and a second n-doped section forming a cathode of the thyristor structure. ... Freescale Semiconductor Inc

12/28/17 / #20170370799

Controlled pulse generation methods and apparatuses for evaluating stiction in microelectromechanical systems devices

Methods and apparatuses are provided for evaluating or testing stiction in microelectromechanical systems (mems) devices utilizing a mechanized shock pulse generation approach. In one embodiment, the method includes the step or process of loading a mems device, such as a multi-axis mems accelerometer, into a socket provided on a device-under-test (dut) board. ... Freescale Semiconductor Inc

12/21/17 / #20170366296

Communication link adjustments in wireless networks based upon composite lqi measurements

Methods and systems are disclosed to adjust communication links within wireless networks based upon composite link quality indicators (lqis). Packet communications are received by a network node through a communication link from a separate network node within a wireless network. ... Freescale Semiconductor Inc

12/21/17 / #20170366221

Clear channel assessment

Circuits and methods concerning signal detection are disclosed. In some example embodiments, an apparatus is configured to detect presence of a spreading sequence in a sample data sequence. ... Freescale Semiconductor Inc

12/14/17 / #20170359892

Shielded and packaged electronic devices, electronic assemblies, and methods

Shielded and packaged electronic devices, electronic assemblies, and methods are disclosed herein. The shielded and packaged electronic devices include a packaged electronic device with a package surface and a plurality of electrically conductive package pads arranged on the package surface, a shielding dielectric layer extending in contact with the package surface and having a shielding layer surface and a plurality of openings that extends between the shielding layer surface and the plurality of electrically conductive package pads, and a plurality of electrical conductors that extends from the plurality of electrically conductive package pads and projects from the shielding layer surface. ... Freescale Semiconductor Inc

12/14/17 / #20170359108

Method and apparatus for performing distributed computation of precoding estimates

A method and apparatus for performing distributed computation of precoding estimates within a das. An rrh comprises a receiver component arranged to receive uplink signals from active user devices. ... Freescale Semiconductor Inc

12/14/17 / #20170358537

Method of wafer dicing for backside metallization

Method embodiments of wafer dicing for backside metallization are provided. One method includes: applying dicing tape to a front side of a semiconductor wafer, wherein the front side of the semiconductor wafer includes active circuitry; cutting a back side of the semiconductor wafer, the back side opposite the front side, wherein the cutting forms a retrograde cavity in a street of the semiconductor wafer, the retrograde cavity has a gap width at the back side of the semiconductor wafer, and the retrograde cavity has sidewalls with negative slope; depositing a metal layer on the back side of the semiconductor wafer, wherein the gap width is large enough to prevent formation of the metal layer over the retrograde cavity; and cutting through the street of the semiconductor wafer subsequent to the depositing the metal layer.. ... Freescale Semiconductor Inc

12/14/17 / #20170357455

Mass storage system and method of storing mass data

A mass storage system for storing mass data generated by a mass data source. The system includes a data buffer coupled to the mass data source, and a file system and command generator. ... Freescale Semiconductor Inc

12/14/17 / #20170356955

Kernel based cluster fault analysis

A fault analysis method comprises: receiving fault data from wafer level testing that identifies locations and test results of a plurality of die; applying a kernel transform to the fault data to produce cluster data, where the kernel transform defines a fault impact distribution that defines fault contribution from the failed die to local die within an outer radial boundary of the fault impact distribution. Applying the kernel transform comprises: centering the fault impact distribution at a location of each die that failed wafer level testing, associating each local die that falls within the outer radial boundary with a respective fault contribution value according to the fault impact distribution, and accruing fault contribution values associated with each respective die of the plurality of die to produce a cluster value for the respective die, which correlates to a probability of failure of the respective die at a future time.. ... Freescale Semiconductor Inc

12/14/17 / #20170356937

Conversion rate control for analog to digital conversion

A method, apparatus, and energy metering system obtains mains samples of a mains power line signal, performs non-white noise (nwn) filtering of the mains power line signal, obtains adjustable clock source samples of an adjustable clock signal of an adjustable clock oscillator, determines a difference based on the mains samples and the adjustable clock source samples, adjusts an adjustable clock source frequency of the adjustable clock oscillator based on the difference, and applies the adjustable clock source frequency to an analog to digital converter (adc) to determine a conversion rate of the adc.. . ... Freescale Semiconductor Inc

12/07/17 / #20170353305

Application specific low-power secure key

A key generator including a low-power key adjust circuit, and a high-power key adjust circuit. The low-power key adjust circuit including a storage location to store an original key, a shifter to shift the original key by a number of steps to shift to create a first key, and an output to provide the first key. ... Freescale Semiconductor Inc

12/07/17 / #20170352756

Semiconductor device and method of making

A semiconductor device is disclosed that includes a first region of a first conductivity type that includes a drain, a region of a second conductivity type abutting the first region in a lateral direction and a vertical direction to form an interface between the first conductivity type and the second conductivity type, wherein the drain region is spaced apart from the interface. A source region of the first conductivity type abuts the second region in the lateral direction and vertical directions. ... Freescale Semiconductor Inc

12/07/17 / #20170351577

Method and apparatus for managing mismatches within a multi-threaded lockstep processing system

A processing system comprising a first processing domain and a second processing domain. Each of the first processing domain and the second processing domain comprises a multi-threaded processor core arranged to output a set of internal state signals representative of current states of internal components of the respective processor core. ... Freescale Semiconductor Inc

12/07/17 / #20170350701

Mems gyroscope device

A microelectromechanical system (mems) gyroscope device includes a substrate having a surface parallel to a plane; first and second proof masses driven to slide back and forth past one another in a first directional axis of the plane, where the first and second proof masses respectively have a first and second recess in a respective side closest to the other proof mass; a pivot structure coupled to the first proof mass within the first recess and to the second proof mass within the second recess; an anchor between the first and second recesses and coupled to a mid-point of the pivot structure; and third and fourth proof masses driven to move toward and away from one another in a second directional axis of the plane that is perpendicular to the first directional axis; where the proof masses move in response to angular velocity in one or more directional axes.. . ... Freescale Semiconductor Inc

11/30/17 / #20170346664

Communicaton unit, circuit for quadrature sampling error estimation and compensation and method therefor

A communication unit comprises a modem configured to generate a first and second test digital quadrature signal. The modem is configured to: estimate a first sampling error performance associated with a first quadrature path from the first received test digital quadrature signal; estimate a second sampling error performance associated with a second quadrature path from the second received test digital quadrature signal; and generate at least one sampling error compensation signal based on the first estimated sampling error performance and second estimated sampling error performance to be applied to at least one of the receiver and transmitter.. ... Freescale Semiconductor Inc

11/30/17 / #20170346579

Communicaton unit receiver, integrated circuit and method for adc dynamic range selection

A communication unit receiver comprising: a multi-section analogue to digital converter, adc, configured to receive an analogue signal and convert at least a first portion of the analogue signal into a digital signal using a first adc dynamic range. A modem, coupled to the multi-section adc, is configured to: process the digital signal; determine a signal-to-noise ratio, snr, for sub-carriers of the analogue signal; and output an adc selection signal to the multi-section adc that selects a subset of sections of the multi-section adc, where the selection signal is based at least partly on the determined snr. ... Freescale Semiconductor Inc

11/30/17 / #20170346280

Sensing and detection of esd and other transient overstress events

An integrated circuit includes an i/o pad and a protection device coupled to the i/o pad and a first supply node. A transient event detector includes a latch; a first transistor having a first current electrode coupled to the i/o pad, a control electrode coupled to a first supply node, and a second current electrode coupled to a data input of the latch, wherein the latch is configured to store an indication that a transient event occurred. ... Freescale Semiconductor Inc

11/30/17 / #20170345746

Integrated circuit package with solder balls on two sides

An integrated circuit package with solder balls on two major sides of the package and a method of making. The integrated circuit package includes at least one die encapsulated in an encapsulant. ... Freescale Semiconductor Inc

11/30/17 / #20170345491

Systems and methods for non-volatile flip flops

An integrated circuit includes a first plurality of flip flops; a first bank of resistive memory cells, wherein each flip flop of the first plurality of flip flops uniquely corresponds to a resistive memory cell of the first bank of resistive memory cells; write circuitry configured to store data from the first plurality of flip flops to the first bank of resistive memory cells; and read circuitry configured to read data from the first bank of resistive memory cells and provide the data from the first bank for storage into the first plurality of flip flops.. . ... Freescale Semiconductor Inc

11/30/17 / #20170343350

Angular rate sensor

A mems sensor for measuring rotational motion about a first axis includes a frame, a base structure under the frame, a drive mass mounted in the frame for rotational movement about a second axis perpendicular to the first axis, and a first drive paddle in the drive mass. A first link includes a first end coupled to a first spring that movably couples the first drive paddle to the drive mass and a second end coupled to a second spring that movably couples the first link to the frame. ... Freescale Semiconductor Inc

11/23/17 / #20170337142

Compiler global memory access optimization in code regions using most appropriate base pointer registers

A processing device includes a target processor instruction memory to store a plurality of target processor instructions that include a plurality of global memory access instructions. The processing device further includes a compiler to communicate with the target processor instruction memory, the compiler including: a global variable candidate detection module to identify a global memory access instruction within a set of code regions that use a set of global variable candidates to access a global memory, and a memory access optimization module to modify the global memory access instruction, wherein the modified global memory access instruction utilizes an unused base pointer register of a set of unused base pointer register candidates within the set of code regions, a global variable from the set of global variable candidates to be used as a base address, and an offset relative to the base address to access the global memory.. ... Freescale Semiconductor Inc

11/23/17 / #20170336973

Memory interleave system and method therefor

Methods and systems for accessing a memory are provided. One method of accessing a memory includes generating a memory access profile for accesses to a memory array. ... Freescale Semiconductor Inc

11/23/17 / #20170334306

Battery monitoring device

A battery monitoring device suitable for monitoring performance of one or more battery cells, such as with respect to a battery pack powering a vehicle. The battery monitoring device includes a signal injector configured to produce a replacement physical set that emulates one or more physical properties associated with the one or more battery cells, a multiplexer configured to selectively output, during different periods of time, the replacement physical set received from the signal injector or a physical set of physical properties received from the one or more battery cells, a sensor circuit configured to separately convert the physical set to a first signal set representing a first digitized measurement of the physical set and the replacement physical set to a second signal set representing a second digitized measurement of the replacement physical set, and a controller configured to compare the first signal set to the second signal set for a variance outside of a predetermined threshold. ... Freescale Semiconductor Inc

11/09/17 / #20170324716

Autonomous key update mechanism with blacklisting of compromised nodes for mesh networks

Various embodiments described herein relate to network key manager which is configured to manage keys in nodes in the network, wherein the network key manager including a memory configured to store an update data structure; a processor configured to: determine which nodes are blacklisted; generate the update data structure of volatile private keys for each node that is not blacklisted, wherein the volatile private key is based upon secret information associated with the node and an index, wherein the volatile private key is used for the indexth key update; determine a neighbor node of the network key manager; remove the volatile private key for the neighbor node from the update data structure; encrypt the resulting update data structure and a new network key with the private key for the neighbor node to produce an encrypted message; and send the encrypted message to the neighbor node.. . ... Freescale Semiconductor Inc

11/09/17 / #20170324715

Light-weight key update mechanism with blacklisting based on secret sharing algorithm in wireless sensor networks

Various embodiments include a network manager for managing network keys in a network having a plurality of nodes, the device including: a memory; and a processor configured to: determine n nodes to blacklist, wherein n is an integer; select a polynomial function from a plurality of polynomial functions of degree k and wherein the polynomial functions define plurality of secret network keys; generate k-n random abscissa values, wherein none of the random abscissa values are not found in a list of node abscissa values; calculate k-n polynomial function values for the k-n random abscissa values; calculate n polynomial function values for n node abscissa values associated with the n blacklisted nodes; transmit a message to nodes in the network including an indication of the selected polynomial function, the k-n random abscissa values, the n node abscissa values associated with the n blacklisted nodes, the k-n calculated polynomial function values, and the n calculated polynomial function values.. . ... Freescale Semiconductor Inc

11/09/17 / #20170324377

Amplitude detection with compensation

A circuit including an amplitude detector. The amplitude detector includes an input to receive a signal having an amplitude voltage and a first pair of transistors configured in parallel. ... Freescale Semiconductor Inc

11/09/17 / #20170322891

Device and method for secure data storage

A device for secure data storage has a host unit that obtains data stored on an external device at an external storage address; a user signal generator that generates a user defined security signal based on the external storage address of the data that indicates a security level of the data; a storage address determining unit that determines an internal storage address for the data based on the security level of the data; and a storage unit that stores the data at the internal storage address corresponding to the security level.. . ... Freescale Semiconductor Inc

11/09/17 / #20170322098

Pressure sensor device and method for testing the pressure sensor device

A pressure sensor device and a method for testing the pressure sensor device is provided. The pressure sensor device includes a first pressure sensor cell having a first capacitance value, and a second pressure sensor cell having a second capacitance value, the second capacitance value being different from the first capacitance value. ... Freescale Semiconductor Inc

10/26/17 / #20170310307

Systems and methods for supplying different voltage levels with shared current

An integrated circuit includes a first portion of a stacked ring oscillator coupled between a first supply voltage node and a common node, wherein the first supply voltage node provides a local supply voltage for the first portion and the common node provides a local ground for the first portion. The integrated circuit includes a second portion of the stacked ring oscillator coupled between the common node and a second supply voltage node wherein the common node provides a local supply voltage for the second portion and the second supply voltage node provides a local ground for the second portion. ... Freescale Semiconductor Inc

10/26/17 / #20170308404

Data processing system having a coherency interconnect

A processing system includes a first processor configured to issue a first request in a first format, an adapter configured to receive the first request in the first format and send the first request in a second format, and a memory coherency interconnect configured to receive the first request in the second format and determine whether the first request in the second format is for a translation lookaside buffer (tlb) operation or a non-tlb operation based on information in the first request in the second format. When the first request in the second format is for a tlb operation, the interconnect routes the first request in the second format to a tlb global ordering point (gop). ... Freescale Semiconductor Inc

10/26/17 / #20170308108

Voltage supply regulator with overshoot protection

A voltage supply regulator includes a first output resistor including a first terminal coupled to an output voltage of the voltage supply regulator and a second terminal; a first comparator including a first input coupled to a reference voltage, a second input coupled to the second terminal of the first output resistor, and an output coupled to a base of a first regulator transistor; a current mirror coupled to a collector of the first regulator transistor; and an slew rate detector coupled to the current mirror that includes a first terminal coupled to control electrodes of first and second transistors in the current mirror, and a detection bipolar junction transistor having a collector coupled to the control electrodes of the first and second transistors in the current mirror, and a base coupled to a second terminal of the capacitor.. . ... Freescale Semiconductor Inc

10/26/17 / #20170307697

Magnetic field sensor with multiple axis sense capability

A sensor for sensing an external magnetic field along a sensing direction comprises a sensor bridge. The sensor bridge has a first sensor leg that includes a first magnetoresistive sense element and a second sensor leg that includes a second magnetoresistive sense element. ... Freescale Semiconductor Inc

10/12/17 / #20170295097

System and method for creating session entry

A system for creating a session entry and forwarding an ip packet includes memories that store session and session template tables, and first and second processors in communication with the memories. When the first processor receives the ip packet, it determines whether the session table includes a session entry corresponding to the ip packet. ... Freescale Semiconductor Inc

10/12/17 / #20170294994

Common public radio interface, cpri, lane controller and method of operating thereof

The present application relates to a common public radio interface, cpri, lane controller and a method of operating thereof. The cpri lane controller comprises a transaction counter, a symbol counter and a comparator. ... Freescale Semiconductor Inc

10/12/17 / #20170294393

Pre-plated substrate for die attachment

A method for attaching a semiconductor die to a substrate includes providing a substrate that includes an attachment layer at a surface of the substrate. The attachment layer is covered by a protective flash plating layer. ... Freescale Semiconductor Inc

10/12/17 / #20170293516

Temporal relationship extension of state machine observer

A method includes receiving a first progress request from a first state machine associated with execution of a first thread on a processor. The method includes updating a current state of a temporal relationship state machine based on the current state, the first progress request, and a predetermined temporal relationship between progress of the first state machine to a first state machine state and progress to a second state. ... Freescale Semiconductor Inc

10/12/17 / #20170293375

Capacitive sensor device and method of operation

A capacitive sensor system includes a capacitive sensor device having a sense electrode that includes a first capacitor, a first supply voltage in , a first switch operable to couple the sense electrode to the first supply voltage during a first mode and an analog to digital converter during a second mode, a second switch operable to couple a second capacitor to a second supply voltage during the first mode and to an open circuit during the second mode, and a resistive element that includes a first terminal coupled between the first capacitor and the first switch, and a second terminal coupled between the second capacitor and the second switch.. . ... Freescale Semiconductor Inc

10/12/17 / #20170293001

Magnetic field sensor with permanent magnet biasing

A magnetic field sensor for sensing an external magnetic field along a sensing direction oriented perpendicular to a plane of the magnetic field sensor comprises a sensor bridge. The sensor bridge has a first sensor leg that includes a first magnetoresistive sense element and a second sensor leg that includes a second magnetoresistive sense element. ... Freescale Semiconductor Inc

10/12/17 / #20170292995

Multi-bit data flip-flop with scan initialization

Multi-bit data flip-flops are disclosed that provide bit initialization through propagation of scan bits. Input multiplexers are configured to select between input data bits and input scan bits based upon mode select signals. ... Freescale Semiconductor Inc

10/05/17 / #20170289842

Method and system for processing lower nfft lte rates over cpri link

A method including receiving, by a radio equipment control (rec) device of a wireless communication system over an interface link, time domain compressed data from a radio equipment (re) device at a first data transmission rate. The method further including transforming, by the rec device, the time domain compressed data to frequency domain decompressed full rate data for a second transmission data rate utilizing a fast fourier processing engine of the rec device.. ... Freescale Semiconductor Inc

10/05/17 / #20170286587

Systems and methods for creating block constraints in integrated circuit designs

Methods for generating constraints associated with an integrated circuit design are provided. The method includes identifying, with a processor, a plurality of paths based on a floor-plan data set, each of the paths specifying a first block, a second block, and a first interconnect between the first block and the second block. ... Freescale Semiconductor Inc

09/28/17 / #20170279268

Power switch module, smart grid power supply arrangement and method therefor

A power switch module comprising a control component. Upon an indicated operating condition fulfilling a protection condition, the control component is arranged to transition the power switch module from an on state to a latched-off state in which the control component is arranged to configure the switching device to be turned off to decouple the load node from the power supply node. ... Freescale Semiconductor Inc

09/28/17 / #20170278961

Semiconductor devices with an enhanced resistivity region and methods of fabrication therefor

Embodiments of a semiconductor device include a base substrate including an upper surface, a nucleation layer disposed over the upper surface of the base substrate, a first semiconductor layer disposed over the nucleation layer, a second semiconductor layer disposed over the first semiconductor layer, a channel within the second semiconductor layer and proximate to an upper surface of the second semiconductor layer, and an enhanced resistivity region with an upper boundary proximate to an upper surface of the first semiconductor layer. The enhanced resistivity region has an upper boundary located a distance below the channel. ... Freescale Semiconductor Inc

09/28/17 / #20170278937

Split gate device with doped region and method therefor

A method of forming a semiconductor device using a substrate includes forming a first select gate over the substrate, a charge storage layer over the first select gate, over the second select gate, and over the substrate in a region between the first select gate and the second select gate, wherein the charge storage layer is conformal, and a control gate layer over the charge storage layer, wherein the control gate layer is conformal. The method further includes performing a first implant that penetrates through the control gate layer in a middle portion of the region between the first select gate and the second select gate to the substrate to form a doped region in the substrate in a first portion of the region between the first select gate and the second select gate that does not reach the first select gate and does not reach the second select gate.. ... Freescale Semiconductor Inc

09/28/17 / #20170278825

Apparatus and methods for multi-die packaging

A packaged semiconductor device includes a first package substrate having a first plurality of lead fingers, a first die attached to a first major surface of the first package substrate, a second package substrate having a second plurality of lead fingers, wherein each of the second plurality of lead fingers extends over the first die and the second package substrate is electrically isolated from the first package substrate. The device also includes a second die attached to a first major surface of the second package substrate, over the first die, and an encapsulant surrounding the first die, the first package substrate, the second die, and the second package substrate, wherein the encapsulant exposes a portion of the first package substrate and a portion of the second package substrate.. ... Freescale Semiconductor Inc

09/28/17 / #20170278768

Packaged device with extended structure for forming an opening in the encapsualant

A packaged device includes an extended structure located at a major side of the packaged device. The extended structure defines an outer area that includes encapsulated material on the major side and an inner area where there is a lack of encapsulant over a portion of the device at the major side. ... Freescale Semiconductor Inc

09/28/17 / #20170278763

Semiconductor device package and methods of manufacture thereof

A method of manufacturing a packaged semiconductor device includes forming an assembly by placing a semiconductor die over a substrate with a die attach material between the semiconductor die and the substrate. A conformal structure which includes a pressure transmissive material contacts at least a portion of a top surface of the semiconductor die. ... Freescale Semiconductor Inc

09/28/17 / #20170277647

Integrated circuit with pin level access to io pins

An integrated circuit (ic) having multiple cores controls write access to its input/output (i/o) pins. The ic includes a pin-control circuit, a memory, and a set of i/o pins. ... Freescale Semiconductor Inc

09/28/17 / #20170276738

Multiple axis magnetic sensor

A magnetic field sensor for sensing an external magnetic field along a sensing direction comprises a sensor bridge. The sensor bridge has a first sensor leg that includes a first magnetoresistive sense element and a second sensor leg that includes a second magnetoresistive sense element. ... Freescale Semiconductor Inc

09/14/17 / #20170265228

Linear combination for rach detection

A method including receiving, by an antenna combiner of a wireless communication system, a set of random access channel (rach) sequences of a first rach signal from a first antenna and a set of rach sequences of a second rach signal from a second antenna. The method further including selecting, by the antenna combiner, each rach sequence of the set of rach sequences of a selected rach signal from a selected antenna that has a best signal to interference plus noise ratio (sinr) from each rach sequence of the set of rach sequences of the first rach signal from the first antenna that has a first sinr and each rach sequence of the set of rach sequences of the second rach signal from the second antenna that has a second sinr.. ... Freescale Semiconductor Inc

09/14/17 / #20170264124

Regulation circuit having analog and digital feedback and method therefor

A regulation circuit for powering a device while charging a battery is provided. The regulation circuit includes at least one analog feedback loop, and a digitally controlled feedback loop. ... Freescale Semiconductor Inc

09/14/17 / #20170263538

Packaged semiconductor device having bent leads and method for forming

A package device has a first lead frame having a first flag. A first integrated circuit is on the first flag. ... Freescale Semiconductor Inc

09/14/17 / #20170263324

Sector retirement for split-gate memory

A memory is provided. The memory includes an array of non-volatile memory (nvm) cells arranged in a plurality sectors. ... Freescale Semiconductor Inc

09/07/17 / #20170257466

System and method for adaptive learning time based network traffic manager

Data packets are received at a media access control interface. An arbitration policy at a traffic management controller adapts to changes in network traffic characteristics by implementing a learning phase during which processing time information based upon individual packets is updated. ... Freescale Semiconductor Inc

09/07/17 / #20170255485

Data processing system having dynamic thread control

A method for managing thread execution in a processing system is provided. The method includes setting a first watchpoint, and generating a first watchpoint trigger corresponding to the first watchpoint. ... Freescale Semiconductor Inc

08/31/17 / #20170250730

Passive equalizer capable of use in high-speed data communication

A passive equalizer is provided. The passive equalizer includes a first resistive element, a first inductive element, a second resistive element, and a first variable capacitor. ... Freescale Semiconductor Inc

08/31/17 / #20170250656

Multiple path amplifier with pre-cancellation

A device includes a first amplifier coupled to a first signal conduction path and a second amplifier coupled to a second signal conduction path. A first coupler is coupled to the first signal conduction path. ... Freescale Semiconductor Inc

08/31/17 / #20170249993

Memory repair system and method therefor

A memory system includes a main memory array, a redundant memory array, and a content addressable memory (cam). The cam includes a plurality of entries, wherein each entry includes a plurality of column address bits and a plurality of maskable row address bits. ... Freescale Semiconductor Inc

08/31/17 / #20170249103

Data processing system having a write request network and a write data network

A data processing system includes a plurality of switch points interconnected by a write data network and a write request network. Each switch point includes write request switch circuitry having write request ingress ports and write request egress ports coupled to the write request network and arbitration circuitry configured to grant a write request received at one of the write request ingress ports access to one of the write request egress ports. ... Freescale Semiconductor Inc

08/31/17 / #20170247247

Integrated capacitive humidity sensor

A semiconductor device composed of a capacitive humidity sensor comprised of a moisture-sensitive polymer layer electrografted to an electrically conductive metal layer situated on an cmos substrate or a combined mems and cmos substrate, and exposed within an opening through a passivation layer, packages composed of the encapsulated device, and methods of forming the capacitive humidity sensor within the semiconductor device, are provided.. . ... Freescale Semiconductor Inc

08/24/17 / #20170244582

Fixed-point conjugate gradient digital pre-distortion (dpd) adaptation

A predistortion method and apparatus are provided which use a dpd actuator (225) to apply a memory polynomial formed with first dpd coefficients to a first input signal x[n], thereby generating a first pre-distorted input signal y[n] which is provided to the non-linear electronic device (253) to produce the output signal, where the memory polynomial may be adaptively modified with a digital predistortion adapter (224) which computes second dpd coefficients u[n] with an iterative fixed-point conjugate gradient method which uses n received digital samples of the first pre-distorted input signal y[n] and a feedback signal z[n] captured from the output signal to process a set of conjugate gradient parameters (u, b, v, r, ω, α, β) at each predetermined interval, thereby updating the first dpd coefficients with the second dpd coefficients u[n] generate a second pre-distorted input signal which is provided to the non-linear electronic device.. . ... Freescale Semiconductor Inc

08/24/17 / #20170244395

Circuit for reducing negative glitches in voltage regulator

A circuit that stabilizes an output signal of a voltage regulator includes a glitch amplifier, a pulse generator, and a transistor. The glitch amplifier amplifies glitches in the output signal and generates a glitch amplifier output signal. ... Freescale Semiconductor Inc

08/10/17 / #20170230311

Buffer allocation and use for packet cloning and mangling

A method of cloning and mangling a received data packet in which an unused space of a receiving buffer can be used to accommodate at least some generated clone packets. Additional memory-use efficiencies can be realized by employing scatter-gather lists in the process of clone-packet generation when the size of the received data packet exceeds a predetermined threshold size. ... Freescale Semiconductor Inc

08/10/17 / #20170229444

Esd protection circuit

Electrostatic discharge (esd) protection circuitry in an integrated circuit is provided. The protection circuitry includes a trigger circuit coupled between a first power supply bus and a second power supply bus. ... Freescale Semiconductor Inc

08/10/17 / #20170227982

Secure clock switch circuit

An integrated circuit (ic) having a clock switch that switches the system clock between an internal clock and an external clock based on whether or not the ic has finished downloading device configuration at boot and on whether or not the internal clock is functional. Further restrictions on the use of the external clock are imposed by the clock switch based on a life-cycle state of the ic. ... Freescale Semiconductor Inc

08/10/17 / #20170227409

On-die temperature sensor for integrated circuit

An on-die temperature sensor measures temperature during a temperature-measurement session. A ptat (proportional-to-absolute-temperature) generator generates an analog ptat voltage that is dependent on temperature. ... Freescale Semiconductor Inc

08/03/17 / #20170223637

Receiver removal detection in wireless charging systems

A wireless charging system has a transmitter and a receiver. The transmitter has (i) a tx coil that wirelessly transfers power to the receiver and (ii) tx circuitry that powers the tx coil and detects receiver removal by comparing tx input power and tx power loss. ... Freescale Semiconductor Inc

08/03/17 / #20170223152

Network application verification at a network processor

A network application is verified at a network processor by selecting network application functions based on a field of an ingress packet. The network application is composed of a set of network application functions, with each function carrying out a corresponding packet processing operation, such as packet parsing, statistical gathering, and the like. ... Freescale Semiconductor Inc

08/03/17 / #20170220491

Direct interface between sram and non-volatile memory

A memory system comprises an sram array and a nvm array. The sram array and nvm array are both organized in rows and columns. ... Freescale Semiconductor Inc

08/03/17 / #20170220414

Multi-dimensional parity checker (mdpc) systems and related methods for external memories

Multi-dimensional parity checker (mdpc) systems and related methods are disclosed to check parity of data regions within external memories. In one embodiment, the mdpc system includes a control register and a parity checker. ... Freescale Semiconductor Inc

07/27/17 / #20170213601

Full address coverage during memory array built-in self-test with minimum transitions

A method and apparatus for generating an address sequence in a memory device is provided. The method includes providing a memory array having a set of unique addresses, storing one of a first subset of the set of unique addresses in a first storage element, storing one of a second subset of the set of unique addresses in a second storage element, and generating a sequence of addresses to test the memory array. ... Freescale Semiconductor Inc

07/27/17 / #20170212800

System and method for performing bus transactions

A system that performs a bus transaction includes a transaction controller and a protection code processing circuit. The transaction controller identifies a set of parameters corresponding to the bus transaction based on address and received control information, and modifies at least one parameter or splits the bus transaction into sub-transactions depending on the parameter values to map the bus transaction to a memory address space. ... Freescale Semiconductor Inc

07/27/17 / #20170212189

Magnetic field sensor with permanent magnet biasing

A magnetic field sensor comprises a sensor bridge having multiple sensor legs. Each sensor leg includes magnetoresistive sense elements located in a plane of the magnetic field sensor. ... Freescale Semiconductor Inc

07/27/17 / #20170212176

Magnetic field sensor with skewed sense magnetization of sense layer

A magnetic field sensor comprises a sensor bridge having multiple sensor legs. Each sensor leg includes magnetoresistive sense elements, each comprising a pinned layer having a reference magnetization parallel to a plane of the sensor and a sense layer having a sense magnetization that is skewed away from three orthogonal axes. ... Freescale Semiconductor Inc

07/27/17 / #20170212175

Magnetic field sensor with multiple sense layer magnetization orientations

A magnetic field sensor comprises a sensor bridge having multiple sensor legs. Each sensor leg includes magnetoresistive sense elements, each comprising a pinned layer having a reference magnetization parallel to a plane of the sensor and a sense layer having a sense magnetization. ... Freescale Semiconductor Inc

07/06/17 / #20170195981

System and method for automatic delay compensation in a radio base station system

A method including performing a delay measurement of a first round trip delay value of an interface link, the first round trip delay value based on a transmission of a first rec synchronization signal to a re and when a rec receives a first re synchronization signal back, wherein frames transmitted by the rec are synchronized based upon the first rec synchronization signal, and frames transmitted by the re are synchronized based upon the first re synchronization signal. Calculating a first delay change value between the first round trip delay value and a previous round trip delay value, in response to determining that the first delay change value violates a delay tolerance value, transmitting an offset indicator that indicates an amount of offset the re is to shift the first re synchronization signal at a future time, and transmitting frames from the rec after shifting the first rec synchronization signal.. ... Freescale Semiconductor Inc

07/06/17 / #20170194488

Semiconductor device with floating field plates

A semiconductor device with a current terminal region located in a device active area of a substrate of the device. A guard region is located in a termination area of the device. ... Freescale Semiconductor Inc

07/06/17 / #20170192790

Providing task-triggered determinisitic operational mode for simultaneous multi-threaded superscalar processor

A task identifier-based mechanism is configured to temporarily disable a dual-issue capability of one or more threads in a superscalar simultaneous multi-threaded core. The core executes a first thread and a second thread which are each provided with a dual-issue capability wherein up to two instructions may be issued in parallel. ... Freescale Semiconductor Inc

07/06/17 / #20170192040

Current sensing circuit and method

The present application relates to a circuit arrangement for sensing a current. The circuit arrangement comprises a current sense circuit configured to cause the sense current through a sense transistor, wherein the sense current is representative of a load current through a load transistor. ... Freescale Semiconductor Inc

06/29/17 / #20170187399

Transmitter output driver circuits for high data rate applications, and methods of their operation

Embodiments of single-ended and differential output driver circuits include one or more complementary data switch pairs, each coupled to a t-coil. Each complementary data switch pair is coupled between a voltage source and a ground reference node, and each complementary data switch pair includes complementary transistors, each with a control terminal, a first current conducting terminal, and a second current conducting terminal. ... Freescale Semiconductor Inc

06/29/17 / #20170185519

Computing system with a cache invalidation unit, a cache invalidation unit and a method of operating a cache invalidation unit in a computing system

The present application relates to a cache invalidation unit for a computing system having a processor unit, cpu, with a cache memory, a main memory and at least one an alternate bus master unit. The cpu, the main memory and the at least one an alternate bus master unit are coupled via an interconnect for data communications between them. ... Freescale Semiconductor Inc

06/22/17 / #20170181192

Apparatus for reception and detection of random access channel (rach) data

An apparatus for reception and detection of rach data in an lte input signal includes a hardware accelerator that has a decimator that filters and down-samples the input signal, a first fourier transform circuit that transforms the decimated signal from the time domain to the frequency domain, and a second transform circuit that multiplies the resulting signal by a complex z-c sequence and performs an inverse fourier transform (ift) operation to transform the multiplied signal from the frequency domain to the time domain. A dsp performs a delay profile analysis operation on the signal resulting from the ift operation.. ... Freescale Semiconductor Inc

06/22/17 / #20170180253

Hash-based packet classification with multiple algorithms at a network processor

A network processor has a “bi-level” architecture including a classification algorithm level and a single-record search level to search a hash database that stores packet classification information based on packet field values. The classification algorithm level implements multiple different classification algorithm engines, wherein the individual algorithm applied to a received packet can be selected based on a field of the packet, a port at which the packet was received, or other criteria. ... Freescale Semiconductor Inc

06/22/17 / #20170179898

Amplifier devices with in-package bias modulation buffer

The embodiments described herein include amplifiers that are typically used in radio frequency (rf) applications. The amplifiers described herein use a buffer that is implemented inside the device package. ... Freescale Semiconductor Inc

06/22/17 / #20170179279

Partial, self-biased isolation in semiconductor devices

A device includes a semiconductor substrate, a buried doped isolation layer disposed in the semiconductor substrate to isolate the device, a drain region disposed in the semiconductor substrate and to which a voltage is applied during operation, and a depletion region disposed in the semiconductor substrate and having a conductivity type in common with the buried doped isolation barrier and the drain region. The depletion region reaches a depth in the semiconductor substrate to be in contact with the buried doped isolation layer. ... Freescale Semiconductor Inc

06/22/17 / #20170179049

Power grid balancing apparatus, system and method

A semiconductor apparatus for power distribution on a die, the semiconductor apparatus, comprising a first die, wherein the first die comprises a first integrated circuit, a dam coupled to the first die, wherein the dam is a metal ring, a second die, wherein the second die comprises a second integrated circuit, wherein the first and second dies are stacked together and are electrically connected, and a pair of metal connectors coupled to the dam and an edge of the first die, wherein power and ground wires are coupled to the dam, wherein the power transmitted through the power and ground wires is distributed through the dam and metal connectors to the first die and wherein the power transmitted to the first die is distributed to the to the second die.. . ... Freescale Semiconductor Inc

06/22/17 / #20170177432

Memory controller and method of operating a memory controller

The present application relates to a memory controller and a method of operating thereof. The memory controller comprises a transaction interface arranged to be coupled to a transaction interconnect to receive a write transaction comprising write data; a mode controller arranged to obtain context information and to select a data protection scheme out of a plurality of data protection schemes based on the obtained context information; at least one data protection module to apply the selected data protection scheme by generating one or more protection code sequences from at least the write data in accordance with the selected data protection scheme; and a physical memory interface coupled to at least one memory device to store the write data and the one or more protection code sequences in the at least one memory device.. ... Freescale Semiconductor Inc

06/22/17 / #20170177428

Memory error detection system

An error detection system detects errors in data packets stored in a memory. A read signature generation circuit generates a read signature of a first data packet. ... Freescale Semiconductor Inc

06/22/17 / #20170176535

Clock gating for x-bounding timing exceptions in ic testing

An integrated circuit includes a clock gate that is used to prevent timing exception paths from affecting data being captured by scan chain registers during at-speed scan testing. A single clock gate can be used to control multiple timing-exception paths, so the amount of x-bounding circuitry inserted into the ic can be drastically reduced compared to that required by conventional x-bounding methodologies.. ... Freescale Semiconductor Inc

06/15/17 / #20170171343

Method and apparatus to accelerate session creation using historical session cache

A method and apparatus receive packets, wherein the packets comprise headers, and the headers comprise session parameter values, route the packets in response to the session parameter values matching an active traffic session entry of the active traffic session entries in an active traffic session cache memory, match the session parameter values against historical session entries in an historical session cache memory in response to the session parameter values not matching any active traffic session entry of the active traffic session entries in the active traffic session cache memory, wherein the historical session entries for traffic sessions in the historical session cache memory persist after the traffic sessions are no longer active, and, in response to the session parameter values not matching any historical session entry of the historical session entries in the historical session cache memory, performing a packet security check on the packets.. . ... Freescale Semiconductor Inc

06/15/17 / #20170171268

System and method for on-the-fly modification of the properties on an active antenna carrier in radio base station communication operation

A method performed by a radio base station, the method including receiving streaming data information, the data information includes a first portion from a first set of antenna carriers and a second portion from a second set of antenna carriers, wherein the first portion is to be processed prior to the second portion. The method further including streaming the first portion of the data information from a radio equipment control device in a first data frame over an interface link that is configured to operate based on a first mapping configuration that indicates a set of locations of the first data frame at which the first portion of information is to be streamed, and streaming the second portion of the data information from the rec device in a second data frame over the interface link that is configured to operate based on a second mapping configuration.. ... Freescale Semiconductor Inc

06/15/17 / #20170171088

System and method for automatic load adaptive antenna carrier bandwidth dynamic reconfiguration in radio base station system

A method performed by a radio base station, the method including determining that one of a direct memory access (dma) buffers of a communication link for a service provider has gone beyond a dma buffer limit (empty or full), the communication link between a radio equipment control (rec) device and a radio equipment (re) device that is operating based on a first bandwidth configuration of the communication link. The method further including in response to determining that the communication link is to change operation (due to reaching the dma buffer limit) based on a second bandwidth configuration of the communication link, instead of the first bandwidth configuration, continuing operation of the communication link based on the second bandwidth configuration. ... Freescale Semiconductor Inc

06/15/17 / #20170171064

Adapative message caches for replay/flood protection in mesh network devices

Adaptive message caches are disclosed for packet replay and/or flood protection in mesh network devices. The adaptive message cache includes a replay protection area (rpa) and a flood protection area (fpa). ... Freescale Semiconductor Inc

06/15/17 / #20170169156

Designing a density driven integrated circuit

A design tool system includes a schematic design tool that computes a total number of devices in an analog circuit schematic based on information extracted from the analog circuit schematic. The schematic design tool selects an optimal row/column device configuration for the total number of devices and creates a temporary layout based upon the optimal row/column device configuration. ... Freescale Semiconductor Inc

06/15/17 / #20170168934

Memory controller with interleaving and arbitration scheme

A memory controller that implements an interleaving and arbitration scheme includes an address decoder that selects a memory bank for an access request based on a set of address least significant bits included in the access request. A core requiring sequential access to memory is routed to consecutive memory banks of the memory for consecutive access requests. ... Freescale Semiconductor Inc

06/15/17 / #20170168745

System and method for modulo addressing vectorization with invariant code motion

A processing device includes a target processor instruction memory to store a plurality of memory access instructions, and a compiler. A vector invariant candidate detection module of the compiler to determine whether the memory access instruction is to be replaced by vector invariant access code, and in response: the complier to generate first replacement code that vectorizes the memory access instruction using vector invariant access code, and to replace the memory access instruction with the first replacement code. ... Freescale Semiconductor Inc

06/08/17 / #20170164333

Base transceiver station for reducing congestion in communcation network

A base transceiver station (bts) includes dedicated memories to store uplink real-time (rt) data received by way of an antenna of the bts and downlink rt data generated by processors of the bts. The dedicated memories serve a dedicated number of processors, which prevents over-run and under-run of antenna buffers and provides deterministic data flow necessary to stream time-critical uplink and downlink rt data. ... Freescale Semiconductor Inc

06/08/17 / #20170163274

Low-power clock repeaters and injection locking protection for high-frequency clock distributions

A low power clock distribution circuit system (200) includes a clock generator (201) for generating a high frequency clock signal that is supplied to a clock interconnect running to multiple lanes of an integrated circuit, each lane including a passive clock repeater circuit (e.g., 203) having a differential-mode rlc network (e.g., 301) that is shielded by an active guard ring structure (e.g., 511) and that is coupled to receive first and second input clock signals (vip, vin) to provide clock signal gain boosting at a predetermined frequency range and clock signal attenuation out of the operating frequency range, thereby generating the first and second output clock signals (vop, von) that are provided to a clocked circuit (e.g., 211).. . ... Freescale Semiconductor Inc

06/08/17 / #20170162168

Adaptive instrument cluster

An adaptive instrument cluster (aic) is employed in a device, such as an automobile, wherein the aic adjusts a display of instrumentation information based on one or more of captured imagery, user eye position, and device conditions. Based on these factors the aic can adjust the appearance, position, information display format, and other aspects of one or more instrument gauges. ... Freescale Semiconductor Inc








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