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Freescale Semiconductor Inc patents (2015 archive)


Recent patent applications related to Freescale Semiconductor Inc. Freescale Semiconductor Inc is listed as an Agent/Assignee. Note: Freescale Semiconductor Inc may have other listings under different names/spellings. We're not affiliated with Freescale Semiconductor Inc, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "F" | Freescale Semiconductor Inc-related inventors


12/31/15 / #20150382316

Search method and apparatus for a communication system

A method of searching of base stations in a mobile communication system has a first stage of detecting at least one slot boundary, a second stage of detecting at least one frame boundary and a scrambling code group, and a third stage of detecting a scrambling code. Multiple possible base stations are identified by determining a first threshold based on correlation values of correlating the input signal with a primary synchronization channel code. ... Freescale Semiconductor Inc

12/31/15 / #20150381220

Adaptive high-order nonlinear function approximation using time-domain volterra series to provide flexible high performance digital pre-distortion

A method is described for predistorting an input signal to compensate for non-linearities caused to the input signal in producing an output signal. The method comprises: providing an input for receiving a first input signal as a plurality of signal samples, x[n], to be transmitted over a non-linear element; providing at least one digital predistortion block comprising, a plurality of iq predistorter cells coupled to the input, each comprising a lookup table (lut) for generating an lut output the at least one digital predistortion block block is configured to apply interpolation between lut entries for the, plurality of luts; and generate an output signal, y[n], by each of the plurality of iq predistorter cells by adaptively modifying the first input signal using interpolated lut entries to compensate for distortion effects in the non-linear element. ... Freescale Semiconductor Inc

12/31/15 / #20150381216

Adaptive high-order nonlinear function approximation using time-domain volterra series to provide flexible high performance digital pre-distortion

A method and apparatus are used to predistort input signal samples according to volterra series approximation model using one or more digital predistortion blocks (300) having a plurality of predistorter cells (301-303), each including an input multiplication stage (366-367) for combining absolute sample values received from an absolute sample delay line (362) into a first stage output, a lookup table (368) connected to be addressed by the first stage output for generating an lut output, and a plurality of output multiplication stages (371-372, 373-374) for combining the lut output with samples received from the amplitude sample delay line (362) and signal sample delay line (363) to generate an output signal sample yq from said predistorter cell, where the output signal samples yq from the predistorter cells are combined at an output adder circuit (375) to generate one or more volterra terms of a combined signal (yout[n]).. . ... Freescale Semiconductor Inc

12/31/15 / #20150381198

Apparatus and method for monitoring electrical current

An apparatus for sensing current of a vehicle battery employs an extended counting analogue-to-digital conversion process to a chopped and amplified voltage appearing across a low ohmic shunt resistor placed between the negative pole of the vehicle's battery and the chassis ground of the vehicle. Gain adjustment control of a programmable gain amplifier by matching the gain to the dynamic range of the adc permits a high dynamic signal sensing.. ... Freescale Semiconductor Inc

12/31/15 / #20150381167

Gate drive circuit and a method for controlling a power transistor

A gate drive circuit drives a control terminal of a power transistor and comprises: a drive terminal for electrically coupling the control terminal, a first reference source, a first switch arranged between the first reference source and the control terminal, a switch control circuit and a measurement circuit. The first switch is switched-on to turn-off the power transistor. ... Freescale Semiconductor Inc

12/31/15 / #20150381140

Method and apparatus for a multi-harmonic matching network

A matching network and method for matching a source impedance to a load impedance is provided. A bias feed microstrip structure is coupled to a direct current (dc) voltage source and has a bias feed microstrip electrical length less than one fifth of a fundamental wavelength of a fundamental frequency component of an input signal. ... Freescale Semiconductor Inc

12/31/15 / #20150381117

Radio frequency devices with surface-mountable capacitors for decoupling and methods thereof

An embodiment of a radio-frequency (rf) device includes at least one transistor, a package, and a surface-mountable capacitor. The package contains the at least one transistor and includes at least one termination. ... Freescale Semiconductor Inc

12/31/15 / #20150380513

Bipolar transistor device fabrication methods

A method of fabricating a bipolar transistor device includes performing a first plurality of implantation procedures to implant dopant of a first conductivity type to form emitter and collector regions laterally spaced from one another in a semiconductor substrate, and performing a second plurality of implantation procedures to implant dopant of a second conductivity type in the semiconductor substrate to form a composite base region. The composite base region includes a base contact region, a buried region through which a buried conduction path between the emitter and collector regions is formed during operation, and a base link region electrically connecting the base contact region and the buried region. ... Freescale Semiconductor Inc

12/31/15 / #20150380408

Method of forming different voltage devices with high-k metal gate

A method and apparatus are described for integrating high voltage (hv) transistor devices and medium voltage or dual gate oxide (dgo) transistor devices with low voltage (lv) core transistor devices on a single substrate, where each high voltage transistor device (160) includes a metal gate (124). An upper high-k gate dielectric layer (120), a middle gate dielectric layer (114) formed with a relatively lower high-k dual gate oxide layer, and a lower high voltage gate dielectric stack (108, 110) formed with one or more low-k gate oxide layers (22), where each dgo transistor device (161) includes a metal gate (124), an upper high-k gate dielectric layer (120), and a middle gate dielectric layer (114) formed with a relatively lower high-k dual gate oxide layer, and where each core transistor device (162) includes a metal gate (124), an upper high-k gate dielectric layer (120), and a base oxide layer (118) formed with one or more low-k gate oxide layers.. ... Freescale Semiconductor Inc

12/31/15 / #20150380353

Method of fabricating an integrated circuit device, and an integrated circuit device therefrom

A method of fabricating an integrated circuit (ic) device includes mounting, via a first surface thereof, at least one semiconductor die on to a surface of an ic device package, mounting, via an interconnect surface thereof, at least one fuse component on to a second surface of the at least one semiconductor die, the second surface of the at least one semiconductor die having at least one terminal of the at least one active component. The at least one fuse component is mounted such that the interconnect surface of the at least one fuse component is thermally coupled to the second surface of the at least one semiconductor die and electrically coupled to the at least one terminal of the at least one active component. ... Freescale Semiconductor Inc

12/31/15 / #20150380317

Semiconductor device and driver circuit with drain and isolation structure interconnected through a diode circuit, and method of manufacture thereof

Embodiments of semiconductor devices and driver circuits include a semiconductor substrate having a first conductivity type, an isolation structure (including a sinker region and a buried layer), an active device within area of the substrate contained by the isolation structure, and a diode circuit. The buried layer is positioned below the top substrate surface, and has a second conductivity type. ... Freescale Semiconductor Inc

12/31/15 / #20150380067

Memory controller

A system provides synchronous read data sampling between a memory and a memory controller, which includes an asynchronous fifo buffer and which outputs a clock and other control signals. An outbound control signal (e.g., read_enable) is used to time-stamp the beginning of a read access using a clock edge counter. ... Freescale Semiconductor Inc

12/31/15 / #20150379971

Display processor and method for display processing

A display processor device is for processing display image data by overlaying a multitude of image layers. Pixel values of at least one of the image layers are stored in a memory and may comprise pixels values having a single predefined value, such as transparency. ... Freescale Semiconductor Inc

12/31/15 / #20150379276

System on a chip, controller and method for securing data

A system on a chip for securing data is described. The system on a chip comprises: a controller arranged to: partition a data block into a plurality of segments; and determine and extract a subset of the plurality of segments to be compressed. ... Freescale Semiconductor Inc

12/31/15 / #20150379181

Routing standard cell-based integrated circuits

This disclosure describes a multi-height routing cell and utilization of the multi-height routing in an integrated circuit to reduce routing congestion in a standard cell design floorplan. The multi-height routing cell includes a bypass connection, or “tunnel,” that routes a signal through a non-routing layer and under an impeding power rail. ... Freescale Semiconductor Inc

12/31/15 / #20150379175

Ic design synthesis using slack diagrams

An updated integrated circuit (ic) design is generated by applying a histogram-based algorithm to an invalid, current ic design. The histogram-based algorithm includes worst negative slack (wns) optimization followed by total negative slack (tns) optimization. ... Freescale Semiconductor Inc

12/31/15 / #20150378944

A method of and circuitry for controlling access by a master to a peripheral, a method of configuring such circuitry, and associated computer program products

A method of controlling access by a master to a peripheral includes receiving one or more interrupt priority levels from one or more interrupt controllers associated with the peripheral, comparing the one or more interrupt priority level with respective one or more pre-established interrupt access levels to obtain an interrupt level comparison result, establishing whether an access condition is satisfied in dependence on at least the interrupt level comparison result, and if the access condition is satisfied, granting access. If the access condition is not satisfied, access is denied. ... Freescale Semiconductor Inc

12/31/15 / #20150378730

System on a chip with managing processor and method therefor

A system on a chip comprises a managing processor for controlling operations of the system on a chip. The managing processor comprises a core monitor control logic circuit operable to: receive at least one instruction; determine whether the instruction is an activation instruction; determine whether the managing processor is in or transitioning to an idle state; and transition the managing processor from a first mode of operation to a second mode of operation in response to the instruction being an activation instruction and the managing processor being in or transitioning to an idle state.. ... Freescale Semiconductor Inc

12/31/15 / #20150378385

Integrated circuit with internal and external voltage regulators

An integrated circuit that supports both internal and external voltage regulators as well as various modes, such as a low power mode or a test mode, includes voltage regulator selection circuitry and power control circuitry. The regulator selection circuitry selects one of internal and external regulators based on two pin conditions. ... Freescale Semiconductor Inc

12/31/15 / #20150377933

Integrated circuit, current sense circuit for a pulse width modulation driver and method therefor

A current sense circuit for a pwm driver comprises: a pwm control circuit comprising: a first switching device arranged to receive a pwm signal from the pwm driver whose current is to be sensed; and a second switching device whose supply current is arranged to track the sensed current of the pwm driver. An adc is operably coupled to the first and second switching device. ... Freescale Semiconductor Inc

12/31/15 / #20150375995

Mems fabrication process with two cavities operating at different pressures

A method and apparatus are described for fabricating a high aspect ratio mems sensor device having multiple vertically-stacked inertial transducer elements (101b, 110d) formed in different layers of a multi-layer semiconductor structure (100) and one or more cap devices (200, 300) bonded to the multi-layer semiconductor structure (100) to protect any exposed inertial transducer element from ambient environmental conditions.. . ... Freescale Semiconductor Inc

12/31/15 / #20150375989

Microelectromechanical systems devices with improved lateral sensitivity

Microelectromechanical system (mems) devices and methods for forming mems devices are provided. The mems devices include a substrate, an anchored structure fixedly coupled to the substrate, and a movable structure resiliently coupled to the substrate. ... Freescale Semiconductor Inc

12/24/15 / #20150372930

Apparatus, system and method for controlling packet data flow

. . A system for use in nodes communicating over a cpri (common public radio interface) allows each networking node in a daisychain configuration to seamlessly manage the control and management hdlc (high-speed data link control) channel for both uplink and downlink. The connection is kept alive through a soft reset flow. ... Freescale Semiconductor Inc

12/24/15 / #20150372130

Power device termination structures and methods

Power device termination structures and methods are disclosed herein. The structures include a trenched-gate semiconductor device. ... Freescale Semiconductor Inc

12/24/15 / #20150371720

System and method for testing address-swap faults in multiport memories

A system method of detecting address-swap faults in a multiport memory as described herein includes minimum testing for inversion faults and bit-swap faults for each port of the multiport memory. Different test types may be performed for inversion and bit-swap including pass/fail, and diagnostic testing for locating faulty ports. ... Freescale Semiconductor Inc

12/24/15 / #20150371711

Control gate driver for use with split gate memory cells

A circuit for driving a control gate of a split-gate nonvolatile memory cell may include a switched current source; a first transistor having a current electrode coupled to the switched current source and a control electrode coupled to a voltage source; a second transistor having a current electrode coupled to a second node of the switched current source, and a control electrode coupled to a third voltage source; a third transistor having a control electrode coupled to the second transistor, a current electrode coupled to the first transistor and a fourth switched voltage source; and a fourth transistor having a current electrode coupled to the first switched voltage source, a control electrode coupled to the switched current source, and a second current electrode coupled to the second transistor at a driver voltage node, wherein a voltage level at the driver voltage node is operable to drive the control gate.. . ... Freescale Semiconductor Inc

12/24/15 / #20150370580

Configuration controller for and a method of controlling a configuration of a circuitry

A configuration controller for and a method of controlling a configuration of a circuitry are provided. The configuration controller comprises an input, a selection checker, a data selector and an output. ... Freescale Semiconductor Inc

12/24/15 / #20150370568

Integrated circuit processor and method of operating a integrated circuit processor

A processor includes an instruction pipeline. The pipeline can be operated alternatively in a multi-thread mode and in a single-thread mode. ... Freescale Semiconductor Inc

12/24/15 / #20150370535

Method and apparatus for handling incoming data frames

A method and apparatus for handling incoming data frames within a network interface controller. The network interface controller comprises at least one controller component operably coupled to at least one memory element. ... Freescale Semiconductor Inc

12/24/15 / #20150370312

Electronic monitoring device having wake-up for daisy chain

A monitoring device has an event monitor, an uplink interface to a chain controller device, and a downlink interface to a further monitoring device, and a daisy controller for coupling the uplink to the chain downlink. The event monitor, in response to detecting an event in sleep mode, generates a wake-up signal. ... Freescale Semiconductor Inc

12/24/15 / #20150370280

Voltage regulator with improved load regulation

A voltage regulator comprises a ground node, a pick-off node, a regulator branch, a load branch, and a current mirror the regulator branch and the load branch are connected in parallel between the pick-off node and the ground node; the load branch comprises one or more resistive connecting lines that are connectable in series with the load to generate a load current through the load branch; the regulator branch comprises a bias node, a resistive element, and a tap node; the bias node is arranged to provide a regulated bias voltage; the resistive element is connected between the bias node and the pick-off node; and the tap node is connected between the bias node and the resistive element. The current mirror is connected to the tap node and arranged to draw a mirror current from the tap node; the mirror current having a component that is proportional to the load current.. ... Freescale Semiconductor Inc

12/24/15 / #20150369903

Active iq and quadrature generator for high frequency applications

An active i/q generator circuit comprises an input node for receiving a reference oscillation signal. The circuit has an i-output and a q-output for respectively outputting an i-signal and a q-signal. ... Freescale Semiconductor Inc

12/24/15 / #20150369845

Integrated circuit with integrated current sensor

An integrated circuit die includes a stack of a substrate and multiple layers extending in parallel to the substrate. A number of integrated electronic components is formed in the stack, and connected to form an electronic circuit. ... Freescale Semiconductor Inc

12/24/15 / #20150368099

Etch release residue removal using anhydrous solution

A method of making a microelectromechanical systems (mems) device includes etching away a sacrificial material layer to release a mechanical element of the mems device. The mems device is formed at least partially on the sacrificial material layer, and the etching leaves a residue in proximity to the mechanical element. ... Freescale Semiconductor Inc

12/17/15 / #20150365845

Wireless communication system with sipto continuity

. . A communication system network element includes a local gateway co-located with a home enodeb. The local gateway has an open flow switch and a flow table, and provides service continuity of active sipto (selective ip traffic offload) sessions using open flow/software defined networking. ... Freescale Semiconductor Inc

12/17/15 / #20150365224

Techiques for time-domain frame synchronization of packets

A technique for frame synchronization in a communication system includes performing symbol correlation on received signal samples. A determination is made as to whether a magnitude of the symbol correlation is greater than a first threshold. ... Freescale Semiconductor Inc

12/17/15 / #20150364996

Power converter and controller device

A switching power converter for dc-dc converting has an inductance coupled between a power output and a high side switch in a controller device. The controller device has an error amplifier coupled to the power output and a reference voltage for activating the high side switch. ... Freescale Semiconductor Inc

12/17/15 / #20150364830

Integrated circuit package with radio frequency coupling structure

An integrated circuit package comprises an electrically conductive material, a first electrically isolating layer having a first side in contact with the electrically conductive material and a second side opposite to the first side, a second electrically isolating layer stacked at the second side with at least the first electrically isolating layer and arranged at a package side, and an integrated antenna structure arranged between the first electrically isolating layer and the second electrically isolating layer. The electrically conductive material is encapsulated by a dielectric material, arranged to partly overlap the integrated antenna structure, separated from the integrated antenna structure by at least the first electrically isolating layer and arranged to reflect a radio frequency signal received by the electrically conductive material through at least the first electrically isolating layer to the package side.. ... Freescale Semiconductor Inc

12/17/15 / #20150364829

Integrated circuit package with radio frequency coupling arrangement

An integrated circuit package comprises a dielectric material, a first stack comprising at least a first electrically isolating layer and a second electrically isolating layer arranged at a first side of the integrated circuit package, an electrically conductive material arranged on a second side opposed to the first side, and an integrated antenna structure for transmitting and/or receiving a radio frequency signal arranged between the first and second electrically isolating layers. The electrically conductive material is separated from the integrated antenna structure by at least the dielectric material and the first electrically isolating layer, arranged to partly overlap the integrated antenna structure and to reflect the radio frequency signal received by the electrically conductive material through at least the first electrically isolating layer and the dielectric material to the first side.. ... Freescale Semiconductor Inc

12/17/15 / #20150364804

Radio frequency coupling structure

A radio frequency coupling structure is arranged to couple a radio frequency signal between a first side of the radio frequency coupling structure to a second side of the radio frequency coupling structure opposite to the first side. The radio frequency coupling structure comprises a dielectric layer, a first electrically conductive layer comprising a first transition structure, a second electrically conductive layer comprising a second transition structure, and an integrated waveguide structure formed by an array of electrically conductive vias extending through the dielectric layer from the first to the second electrically conductive layer to enclose a portion of the dielectric layer. ... Freescale Semiconductor Inc

12/17/15 / #20150364576

Reliability in mergeable semiconductor devices

A method of fabricating a transistor device having a channel of a first conductivity type formed during operation in a body region having a second conductivity type includes forming a first well region of the body region in a semiconductor substrate, performing a first implantation procedure to counter-dope the first well region with dopant of the first conductivity type to define a second well region of the body region, and performing a second implantation procedure to form a source region in the first well region and a drain region in the second well region.. . ... Freescale Semiconductor Inc

12/17/15 / #20150364439

Semiconductor device having power distribution using bond wires

A semiconductor device uses insulated bond wires to connect peripheral power supply and ground bond pads on the periphery of the device to array power supply and ground bond pads located on an interior region of a integrated circuit die of the device. Power supply and ground voltages are conveyed from array bond pads using vertical vias down to one or more corresponding inner power distribution layers. ... Freescale Semiconductor Inc

12/17/15 / #20150364212

Margin tool for double data rate memory systems

A tool for testing a double data rate (“ddr”) memory controller to ensure that data strobe transitions are aligned with data eyes to achieve a desired data integrity during data transfers between the memory controller and the memories. After the memory controller completes its training sequence during the initialization process, the tool sweeps the data strobe transition across the data eye. ... Freescale Semiconductor Inc

12/17/15 / #20150363533

Voltage and current limits for electronic device based on temperature range

A design verification system simulates operation of an electronic device to identify one or more power characteristic vs. Temperature (pc-t) curves for the electronic device. ... Freescale Semiconductor Inc

12/17/15 / #20150363448

Method of, and a device for updating a multiple-processing entity packet management system, and associated computer program product

There is described a method of managing a flow of data packets in a multiple-processing entity system comprising a plurality of look-up tables adapted to store information associated to actions to be performed on packets received by the system. The method comprises storing, on a per entry basis, in a shadowed entry associated to any table entry being updated, the previous content of said table entry being updated, in association with a table entry version number, for use for managing packets received in the system prior to any update operation. ... Freescale Semiconductor Inc

12/17/15 / #20150363227

Data processing unit and method for operating a data processing unit

A data processing unit providing a core instruction set wherein the core instruction set comprises a specific core instruction that is adapted to receive data for specifying a hardware component to be called, call the hardware component for executing a job, perform a first context switch that suspends an actual task, wherein the actual task previously called the hardware component using the specific core instruction, perform a second context switch that resumes the actual task when the hardware component finished the job and a method for operating such a data processing unit.. . ... Freescale Semiconductor Inc

12/17/15 / #20150362942

Method of trimming current source using on-chip adc

A method of trimming a current source in an ic includes deriving a reference voltage from an external supply, and developing a measurement voltage across an external reference resistance receiving the current to be trimmed. An on-chip adc is used to provide corresponding digital reference and digital measurement signals. ... Freescale Semiconductor Inc

12/10/15 / #20150357452

Semiconductor device with selectively etched surface passivation

. . A semiconductor device includes a semiconductor substrate configured to include a channel, first and second ohmic contacts supported by the semiconductor substrate, in ohmic contact with the semiconductor substrate, and spaced from one another for current flow between the first and second ohmic contacts through the channel, and first and second dielectric layers supported by the semiconductor substrate. At least one of the first and second ohmic contacts extends through respective openings in the first and second dielectric layers. ... Freescale Semiconductor Inc

12/10/15 / #20150357338

Methods and structures for multiport memory devices

A memory device includes a storage unit formed using a substrate, a true bit line bl0 for carrying a bit of data, and a complementary bit line for carrying the bit of data carried by the first true bit line in complementary form. The true bit line is coupled to the storage unit and runs laterally over the substrate. ... Freescale Semiconductor Inc

12/10/15 / #20150357324

Semiconductor device and driver circuit with source and isolation structure interconnected through a diode circuit, and method of manufacture thereof

Embodiments include methods of forming a semiconductor device having a first conductivity type, an isolation structure (including a sinker region and a buried layer), an active device within area of the substrate contained by the isolation structure, and a diode circuit. The buried layer is positioned below the top substrate surface, and has a second conductivity type. ... Freescale Semiconductor Inc

12/10/15 / #20150357270

Integrated electronic package and method of fabrication

An integrated electronic package includes an integrated circuit (ic) die and conductive discrete components. Electrical interconnects are formed directly between bond pads on an active side of the ic die and contacts on the conductive discrete components without an intervening lead frame. ... Freescale Semiconductor Inc

12/10/15 / #20150356224

Method and control device for circuit layout migration

A method for circuit layout migration comprises creating a list of layout components in a source layout; determining a plurality of first groups of layout components being regularly aligned horizontally or vertically; determining first subsets of layout components which each belong to at least two of a respective set of determined first groups; determining a plurality of second groups of layout components, each second group comprising mutually exclusive ones of the first subsets of layout components; determining symmetry axes for pairs of second groups; building a constraint graph of the layout components of the source layout using alignment constraints for the alignment of layout components within each of the second groups and distance constraints for preserving a regularity pattern within each of the second groups and symmetry constraints for the determined symmetry axes for pairs of second groups; and performing constraint-graph-based compaction of the source layout.. . ... Freescale Semiconductor Inc

12/10/15 / #20150356054

Data processor and method for data processing

A integrated circuit device has at least one instruction processing module arranged for executing vector data processing upon receipt of a respective one of a set of data processing instructions. The data processing instructions include at least one matrix processing instruction for processing elements of a matrix. ... Freescale Semiconductor Inc

12/10/15 / #20150356016

Method of establishing pre-fetch control information from an executable code and an associated nvm controller, a device, a processor system and computer program products

A method of establishing pre-fetch control information from an executable code is described. The method comprises inspecting the executable code to find one or more instructions corresponding to an unconditional change in program flow during an execution of the executable code when the executable code is retrieved from a non-volatile memory [nvm] comprising a plurality of nvm lines. ... Freescale Semiconductor Inc

12/10/15 / #20150355938

System and method for conditional task switching during ordering scope transitions

A data processing system includes a processor core and a hardware module. The processor core performs tasks on data packets. ... Freescale Semiconductor Inc

12/10/15 / #20150355260

Ground-loss detection circuit

A ground-loss detection circuit for an integrated circuit, (ic) device including a first dynamic threshold metal oxide semiconductor (dtmos) device operably coupled between a first ground plane of the ic device and at least one further ground plane of the ic device, at least one of the first and at least one further ground planes comprising an external ground connection of the ic device, at least one further dtmos device operably coupled between the first and at least one further ground planes of the ic device in an opposing manner to the first dtmos device, and at least one ground-loss detection component operably coupled to at least one of the first and at least one further dtmos devices and arranged to detect a ground-loss for at least one of the first and at least one further ground planes based at least partly on a drain current of the at least one of the first and at least one further dtmos device(s).. . ... Freescale Semiconductor Inc

12/03/15 / #20150350927

Timing event generation circuit for wireless communication apparatus

. . A system or circuit for generating timing events for mobile communications includes fetching network parameters corresponding to a transmission configuration. The network parameters are used to program a set of programmable registers. ... Freescale Semiconductor Inc

12/03/15 / #20150349776

High side driver component and method therefor

A high side driver component for generating a drive signal at an output thereof for driving a high side switching device within a high voltage driver circuit. The high side driver component is arranged to operate in at least one reduced slew rate mode in which at least one drive stages is arranged to be in a non-drive state, and the high side driver component further comprises at least one discharge protection component arranged to, when the high side driver component is operating in the at least one reduced slew rate mode, receive an indication of the high voltage driver circuit being in an idle state, and cause the second switching device within the at least one drive stage in a non-drive state to be turned on, in response to the indication of the high voltage driver circuit being in an idle state.. ... Freescale Semiconductor Inc

12/03/15 / #20150349720

Power amplifiers with signal conditioning

A device includes an amplifier having a first path and a second path and a first variable attenuator connected to the first path. The device includes a controller coupled to the first variable attenuator. ... Freescale Semiconductor Inc

12/03/15 / #20150349499

Device and method for connecting an rf generator to a coaxial conductor

The present disclosure presents a device and method for connecting an rf generator to a coaxial conductor. The device includes a substrate, a radio frequency generator on the substrate, and a coaxial conductor coupled to a first surface of the substrate. ... Freescale Semiconductor Inc

12/03/15 / #20150349397

Resonating filter and method thereof

In general the embodiments described herein can provide alternating-current (ac) resonating filters. These resonating filters comprise a transmission line, a first resonator, and a second resonator. ... Freescale Semiconductor Inc

12/03/15 / #20150348920

Microelectronic packages having radiofrequency stand-off layers and methods for the production thereof

Microelectronic packages and methods for fabricating microelectronic packages are provided. In one embodiment, the method includes producing a plurality of vertically-elongated contacts in ohmic contact with interconnect lines contained within one or more redistribution layers built over the frontside of a semiconductor die. ... Freescale Semiconductor Inc

12/03/15 / #20150348898

Apparatus and method for placing stressors within an integrated circuit device to manage electromigration failures

A method for selecting locations within an integrated circuit device for placing stressors to manage electromigration failures includes calculating an electric current for an interconnect within the integrated circuit device and determining an electromigration stress profile for the interconnect based on the electric current. The method further includes determining an area on the interconnect for placing a stressor to alter the electromigration stress profile for the interconnect.. ... Freescale Semiconductor Inc

12/03/15 / #20150348648

Apparatus for measuring signal skew of asynchronous flash memory controller

A method of measuring skew between signals from an asynchronous integrated flash memory controller (ifc) includes connecting input/output (i/o) pins of the ifc to cycle based test equipment (ate). The ate applies a pattern of test signals as input drive to the ifc. ... Freescale Semiconductor Inc

12/03/15 / #20150348514

A method and apparatus for adaptive graphics compression and display buffer switching

There is provided a multimedia computing apparatus for processing and displaying video data with overlay graphic data, said multimedia computing apparatus comprising a compression unit arranged to compress graphic overlay data prior to storage of said compressed overlay graphic data in a compressed display buffer, and a control unit arranged to determine when to compress the overlay graphic data dependent upon a refresh parameter of the overlay graphic data. There is also provided a method of adaptively compressing graphics data in a multimedia computing system comprising dynamically controlling compression of graphic overlay data in a display buffer dependent upon a refresh parameter of the graphic overlay data.. ... Freescale Semiconductor Inc

12/03/15 / #20150347655

Apparatus for and a method of making a hierarchical integrated circuit design of an integrated circuit design, a computer program product and a non-transitory tangible computer readable storage medium

An apparatus for and a method of making a hierarchical integrated circuit design of an integrated circuit design, a computer program product and a non-transitory tangible computer readable storage medium are provided. The apparatus comprises an input for receiving an hierarchical integrated circuit design, a selector for selecting a candidate output pin, a cloner for adapting the hierarchical integrated circuit design, a re-connector for adapting the hierarchical integrated circuit design, and an output for outputting the adapted hierarchical circuit design. ... Freescale Semiconductor Inc

12/03/15 / #20150347653

Method and apparatus for calculating delay timing values for an integrated circuit design

A method and apparatus for calculating delay timing values for at least a part of an integrated circuit design. The method comprises applying a first negative/positive bias temperature instability compensation margin to delay values for elements within the at least part of the ic design, identifying at least one lower-rate switching element within the at least part of the ic design, and applying at least one further, increased n/pbti compensation margin to the delay value(s) for the at least one identified lower-rate switching element.. ... Freescale Semiconductor Inc

12/03/15 / #20150347645

Correlation of test results and test coverage for an electronic device design

A device simulation system performs a set of tests by applying, for each test in the set, a corresponding test stimulus to a simulation of the electronic device. In response to each test stimulus, the simulation generates corresponding output information which the device simulation system compares to a specified expected outcome to identify a test result for that test stimulus. ... Freescale Semiconductor Inc

12/03/15 / #20150347332

A common public radio interface lane controller

A common public radio interface, cpri, lane controller of a processor, in a time division duplex, tdd, system, said cpri lane controller comprising: a direct memory access (or more than one), dma, controller connected to a memory through a switch fabric to perform read or/and write memory access transactions via an internal system bus of said processor, wherein said dma controller is adapted to generate a rx/tx transaction interrupt(s) for each completed memory access rx/tx transaction counted by a corresponding transaction counter(s) which provides a tdd slot awareness interrupt(s) when a rx/tx tdd slot has terminated, wherein said dma controller has a steering control(s) adapted to steer the memory access transactions either to said memory or to be legitimately blocked by said switch fabric in response to said tdd slot awareness interrupt(s) to save bandwidth, bw, of the internal system bus of said processor.. . ... Freescale Semiconductor Inc

12/03/15 / #20150347218

Indicating internal transmitter errors in a controller area network (can)

Systems and methods for indicating internal transmitter errors in a controller area network (can). In some embodiments, a method may include initiating, by a device coupled to a can, transmission of a message via the can; detecting an error by the device during the transmission; and continuing, by the device after having detected the error, the transmission of the message without causing or indicating a bus error condition. ... Freescale Semiconductor Inc

12/03/15 / #20150347185

Explicit barrier scheduling mechanism for pipelining of stream processing algorithms

A method for pipelined data stream processing of packets includes determining a task to be performed on each packet of a data stream, the task having a plurality of task portions including a first task portion. Determining the first task portion is to process a first packet. ... Freescale Semiconductor Inc

12/03/15 / #20150346290

Magnetic field sensor with z-axis self-test capability

A magnetic field sensor includes in-plane sense elements located in a plane of the magnetic field sensor and configured to detect a magnetic field oriented perpendicular to the plane. A current carrying structure is positioned proximate the magnetic field sensor and includes at least one coil surrounding the in-plane sense elements. ... Freescale Semiconductor Inc

12/03/15 / #20150346277

Electronic device and method for state retention

An electronic device includes a set of two or more scan chains and a buffer chain. Each of the scan chains includes a sequence of stateful elements connected in series, and each of the scan chains is arranged to hold a string having a length identical to the length of the (50) respective scan chain. ... Freescale Semiconductor Inc

12/03/15 / #20150346274

Input/output cell, integrated circuit device and methods of providing on-chip test functionality

An i/o cell comprising a first set of driver stages comprising, each driver stage of the first set comprising a high side switch controllable to couple an i/o node of the i/o cell to a first high voltage supply node and a low side switch controllable to couple the i/o node of the i/o cell to a first low voltage supply node. The i/o cell further comprising a second set of driver stages, each driver stage of the second set comprising a high side switch controllable to couple the i/o node of the i/o cell to a second high voltage supply node and a low side switch controllable to couple the i/o node of the i/o cell to a second low voltage supply node. ... Freescale Semiconductor Inc

12/03/15 / #20150346272

System for testing integrated circuit

An integrated circuit (ic) is connected to an automated test equipment (ate) with pogo pins. The ic includes an analog-to-digital converter (adc), a voltage controlled oscillator (vco), and a compensation circuit. ... Freescale Semiconductor Inc

12/03/15 / #20150346046

Pressure sensor having multiple pressure cells and sensitivity estimation methodology

A pressure sensor (20) includes a test cell (32) and sense cell (34). The sense cell (34) includes an electrode (42) formed on a substrate (30) and a sense diaphragm (68) spaced apart from the electrode (42) to produce a sense cavity (64). ... Freescale Semiconductor Inc

12/03/15 / #20150345946

Drive circuitry and method for a vibration gyroscope

A drive circuitry for a vibration gyroscope is described. The drive circuitry comprises a digital phase shifter, a variable gain amplifier and a pulse signal generator arranged to generate a digital pulse signal having a frequency substantially equal to a drive frequency of the vibration gyroscope. ... Freescale Semiconductor Inc

11/26/15 / #20150342069

Housing for electronic devices

. . Traces are formed and electronic components are mounted on an interior surface of a housing of an electronic device. Various methods are disclosed for integrating the housing with the electronic components including vacuum molding, metal forming, injection molding, and 3d printing of traces. ... Freescale Semiconductor Inc

11/26/15 / #20150341429

Packet processing architecture and method therefor

A packet processing architecture includes a plurality of packet processing stages, wherein at least one of the packet processing stages includes multiple next processing stage modules that are operably coupled to respective further processing stages, wherein the multiple next processing stage modules are dynamically configurable.. . ... Freescale Semiconductor Inc

11/26/15 / #20150341029

Semiconductor device and power circuit including a sense transistor for current sensing

A semiconductor device comprises a power transistor and a sense transistor. The power transistor conducts a power transistor current. ... Freescale Semiconductor Inc

11/26/15 / #20150340980

Device for determining a position of a rotor of a polyphase electric motor

A device for determining a rotor position in a polyphase electric motor having a first phase, a second phase and a third phase. A power control unit applies a first voltage on the first phase, and a second voltage on the second phase, the first voltage and the second voltage being periodic signals of opposite polarity, alternating between a first part and a second part of the alternating period, such as square waves. ... Freescale Semiconductor Inc

11/26/15 / #20150340305

Stacked die package with redistribution layer

A packaged semiconductor device has lead fingers that define a cavity, and a first die located within the cavity. A second die abuts an inactive side of the first die. ... Freescale Semiconductor Inc

11/26/15 / #20150339427

Integrated circuit hierarchical design tool apparatus and method of hierarchically designing an integrated circuit

An integrated circuit hierarchical design tool apparatus comprises a processor arranged to support a block coupling reconfiguration unit. The block coupling reconfiguration unit is capable of receiving block layout data comprising block placement, terminal location data and intra-block connectivity data. ... Freescale Semiconductor Inc

11/26/15 / #20150339413

Method and apparatus for performing logic synthesis

A method of performing logic synthesis of at least a part of an integrated circuit design. The method comprises identifying a first and at least one further module within the ic design that are mutually exclusive, selecting at least one register element within the first identified module and at least one register element within the at least one further identified module to be shared, and merging the first and at least one further mutually exclusive modules such that at least one common register element is shared between the first and at least one further mutually exclusive modules for the register elements selected to be shared.. ... Freescale Semiconductor Inc

11/26/15 / #20150339264

Processing device and method for performing a stage of a fast fourier transform

A data processing device and a method for performing second or next stage of an n point fast fourier transform is suggested. The processing device comprises an input operand memory unit and an input buffer comprising a plurality of addressable memory cells arranged in lines and columns. ... Freescale Semiconductor Inc

11/26/15 / #20150339177

Processing device and method of executing an instruction sequence

A processing device and a method of executing an instruction sequence are described. The processing device comprises a status register for providing a status word, wherein execution of an instruction by the processing device comprises updating the status word, wherein the instruction sequence comprises a subsequence of one or more selected instructions, and wherein execution of a selected instruction by the processing device further comprises a status check which comprises: providing a set of valid status words; verifying whether the updated status word is in the set of valid status words; and initiating an alert action if the updated status word is not in the set of valid status words.. ... Freescale Semiconductor Inc

11/26/15 / #20150339124

System and method for selectively allocating entries at a branch target buffer

A branch instruction and a corresponding branch instruction address are received at a data processing system. A first value is received and is compared to a portion of the branch instruction address. ... Freescale Semiconductor Inc

11/26/15 / #20150338864

Supply voltage regulation with temperature scaling

A supply voltage regulation system for an ic including a temperature sensor that detects temperature of the ic, a scaling resistor coupled between a power grid and a feedback node of the ic, a regulator amplifier that compares a voltage of the feedback node with a reference voltage for developing a supply voltage for the ic, and a temperature scaling circuit that drives a scaling current to the scaling resistor via the feedback node to adjust the supply voltage based on temperature. The temperature scaling circuit may include one or more comparators that compare a temperature signal with corresponding temperature thresholds for selectively applying one or more bias currents to the scaling resistor. ... Freescale Semiconductor Inc

11/26/15 / #20150338464

Method and apparatus for sampling a signal

There is provided a method, apparatus and integrated circuit for measuring a signal, the apparatus comprising a plurality of sample stages arranged in series, each sample stage comprising a delay element, and a sample element, wherein an input of the sample element is coupled to an output of the delay element, and a strobe line for controlling a sample time of the sample elements, the strobe line comprising a plurality of strobe delay elements arranged in series, wherein an output of each strobe delay element is coupled to one or more sample elements.. . ... Freescale Semiconductor Inc

11/26/15 / #20150338227

Navigation system

An electronic device is for providing navigation information for a driver of a vehicle. The device has a location unit for determining geographical location data based on satellite signals, a navigation processor coupled to at least one sensor comprising a sound sensor. ... Freescale Semiconductor Inc

11/26/15 / #20150336556

A homogeneity detection circuit, a valve driving system and a method of homogeneity detection in a valve driving system

A homogeneity detection circuit, a valve driving system, a vehicle, an integrated circuit and a method of homogeneity detection in a valve driving system are provided. The homogeneity detection circuit comprises a first input, a second input and a comparison circuit. ... Freescale Semiconductor Inc

11/19/15 / #20150333805

Methods of manufacturing and operating die-to-die inductive communication devices

Embodiments of inductive communication devices include first and second ic die and an inductive coupling substrate. The first ic die has a first coil. ... Freescale Semiconductor Inc

11/19/15 / #20150333754

Method and control device for recovering nbti/pbti related parameter degradation in mosfet devices

The invention provides a method for recovering nbti/pbti related parameter degradation in mosfet devices. The method includes operating the at least one mosfet device in a standby mode, exiting the at least one mosfet device from the standby mode, holding the at least one mosfet device in an active state for a predetermined time span after exiting the standby mode, and operating the at least one mosfet device in an operational mode after the predetermined time span has elapsed.. ... Freescale Semiconductor Inc

11/19/15 / #20150333706

Radio frequency power amplifier circuit

An rf power amplifier circuit has an input terminal for receiving an input signal having an input power, and an output terminal for outputting an output signal. The rf power amplifier circuit comprises three amplifier stages and an input power splitter for providing respective power fraction signals to respective inputs of each amplifier stage. ... Freescale Semiconductor Inc

11/19/15 / #20150333695

Voltage controlled oscillator

A voltage controlled oscillator (vco) comprising a first supply node, a second supply node, an oscillation transistor, a biasing network, an output node and a feedback network is described. The vco is be powered by a supply voltage applied across the first and second supply nodes. ... Freescale Semiconductor Inc

11/19/15 / #20150333568

Supply-switching system

A system for providing a first voltage generated by a main supply and a second voltage generated by a battery to an integrated circuit (ic) includes supply-selection, control logic and switching circuits. The supply-selection circuit includes first, second, and third transistors. ... Freescale Semiconductor Inc

11/19/15 / #20150333556

Single power supply level shifter

A single power supply level shifter has first and second inverters in tandem that invert an input signal from a first voltage domain and provide a first inverted signal and an output signal in a second voltage domain. A charging control circuit charges a capacitor towards the second voltage when the input signal is high, and conducts a discharge current from the capacitor during a transition of the input signal from high to low to accelerate a corresponding transition of the first inverted signal from low to high. ... Freescale Semiconductor Inc

11/19/15 / #20150333189

Zener diode devices and related fabrication methods

Zener diode structures and related fabrication methods and semiconductor devices are provided. An exemplary semiconductor device includes first and second zener diode structures. ... Freescale Semiconductor Inc

11/19/15 / #20150333177

Semiconductor device with composite drift region and related fabrication method

A device includes a semiconductor substrate, a body region in the semiconductor substrate having a first conductivity type and in which a channel is formed during operation, source and drain regions in the semiconductor substrate and having a second conductivity type, the source region being disposed on the body region, and a composite drift region in the semiconductor substrate, having the second conductivity type, and through which charge carriers from the source region drift to reach the drain region after passing through the channel. The composite drift region includes a first section adjacent the channel, a second section adjacent the drain region, and a third section disposed between the first and second sections. ... Freescale Semiconductor Inc

11/19/15 / #20150333031

Semiconductor device with mechanical lock features between a semiconductor die and a substrate

An embodiment of a method of attaching a semiconductor die to a substrate includes placing a bottom surface of the die over a top surface of the substrate with an intervening die attach material. The method further includes contacting a top surface of the semiconductor die and the top surface of the substrate with a conformal structure that includes a non-solid, pressure transmissive material, and applying a pressure to the conformal structure. ... Freescale Semiconductor Inc

11/19/15 / #20150332980

Programmable stitch chaining of die-level interconnects for reliability testing

A method includes fabricating a set of die in a production run, each die comprising a set of pads at a periphery of a top metal layer, a first set of fuse elements, and a second set of fuse elements. Each fuse element of the first set of fuse elements couples a corresponding pad of the set to a corresponding bus when in a conductive state, and each fuse element of the second set couples a corresponding subset of pads of the set together when in a conductive state. ... Freescale Semiconductor Inc

11/19/15 / #20150332069

Programmable direct memory access channels

A storage location of a device that can be configured to act as a master in a particular security mode, such as a direct memory access (dma) having one or more channels, can be programmed to indicate a security indicator to be provided when configured to operate as a master device.. . ... Freescale Semiconductor Inc

11/19/15 / #20150331740

Error pad for safety device

A safety device with an error indication function includes at least one error pad configured between the error indication function and at least one normal function, and a set of multiplexers connected to the error pad. The safety device further includes an error indication block and a functional block multiplexed by the set of multiplexers. ... Freescale Semiconductor Inc

11/19/15 / #20150331466

Method and apparatus for managing a thermal budget of at least a part of a processing system

A method of managing a thermal budget, for at least a part of a processing system, is described. The method comprises, upon detection of a use case event, determining a thermal budget violation time window for a current use case scenario of the at least part of the processing system, and managing the thermal budget for the at least part of the processing system based at least partly on the determined thermal budget violation time window.. ... Freescale Semiconductor Inc

11/19/15 / #20150331047

A method and apparatus for scan chain data management

Processing logic circuit for use in a computing system has state retention power gating logic circuit including at least two scan chains having different lengths and operable to collect state information about at least a portion of the processing logic circuit before the at least a portion of the processing logic circuit is placed from a first state into a second, different, state. The processing logic circuit includes a memory operable to store collected state information about the at least a portion of the processing logic circuit, and logic circuit operable to rearrange the collected state information data for scan chains shorter than a longest scan chain within the at least a portion of the processing logic circuit, to enable valid return of the collected state information data, for the scan chains shorter than a longest scan chain, to the at least a portion of the processing logic circuit when the at least a portion of the processing logic circuit returns to the first state.. ... Freescale Semiconductor Inc

11/19/15 / #20150331044

Scan flip-flop circuit with los scan enable signal

A scan flip-flop for generating an output signal based on a first input signal, a clock signal, a test input signal, a launch on shift (los) signal, a test enable signal, and a reset signal includes a logic circuit, a multiplexer and a flip-flop circuit. The logic circuit receives an inverted clock signal, the test enable signal, a intermediate test enable signal, and the los signal, and generates an intermediate output signal that is an inherent los scan enable signal. ... Freescale Semiconductor Inc

11/19/15 / #20150331040

Integrated circuit device, safety circuit, safety-critical system and method of manufacturing an integrated circuit device

An integrated circuit device comprises a first integrated circuit and a second integrated circuit wherein the first and second integrated circuits are comprised on a single semiconductor die. The second integrated circuit is a safety circuit arranged to monitor the operation of the first integrated circuit, report any detected faults and drive the device into a failsafe state if a fault is detected. ... Freescale Semiconductor Inc

11/19/15 / #20150329352

Microelectronic packages having stacked accelerometer and magnetometer die and methods for the production thereof

Methods for fabricating multi-sensor microelectronic packages and multi-sensor microelectronic packages are provided. In one embodiment, the method includes positioning a magnetometer wafer comprised of an array of non-singulated magnetometer die over an accelerometer wafer comprised of an array of non-singulated accelerometer die. ... Freescale Semiconductor Inc

11/12/15 / #20150326235

Capacitive arrangement for frequency synthesizers

An electronic device has a capacitive arrangement for controlling a frequency characteristic. The capacitive arrangement has varactor banks having a number of parallel coupled varactors and a control input for switching the respective varactors on or off. ... Freescale Semiconductor Inc

11/12/15 / #20150326114

Self-bootstrap driving circuit and dc-dc converter

A self-bootstrap driving circuit includes a first input receiving a first control signal; an output, to which a load having an electro-inductive component may be connected; a power switch having first and second current terminals and a control terminal, and being arranged to drive power from a power supply terminal to the load; a bootstrap circuitry arranged to drive the control terminal of the power switch based on the control signal; and a current path between the electro-inductive component of the load and the control terminal of the switch, said current path being arranged to provide direct transfer from said electro-inductive component to said control terminal of the switch of an overvoltage generated at the electro-inductive component to provide an overdrive voltage to said control terminal of the switch.. . ... Freescale Semiconductor Inc

11/12/15 / #20150325908

Electronic high frequency device and manufacturing method

An electronic device includes a wiring board having one or more layers, an integrated circuit arranged on the wiring board, an antenna, and a signal path. The integrated circuit generates a high frequency signal and feeds it to the signal path. ... Freescale Semiconductor Inc

11/12/15 / #20150325674

Methods of fabricating diodes with multiple junctions

An embodiment of a method of fabricating a diode having a plurality of regions of a first conductivity type and a buried region of a second conductivity type includes performing a first dopant implantation procedure to form the buried region, performing a second dopant implantation procedure to form an intermediate region of the plurality of regions, and performing a third dopant implantation procedure to form a contact region of the plurality of regions. The second and third dopant implantation procedures are configured such that the intermediate region is electrically connected with the contact region. ... Freescale Semiconductor Inc

11/12/15 / #20150325565

Composite semiconductor device with multiple threshold voltages

A device includes a semiconductor substrate, a first constituent transistor including a first plurality of transistor structures in the semiconductor substrate connected in parallel with one another, and a second constituent transistor including a second plurality of transistor structures in the semiconductor substrate connected in parallel with one another. The first and second constituent transistors are disposed laterally adjacent to one another and connected in parallel with one another. ... Freescale Semiconductor Inc

11/12/15 / #20150325305

Power supply slew rate detector

In some embodiments, a power supply slew rate detector may include a filter circuit having a capacitive element operably coupled to a power supply output provided to a flash memory circuit and a resistive element operably coupled to the capacitive element and to ground, and a schmitt trigger including an input operably coupled to a node between the capacitive element and the resistive element, the schmitt trigger further including an output configured to indicate a slew rate of the power supply output.. . ... Freescale Semiconductor Inc

11/12/15 / #20150324611

Layout-optimized random mask distribution system and method

A data processing system includes a module for generating and distributing random masks to a number of cryptographic accelerators while providing for fewer total interconnects among the components generating the random masks. The module segments the tasks associated with generating random masks across a number of modules and blocks such that routing and timing problems can be minimized and layout can be optimized. ... Freescale Semiconductor Inc

11/12/15 / #20150324584

Method and device for providing a security breach indicative audio alert

A device for providing a security breach indicative audio alert. The device includes: a security monitor adapted to detect a security breach in device and a loudspeaker, the device wherein including a secure audio alert generating hardware, adapted to participate, in response to the detection of the security breach, in a generation of a security breach indicative audio alert. ... Freescale Semiconductor Inc

11/12/15 / #20150324287

A method and apparatus for using a cpu cache memory for non-cpu related tasks

There is provided a processor for use in a computing system, said processor including at least one central processing unit (cpu), a cache memory coupled to the at least one cpu, and a control unit coupled to the cache memory and arranged to obscure the existing data in the cpu cache memory, and assign control of the cpu cache memory to at least one other entity within the computing system. There is also provided a method of using a cpu cache memory for non-cpu related tasks in a computing system.. ... Freescale Semiconductor Inc

11/12/15 / #20150321907

Sequential wafer bonding

Embodiments of a sensor device include a sensor substrate and a first cap substrate attached to the sensor substrate with a first bond material. The first bond material is arranged to define a first device cavity. ... Freescale Semiconductor Inc

11/05/15 / #20150318848

Segmented driver for a transistor device

A segmented driver including at least one drive pin and a sense pin, a driver circuit, a comparator, and a controller. The driver circuit activates a selected drive level between the drive pins and a reference node. ... Freescale Semiconductor Inc

11/05/15 / #20150318842

Apparatus and method for preventing multiple resets

Multiple resets in a system-on-chip (soc) during boot where on-board regulators and low voltage detector circuits have different trimmed and untrimmed values may be avoided by the inclusion of a series of latches that latch the trimmed values during boot and retain the trim values even during a soc reset event. The soc is prevented from entering into a reset loop during boot or when exiting reset for any reason other than boot. ... Freescale Semiconductor Inc

11/05/15 / #20150318832

Configurable power amplifier and related construction method

A multiple-path, configurable, radio-frequency (rf) circuit is provided, including: a first amplifier path amplify a first rf signal to generate a first amplified signal; a second amplifier path configured to amplify a second rf signal to generate a second amplified signal; a corrective input matching circuit, configured to change first input-impedance-matching properties of the first amplifier path, and to change second input-impedance-matching properties of the second amplifier path; a first isolation element configured to selectively ground an input node of the second amplifier path; a second isolation element configured to selectively ground an output node of the second amplifier path; and a third isolation element connected between the first and second amplifier paths, configured to selectively isolate the corrective input matching circuit from first and second input nodes of the first and second amplifier paths, respectively, or connect the corrective input matching circuit to the first and second input nodes.. . ... Freescale Semiconductor Inc

11/05/15 / #20150318827

Power amplifier with envelope injection

A device and a method for an amplifier having reduced intermodulation (im) distortion output products are presented. An amplifier has an output, and at least one of a gate bias input and a drain supply input. ... Freescale Semiconductor Inc

11/05/15 / #20150318240

Aluminum clad copper structure of an electronic component package

An electronic component package that includes a package substrate having an aluminum bond pad formed from an aluminum clad copper structure. The aluminum clad copper structure is attached to a dielectric layer. ... Freescale Semiconductor Inc

11/05/15 / #20150317496

Method and apparatus for limiting access to an integrated circuit (ic)

A method and apparatus for limiting access to an integrated circuit (ic) upon detection of abnormal conditions is provided. At least one of abnormal voltage detection, abnormal temperature detection, and abnormal clock detection are provided with low power consumption. ... Freescale Semiconductor Inc

11/05/15 / #20150317119

Method and apparatus for estimating a fragment count for the display of at least one three-dimensional object

A method of estimating a fragment count for the display of at least one three-dimensional (3d) object. The method comprises determining an ellipsoid representative of a set of vertices defined by coordinates of the at least one 3d object, applying a transformation to the ellipsoid, calculating a projection area of the transformed ellipsoid, and estimating the fragment count for the display of the 3d object based at least partly on the calculated projection area of the transformed ellipsoid.. ... Freescale Semiconductor Inc

11/05/15 / #20150316950

Dual-edge gated clock signal generator

A clock signal generator provides a gated clock signal gclk to trigger operation of dual-edge triggered circuits. A first detector generates, while a clock gating signal /en is asserted, a first detector output signal that is asserted or de-asserted as a function of disjunction or conjunction respectively of the values that an input clock signal clk and the gated clock signal gclk had when the clock gating signal /en transitioned. ... Freescale Semiconductor Inc

11/05/15 / #20150316602

Apparatus and method for monitoring operation of an insulated gate bipolar transistor

Operation of an insulated gate bipolar transistor (igbt) is monitored by an apparatus that has a capacitor connected between a collector of the igbt and an input node. A processing circuit, coupled to the input node, responds to current flowing through the capacitor by providing an indication whether a voltage level at the collector is changing and the rate of that change. ... Freescale Semiconductor Inc

11/05/15 / #20150316503

Differential pair sensing circuit structures

A differential pair sensing circuit (300) includes control gates (306, 316) for separately programming a reference transistor (350) and a chemically-sensitive transistor (351) to a desired threshold voltage vt to eliminate the mismatch between the transistors in order to increase the sensitivity and/or accuracy of the sensing circuit without increasing the circuit size.. . ... Freescale Semiconductor Inc

10/29/15 / #20150311898

Spare gate cell for integrated circuit

Spare gate cells for inclusion in an integrated circuit have multiple inputs and outputs and are capable of selectively performing, concurrently, multiple logic functions on signals appearing at the inputs. Selection of required logic functions depends on the connections of at least one of the inputs of the spare cell. ... Freescale Semiconductor Inc

10/29/15 / #20150311842

Method and apparatus for detecting a state of an alternator regulator

A detection circuit for an alternator regulator, and method therefor. The detection circuit comprises an input circuit arranged to receive a phase signal from an alternator regulator and to output an attenuated sense signal representative of the received phase signal, a detection component operably coupled to the input circuit and arranged to receive the attenuated sense signal output by the input circuit, and a blocking capacitance operably coupled between the input circuit and the detection component and arranged to block a dc component of the attenuated sense signal. ... Freescale Semiconductor Inc

10/29/15 / #20150311193

A semiconductor device comprising an esd protection device, an esd protection circuitry, an integrated circuit and a method of manufacturing a semiconductor device

A semiconductor device is provided which comprises an esd protection device. The esd protection device is being formed by one or more pnp transistors which are present in the structure of the semiconductor device. ... Freescale Semiconductor Inc

10/29/15 / #20150311143

Lead frames having metal traces with metal stubs

A lead frame has a trace embedded in an encapsulant and a plurality of stubs (i) embedded in the encapsulant and (ii) connected to and extending from the trace at different locations along the length of the trace. The stubs inhibit the formation of cracks that may otherwise form along the trace due to thermal or mechanical bending of the lead frame, especially cracks that tend to occur along the four linear edge traces located at the periphery of some conventional embedded lead frames.. ... Freescale Semiconductor Inc

10/29/15 / #20150311131

Semiconductor package and system with an isolation structure to reduce electromagnetic coupling

A system and method for packaging a semiconductor device that includes a structure to reduce electromagnetic coupling is presented. The semiconductor device has a substrate on which a first circuit and a second circuit with inputs and outputs are formed proximate to each other. ... Freescale Semiconductor Inc

10/29/15 / #20150311084

Method for improving e-beam lithography gate metal profile for enhanced field control

A semiconductor device is provided which includes a gan-on-sic substrate (50-51) and a multi-layer passivation stack (52-54) in which patterned step openings (76) are defined and filled with gate metal layers using a lift-off gate metal process to form a t-gate electrode (74) as a stepped gate electrode having sidewall extensions and a contact base portion with one or more gate ledges.. . ... Freescale Semiconductor Inc

10/29/15 / #20150310229

System on chip

A system on chip having two or more responder units and two or more protection units is provided. Each of the responder units comprises a set of responder elements. ... Freescale Semiconductor Inc

10/29/15 / #20150310152

Method and apparatus for calculating delay timing values for an integrated circuit design

A method of calculating at least one delay timing value for at least one setup timing stage within an integrated circuit design includes applying negative/positive bias temperature instability (n/pbti) compensation margins to delay values for elements within the at least one setup timing stage, and calculating the at least one delay timing value for the at least one setup timing stage based at least partly on the n/pbti compensated delay values. The method further includes identifying at least partially equivalent elements within parallel timing paths of the at least one setup timing stage, and applying reduced n/pbti compensation margins to delay values for the identified at least partially equivalent elements within parallel timing paths of the at least one setup timing stage.. ... Freescale Semiconductor Inc

10/29/15 / #20150309847

Testing operation of multi-threaded processor having shared resources

A method of testing simultaneous multi-threaded operation of a shared execution resource in a processor includes running test patterns including irritator threads and non-irritator threads that try to simultaneously use the shared execution resource. Synchronizing the starts of the access of the irritator threads and the non-irritator threads to the shared execution resource includes the initial instructions of the irritator thread disabling execution of the irritator thread using a thread management register, and the initial instructions of the non-irritator thread enabling the irritator thread using the thread management register and starting execution of the non-irritator thread. ... Freescale Semiconductor Inc

10/29/15 / #20150309803

Method and apparatus for booting processor

A fail-safe booting system suitable for a system-on-chip (soc) automatically detects and rectifies failures in power-on reset (por) configuration or boot loader fetch operations. If a failure due to a boot loader fetch occurs, a por configuration and boot loader are fetched from a different non-volatile memory. ... Freescale Semiconductor Inc

10/29/15 / #20150309767

Adaptive control of an audio unit using motion sensing

A system for adaptive control of an audio unit associated with a vehicle includes an electronic key fob, wherein the electronic key fob includes a sensor adapted to detect a motion event imposed on the electronic key fob by a user and a controller coupled to the sensor and configured to produce a control signal in response to the motion event. The system further includes a receiver installed in the vehicle and adapted to receive the control signal and another controller installed in the vehicle and interconnected between the receiver and the audio unit. ... Freescale Semiconductor Inc

10/29/15 / #20150309730

System performance control component and method therefor

A system performance control component, and method therefor, for configuring at least one system performance parameter within a signal processing system. The system performance control component is arranged to receive an indication of an address of a memory access performed by at least one signal processing component, compare the received indication of an address of a memory access to at least one address value, and configure at least one system performance parameter based at least partly on the comparison of the received indication of an address of a memory access to at least one address value.. ... Freescale Semiconductor Inc

10/29/15 / #20150309527

Temperature coefficient factor circuit, semiconductor device, and radar device

A temperature coefficient factor circuit is provided which generates a current which varies with temperature according to a programmable temperature coefficient factor. The temperature coefficient factor circuit comprises a first current source providing a first current with a positive temperature coefficient factor, a second current source providing a second current with a negative temperature coefficient factor, a common terminal, a first programmable amplifying current mirror, a second programmable amplifying current mirror and a current output circuit. ... Freescale Semiconductor Inc

10/22/15 / #20150304971

Synchronization circuitry, common public radio interface enable device, and a method of synchronizing a synchronized clock signal of a second transceiver to a clock of a first transceiver

A controller device can control the time of a slave sub-system in a chain in a base station system. The controller device comprises a slave transceiver for receiving/transmitting from/to a master sub-system, and a synchronization device for synchronizing a clock of the slave transceiver to a clock of the master sub-system based on the received signal received from the master sub-system. ... Freescale Semiconductor Inc

10/22/15 / #20150303881

Radio frequency power amplifier module and a radio frequency power amplifier package

A rf power amplifier module comprises a die with a rf power transistor and the rf power transistor comprises a control terminal, a transistor output terminal and a transistor reference terminal. The rf power amplifier module further comprises a module input terminal, a module output terminal and at least two module reference terminals being electrically coupled to the control terminal, the transistor output terminal and the transistor reference terminal, respectively. ... Freescale Semiconductor Inc

10/22/15 / #20150303805

An inductive load control circuit, a braking system for a vehicle and a method of measuring current in an inductive load control circuit

A method and circuit for controlling current through an inductive load such as an electromagnetic valve of a vehicle anti-lock braking system includes first and second driver stages, controlled by pwm (pulse width modulation) signals, for providing, respectively, an actuation path for valve current in an “on” phase and a recirculation path for valve current in an “off” phase. A peak value of current flowing in the actuation path at the end of an “on” phase is compared with a peak value of current flowing in the recirculation path at the start of the “off” phase in order to detect any malfunction of the circuit. ... Freescale Semiconductor Inc

10/22/15 / #20150303137

Multi-use substrate for integrated circuit

A sub-assembly for a packaged integrated circuit (ic) device has a planar substrate. The substrate's top side has multiple sets electrically connected bond posts arranged in corresponding nested contour zones. ... Freescale Semiconductor Inc

10/22/15 / #20150301975

Multi-core processor for managing data packets in communication network

A system for managing data packets has multiple cores, a data buffer, a hardware accelerator, and an interrupt controller. The interrupt controller transmits a first interrupt signal to a first one of the cores based on a first hardware signal received from the hardware accelerator. ... Freescale Semiconductor Inc

10/22/15 / #20150301890

Apparatus for error detection in memory devices

The invention relates to an apparatus for transfer of data elements between a bus controller, such as a cpu, and a memory controller. An address translator is arranged to receive a write address from the cpu, to modify the write address and to send the modified write address to the memory controller. ... Freescale Semiconductor Inc

10/22/15 / #20150301828

Processor core arrangement, computing system and methods for designing and operating a processor core arrangement

The invention relates to a method of designing a processor core arrangement which comprises a first processor core for operation at a first operation frequency and having an associated first leakage and a second processor core for operation at a second operation frequency lower than the first operation frequency and having an associated second leakage lower than the first leakage. The processor core arrangement is capable of switching from the first processor core to the second processor core and vice versa.. ... Freescale Semiconductor Inc

10/22/15 / #20150300905

Semiconductor sensor with gel filled cavity

A pressure sensor has a housing having a bottom surface and side walls that form a cavity. A pressure sensor die is attached to the bottom of the cavity and covered with a layer of low modulus gel. ... Freescale Semiconductor Inc

10/22/15 / #20150300889

Temperature sensor circuitry

Temperature sensing circuitry implemented on a semiconductor integrated circuit that senses the temperature at a site, digitizes the sensed temperature, and then outputs a signal representing such a sensed temperature. The temperature sensing circuitry converts a voltage signal that is proportional to the temperature to a frequency-based signal, which is converted to a digital bit value. ... Freescale Semiconductor Inc

10/22/15 / #20150298964

Inhibiting propagation of surface cracks in a mems device

A microelectromechanical systems (mems) device includes a structural layer having a top surface. The top surface includes surface regions that are generally parallel to one another but are offset relative to one another such that a stress concentration location is formed between them. ... Freescale Semiconductor Inc

10/01/15 / #20150281742

Circuit arrangement and method for processing a digital video stream and for detecting a fault in a digital video stream, digital video system and computer readable program product

The present invention relates to a circuit arrangement for processing a digital video stream, the circuit arrangement comprising: an input interface for receiving a digital video stream, a processing circuit which is arranged to process the digital video stream, a hang-up detecting circuit for detecting a fault in the processed digital video stream, the hang-up detecting circuit comprising: a checksum generating circuit which is arranged to generate checksums for the frames of the processed digital video stream, a memory for storing generated checksums and an analyzing device arranged to compare a currently generated checksum to a plurality of corresponding checksums of preceding frames stored in the memory and to generate an error signal if at least one predefined amount of compared checksums are matching. The present invention also relates to a digital video system, a method for processing a digital video stream and a computer readable program product.. ... Freescale Semiconductor Inc

10/01/15 / #20150280732

Communication unit, digital band-pass sigma-delta modulator and method therefor

A communication unit comprises a power dac. The dac comprises: a switched mode power amplifier (smpa); and a digital band-pass sigma-delta modulator operably coupled to the smpa. ... Freescale Semiconductor Inc

10/01/15 / #20150280706

Self-powered gate drive circuit apparatus and method

A self-powered gate drive circuit comprising a first capacitor electrically coupled to a power semiconductor collector node of the circuit; a first switch arranged between the first capacitor and a second capacitor, the first switch electrically coupling the first and second capacitors when switched on; the second capacitor; a first diode, the first diode anode electrically coupled to the first capacitor and the first diode cathode electrically coupled to the first switch; a second diode, the second diode cathode electrically coupled to the first capacitor and the second diode anode electrically coupled with a ground node of the circuit; and a second switch, wherein the second switch electrically couples the second capacitor with a power semiconductor gate node when switched on.. . ... Freescale Semiconductor Inc

10/01/15 / #20150280705

Start-up technique and system for a self-powered gate drive circuit

A start-up method for a self-powered gate drive circuit driving a power transistor gate. The method comprises charging, with a single-supply voltage, a first supply capacitor of a first gate drive circuit; switching on a first power transistor by applying a current supplied by a discharge of the first supply capacitor of the first gate drive circuit to the gate of the first power transistor; charging a second supply capacitor of the first gate drive circuit using an output signal from the first power transistor; and re-charging the first supply capacitor by applying a current supplied by a discharge of the second supply capacitor to the first capacitor.. ... Freescale Semiconductor Inc

10/01/15 / #20150280665

Phase shift and attenuation circuits for use with multiple-path amplifiers

Embodiments of circuits for use with an amplifier that includes multiple amplifier paths include a first circuit and a second circuit in parallel with the first circuit. The first circuit includes a first input coupled to a first power divider output, a first output coupled to a first amplifier path of the multiple amplifier paths, and a first adjustable phase shifter and a first attenuator series coupled between the first input and the first output. ... Freescale Semiconductor Inc

10/01/15 / #20150280647

Converter unit for an m-order digital modulation and a method thereof

A converter unit for an m-order digital modulation to map l input binary sequences of n bits onto m complex values being transmitted through a communication channel, where m=2n and l and n are positive integers. The converter unit comprises an input to receive a respective input binary sequence. ... Freescale Semiconductor Inc

10/01/15 / #20150279836

Integrated circuit electrical protection device

An integrated circuit electrical protection device is disclosed that includes a semiconductor substrate and a plurality of transistor fingers partitioned into a plurality of segments. The segments are distinguished from one another by well-ties spaced apart from each other within a source/drain region that is shared by adjacent segments.. ... Freescale Semiconductor Inc

10/01/15 / #20150278010

Digital device

A digital device includes one or more requestor units, one or more responder units, and a bus. Each responder unit is connected to the requestor units via the bus and includes a plurality of responder elements which are accessible by the requestor units via the bus and which include one or more critical responder elements. ... Freescale Semiconductor Inc

10/01/15 / #20150277978

Network processor for managing a packet processing acceleration logic circuitry in a networking device

The invention relates to a network processor for managing communication between a central processing unit running tasks on one or more partitions, and a ppa logic circuitry. Management portals pass messages to and from the central processing unit. ... Freescale Semiconductor Inc

10/01/15 / #20150277973

System and method for conditional task switching during ordering scope transitions

A data processing system includes a processor core and a hardware module. The processor core performs tasks on data packets. ... Freescale Semiconductor Inc

10/01/15 / #20150277972

System and method for conditional task switching during ordering scope transitions

A data processing system includes a processor core and ordering scope manager circuitry. The processor core sends an indication of a first ordering scope identifier for a current ordering scope a task currently being executed by the processor core and a second ordering scope identifier for a next-in-order ordering scope of the task. ... Freescale Semiconductor Inc

10/01/15 / #20150276870

Method and apparatus for performing state retention for at least one functional block within an ic device

A method of performing state retention, for example during power gating, for at least one functional block within an integrated circuit device. The method comprises enabling at least one scan chain within the at least one functional block, scanning out a set of scan chain values from the at least one scan chain, a subset of the set of scan chain values comprising validation values, and writing the set of scan chain values to at least one memory element. ... Freescale Semiconductor Inc

10/01/15 / #20150276854

Integrated circuit interconnect crack monitor circuit

A circuit device mounted on a substrate includes a detection circuit that monitors a characteristic of a return signal to determine an integrity of various interconnects of the device.. . ... Freescale Semiconductor Inc

10/01/15 / #20150276847

Method and system for testing a semiconductor device against electrostatic discharge

A method of testing a semiconductor device against electrostatic discharge includes operating the semiconductor device, and, while operating the semiconductor device, monitoring a functional performance of the semiconductor device. The monitoring includes monitoring one or more signal waveforms of respective one or more signals on respective one or more pins of the semiconductor device to obtain one or more monitor waveforms, and monitoring one or more register values of one or more registers of the semiconductor device to obtain one or more monitor register values as function of time. ... Freescale Semiconductor Inc

10/01/15 / #20150276815

High bandwidth current sensor and method therefor

A current sensor comprises a current carrying trace located within a substrate; and a sensing trace located within the substrate proximate to the current carrying trace; wherein the sensing trace detects an electromagnetic force (emf) generated by magnetic flux inductively coupled from the current carrying trace for transmitting to a current sensing device.. . ... Freescale Semiconductor Inc

09/24/15 / #20150270997

Device for receiving interleaved communication signals

A signal decoder in a communication system is for decoding signal elements in a communication signal having interleaved carrier frequencies. The decoder receives antenna signals in a frequency domain, and has a multiplier for multiplying the antenna signals by a complex-valued mathematical sequence such as the zadoff-chu sequence, to generate multiplied antenna signals. ... Freescale Semiconductor Inc

09/24/15 / #20150270869

Frequency hopping radio system

An electronic device is provided for determining a hopset for a frequency hopping radio communication system. The hopset is a number of radio channels in a range of channels available for radio communication, and other channels in the range constituting a channel pool of pool channels. ... Freescale Semiconductor Inc

09/24/15 / #20150270703

Methods and circuits for reverse battery protection

A circuit is configured for providing reverse battery protection. The circuit includes a load driver circuit having at least a first half-bridge circuit with topside and bottomside transistors coupled at a midpoint node by a first current terminal of both the topside and bottomside transistors. ... Freescale Semiconductor Inc

09/24/15 / #20150270333

Semiconductor device with peripheral breakdown protection

A device includes a semiconductor substrate, source and drain regions disposed in the semiconductor substrate and having a first conductivity type, a body region disposed in the semiconductor substrate, having a second conductivity type, and in which the source region is disposed, a drift region disposed in the semiconductor substrate, having the first conductivity type, and through which charge carriers drift during operation upon application of a bias voltage between the source and drain regions, a device isolation region disposed in the semiconductor substrate and laterally surrounding the body region and the drift region, and a breakdown protection region disposed between the device isolation region and the body region and having the first conductivity type.. . ... Freescale Semiconductor Inc

09/24/15 / #20150270259

Integrated circuit, integrated circuit package and method of providing protection against an electrostatic discharge event

An integrated circuit comprising a power supply node, a ground node and a gated domain coupled between the power node and the ground node. A charged device model electrostatic discharge protection module is provided for shunting electrical energy of a cdm esd event away from the gated domain. ... Freescale Semiconductor Inc

09/24/15 / #20150270206

Pressure sensor device with through silicon via

A semiconductor pressure sensor device having a pressure-sensing die electrically connected to a microcontrol unit (mcu) using either through silicon vias (tsvs) or flip-chip bumps. An active surface of the pressure-sensing die is in facing relationship with the mcu. ... Freescale Semiconductor Inc

09/24/15 / #20150270195

Lead frame with mold lock structure

A lead frame for a semiconductor device includes a die paddle and leads situated on a perimeter of the lead frame. The die paddle has a metal frame and a number of substantially linear metal connecting bars within the frame. ... Freescale Semiconductor Inc

09/24/15 / #20150269829

Method and apparatus for maintaining alertness of an operator of a manually-operated system

An apparatus for maintaining alertness of an driver of a motor vehicle periodically generates an audible alert signal to which the driver responds by pressing a button on the vehicle's steering wheel. The response time of the driver to the signal is monitored and if an increase is detected, the repetition rate of the alert signal is increased. ... Freescale Semiconductor Inc

09/24/15 / #20150269049

Verification system and method for automated verification of register information for an electronic system

A system for verifying register information includes a design database containing a description of the electronic system, a register description database containing register information relating to the electronic system, a customization information module for storing a customization information extracted from the design database and a simulator which is arranged to execute verification stimuli in accordance with at least one check function and to generate a verification result. Verification stimuli are generated by combining register information with customization information. ... Freescale Semiconductor Inc

09/24/15 / #20150268985

Low latency data delivery

The present invention relates to apparatus and methods for low latency data delivery within multi-core processing systems. The apparatus and method comprises assigning a task to a processing core; identifying a job within the task to be performed via an accelerator; performing and completing the job via the accelerator; generating output data including associated status information via the accelerator, the status information including an associated inactive write strobe; snooping the status information to determine when the job being performed by the accelerator is completed, the snooping comprising snooping the status information; and continuing executing the task using the output data associated with the status information.. ... Freescale Semiconductor Inc

09/24/15 / #20150268269

Sensor with combined sense elements for multiple axis sensing

A mems sensor includes a movable element spaced apart from a surface of a substrate and fixed sense elements attached to the substrate, where all of the fixed sense elements are oriented parallel to one another. The movable element includes movable sense elements adjacent to the fixed sense elements. ... Freescale Semiconductor Inc

09/24/15 / #20150268268

Inertial sensor with trim capacitance and method of trimming offset

An inertial sensor (20) includes a movable element (24) coupled to a substrate (28) and adapted for motion about a rotational axis (34). The sensor (20) further includes a trim elements (36, 38). ... Freescale Semiconductor Inc

09/24/15 / #20150266484

Method and apparatus for generating an indicator of a risk level in operating systems

A method and apparatus for generating an indicator of a risk level in motor vehicle and notifying vehicle systems when a risk level is above a specific threshold includes, receiving a plurality of driver distraction indicators, assigning a weighting value to each indicator, applying a scaling factor to the weighting value assigned to those indicators which are identified as being related, and summing the weighting values to produce an output value indicating a risk level. Distraction indicators can include on-board system and sensor outputs and stored data relating to driver attributes. ... Freescale Semiconductor Inc

09/17/15 / #20150263709

Electronic device and method for generating clock signals with and without frequency jitter for one source clock signal generated by a single narrow-band source clock signal

. . The present application suggests an electronic device and method for generating clock signals with and without frequency jitter for one source clock signal generated by a single narrow-band source clock signal. The device comprises a random number generator to generate a random number signal varying in time which represents a divisor fraction signal; a signal mixer to mix the timely varying random number signal and a clock divisor signal and to output a mixed divisor signal; and a fractional clock divider to generate an output clock signal from a source clock signal, wherein the output clock signal has a frequency fout(t), which is substantially equal to the frequency fsource of the source clock signal being a narrow-band clock signal divided by a divisor d(t) represented by the mixed divisor signal.. ... Freescale Semiconductor Inc

09/17/15 / #20150263681

Multi-path devices with mutual inductance compensation networks and methods thereof

The embodiments described herein provide compensation for mutual inductance in a multi-path device. In one embodiment, a device includes a multi-path integrated device. ... Freescale Semiconductor Inc

09/17/15 / #20150263677

System and method for adaptive linearization of rf amplifiers

A variable-bias power amplifier is provided, comprising: a first variable voltage source generating first bias voltages based on bias control signals; a first amplifier circuit amplifying an output rf signal to generate a first amplified signal based on the first bias voltages; a second variable voltage source generating second bias voltages based on the bias control signals; a second amplifier circuit amplifying the output rf signal to generate a second amplified signal based on the second bias voltages; and a dc isolation circuit between the first amplifier circuit and the second amplifier circuit, electrically isolating dc currents at the first amplifier from dc currents at the second amplifier, wherein the first variable voltage source can be controlled independently from the second variable voltage source, and the first amplifier circuit, the second amplifier circuit, and the dc isolation circuit are all formed on a single die.. . ... Freescale Semiconductor Inc

09/17/15 / #20150263504

Protection circuit, circuit employing same, and associated method of operation

A buffer or voltage protection circuit, a circuit including same, and an associated method of operation are disclosed. In one example embodiment, the integrated circuit includes a first input terminal, a first circuit portion having a second input terminal, and a second circuit portion. ... Freescale Semiconductor Inc

09/17/15 / #20150262961

Wedge bond foot jumper connections

A semiconductor device includes a substrate, first and second bond pad structures supported by the substrate and spaced from one another by a gap, and a wire bond foot jumper extending across the gap and bonded to the first and second bond pad structures.. . ... Freescale Semiconductor Inc

09/17/15 / #20150260785

Method for testing integrated circuit and integrated circuit configured to facilitate performing such a method

An integrated circuit, such as for example an application specific integrated circuit, as well as a method of testing such a circuit, are disclosed herein. In one example embodiment, the integrated circuit includes a plurality of pins including a power pin, a ground pin, and a first communication pin, a test mode circuit, and a communication circuit. ... Freescale Semiconductor Inc

09/17/15 / #20150260766

Semiconductor device

A semiconductor device, comprising a substrate and an electronic circuit formed thereon is described. The substrate is susceptible to conducting a substrate current. ... Freescale Semiconductor Inc

09/17/15 / #20150260548

Variable reluctance sensor interface with integration based arming threshold

An interface for processing a variable reluctance sensor signal provided by a variable reluctance sensor including an integrator, an arming comparator and a detect circuit. The integrator includes an input for receiving the variable reluctance sensor signal and an output providing an integrated signal indicative of total flux change of the variable reluctance sensor. ... Freescale Semiconductor Inc

09/10/15 / #20150256165

Methods and apparatus for generating a modulated waveform

A system and method are present for generating a modulated waveform. A timer is configured to generate a first modulated waveform signal, and an adder module is configured to calculate a delay. ... Freescale Semiconductor Inc

09/10/15 / #20150256135

Rail-to-rail follower circuits

Rail-to-rail follower circuits. In some embodiments, a source follower circuit may include a first level shifter configured to receive an input voltage; an n-type metal-oxide-semiconductor (nmos) transistor having a gate terminal coupled to an output of the first level shifter; a second level shifter configured to receive the input voltage; a p-type metal-oxide-semiconductor (pmos) transistor having a gate terminal coupled to an output of the second level shifter and a source terminal coupled to a source terminal of the nmos transistor; and an amplifier configured to receive the input voltage and to output a current at a node between the source terminal of the nmos transistor and the source terminal of the pmos transistor, wherein the current is determined based upon a difference between the input voltage and a reference voltage.. ... Freescale Semiconductor Inc

09/10/15 / #20150255537

Deep trench isolation structure layout and method thereof

The embodiments described herein provide a semiconductor device layout and method that can be utilized in a wide variety of semiconductor devices. In one embodiment a semiconductor device is provided that includes a plurality of deep trench isolation structures that define and surround a first plurality of first trench-isolated regions in the substrate, and further define a second plurality of second trench-isolated regions in the substrate. ... Freescale Semiconductor Inc

09/10/15 / #20150255371

Semiconductor package with thermal via and method for fabrication thereof

A semiconductor package includes a semiconductor die having an active face and dielectric layers disposed on the active face of the semiconductor die. At least one opening is formed through the dielectric layers and extends from a non-bond pad area of the active face to an exterior surface of the dielectric layers. ... Freescale Semiconductor Inc

09/10/15 / #20150254017

Trusted execution and access protection for embedded memory

A semiconductor device includes, in various embodiments, a memory and a processor, with the processor configured to perform a permission check prior to execution of a memory-access instruction. The permission check comprises evaluating a permission attribute of the memory-access instruction and a permission attribute of a memory location to be accessed. ... Freescale Semiconductor Inc

09/10/15 / #20150253511

Method and apparatus for beam control with optical mems beam waveguide

A high density, low power, high performance information system, method and apparatus are described in which perpendicularly oriented processor and memory die stacks (130, 140, 150, 160, 170) include integrated deflectable mems optical beam waveguides (e.g., 190) at each die edge (e.g., 151) to provide optical communications (184) in and between die stacks by using a beam control method and circuit to maintain and adjust alignment over time by calibrating and updating x and y counter values stored in deflection registers (541-542) to control dac circuitry (546, 548) which generates and supplies deflection voltages to charging capacitors (551, 552) connected to deflection electrodes (195-197) positioned on and around each mems optical beam waveguide (193-194) to provide two-dimensional alignment and controlled feedback to adjust beam alignment and establish optical communication links between die stacks.. . ... Freescale Semiconductor Inc

09/03/15 / #20150249560

System and method for fsk demodulation

. . A system and method for frequency-selective demodulation is presented. An input signal is received that is modulated by frequency shift keying (fsk) and encodes data at a first and second frequency. ... Freescale Semiconductor Inc

09/03/15 / #20150249048

Stress migration mitigation utilizing induced stress effects in metal trace of integrated circuit device

An integrated circuit (ic) device includes a plurality of metal layers having metal traces, and a plurality of vias interconnecting the metal traces. The presence of vacancies within the metal layers may disrupt the functionality of the ic device if the vacancies migrate to the vias interconnecting the metal layers. ... Freescale Semiconductor Inc

09/03/15 / #20150249021

Packaged leadless semiconductor device

A method for a packaged leadless semiconductor device including a heat sink flange to which semiconductor dies are coupled using a high temperature die attach process. The semiconductor device further includes a frame structure pre-formed with bent terminal pads. ... Freescale Semiconductor Inc

09/03/15 / #20150248924

Method and apparatus for maintaining an accurate i/o calibration cell

An integrated circuit includes an input/output “i/o” cell arranged to drive an output signal and an activity analysis unit arranged to generate an activity factor based on the output signal. The activity factor represents a switching activity intensity of the i/o cell. ... Freescale Semiconductor Inc

09/03/15 / #20150248355

Memory management unit for a microprocessor system, microprocessor system and method for managing memory

A first storage location at a memory management unit stores physical address information mapping logical physical addresses to actual physical addresses. A second storage location stores an allowed address range of actual physical addresses. ... Freescale Semiconductor Inc

09/03/15 / #20150248343

Method and apparatus for implementing instrumentation code

A method and apparatus for implementing instrumentation code within application program code is provided. The method includes, within a software development tool, defining at least one instrumentation point within the application program code, associating at least one instrumentation code object with the at least one defined instrumentation point, the at least one instrumentation code object comprising instrumentation code, and causing the instrumentation code of the at least one instrumentation code object associated with the at least one instrumentation point to be incorporated into the application program code prior to compilation of the application program code.. ... Freescale Semiconductor Inc

09/03/15 / #20150247899

Scan test system

A method generates scan patterns for testing an electronic device called dut having a scan path. A scan tester is arranged for executing a scan shift mode and a capture mode. ... Freescale Semiconductor Inc

08/27/15 / #20150245116

Audio unit and method for generating a safety critical audio signal

. . An audio unit, connected or connectable to a safety-critical apparatus, or integrated or integrable in the apparatus, is proposed. The audio unit may comprise a driver unit, a detection unit, and an alert unit. ... Freescale Semiconductor Inc

08/27/15 / #20150244639

Method and apparatus for deriving a packet select probability value

A method and apparatus for deriving a packet select probability value for a data packet. The method comprises determining a queue length value for a target buffer of the data packet, calculating a queue congestion value based at least partly on the queue length value and a packet select queue length range, and calculating the packet select probability value for the data packet based at least partly on an exponential function e−x, where x is computed based at least partly on the queue congestion value.. ... Freescale Semiconductor Inc

08/27/15 / #20150244393

Multiple bit sigma-delta modulator with a common mode compensated quantizer

A quantizer for an analog to digital converter has an input for receiving an analog input signal. A detector senses a common mode voltage component of the input signal. ... Freescale Semiconductor Inc

08/27/15 / #20150243781

Resurf semiconductor device charge balancing

Breakdown voltage bvdss is enhanced and on-resistance reduced in resurf devices, e.g., ldmos transistors, by careful charge balancing, even when body and drift region charge balance is not ideal, by: (i) providing a plug or sinker near the drain and of the same conductivity type extending through the drift region at least into the underlying body region, and/or (ii) applying bias viso to a surrounding lateral doped isolation wall coupled to the device buried layer, and/or (iii) providing a variable resistance bridge between the isolation wall and the drift region. The bridge may be a fet whose source-drain couple the isolation wall and drift region and whose gate receives control voltage vc, or a resistor whose cross-section (x, y, z) affects its resistance and pinch-off, to set the percentage of drain voltage coupled to the buried layer via the isolation wall.. ... Freescale Semiconductor Inc

08/27/15 / #20150243606

Integrated circuit for generating or processing a radio frequency signal

An integrated circuit includes a signal line for carrying a radio frequency signal; a coupling line inductively coupled to the signal line for delivering an induced signal in dependence on the radio frequency signal; a connecting line connected to a pick-off point of the coupling line for picking off the induced signal from the coupling line; and a conductive part for shielding the coupling line against electromagnetic interference and for enhancing inductive coupling between the signal line and the coupling line. The conductive part may have a uniform flat surface facing the coupling line. ... Freescale Semiconductor Inc

08/27/15 / #20150243588

Multiple die lead frame

An electronic apparatus includes a packaging enclosure, first and second die pads disposed within the packaging enclosure, first and second semiconductor die disposed on the first and second die pads, respectively, a plurality of packaging leads, each packaging lead projecting outward from the packaging enclosure, a plurality of packaging posts disposed within the packaging enclosure and extending inward from opposite sides of the packaging enclosure between the first and second die pads, each packaging post being connected with a respective one of the plurality of packaging leads, and a plurality of wire bonds disposed within the packaging enclosure. Each packaging post of the plurality of packaging posts is connected via a first wire bond of the plurality of wire bonds to the first semiconductor die and via a second wire bond of the plurality of wire bonds to the second semiconductor die. ... Freescale Semiconductor Inc

08/27/15 / #20150243365

Antifuse with bypass diode and method thereof

The embodiments described herein provide antifuse devices and methods that can be utilized in a wide variety of semiconductor devices. In one embodiment a semiconductor device is provided that includes an antifuse, a first diode coupled with the antifuse in a parallel combination, and a second diode coupled in series with the parallel combination. ... Freescale Semiconductor Inc

08/27/15 / #20150242561

Efficient extraction for colorless multi patterning

A method for parasitic capacitance extraction for integrated circuit (ic) designs fabricated involving multiple patterning that includes identifying, at a computing system, metal features in a metal layer of an ic design and generating, at the computing system, a graph based on spacing relationships between the metal features. The method further includes predicting, at the computing system, which metal features are to be formed by the same mask in the multiple patterning lithography process from the graph. ... Freescale Semiconductor Inc

08/27/15 / #20150242544

Method of simulating a semiconductor integrated circuit, computer program product, and device for simulating a semiconductor integrated circuit

A there is proposed a method and device for simulating a semiconductor ic is provided, which comprises generating a high level description of the ic, generating a low level description of the ic comprising a plurality of instances describing the operation of the ic, conducting a low level function analysis of the ic based on metrics values associated with the instances, and performing a design optimization scheme. The scheme comprises mapping the metric values of instances describing functional units different from standard cells, to standard cells logically connected to said instances, by dividing each of the instance metrics values between a group of standard cells logically connected to the corresponding instance and adding each resulting portion of said instance metric value to the metric value of each of the group of standard cells, respectively.. ... Freescale Semiconductor Inc

08/27/15 / #20150242301

Method and system for obtaining run-time information associated with executing an executable

A method of obtaining run-time information associated with executing an executable is described. The method comprises receiving an external database comprising one or more external debugging information entries, retrieving the one or more external debugging information entries from the external database and storing the one or more external debugging information entries retrieved from the external database in a debugging information entries collection. ... Freescale Semiconductor Inc

08/27/15 / #20150242269

Memory redundancy to replace addresses with multiple errors

A method and apparatus are provided for error correction of a memory by using a first memory (18), second memory (14), and redundant memory (19) to perform error correction code (ecc) processing on data retrieved from the first memory (18) by using the redundant memory (19) to replace entries in the second memory (14) having repeat addresses, thereby freeing entries in the second memory (14) for use in detecting and managing errors identified by the ecc processing.. . ... Freescale Semiconductor Inc

08/27/15 / #20150241901

Power supply control device

An electronic device is for controlling multiple switching power circuits in a power supply system. Each switching power circuit has a power clock for controlling switching of a supply side switch that enables charging. ... Freescale Semiconductor Inc

08/20/15 / #20150237674

Method of discontinuous transmission detection

A network node of a wireless communication network comprises a receiver receiving an input signal from a remote transmitter of the wireless communication system via a transmission channel. A signal to noise ratio calculator is arranged to calculate a signal to noise ratio of the received input signal. ... Freescale Semiconductor Inc

08/20/15 / #20150237673

Method of dtx detection in a wireless communication system

There is provided a network node of a wireless communication network, such as a umts network. The network node is arranged to perform a method of detecting signal discontinuous transmission on a channel in the wireless communication network. ... Freescale Semiconductor Inc

08/20/15 / #20150237174

Multi-frame and frame streaming in a controller area network (can) with flexible data- rate (fd)

Systems and methods for multi-frame and frame streaming in a controller area network (can) with flexible data-rate (fd). In some embodiments, a method may include creating, by a device coupled to a can network configured to support a can flexible data-rate (fd) protocol, a data frame comprising a field that indicates a multi-frame or streaming transmission, and transmitting the data frame in the multi-frame or streaming transmission. ... Freescale Semiconductor Inc

08/20/15 / #20150236035

Methods for forming contact landing regions in split-gate non-volatile memory (nvm) cell arrays

Methods and related structures are disclosed for forming contact landing regions in split-gate nvm (non-volatile memory) systems. A dummy select gate structure is formed while also forming select gates for split-gate nvm cells. ... Freescale Semiconductor Inc

08/20/15 / #20150236009

Low voltage npn with low trigger voltage and high snap back voltage for esd protection

An area-efficient, low voltage esd protection device (200) is provided for protecting low voltage pins (229, 230) against esd events by using one or more stacked low voltage npn bipolar junction transistors, each formed in a p-type material with an n+ collector region (216) and p+ base region (218) formed on opposite sides of an n+ emitter region (217) with separate halo extension regions (220-222) formed around at least the collector and emitter regions to improve the second trigger or breakdown current (it2) and set the snapback voltage (vsb) and triggering voltage (vt1) at the desired level.. . ... Freescale Semiconductor Inc

08/20/15 / #20150235998

Integrated circuit device

Aspects of the invention relate to an integrated circuit device and method of production thereof. The integrated circuit device comprises at least one application semiconductor die comprising at least one functional component arranged to provide application functionality, at least one functional safety semiconductor die comprising at least one component arranged to provide at least one functional safety undertaking for the at least one application semiconductor die, and at least one system in package, sip, connection component operably coupling the at least one functional safety semiconductor die to the at least one application semiconductor die to enable the at least one functional safety semiconductor die to provide the at least one functional safety undertaking for the at least one application semiconductor die.. ... Freescale Semiconductor Inc

08/20/15 / #20150235933

Semiconductor devices, semiconductor device packages, and packaging techniques for impedance matching and/or low frequency terminations

A semiconductor device, related package, and method of manufacturing same are disclosed. In at least one embodiment, the semiconductor device includes a radio frequency (rf) power amplifier transistor having a first port, a second port, and a third port. ... Freescale Semiconductor Inc

08/20/15 / #20150234679

Method to communicate task context information and device therefor

Task context information is transferred concurrently from a processor core to an accelerator and to a context memory. The accelerator performs an operation based on the task context information and the context memory saves the task context information. ... Freescale Semiconductor Inc

08/20/15 / #20150234582

Debug configuration tool with layered graphical user interface

A debug configuration tool for configuration of on-chip debug features comprises a database comprising predefined analysis points, each relating to a configurable chip entity, and comprising a configurable condition and a configurable action for the chip entity, a plurality of predefined analysis groups, each relating to a group of configurable chip entities, and comprising a configurable condition and a configurable action for the group of chip entities. The tool comprises a graphical user interface module arranged to display representations of at least some of the analysis points and the analysis groups on different levels of detail, and to receive input from a user to set the configurable conditions and/or actions for the displayed analysis points and the analysis groups. ... Freescale Semiconductor Inc

08/20/15 / #20150234419

Methods and apparatus for adaptive time keeping for multiple timers

A timer distribution module supports multiple timers and comprises: a command decoder arranged to determine expiration times of a plurality of timers; and a timer link list distribution adapter, llda, operably coupled to the command decoder. The llda is arranged to: receive a time reference from a master clock; receive timer data from the command decoder wherein the timer data comprises at least one timer expiration link list; construct a plurality of timer link lists based on at least one of: the timer expiration link list, at least one configurable timing barrier; dynamically split the link list timer data into a plurality of granularities based on the timer expiration link list; and output the dynamically split link list timer data.. ... Freescale Semiconductor Inc

08/20/15 / #20150234415

Method and apparatus for providing electrical isolation

An isolation circuit arranged to provide electrical isolation between at least one control module and at least one driver module. The isolation circuit comprises at least one boost circuit arranged to receive at least one control signal from the at least one control module, and boost the at least one control signal from a first voltage level signal to an increased voltage level signal. ... Freescale Semiconductor Inc

08/20/15 / #20150233995

System and method for evaluating a capacitive interface

A method of evaluating a capacitive interface including discharging the capacitive interface to a lower voltage, timing while applying a unit charge to the capacitive interface until a voltage of the capacitive interface rises to a reference voltage and determining a corresponding charge time value, charging the capacitive interface to an upper voltage that is greater than the reference voltage, and timing while removing the unit charge from the capacitive interface until a voltage of the capacitive interface falls to the reference voltage and determining a corresponding discharge time value. The charge and discharge time values may be used to evaluate the capacitive interface by determining capacitance and leakage current. ... Freescale Semiconductor Inc

08/20/15 / #20150232332

Method for shielding mems structures during front side wafer dicing

A method includes applying a compressive force against mems structures at a front side of a mems wafer using a protective material covering at least a portion of the front side of the mems wafer. The method further includes concurrently dicing through the protective material and the mems wafer from the front side to produce a plurality of mems dies, each of which includes at least one of the mems structures. ... Freescale Semiconductor Inc

08/13/15 / #20150229213

Switching module

A switching module comprising at least one power switching device arranged to output from an output node thereof a load current for the switching module, and at least one current sense component arranged to generate at least one sense current representative of the load current. The at least one current sense component comprises at least one temperature coefficient compensation resistance within the path of the at least one sense current and arranged to cause the at least one sense current to be at least partly compensated for a temperature coefficient caused by at least one parasitic routing resistance of a load current path for the at least one power switching device.. ... Freescale Semiconductor Inc

08/13/15 / #20150228713

High voltage diode

A trench-isolated resurf diode structure (100) is provided which includes a substrate (150) in which is formed anode (130, 132) and cathode (131) contact regions separated from one another by a shallow trench isolation region (114, 115), along with a non-uniform cathode region (104) and peripheral anode regions (106, 107) which define vertical and horizontal p-n junctions under the anode contact regions (130, 132), including a horizontal cathode/anode junction that is shielded by the heavily doped anode contact region (132).. . ... Freescale Semiconductor Inc

08/13/15 / #20150228560

Semiconductor device package and method of manufacture

A structure to improve saw singulation quality and wettability of integrated circuit packages (140) is assembled with lead frames (112) having half-etched recesses (134) in leads. In one embodiment, the structure is a lead frame strip (110) having a plurality of lead frames. ... Freescale Semiconductor Inc

08/13/15 / #20150228545

Methods of making a monolithic microwave integrated circuit

Low q associated with passive components of monolithic integrated circuits (ics) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., ≧100 ohm-cm) semiconductor substrates and lower resistance inductors for the ic. This eliminates significant in-substrate electromagnetic coupling losses from planar inductors and interconnections overlying the substrate. ... Freescale Semiconductor Inc

08/13/15 / #20150227665

Method of optimizing the design of an electronic device with respect to electromagnetic emissions based on frequency spreading introduced by hardware, computer program product for carrying out the method and associated article of manufacture

There is described a method of optimizing the design of an electronic device with respect to electromagnetic emissions based on frequency spreading. With the method, a designer can add frequency spreading with specific parameters by hardware. ... Freescale Semiconductor Inc

08/13/15 / #20150227664

Method of optimizing the design of an electronic device with respect to electromagnetic emissions based on frequency spreading introduced by software, computer program product for carrying out the method and associated article of manufacture

There is described a method of optimizing the design of an electronic device with respect to electromagnetic emissions based on frequency spreading. With the method, a designer can, for example, perform a transient simulation on the device only once, and then add frequency spreading with specific parameters by simulation. ... Freescale Semiconductor Inc

08/13/15 / #20150227663

Method of optimizing the design of an electronic device with respect to electromagnetic emissions based on frequency spreading introduced by data post-processing, computer program product for carrying out the method and associated article of manufacture

There is described a method of optimizing the design of an electronic device with respect to electromagnetic emissions based on frequency spreading. With the method, a designer can, for example, perform a transient simulation on the device only once, and then process the obtained signal data to add frequency spreading with specific parameters by post-processing. ... Freescale Semiconductor Inc

08/13/15 / #20150227413

Electronic device and method for protecting an electronic device against unauthorized use

An electronic device comprising a clock unit and a processing unit connected to the clock unit is described. The clock unit may deliver an output clock signal for operating the processing unit in accordance with the output clock signal. ... Freescale Semiconductor Inc

08/06/15 / #20150222297

Viterbi decoding device and method for decoding a signal produced by a convolutional encoder

. . . . A convolutional encoder may have n different states, each having two predecessor states, each branch from each of the two predecessor states having a static code word cw=(b0, b1) and produces a signal having a sequence of the code words. A viterbi decoding device includes an analog-to-digital conversion unit arranged to extract a soft symbol s=(s1, s2) from the signal; and a digital processing unit connected to the analog-to-digital conversion unit and arranged to compute, for each of the n states, a branch metric value bm_0_k in dependence on the soft symbol s, k being an index identifying the respective state. ... Freescale Semiconductor Inc

08/06/15 / #20150221633

Semiconductor device comprising an esd protection device, an esd protection circuitry, an integrated circuit and a method of manufacturing a semiconductor device

A semiconductor device includes an esd protection device. In a n-well, two p+ doped regions form a collector and emitter of a parasitic transistor of the esd protection device. ... Freescale Semiconductor Inc

08/06/15 / #20150221629

Semiconductor device and an integrated circuit comprising an esd protection device, esd protection devices and a method of manufacturing the semiconductor device

A semiconductor device is provided which comprises an esd protection device. The structure of the semiconductor device comprises a p-doped isolated region in which a structure is manufactured which operates as a silicon controlled rectifier which is coupled between an i/o pad and a reference voltage or ground voltage. ... Freescale Semiconductor Inc

08/06/15 / #20150220393

Method and apparatus for storing trace data

A method and apparatus for storing trace data within a processing system. The method comprises configuring at least one error correction code, ecc, component within the processing system to operate in a trace data storage operating mode, generating trace data at a debug module of the processing system, and conveying the trace data from the debug module to the at least one ecc component for storing in an area of memory used for ecc information.. ... Freescale Semiconductor Inc

08/06/15 / #20150219753

Circuitry for and method of generating a frequency modulated radar transmitter signal, a radar transceiver circuit and a radar system

A circuitry for and a method of generating a frequency modulated radar transmitter signal are provided. The circuitry comprises a modulation signal generator for generating a modulation signal having a waveform describing a required frequency modulation of the frequency modulated radar transmitter signal and comprises a pll circuitry for generating the frequency modulated radar transmitter signal in dependence of the modulation signal. ... Freescale Semiconductor Inc

08/06/15 / #20150219717

A circuit arrangement for logic built-in self-test of a semiconductor device and a method of operating such circuit arrangement

A circuit arrangement for logic built-in self-test (lbist) includes a clock source configured to generate a system clock, a first clock division circuitry configured to derive a first punched-out clock and a plurality of scan chains operable at the first punched-out clock. Each scan chain has an associated output circuitry responsive to a leading edge of the first punched-out clock. ... Freescale Semiconductor Inc

08/06/15 / #20150217998

Shielding mems structures during wafer dicing

A mems wafer (46) includes a front side (52) having a plurality of mems structure sites (60) at which mems structures (50) are located. A method (40) for protecting the mems structures (50) includes applying (44) a non-active feature (66) on the front side of the mems wafer in a region that is devoid of the mems structures and mounting (76) the front side of the mems wafer in a dicing frame (86) such that a back side (74) of the mems wafer is exposed. ... Freescale Semiconductor Inc

07/30/15 / #20150214208

Microelectronic assembly having a heat spreader for a plurality of die

A method of manufacturing a microelectronic assembly (100) and a microelectronic device (4100) that include a stacked structure (101). The stacked structure includes a heat spreader (104), at least one die (106) thermally coupled to at least a portion of one side of the heat spreader, at least one other die (108) thermal coupled to at least a portion of an opposite side of the heat spreader, at least one opening (401) in the heat spreader located in a region of between the two die, an insulator (603) disposed in the at least one opening, and electrically conductive material (1308, 1406) in an insulated hole (705) in the insulator. ... Freescale Semiconductor Inc

07/30/15 / #20150214177

Coating layer for a conductive structure

A coating layer for use in copper integrated circuit interconnect and other conductive structures hinders and decreases oxide growth on surfaces of such conductive structures. The coating layer includes an amorphous copper containing layer deposited on a crystalline copper substrate, such as utilized for a lead frame and a bonding wire. ... Freescale Semiconductor Inc

07/30/15 / #20150213171

Method and apparatus to facilitate simulating a circuit connected to a multiport interconnect structure

A method facilitates simulating a plurality of circuit elements connected to a multiport interconnect structure having a first set of ports. The method includes: receiving a first set of data that models electrical behavior of the first set of ports and a first portion of the plurality of circuit elements; determining a first subset of the first data, which models electrical behavior of a set of exposed ports of the first set of ports, and a second subset of the first data, which models electrical behavior of a set of non-exposed ports of the first set of ports and the first portion of the plurality of circuit elements; and combining the second subset of the first data into the first subset of the first data to generate a second set of data that models electrical behavior of a second interconnect structure having fewer ports than the multiport interconnect structure.. ... Freescale Semiconductor Inc

07/30/15 / #20150212917

Statistical power indication monitor

A statistical power indication monitor including a random pattern generator that generates random sample assertions of a sample signal, a total counter that counts a total number of the random sample assertions within a sample time interval, detect logic that provides a detection signal for each power indication signal that is asserted coincident with the sample signal, and counter logic that counts a number of assertions of each detection signal during the sample time interval. The assertion count of each power indication signal divided by the total count provides a statistical indication of power consumption of a corresponding system. ... Freescale Semiconductor Inc

07/30/15 / #20150212648

Method for performing touch detection and touch detection module therefor

A method and apparatus for performing touch detection within a touch sensing application is described. Touch sensor signal data is received, a first filtering of the received touch sensor signal data to create a first filtered data signal is performed, a second filtering of the received touch sensor signal data to create a second filtered data signal is also performed, a difference between the first and second filtered data signals to determine a delta value is calculated, and an occurrence of a touch based at least partly on the determined delta value is determined.. ... Freescale Semiconductor Inc

07/30/15 / #20150212531

Linear power regulator device and electronic device

The present invention pertains to a linear power regulator device that includes an internal pass device, a driver device having a driver output arranged to drive the internal pass device via the driver output. The linear power regulator device also includes an external connection connectable or connected to an external pass device; and the driver device is arranged to drive the external pass device via the driver output and the external connection.. ... Freescale Semiconductor Inc

07/30/15 / #20150211470

Cold-crank event management

Systems and methods for managing cold-crank events. In an embodiment, a method may include detecting a cold-crank event and setting a switching circuit to a non-conductive state, where the switching circuit is configured to couple a first regulator to a memory circuit such that setting the switching circuit to the non-conductive state de-couples the memory circuit from the first regulator. ... Freescale Semiconductor Inc

07/23/15 / #20150208510

Thin low profile strip dual in-line memory module

A low profile strip dual in-line memory module (200) includes a passive interposer support structure (90) with patterned openings (91-97) formed between opposing top and bottom surfaces, a plurality of memory chips (d1-d8) attached to the top and bottom surfaces, and vertical solder ball conductors (98) extending through the patterned openings to electrically connect the plurality of memory chips, where each memory chip has an attachment surface facing the passive interposer structure and a patterned array of horizontal conductors (e.g., 82-86) formed on the attachment surface with contact pads electrically connected to the plurality of vertical conductors to define at least one bus conductor that is electrically connected to each memory die in the first and second plurality of memory die.. . ... Freescale Semiconductor Inc

07/23/15 / #20150208022

Display control unit and method for generating a video signal

A display control unit is connected to a display and arranged to generate a video signal representing a sequence of video frames to be displayed consecutively on said display. The display control unit may include a first memory unit arranged to buffer a set of image descriptors; a second memory unit connected between said first memory unit and said display; an update unit connected to said first memory unit and arranged to update said image descriptors in said first memory unit and to generate a proceed signal only when said set of image descriptors in said first memory unit is up to date; a copy unit arranged to copy said image descriptors from said first memory unit to said second memory unit in response to said proceed signal; and a video unit arranged to generate said video signal on the basis of said image descriptors in said second memory unit.. ... Freescale Semiconductor Inc

07/23/15 / #20150207577

Receiver unit and method for correcting a value of a receive signal strength indicator

A receiver unit comprising a mixer, a test signal unit, a multiplexer unit, an amplifier unit, a signal strength unit, and a digital control unit is described. The mixer may be arranged to downconvert a received radio-frequency signal to an intermediate frequency, thereby generating a reception signal having the intermediate frequency. ... Freescale Semiconductor Inc

07/23/15 / #20150206892

Fast programming antifuse and method of manufacture

The embodiments described herein provide an antifuse that includes a substrate material and an isolation trench formed in the substrate material, where the isolation trench has a first side and a second side opposite the first side. An electrode is positioned above the substrate material and proximate to the first side of the isolation trench. ... Freescale Semiconductor Inc

07/23/15 / #20150206843

Semiconductor device having a nanotube layer and method for forming

A method of forming a semiconductor device includes forming a first conductive layer over the substrate. A dielectric layer, having a first opening, is formed over the first conductive layer. ... Freescale Semiconductor Inc

07/23/15 / #20150206598

Sample-and-hold circuit, capacitive sensing device, and method of operating a sample-and-hold circuit

A sample-and-hold circuit is provided. The sample-and-hold circuit includes an input one or more dedicated capacitive elements, one or more parasitic capacitive elements connected to said one or more dedicated capacitive elements, an output, a group of switches, and a control unit. ... Freescale Semiconductor Inc

07/23/15 / #20150205041

Copper tube interconnect

A method and apparatus are provided for fabricating an electro-optical interconnect on an integrated circuit (101, 114) in which an optical circuit element (102) is formed by forming a cylinder-shaped conductive interconnect structure (120, 122, 126, 128) with one or more conductive layers formed around a central opening (129) which is located over an optically transparent layer (118) located over the optical circuit element (102).. . ... Freescale Semiconductor Inc

07/23/15 / #20150204951

Apparatus and method for reconditioning z-axis sensor flux guides

A sensor package includes a magnetic field sensor, where the magnetic field sensor includes an in-plane sense element and a flux guide configured to direct a magnetic field oriented perpendicular to a plane of the magnetic field sensor into the plane. A current carrying structure is positioned proximate to the flux guide and circuitry is coupled to the current carrying structure. ... Freescale Semiconductor Inc

07/23/15 / #20150204917

System and method for on-die voltage difference measurement on a pass device, and integrated circuit

A system for on-die voltage difference measurement on a pass device comprises a first voltage controlled oscillator circuit having a first voltage control input connectable to a first terminal of the pass device; a second voltage controlled oscillator circuit having a second voltage control input connectable to a second terminal of the pass device; a first counter circuit arranged to count oscillation periods of a first output signal from the first voltage controlled oscillator circuit and to provide a stop signal when a predefined number of the oscillation periods of the first output signal is counted; and a second counter circuit arranged to count oscillation periods of a second output signal from the second voltage controlled oscillator circuit and to stop counting depending on the stop signal.. . ... Freescale Semiconductor Inc

07/16/15 / #20150200650

Capacitively coupled input buffer

A buffer circuit comprising a capacitor, the capacitor comprising a first terminal and a second terminal, an input signal being coupled to the first terminal; a first buffer stage coupled to the second terminal of the capacitor such that the input signal is capacitively coupled to the first buffer stage; and, a pulse generator coupled to control the first buffer stage, the pulse generator being configured to generate a control pulse corresponding to a hold time of the first buffer stage such that the buffer circuit detects a transition of the input signal during the hold time.. . ... Freescale Semiconductor Inc

07/16/15 / #20150199468

Method and apparatus for selecting data path elements for cloning

A method and apparatus for selecting data path elements for cloning within an integrated circuit (ic) design is described. The method comprises performing timing analysis of at least one data path within the ic design to determine at least one timing slack value for the at least one data path, calculating at least one annotated delay value for cloning a candidate element within the at least one data path, calculating at least one modified slack value for the at least one data path in accordance with the at least one calculated annotated delay value, and validating the cloning of the candidate element based at least partly on the at least one modified slack value.. ... Freescale Semiconductor Inc

07/16/15 / #20150199233

Memory ecc with hard and soft error detection and management

A method and apparatus are provided for error correction of a memory by using a first memory (18) and second memory (14) to perform error correction code (ecc) processing on data retrieved from the first memory and to use status control bits (35-37) in the second memory to detect and manage hard and soft errors identified by the ecc processing.. . ... Freescale Semiconductor Inc

07/16/15 / #20150198666

Switch detection device and method of use

A method of switch detection is disclosed that comprises, enabling a low power mode on a switch detection device, activating a first detection circuit for detecting, at a first expiration of a first polling time interval, a first switch state of a first switch having a first priority level, the first switch state including one of a first open state and a first closed state, comparing the detected first switch state with a prior first switch state, and activating a second detection circuit for detecting, at a second expiration of a second polling time interval, a second switch state of a second switch having a second priority level, the second switch including one of a second open state and a second closed state, and the second polling time interval being greater than the first polling time interval, and the second priority level being different from the first priority level.. . ... Freescale Semiconductor Inc

07/16/15 / #20150198628

System and method for calibrating an inertial sensor

A system (40) for calibrating an inertial sensor (20) includes a power source (42), a frequency measurement subsystem (44, 48), and a gain determination subsystem (52). A calibration process (110) using the system (40) entails applying (116) a bias voltage (66) to the inertial sensor (20), measuring (114) a drive resonant frequency (46), and measuring (118) a sense resonant frequency (50) of the inertial sensor (20) produced in response to the bias voltage (66). ... Freescale Semiconductor Inc

07/16/15 / #20150198466

Variable reluctance sensor interfaces with clearing and methods of their operation

The embodiments described herein include systems with a variable reluctance sensor (vrs) interface and methods of their operation. Embodiments of vrs interfaces include a clearing signal generator configured to generate a clearing signal corresponding with the timing of a noise event. ... Freescale Semiconductor Inc

07/09/15 / #20150195740

System and method for processing data flows

A digital signal processor (300), compatible with the common public radio interface (cpri), permits reading and writing of iq data of antenna carriers which have two different sampling rates by using just two single sample rate dma (direct memory access) modules (306,313). The digital signal processor (300) is capable of processing data of different sampling rates on just one cpri lane comprising one framer (302). ... Freescale Semiconductor Inc

07/09/15 / #20150195107

Channel estimation in wireless communication

A channel estimation processor for a receiver in a wireless communication system is described. The channel estimation processor includes a stage-1 processor (stg1) arranged to pluralities of nsym reference symbol correlation values per slot. ... Freescale Semiconductor Inc

07/09/15 / #20150194949

Temperature-compensated high accuracy clock

A tunable clock circuit has a dual overlapping digital to analog converter (dac) and an oscillator. The dual overlapping dac provides a first output selectable with a first resolution and a second output selectable with a second resolution. ... Freescale Semiconductor Inc

07/09/15 / #20150194887

Power gating techniques with smooth transition

In an embodiment, an electronic device includes an integrated circuit (ic) having a plurality of power domains, a first regulator coupled to a given power domain, a second regulator coupled to the given power domain, and a switching circuit coupled between the first and second regulators and configured to control an amount of current drawn by the power domain from the first and/or second regulators. In another embodiment, a method includes controlling an impedance of a switching circuit to change an amount of current, the switching circuit coupled to a given power domain of an ic configured to operate in a first mode followed by a second mode, where the switching circuit is coupled to a first regulator configured to provide more power to the ic than a second regulator, and a transition period includes turning off the first regulator and turning on the second regulator.. ... Freescale Semiconductor Inc

07/09/15 / #20150194439

Embedded nvm in a hkmg process

A process integration is disclosed for fabricating complete, planar non-volatile memory (nvm) cells (110) prior to the formation of high-k metal gate electrodes for cmos transistors (212, 213) using a planarized dielectric layer (26) and protective mask (28) to enable use of a gate-last hkmg cmos process flow without interfering with the operation or reliability of the nvm cells.. . ... Freescale Semiconductor Inc

07/02/15 / #20150188426

Power switching device, three phase bridge inverter, and method of operating a power switching device

A power switching device connected or connectable between a power supply and a load is described. The device may have at least two different operating states, each operating state having a different level of said output voltage associated with it. ... Freescale Semiconductor Inc

07/02/15 / #20150188328

Charging circuit, an inductive load control circuit, an internal combustion engine, a vehicle and a method of charging a bootstrap storage element

A charging circuit for a bootstrap capacitor comprises a p mosfet having a body diode and an n channel power mosfet also having a body diode. The drain of the p mosfet is coupled to the source of the n channel power mosfet, and the source of the p mosfet receives current from a vehicle's battery. ... Freescale Semiconductor Inc

07/02/15 / #20150187690

Ic package with metal interconnect structure implemented between metal layers of die and interposer

An integrated circuit package includes a die having a first substrate implementing an integrated circuit comprising circuit elements. The die includes a first plurality of metal layers implementing a first portion of a metal interconnect structure for the integrated circuit. ... Freescale Semiconductor Inc

07/02/15 / #20150186213

Data processing system having end-to-end error correction and method therefor

In a data processing system having a plurality of error coding function circuitries, a method includes receiving an address which indicates a first storage location for storing a first data value; using a first portion of the address to select one of the plurality of error coding function circuitries as a selected error coding function circuitry; and using the selected error coding function circuitry to generate a first checkbit value, wherein the selected error coding function circuitry uses the first data value to generate the first checkbit value. When the first portion of the address has a first value, a first one of the plurality of error coding function circuitries is selected as the selected error coding function circuitry. ... Freescale Semiconductor Inc

07/02/15 / #20150186049

System and method for low cost patching of high voltage operation memory space

A low semiconductor area impact mechanism for patching operations stored in a boot memory area is provided, thereby providing flexibility to such code. In this manner, current flash memory manager scram, which is used for memory operations when the flash memory is unavailable (e.g., high voltage operations) can be replaced with a significantly smaller register area (e.g., a flip flop array) that provides a small patch space, variable storage, and stack. ... Freescale Semiconductor Inc

07/02/15 / #20150185909

Method of sensing a user input to a capacitive touch sensor, a capacitive touch sensor controller, an input device and an apparatus

A method of sensing a user input to a capacitive touch sensor having a sense electrode is described. The method comprises obtaining a measure of capacitance of the sense electrode of the capacitive touch sensor, determining an indication of contact between a finger of a user and the capacitive touch sensor from comparing the measure of capacitance to a first threshold and determining an indication of exceeding a minimum pressure exercised by the finger of the user on the capacitive touch sensor from comparing the measure of capacitance to a second threshold, the second threshold being different from the first threshold. ... Freescale Semiconductor Inc

07/02/15 / #20150185011

Micro-electro-mechanical system drive-mode oscillator module and method therefor

A drive-mode oscillator module for use within a micro-electro-mechanical system (mems) device is described. The drive-mode oscillator module is arranged to receive a proof-mass measurement signal from a proof-mass of the mems device and to output a proof-mass actuation signal to the proof-mass of the mems device. ... Freescale Semiconductor Inc

07/02/15 / #20150182995

Apparatus fabrication using localized annealing

A method for fabricating an apparatus using radiation annealing includes forming an annealable layer on a substrate. A radiation absorbing layer is also formed on the substrate, wherein the radiation absorbing layer heats up in response to radiation, and the radiation absorbing layer is formed adjacent to at least a portion of the annealable layer and non-adjacent to a portion of the apparatus. ... Freescale Semiconductor Inc

06/25/15 / #20150181211

Video information processing system with selective chroma deblock filtering

A video information processing system including a processing circuit and a deblocking filter. The processing circuit provides video information including a chroma component and a luma component. ... Freescale Semiconductor Inc

06/25/15 / #20150180475

Input/output driver circuit, integrated circuit and method therefor

An input/output (io) driver circuit is described. The io buffer driver circuit comprises: at least one input for receiving an input signal and at least one output for providing at least one output signal; and a plurality of switches arranged to provide a variable voltage level between a low voltage value and a high voltage value to the at least one output. ... Freescale Semiconductor Inc

06/25/15 / #20150180454

Delay compensation circuit

An integrated circuit includes a delay compensation circuit (221, 222) that further includes a terminal for receiving a varying signal from a circuit external to the integrated circuit; a sampler circuit that samples and holds a present value of the varying signal at each occurrence of a transition in a digital signal; an integrator, coupled to the sampler circuit, that integrates a voltage difference between a sample of the varying signal and a reference signal, and that outputs results of the integration, wherein a time constant of the integrator is greater than a period of the varying signal; a waveform generator that generates a decreasing voltage in response to a transition in a second digital signal; and a comparator that has one input terminal for receiving the decreasing voltage, an inverted input terminal for receiving the results, and an output terminal for outputting a signal that generates an output signal.. . ... Freescale Semiconductor Inc

06/25/15 / #20150180452

Low leakage cmos cell with low voltage swing

A cmos cell incorporated on an integrated circuit including a pmos transistor and an nmos transistor. The current terminals of the pmos and nmos transistors are coupled in series between a lower voltage supply rail and a reference rail. ... Freescale Semiconductor Inc

06/25/15 / #20150179821

Selective gate oxide properties adjustment using fluorine

Fluorine is located in selective portions of a gate oxide to adjust characteristics of the gate oxide. In some embodiments, the fluorine promotes oxidation which increases the thickness of the selective portion of the gate oxide. ... Freescale Semiconductor Inc

06/25/15 / #20150179566

Semiconductor devices with inner via

A semiconductor device includes a semiconductor substrate having an inactive area and a pair of active areas separated by the inactive area, a control terminal supported by the semiconductor substrate and extending across the pair of active areas and the inactive area to define a conduction path during operation between a first conduction region in each active area and a second conduction region in each active area, a conduction terminal supported by the semiconductor substrate and extending across the pair of active areas and the inactive area for electrical connection to each first conduction region, and a via extending through the semiconductor substrate, electrically connected to the conduction terminal, and positioned in the inactive area.. . ... Freescale Semiconductor Inc

06/25/15 / #20150178102

System-on-chip, method of manufacture thereof and method of controlling a system-on-chip

A system-on-chip comprises a plurality of functional domains. The plurality of functional domains comprise a first domain and a second domain, the first domain having a first active mode of operation and the second domain having a second active mode of operation different from the first active mode of operation. ... Freescale Semiconductor Inc

06/25/15 / #20150177976

Method and system for scrolling a data set across a screen

A method of scrolling a data set stored in a memory across a screen is described. The method comprises presenting a user interface widget on the screen. ... Freescale Semiconductor Inc

06/25/15 / #20150177775

Digital sample clock generator, a vibration gyroscope circuitry comprising such digital sample clock generator, an associated apparatus, an associated semiconductor device and associated methods

A digital sample clock generator for generating a sample clock signal from an input signal derived from a drive measurement voltage signal of a vibrating mems gyroscope is provided.. . ... Freescale Semiconductor Inc

06/25/15 / #20150177755

Linear voltage regulator device and electronic device

The present invention pertains to a linear power regulator device, comprising an internal pass device, a driver device having a driver output arranged to drive the internal pass device via the driver output, wherein the linear power regulator device comprises an external connection connectable or connected to an external pass device; and wherein the driver device is arranged to drive an external pass device via the driver output and the external connection. The invention also pertains to a corresponding electronic device.. ... Freescale Semiconductor Inc

06/25/15 / #20150177075

Production-test die temperature measurement method and apparatus

A die temperature measurement system (300) includes an external test environment setup (352) and an integrated circuit (302). The external test environment setup (352) includes means to force and accurately measure electrical variables. ... Freescale Semiconductor Inc

06/18/15 / #20150172220

Ethercat packet forwarding with distributed clocking

An ethercat packet forwarding system with distributed clocking is provided. The system comprises a master device and a plurality of slaves. ... Freescale Semiconductor Inc

06/18/15 / #20150171866

Level shifter circuit

A level shifting circuit that includes a level shifter and a circuit stage. The circuit stage includes a pair of diodes circuits. ... Freescale Semiconductor Inc

06/18/15 / #20150171057

Method and apparatus for multi-chip structure semiconductor package

A packaged semiconductor device may include a leadframe and a die carrier mounted to the leadframe. The die carrier is formed from an electrically and thermally conductive material. ... Freescale Semiconductor Inc

06/18/15 / #20150170986

Semiconductor package having an isolation wall to reduce electromagnetic coupling

A system and method for packaging a semiconductor device that includes a wall to reduce electromagnetic coupling is presented. A semiconductor device has a substrate on which a first circuit and a second circuit are formed proximate to each other. ... Freescale Semiconductor Inc

06/18/15 / #20150169494

Data path configuration component, signal processing device and method therefor

A data path configuration component for configuring at least one data path setting within a signal processing device is described. The data path configuration component is arranged to receive an indication of an operating mode of the signal processing device, and dynamically configure the at least one data path setting within the signal processing device based at least partially on the received indication of an operating mode of the signal processing device.. ... Freescale Semiconductor Inc

06/11/15 / #20150163496

Method and apparatus for performing compression of image data

A method of performing compression of image data for at least one image is described. The method comprises receiving image data of at least a part of the at least one image, encoding the received image data into at least one compressed data block, applying at least one bandwidth limit to the at least one compressed data block, and outputting the at least one bandwidth limited compressed data block to a buffer. ... Freescale Semiconductor Inc

06/11/15 / #20150163046

Clock for serial communication device

Versatility and flexibility of integrated circuits can be accomplished by remote control via a serial interface, such as spi. Read/write accesses to the spi slave node can be achieved according to spi protocol by the master node. ... Freescale Semiconductor Inc

06/11/15 / #20150162818

System on a chip, apparatus and method for voltage ripple reduction on a power supply line of an integrated circuit device operable in at least two modes

An apparatus for voltage ripple reduction on a power supply line of an integrated circuit device is provided to be operable in at least two modes. The apparatus includes: one or more clamping devices connectable to the power supply line; a clamp control unit; and a mode change detection unit arranged to monitor an interface of the integrated circuit device for one or more information indicating an upcoming mode change of the integrated circuit device and to provide a mode change signal to the clamp control unit when the one or more information is detected. ... Freescale Semiconductor Inc

06/11/15 / #20150161759

Diagnostic data generation apparatus, integrated circuit and method of generating diagnostic data

A diagnostic data generation apparatus for a display controller comprises an underrun detector arranged to monitor, when in use, buffer depletion in order to detect an underrun condition. The underrun condition results from a data feed lag associated with a mismatch between a buffer fill rate and a predetermined output data rate. ... Freescale Semiconductor Inc

06/11/15 / #20150160718

Memory circuit with power status sensor

Power control circuitry for a data processor supplies a memory array with a supply voltage corresponding to a memory performance level. The performance levels include a full performance level and a power-saving performance level. ... Freescale Semiconductor Inc

06/11/15 / #20150160668

Voltage reculator circuit and method therefor

A voltage regulator circuit arranged to receive a voltage supply signal, and to output a regulated voltage signal is described. The voltage regulator circuit comprises at least one switched mode power supply component selectively configurable to perform regulation of the voltage supply signal, at least one linear voltage regulator component selectively configurable to perform regulation of the voltage supply signal, and at least one controller component. ... Freescale Semiconductor Inc

06/11/15 / #20150160089

Pressure sensor with built-in calibration capability

A mems pressure sensor (70) includes a sense cell (80), a test cell (82), and a seal structure (84). The test cell includes a test cavity (104), and the seal structure (84) is in communication with the test cavity, wherein the seal structure is configured to be breached to change an initial cavity pressure (51) within the test cavity (104) to ambient pressure (26). ... Freescale Semiconductor Inc

06/04/15 / #20150156828

Systems that include microwave adaptors and methods of their operation

Systems and methods for translating an oscillating electrical signal from a first impedance to an input impedance of a load include an adaptor that further includes at least one coaxial portion and an antenna portion. The at least one coaxial portion has a first end and a second end, and is configured to translate the oscillating electrical signal to the input impedance of the load. ... Freescale Semiconductor Inc

06/04/15 / #20150156179

Security key generator

A communication system has a first and a second communicating device operable to send and receive data units through a communication channel. Some of the data are encrypted using a security key. ... Freescale Semiconductor Inc

06/04/15 / #20150156128

Scheduling module and method thereof

A scheduling module arranged to schedule the transmission of data from a plurality of data sources over a serial communication interface. The scheduling module comprises a register array and is arranged to selectively couple one of the data sources to the serial communication interface based at least partly on a source identifier value stored within a currently selected register within the register array. ... Freescale Semiconductor Inc

06/04/15 / #20150155840

Multiple-state, switch-mode power amplifier systems and methods of their operation

An embodiment of an amplifier includes n (n>1) switch-mode power amplifier (smpa) branches. Each smpa branch includes two drive signal inputs and one smpa branch output. ... Freescale Semiconductor Inc

06/04/15 / #20150155838

Amplifier with adjustable load

A device includes a doherty amplifier having a carrier path and a peaking path. The doherty amplifier includes a carrier amplifier configured to amplify a signal received from the carrier path and a peaking amplifier configured to amplify a signal received from the peaking path. ... Freescale Semiconductor Inc

06/04/15 / #20150155830

Multiple-state, switch-mode power amplifier systems and methods of their operation

An embodiment of an amplifier includes n (n>1) switch-mode power amplifier (smpa) branches. Each smpa branch includes two drive signal inputs and one smpa branch output. ... Freescale Semiconductor Inc

06/04/15 / #20150155350

Resurf high voltage diode

A trench-isolated resurf diode structure (100) is provided which includes a substrate (150) in which is formed anode (130, 132) and cathode (131) contact regions separated from one another by a shallow trench isolation region (114, 115), along with a buried cathode extension region (104) formed under a resurf anode extension region (106, 107) such that the cathode extension region (104) extends beyond the cathode contact (131) to be sandwiched between upper and lower regions (103, 106, 107) of opposite conductivity type.. . ... Freescale Semiconductor Inc

06/04/15 / #20150155017

Bypass system and method that mimics clock to data memory read timing

A bypass system and method that mimics read timing of a memory system which includes a self-timing circuit and a sense amplifier. When prompted, the self-timing circuit initiates the sense amplifier to evaluate its differential input. ... Freescale Semiconductor Inc

06/04/15 / #20150153409

Circuit for testing power supplies in multiple power modes

A bist circuit is provided for testing the status of power supplies in an integrated circuit in multiple power modes including multiple circuit blocks. The bist circuit includes a finite state machine (fsm), power monitors and a comparator. ... Freescale Semiconductor Inc

06/04/15 / #20150152833

Rf power amplification and distribution systems, plasma ignition systems, and methods of operation therefor

An embodiment of a plasma ignition system for an internal combustion engine having up to n cylinders includes a power splitter, n phase shifters, n amplifiers, a power combiner network, and up to n radiation devices. The power splitter divides an input rf signal into n divided rf signals. ... Freescale Semiconductor Inc

05/28/15 / #20150149446

Circuitry for a computing system and computing system

Circuitry for a computing system includes a memory arrangement having at least one memory management unit and at least one processor. The at least one processor is arranged to issue a memory query to the memory management unit. ... Freescale Semiconductor Inc

05/28/15 / #20150146835

Calibration arrangement for frequency synthesizers

An electronic device has a calibration arrangement for controlling a frequency characteristic of a pll circuit having a phase comparator having an output for generating a phase difference signal, a voltage controlled oscillator and a divider. The divisor of the divider is programmable, and the oscillator is also directly modulated by an oscillator modulation signal. ... Freescale Semiconductor Inc

05/28/15 / #20150146613

Method and apparatus for resetting at least one node within a cpri radio base station system

A method of resetting at least one node within a common public radio interface (cpri) radio base station system is described. The method comprises, at an end-point radio equipment controller (rec) node within the cpri radio base station system, receiving on a slave port a reset notification, and in response thereto transmitting on the slave port a reset notification comprising a reset bit being set within at least ten hyperframes.. ... Freescale Semiconductor Inc

05/28/15 / #20150146612

Method and system for processing data flows

The method and system supports multiple bandwidth traffic over a single cpri (common public radio interface) link (109) using a single bandwidth dma (direct memory access) engine (505) and fast fourier transform/inverse fast fourier transform processing. (402, 404) the invention exploits fast fourier transform/inverse fast fourier transform properties and is particularly suitable for supporting lte (long term evolution) cellular communication systems (100) the cpri media access control is configured in each cpri lane to run at the maximum bandwidth among the bandwidths required. ... Freescale Semiconductor Inc

05/28/15 / #20150145706

Pin entry device, a user identification terminal and a method of obtaining a pin code

A pin entry device is described. The pin entry device has a plurality of push keys arranged to allow a user to input a pin code, a plurality of value indicators associated with the plurality of push keys, each value indicator being controllable to indicate a value of the associated push key to the user in dependence on a value assignment signal, and a key value controller arranged to dynamically generate a value assignment signal representing an assignment of a plurality of values to the plurality of push keys and provide the value assignment signal to the plurality of value indicators. ... Freescale Semiconductor Inc

05/28/15 / #20150145563

Differential line driver circuit and method therefor

A differential line driver circuit comprising a plurality of driver stages is described. Each driver stage is operably coupled to at least one output of the line driver circuit and arranged to receive at least one control signal and to drive at least one output signal on the at least one output of the line driver circuit in accordance with the at least one control signal received thereby. ... Freescale Semiconductor Inc

05/28/15 / #20150145556

Io driver impedance calibration

An io driver for an integrated circuit and a method for calibrating such an io driver are provided. The io driver comprises a plurality of io driver cells, a plurality of io partial driver cells and an external resistor. ... Freescale Semiconductor Inc

05/28/15 / #20150145543

Mems device positioning apparatus, test system, and test method

A positioning apparatus includes a support structure, a positioning structure, and a fixture for retaining mems devices. A shaft spans between the support structure and the positioning structure, and is configured to rotate about a first axis relative to the support structure in order to rotate the positioning structure and the fixture about the first axis. ... Freescale Semiconductor Inc

05/28/15 / #20150145148

Copper ball bond interface structure and formation

An integrated circuit copper wire bond connection is provided having a copper ball (32) bonded directly to an aluminum bond pad (31) formed on a low-k dielectric layer (30) to form a bond interface structure for the copper ball characterized by a first plurality of geometric features to provide thermal cycling reliability, including an aluminum minima feature (z1, z2) located at an outer peripheral location (42) under the copper ball to prevent formation and/or propagation of cracks in the aluminum bond pad.. . ... Freescale Semiconductor Inc

05/28/15 / #20150145114

Thermally enhanced package with lid heat spreader

A method and apparatus are provided for manufacturing a lead frame based thermally enhanced package (9) with exposed heat spreader lid array (96) designed to be optimized for compression mold encapsulation of an integrated circuit die (94) by including a perimeter reservoir regions (97r) in each heat spreader lid (96) for movement of mold compound (98) displaced during the mold compression process.. . ... Freescale Semiconductor Inc

05/21/15 / #20150143308

Simulation system and method for testing a simulation of a device against one or more violation rules

A simulation system for testing a simulation of a device against one or more violation rules is described. The simulation system comprises a device simulator for executing the simulation of a device using a device design, a device model and a simulation scenario; and one or more violation monitors, one for each violation rule. ... Freescale Semiconductor Inc

05/21/15 / #20150139500

Method and system for optimizing image processing in driver assistance systems

An imager simulator configured to be used in lieu of an imager within a vehicle is provided. The imager simulator includes an image source configured to store pre-determined reference data; and an imager interface unit configured to generate image data based on the pre-determined reference data. ... Freescale Semiconductor Inc

05/21/15 / #20150139011

Method and apparatus for detecting a set up signal used for data communication over a communication network

A method of detecting a set up signal having a predetermined frequency and used for data transmissions over a communication network comprises comparing an energy level of a filtered received signal with a first predetermined value and providing a first detect signal, comparing an energy level of a component of the received signal at a predetermined frequency with a second predetermined value and providing a second detect signal. In addition, an autocorrelation function is performed on the received signal to discriminate between the set up signal and other signals in the received signal and a check signal is provided when the autocorrelation function identifies the set up signal. ... Freescale Semiconductor Inc

05/21/15 / #20150137841

Built-in self test system, system on a chip and method for controlling built-in self tests

A built-in self test system comprises an integrated circuit device comprising a plurality of functional units coupled to built-in self test circuitry; a low power control unit operable to switch the integrated circuit device into a low power mode and to generate a bist wake-up signal during or before entering the low power mode; and a built-in self test control unit coupled to the built-in self test circuitry and the low power control unit and arranged to initiate a built-in self test when receiving the bist wake-up signal.. . ... Freescale Semiconductor Inc

05/07/15 / #20150128001

Efficient apparatus and method for testing digital shadow logic around non-logic design structures

A circuit for efficiently testing digital shadow logic (504, 514) in isolation from an associated non-logic design structure (510) includes a width and delay matched bypass circuit (520) coupled to receive an n-bit input from shadow logic (504) and to generate therefrom an m-bit test output which is selectively connected to replace an m-bit output to the shadow logic (514) from the non-logic design structure (510) in a shadow logic test mode, thereby flexibly emulating the non-logic design structure to allowing separate isolated tests on the shadow logic and on the non-logic design structure. . ... Freescale Semiconductor Inc

05/07/15 / #20150124519

Circuitry including resistive random access memory storage cells and methods for forming same

A method of forming a circuitry includes providing a substrate comprising a plurality of die. Each die includes a plurality of resistive random access memory (rram) storage cells. ... Freescale Semiconductor Inc

05/07/15 / #20150123938

Electronic device for proximity detection, a light emitting diode for such electronic device, a control unit for such electronic device, an apparatus comprising such electronic device and an associated method

An electronic device for proximity detection is described. The electronic device has a first light emitting diode and a control unit. ... Freescale Semiconductor Inc

05/07/15 / #20150123236

Diodes with multiple junctions and fabrication methods therefor

An embodiment of a diode includes a semiconductor substrate, a first contact region having a first conductivity type, a second contact region laterally spaced from the first contact region, and having a second conductivity type, an intermediate region disposed in the semiconductor substrate between the first and second contact regions, electrically connected with the first contact region, and having the first conductivity type, and a buried region disposed in the semiconductor substrate, having the second conductivity type, and electrically connected with the second contact region. The buried region extends laterally across the first contact region and the intermediate region to establish first and second junctions, respectively. ... Freescale Semiconductor Inc

05/07/15 / #20150123222

Sensor protective coating

A method of fabricating a sensor device includes forming a plurality of sensor structures on a wafer, covering the plurality of sensor structures with a polymer layer, and dicing the wafer into a plurality of die while each sensor structure remains covered by the polymer layer.. . ... Freescale Semiconductor Inc

05/07/15 / #20150123168

Mishfet and schottky device integration

A semiconductor device includes a substrate comprising a heterostructure configured to support formation of a channel during operation, first and second dielectric layers supported by the substrate, the second dielectric layer being disposed between the first dielectric layer and the substrate, a gate supported by the substrate, disposed in a first opening in the first dielectric layer, and to which a bias voltage is applied during operation to control current flow through the channel, the second dielectric layer being disposed between the gate and the substrate, and an electrode supported by the substrate, disposed in a second opening in the first and second dielectric layers, and configured to establish a schottky junction with the substrate.. . ... Freescale Semiconductor Inc

04/30/15 / #20150121325

Simulation system and method for testing a simulation of a device against one or more violation rules

A simulation system for testing a simulation of a device against one or more violation rules is described. The simulation system comprises a device simulator for executing the simulation of a device using a device design, a device model and a simulation scenario; and one or more violation monitors, one for each violation rule. ... Freescale Semiconductor Inc

04/30/15 / #20150120234

Smart handler resource distribution system

A system for concurrently testing multiple semiconductor components includes multiple testers, each including a processor and a memory configured to store and execute control signals for completing testing of one of the semiconductor components, a tester side docking board, and a tester communication port. A handler has multiple test sites, each of which is configured to receive one of the semiconductor components, a handler side docking board, and a handler communication port. ... Freescale Semiconductor Inc

04/30/15 / #20150118802

Dual corner top gate molding

A mold die includes a side wall forming a hollow cavity and opposing first and second axial ends. The side wall has first and second openings respectively at the first and second axial ends. ... Freescale Semiconductor Inc

04/30/15 / #20150117446

Cut-through forwarding module and a method of receiving and transmitting data frames in a cut-through forwarding mode

The disclosure relates to cut-through forwarding module, an integrated circuit, a semiconductor device and a method of receiving and transmitting data frames in a cut-through forwarding mode. The cut-through forwarding module processes received data frames in data blocks. ... Freescale Semiconductor Inc

04/30/15 / #20150116039

Adaptive adjustment of power splitter

A device includes a power splitter configured to couple to an amplifier having a first path and a second path. The device includes a controller coupled to first and second variable attenuators and first and second adjustable phase shifters. ... Freescale Semiconductor Inc

04/30/15 / #20150115936

Signal error compensation for a magnetometer in a sensor package

A device (50) includes a magnetometer (54) adapted to produce an output signal (30) indicative of a sensed magnetic field (38), a second sensor (24), and a processing unit (56) connected to each of the magnetometer and the second sensor. The processing unit is configured to perform operations that include detecting (188) whether the second sensor is in an operational state (94) in which the second sensor is drawing an electric current (82, 86), and when the second sensor is in the operational state, applying (194, 196) a trim parameter (72) to the output signal, the trim parameter canceling at least a portion of a signal error (70) on the output signal, wherein the signal error is generated at the magnetometer in response to the electric current drawn by the second sensor in the operational state.. ... Freescale Semiconductor Inc

04/30/15 / #20150115451

Method and apparatus for high temperature semiconductor device packages and structures using a low temperature process

A semiconductor device package that incorporates a combination of ceramic, organic, and metallic materials that are coupled using silver is provided. The silver is applied in the form of fine particles under pressure and a low temperature. ... Freescale Semiconductor Inc

04/30/15 / #20150115266

Die crack detector with integrated one-time programmable element

The embodiments described herein provide a die crack detector and method that use a conductive trace arranged to at least substantially extend around a perimeter of an integrated circuit die. A one-time programmable element, such as a fuse, is coupled in series with the conductive trace, and a package lead is electrically coupled to both the fuse and another operational element on the integrated circuit die. ... Freescale Semiconductor Inc

04/30/15 / #20150114572

Devices and methods of operation for separating semiconductor die from adhesive tape

The embodiments described herein provide an apparatus and method for separating dies from adhesive tape. In general, these techniques use applied vacuum and one or more channels in an extractor base surface to progressively peel adhesive tape away from the die. ... Freescale Semiconductor Inc

04/23/15 / #20150110126

Cut through packet forwarding device

An electronic device communicates according to a network protocol that defines data packets, for example ethercat. The device has a processor for performing input control on incoming data packets and performing output control on outgoing data packets, and a shared fifo buffer comprising a multiuser memory. ... Freescale Semiconductor Inc

04/23/15 / #20150109330

Display controller with blending stage

A display controller comprising a blending stage and a blending controller. The blending stage is provided for blending multiple image layers into one display output image and comprises a plurality of input channels for receiving pixel data for the multiple image layers. ... Freescale Semiconductor Inc

04/23/15 / #20150109054

Ready-flag circuitry for differential amplifiers

Ready-flag circuitry for differential amplifiers. In some embodiments, a semiconductor device may include an amplifier including two inputs, and a ready-flag circuit operably coupled to the amplifier, the ready-flag circuit configured to monitor two or more internal nodes of the amplifier and to produce a signal indicating whether a voltage or current difference between the two inputs has been minimized. ... Freescale Semiconductor Inc

04/23/15 / #20150108936

Method and apparatus for charging a bootstrap charge storage device

A charging circuit for at least one bootstrap charge storage element within an inertial load driver circuit is described, the at least one bootstrap charge storage element comprising a first node operably coupled to an output node of at least one switching element of the inertial load driver circuit. The charging circuit comprises at least one current source controllable to provide a current to a second node of the at least one bootstrap charge storage element, and at least one detection component arranged to receive at a first input thereof an indication of a voltage level at the output node of the at least one switching element of the inertial load driver circuit, detect when the voltage level at the output node of the switching element of the inertial load driver circuit is below a negative threshold voltage level, and control the at least one current source to provide a current to the second node of the at least one bootstrap charge storage element when the voltage level at the output node of the switching element of the inertial load driver circuit is below the negative threshold voltage level.. ... Freescale Semiconductor Inc

04/23/15 / #20150108625

Semiconductor device with heat spreader

A semiconductor device includes a package body, a semiconductor die embedded in the package body and a heat spreader attached to a top surface of the package body and spaced from semiconductor die. The heat spreader may be formed of solder that is melted within a recess in the top surface of the package body.. ... Freescale Semiconductor Inc

04/16/15 / #20150106671

Memory device retention mode based on error information

A controller for a memory device has a power control section to control power to a memory element in an operation mode and in a retention mode. A monitoring section receives and monitors error information and a storage section stores a retention parameter. ... Freescale Semiconductor Inc

04/16/15 / #20150106415

True random number generator with repeatedly activated oscillator

A true random number generator (rng) has one or more oscillators and an output register for storing a random number output. Each of the oscillators is activated, successively, in a free-running oscillation phase, and a capture phase during which the oscillator is quiescent. ... Freescale Semiconductor Inc

04/16/15 / #20150104886

Semiconductor device arrangement, a method of analysing a performance of a functional circuit on a semiconductor device and a device analysis system

A semiconductor device arrangement comprising a functional circuit comprising a plurality of timing components and a reference module comprising a plurality of reference components is described. Each reference component comprises a reference timing component corresponding to a timing component of the plurality of timing components and a controllable timing component. ... Freescale Semiconductor Inc

04/16/15 / #20150102839

Low power inverter circuit

A low power inverter circuit includes first and second transistors that receive an input signal at their gate terminals. The first and second transistors are connected by way of their source terminals to third and fourth transistors, respectively. ... Freescale Semiconductor Inc

04/16/15 / #20150102437

Mems sensor device with multi-stimulus sensing and method of fabrication

A device (20) includes sensors (30, 32, 34) that sense different physical stimuli. Fabrication (90) entails forming (92) a device structure (22) to include the sensors and coupling (150) a cap structure (24) with the device structure so that the sensors are interposed between the cap structure and a substrate layer (28) of the device structure. ... Freescale Semiconductor Inc

04/16/15 / #20150102384

Esd protection with asymmetrical bipolar-based device

An electrostatic discharge (esd) protection device includes a semiconductor substrate comprising a buried insulator layer and a semiconductor layer over the buried insulator layer having a first conductivity type, and first and second bipolar transistor devices disposed in the semiconductor layer, laterally spaced from one another, and sharing a common collector region having a second conductivity type. The first and second bipolar transistor devices are configured in an asymmetrical arrangement in which the second bipolar transistor device includes a buried doped layer having the second conductivity type and extending along the buried insulator layer from the common collector region across a device area of the second bipolar transistor device.. ... Freescale Semiconductor Inc

04/09/15 / #20150100792

Semiconductor device and a method of manufacturing a semiconductor device

A semiconductor device having a plurality of on-chip processors, a plurality of key rams, a plurality of key ram controllers, a fuse bank, a fuse bank controller and a boot controller is described. The boot controller is arranged to, in a first programming stage, allocate a first array of fuses in the fuse bank in dependence on the size of a first device key for storing the first device key in the fuse bank, and, during boot-time, provide the first device key to a first key ram controller. ... Freescale Semiconductor Inc

04/09/15 / #20150098540

Clock distribution module, synchronous digital system and method therefor

A clock distribution module for a digital synchronous system is described. The clock distribution module comprising a first node arranged to comprise a clock signal comprising a propagation delay relative to a reference clock signal, at least one further node arranged to comprise a clock signal comprising a propagation delay relative to the reference clock signal corresponding to that of the first node, and a clock configuration module. ... Freescale Semiconductor Inc

04/09/15 / #20150098160

Protection circuit and a gate driving circuitry

A protection circuit and a gate driving circuitry. The protection circuit is for protecting a p-type back-to-back mos switch. ... Freescale Semiconductor Inc

04/09/15 / #20150097623

Power amplifiers with signal conditioning

A device includes an amplifier having a first path and a second path and a first variable attenuator connected to the first path. The device includes a controller coupled to the first variable attenuator. ... Freescale Semiconductor Inc

04/09/15 / #20150097557

Variable reluctance sensor interfaces with signal pre-processing and methods of their operation

The embodiments described herein can provide a variable reluctance sensor (vrs) interface that may reduce the probability of erroneous transitions in a resulting generated detect signal. As such, the vrs interface can improve the accuracy of position and/or motion determinations, and thus can improve the performance of a wide variety of devices that use variable reluctance sensors. ... Freescale Semiconductor Inc

04/09/15 / #20150097556

Variable reluctance sensor interfaces and methods of their operation

The embodiments described herein include systems with a variable reluctance sensor (vrs) interface and methods of their operation that may reduce the probability of erroneous transitions in a resulting generated detect signal. As such, the vrs interface can improve the accuracy of position and/or motion determinations, and thus can improve the performance of a wide variety of devices that use variable reluctance sensors. ... Freescale Semiconductor Inc

04/09/15 / #20150097280

Heat conductive substrate for integrated circuit package

An integrated circuit package includes a substrate having a heat conducting portion integrally formed with a heat dissipating portion. First and second integrated circuit dies are mounted to opposite sides of the heat conducting portion of the substrate. ... Freescale Semiconductor Inc

04/09/15 / #20150097278

Surface mount semiconductor device with additional bottom face contacts

Assembling a surface mount semiconductor device includes providing a lead frame structure with peripheral leads and additional bottom face contacts integral with frame members. Outer portions of the bottom face contact members are interposed between inner portions of adjacent pairs of the peripheral leads. ... Freescale Semiconductor Inc

04/09/15 / #20150097265

Semiconductor device with buried conduction path

A device includes a semiconductor substrate, emitter and collector regions disposed in the semiconductor substrate, having a first conductivity type, and laterally spaced from one another, and a composite base region disposed in the semiconductor substrate, having a second conductivity type, and including a base contact region, a buried region through which a buried conduction path between the emitter and collector regions is formed during operation, and a base link region electrically connecting the base contact region and the buried region. The base link region has a dopant concentration level higher than the buried region and is disposed laterally between the emitter and collector regions.. ... Freescale Semiconductor Inc

04/09/15 / #20150097238

Mergeable semiconductor device with improved reliability

A device includes a semiconductor substrate, source and drain regions disposed in the semiconductor substrate, having a first conductivity type, and laterally spaced from one another, and a composite body region disposed in the semiconductor substrate and having a second conductivity type. The composite body region includes a first well region that extends laterally across the source and drain regions and a second well region disposed in the first well region. ... Freescale Semiconductor Inc

04/02/15 / #20150095525

Integrated circuit comprising an io buffer driver and method therefor

. . An integrated circuit for bias stress condition removal comprising at least one input/output (io) buffer driver circuit comprising at least one input signal is described. A primary buffer driver stage receives the at least one input signal and providing an output signal in a first time period; and a secondary buffer driver stage receives the at least one input signal and providing an output signal in a second time period. ... Freescale Semiconductor Inc

04/02/15 / #20150095393

Method and device for generating floating-point values

A floating-point value can represent a number or something that is not a number (nan). A floating-point value that is a nan includes a portion that stores information about the source operands of the instruction.. ... Freescale Semiconductor Inc

04/02/15 / #20150093864

Non-volatile memory (nvm) and high-k and metal gate integration using gate-last methodology

A method of making a semiconductor structure uses a substrate and includes a logic device in a logic region and a non-volatile memory (nvm) device in an nvm region. An nvm structure is formed in the nvm region. ... Freescale Semiconductor Inc

04/02/15 / #20150091622

System and method for enabling maximum performance operation within an extended ambient temperature range

A system method of initializing operation of a semiconductor device including detecting de-assertion of an external reset signal while the semiconductor device in a reset state, monitoring a temperature level of the semiconductor device, and while the temperature level is below a predetermined minimum operating temperature level that allows the semiconductor device to operate at a maximum performance level, keeping the semiconductor device in the reset state and asserting at least one operating parameter on the semiconductor device at an elevated level to generate heat on the semiconductor device, and releasing the reset condition when the temperature level is at least the predetermined minimum operating temperature level. The operating parameter may be clock frequency or supply voltage level or a combination of both. ... Freescale Semiconductor Inc

04/02/15 / #20150091607

Sequential logic circuit and method of providing setup timing violation tolerance therefor

A sequential logic circuit comprising a first latch component comprising a data input arranged to receive an input signal, a data output arranged to output a current logical state of the first latch component and a clock input arranged to receive a clock signal; the first latch component being arranged to comprise a transparent state upon the clock signal received thereby comprising a first logical state, and to comprise a latched state upon the clock signal received thereby comprising a second logical state, and a second latch component comprising a data input arranged to receive an input signal, a data output operably coupled to an output of the sequential logic circuit and arranged to output a current state of the second latch component and a clock input arranged to receive a clock signal; the second latch component being arranged to comprise a transparent state upon the clock signal received thereby comprising a second logical state, and to comprise a latched state upon the clock signal received thereby comprising a first logical state. The sequential logic circuit is arranged to operate in at least a first operating mode in which the data input of the first latch component and the data input of the second latch component are operably coupled to a first input of the sequential logic circuit, and in which the clock signals provided to the first and second latch components are such that a transition of the second latch component from a transparent state to a latched state is delayed relative to a corresponding transition of the first latch component from a transparent state to a latched state for a time period for receiving late data.. ... Freescale Semiconductor Inc

04/02/15 / #20150091187

3d device packaging using through-substrate posts

A method for 3d device packaging utilizes through-hole metal post techniques to mechanically and electrically bond two or more dice. The first die includes a set of through-holes extending from a first surface of the first die to a second surface of the first die. ... Freescale Semiconductor Inc

04/02/15 / #20150091178

3d device packaging using through-substrate pillars

A method for 3d device packaging utilizes through-substrate pillars to mechanically and electrically bond two or more dice. The first die includes a set of access holes extending from a surface of the first die to a set of pads at a metal layer of the first die. ... Freescale Semiconductor Inc

04/02/15 / #20150091160

3d device packaging using through-substrate posts

A method for 3d device packaging utilizes through-substrate metal posts to mechanically and electrically bond two or more dice. The first die includes a set of access holes extending from a surface of the first die to a set of pads at a metal layer of the first die. ... Freescale Semiconductor Inc

04/02/15 / #20150091079

Non-volatile memory (nvm) and high-k and metal gate integration using gate-first methodology

A method of making a semiconductor structure includes forming a select gate over a substrate in an nvm portion and a first protection layer over a logic portion. A control gate and a storage layer are formed over the substrate in the nvm portion, wherein the control and select gates have coplanar top surfaces. ... Freescale Semiconductor Inc

03/26/15 / #20150089305

Interrupt supervision system, processing system and method for interrupt supervison

An interrupt supervision system comprises an interrupt controller device comprising a plurality of interrupt request input lines and at least one output line connectable to a processing device. The interrupt controller device is arranged to receive, on the plurality of interrupt request input lines, a plurality of corresponding interrupt requests and to provide, on the at least one output line, the plurality of interrupt requests to the processing device in a sequence generated by the interrupt controller device depending on one or more priorities assigned to the interrupt requests; and one or more interrupt checker devices, each being arranged to receive a reception indication when the interrupt controller device receives, on a selected one of the plurality of interrupt request lines, a corresponding selected interrupt request, and to provide a corresponding error indication when an output of the corresponding selected interrupt request from the interrupt controller device on the at least one output line is not confirmed within a latency period assigned to the corresponding selected interrupt request, wherein the assigned latency period begins when the interrupt checker device receives the reception indication.. ... Freescale Semiconductor Inc

03/26/15 / #20150084684

Temperature dependent biasing for leakage power reduction

Temperature dependent biasing for leakage power reduction. In some embodiments, a semiconductor device may include a biasing circuit configured to generate a voltage that varies dependent upon a temperature of the semiconductor device and a logic circuit operably coupled to the biasing circuit, where the voltage is applied to a bulk terminal of one or more transistors within the logic circuit, and where the voltage has a value outside of a voltage supply range of the logic circuit. ... Freescale Semiconductor Inc

03/26/15 / #20150084657

Heating system and method of testing a semiconductor device using a heating system

A heating system is described for generating heat and bringing heat to a semiconductor device under test. The heating system comprises a conduction heating unit comprising a heating resistor, a thermal contact area for thermally contacting the semiconductor device under test, and a thermally conductive and electrically insulating connection between the heating resistor and the thermal contact area. ... Freescale Semiconductor Inc

03/26/15 / #20150084417

Electronic device and method for operating a power switch

An electronic device comprising a first power switch connectable or connected between a first voltage source and a load is proposed. The first power switch assumes a conductive state in response to a power-on request and a non-conductive state in response to a power-off request, for energizing and deenergizing the load, so that a voltage across the first power switch tends to a positive high level when the first power switch is in the non-conductive state and to a positive low level when the first power switch is in the conductive state. ... Freescale Semiconductor Inc

03/26/15 / #20150084199

Copper ball bond features and structure

An integrated circuit wire bond connection is provided having an aluminum bond pad (51) that is directly bonded to a copper ball (52) to form an aluminum splash structure (53) and associated crevice opening (55) at a peripheral bond edge of the copper ball (54), where the aluminum splash structure (53) is characterized by a plurality of geometric properties indicative of a reliable copper ball bond, such as lateral splash size, splash shape, relative position of splash-ball crevice to the aluminum pad, crevice width, crevice length, crevice angle, and/or crevice-pad splash index.. . ... Freescale Semiconductor Inc

03/26/15 / #20150084138

Integrated circuit having varying substrate depth and method of forming same

A semiconductor device is formed such that a semiconductor substrate of the device has a non-uniform thickness. A cavity is etched at a selected side of the semiconductor substrate, and the selected side is then fusion bonded to another substrate, such as a carrier substrate. ... Freescale Semiconductor Inc

03/19/15 / #20150082284

Method and system for generating a memory trace of a program code executable on a programmable target

A method of generating an instrumented code from a program code executable on a programmable target is described. The method comprises analysing the program code to detect a loop nest with regular memory access in the program code, providing a record of static memory address information associated with the loop nest, and instrumenting the program code to provide an instrumented code corresponding to the program code supplemented with an instrumentation instruction to output an information message comprising a dynamic memory address information field formatted to store a dynamic memory address information associated with the loop nest.. ... Freescale Semiconductor Inc

03/19/15 / #20150082017

Electronic device having a pin for setting its mode of operation and method to set a mode of operation for an electronic device having a pin

An electronic device having a pin for setting its mode of operation, wherein the pin is connected or connectable to a first connection of a resistor, wherein the electronic device is arranged to detect a location of the resistor, wherein the electronic device is arranged to detect a size of the resistor, wherein the electronic device is arranged to determine a first setting based on the location of the resistor, and wherein the electronic device is arranged to determine a second setting based on the size of the resistor.. . ... Freescale Semiconductor Inc

03/19/15 / #20150082005

Processing system and method of instruction set encoding space utilization

A processing system comprises a processing device; a first instruction set encoded in a first encoding space and comprising one or more first instructions; a second instruction set encoded in a second encoding space different from the first encoding space and comprising two or more orthogonal second instructions; and an instruction encoder arranged to encode and encapsulate subsets of the second instructions in instruction containers, each instruction container sized to comprise a plurality of the second instructions.. . ... Freescale Semiconductor Inc

03/19/15 / #20150077163

Dynamic frequency divider circuit

The invention relates to a frequency divider circuit for dividing an input rf signal to a frequency divided rf signal. The circuit comprises a rf pair, a switching-quad pair coupled in series with a transimpedance amplifier and a double pair of emitter followers. ... Freescale Semiconductor Inc

03/19/15 / #20150076556

Integrated circuit device and a method for providing esd protection

An integrated circuit (ic) device including an electrostatic discharge (esd) protection network for a high voltage application. The esd protection network includes a common diode structure coupled between an external contact of the ic device and a substrate of the ic device, such that the common diode structure is forward biased towards the external contact, a darlington transistor structure coupled between the external contact and the substrate of the ic device, and the darlington transistor structure includes: an emitter node coupled to the external contact; a collector node coupled to the substrate; and a base node coupled between the emitter node of the darlington transistor structure and the common diode structure. ... Freescale Semiconductor Inc

03/19/15 / #20150075401

Squib driver diagnostic circuit and method

A diagnostic circuit is provided that includes a fet having a source connected to a first node, a drain, and a gate; a first switch connecting a current-supply node to one of the gate and a second node; a second switch connecting the first node and the second node; a variable current source providing one of a drive current and a test current to the current-supply node; a fire current source configured to provide a fire current to the drain; an error-detecting circuit connected to the second node, a reference terminal, and an error node, the error-detecting circuit generating an error signal to the error node indicating whether an error-detecting parameter at the second node exceeds a reference parameter at the reference terminal; and a control circuit generating control signals to control the variable current source, and the first and second switches.. . ... Freescale Semiconductor Inc

03/12/15 / #20150074319

Universal spi (serial peripheral interface)

A universal spi interface is provided that is compatible, without the need for additional interface logic or software, with the spi bus, existing dsa and other serial busses similar to (but not directly compatible with) the spi bus, and parallel busses requiring compatibility with 74xx164-type signaling. In an additional aspect, a reduced-pincount universal spi interface is provided that provides the same universal interface, but using fewer external output pins. ... Freescale Semiconductor Inc

03/12/15 / #20150069624

Recessed semiconductor die stack

Recessed semiconductor die stacks. In some embodiments, a semiconductor device includes a first die including an active side and a back side, the back side including a non-recessed portion thicker than a recessed portion, the recessed portion including one or more through-die vias on a recessed surface; and a second die located in the recessed portion, the second die including an active side facing the recessed surface of the first die and coupled thereto through the one or more through-die vias. ... Freescale Semiconductor Inc

03/12/15 / #20150069524

Method of forming different voltage devices with high-k metal gate

A method and apparatus are described for integrating high voltage (hv) transistor devices and medium voltage or dual gate oxide (dgo) transistor devices with low voltage (lv) core transistor devices on a single substrate, where each high voltage transistor device (160) includes a metal gate (124), an upper high-k gate dielectric layer (120), a middle gate dielectric layer (114) formed with a relatively lower high-k dual gate oxide layer, and a lower high voltage gate dielectric stack (108, 110) formed with one or more low-k gate oxide layers (22), where each dgo transistor device (161) includes a metal gate (124), an upper high-k gate dielectric layer (120), and a middle gate dielectric layer (114) formed with a relatively lower high-k dual gate oxide layer, and where each core transistor device (162) includes a metal gate (124), an upper high-k gate dielectric layer (120), and a base oxide layer (118) formed with one or more low-k gate oxide layers.. . ... Freescale Semiconductor Inc

03/05/15 / #20150067662

Computer system and a method for generating an optimized program code

A computer system for generating an optimized program code from a program code having a loop with an exit branch, wherein the computer system comprises a processing unit, wherein the processing unit is arranged to convert an exit instruction of the exit branch into a predicated exit instruction, wherein the processing unit is arranged to determine common dependencies within the loop, wherein the processing unit is arranged to generate modified dependencies by adding additional dependencies to the common dependencies, and wherein the processing unit is arranged to apply an algorithm that uses software pipelining for generating an optimized program code for the loop based on the modified dependencies.. . ... Freescale Semiconductor Inc

03/05/15 / #20150067429

Wafer-level gate stress testing

A method of testing a semiconductor device includes forming a test circuit over a semiconductor substrate. The test circuit includes a plurality of interconnects electrically connected to a set of device structures supported by the semiconductor substrate. ... Freescale Semiconductor Inc

03/05/15 / #20150067428

System-on-chip, method of manufacture thereof and method of communicating diagnostic data

A system-on-chip comprises an internal module having diagnostic functionality, and a physical communications port coupled to a first data path and arranged to support, when in use, a datagram-based communications interface for communicating with an external data communications unit. Debug logic circuitry is operably coupled to a debug interface and the internal module, the debug interface being arranged to support communication of debug data relating to the internal module. ... Freescale Semiconductor Inc

03/05/15 / #20150067279

Data processing system and method for operating a data processing system

A data processing system comprising a processing unit, a first memory, and a second memory, wherein the data processing system is arranged to hardware protect the second memory when a write access to the first memory is executed, wherein the processing unit is arranged to execute a program having at least one jump instruction and at least one return instruction, wherein the processing unit is arranged to store a program stack in the first memory, wherein the processing unit is arranged to store a return address on the program stack and to store a return address copy in the second memory when the at least one jump instruction is executed, and wherein the processing unit is arranged to compare the return address with the return address copy when the at least one return instruction is executed.. . ... Freescale Semiconductor Inc

03/05/15 / #20150061780

Oscillator circuit, a semiconductor device and an apparatus

An oscillator circuit for providing an output clock signal is described. The oscillator circuit comprising a voltage reference, a first current source, first capacitor, first capacitor switch, second current source, second capacitor, second capacitor switch, first comparator, second comparator and flip-flop. ... Freescale Semiconductor Inc

03/05/15 / #20150061750

Method and circuit for controlling turnoff of a semiconductor switching element

A circuit performs a method for controlling turn-off of a semiconductor switching element. The method includes determining at least one operating parameter for the semiconductor switching element during an operating cycle and determining a gate discharge current based on the at least one operating parameter. ... Freescale Semiconductor Inc

03/05/15 / #20150061728

Electronic device and method for maintaining functionality of an integrated circuit during electrical aggressions

An electronic device for generating an error signal in response to an electrostatic discharge perturbation is described. The device may comprise: a detection unit for generating a detection signal in response to said electrostatic discharge perturbation, said detection signal correlating in time with said electrostatic discharge perturbation; a clock for generating a clock signal having a clock period; and a protection unit for generating an error signal in response to said detection signal only when a duration of said detection signal exceeds a predefined multiple of said clock period. ... Freescale Semiconductor Inc

03/05/15 / #20150061637

Negative voltage measurement

A method of measuring a negative voltage using a device including a first transistor and a second transistor is provided. The first transistor is coupled to the second transistor and the negative voltage is supplied to a gate of the second transistor. ... Freescale Semiconductor Inc

03/05/15 / #20150061612

Switch mode power supply

A switch mode power supply has a first and second branch of an inductive element; a first switching element and a second switching element connected in series. Both branches are coupled to a power source in parallel. ... Freescale Semiconductor Inc

03/05/15 / #20150061577

Wireless power transmitters with wide input voltage range and methods of their operation

The embodiments described herein provide a power transmitter for wireless charging of an electronic device and methods of its operation. The power transmitter uses an inverter configured to generate a square wave from a potentially wide ranging dc input voltage. ... Freescale Semiconductor Inc

03/05/15 / #20150061106

Cavity-type semiconductor package and method of packaging same

A method (30) of forming a semiconductor package (20) entails applying (56) an adhesive (64) to a portion (66) of a bonding perimeter (50) of a base (22), with a section (68) of the perimeter (50) being without the adhesive (64). A lid (24) is placed on the base (22) so that a bonding perimeter (62) of the lid (24) abuts the bonding perimeter (50) of the base (22). ... Freescale Semiconductor Inc

03/05/15 / #20150061097

Edge coupling of semiconductor dies

Edge coupling of semiconductor dies. In some embodiments, a semiconductor device may include a first semiconductor die, a second semiconductor die disposed in a face-to-face configuration with respect to the first semiconductor die, and an interposer arranged between the first semiconductor and second semiconductor dies, the interposer having an edge detent configured to allow an electrical coupling between the first and second semiconductor dies. ... Freescale Semiconductor Inc

03/05/15 / #20150061044

Sequential wafer bonding

Embodiments of methods of fabricating a sensor device includes attaching a first wafer to a sensor wafer with a first bond material, and attaching a second wafer to the sensor wafer with a second bond material, the second bond material having a lower bonding temperature than the first bond material. After attaching the second wafer, an opening (e.g., a trench cut) through the second wafer is formed, and an adhesive material is provided through the opening to further secure the second wafer to the sensor wafer. ... Freescale Semiconductor Inc

03/05/15 / #20150059473

Multiple sense axis mems gyroscope having a single drive mode

A gyroscope includes a first drive mass driven in a first drive motion along a first axis, the first drive motion generating a first sense motion of a first sense mass in response to rotation of the gyroscope. The gyroscope further includes a second drive mass driven in a second drive motion along a second axis that is transverse to the first axis. ... Freescale Semiconductor Inc

02/26/15 / #20150054562

Level shifter with static precharge circuit

A level shifter includes a static precharge circuit. During a precharge phase, two nodes of the level shifter are precharged to a voltage at or near a reference voltage. ... Freescale Semiconductor Inc

02/26/15 / #20150054487

Reference voltage source and method for providing a curvature-compensated reference voltage

A reference voltage source comprises a bandgap voltage reference circuit having a first node and an output node, the output node being arranged for providing a reference voltage. A curvature correction circuit has an input node connected to the output node and/or to a base of a first bipolar device of the bandgap voltage reference circuit and/or to a base of a second bipolar device of the bandgap voltage reference circuit. ... Freescale Semiconductor Inc

02/26/15 / #20150054477

Power switch with current limitation and zero direct current (dc) power consumption

Power switches with current limitation and zero direct current (dc) power consumption. In an embodiment, an integrated circuit includes switching circuitry coupled between a voltage supply node and a given one of a plurality of power domains, the switching circuitry configured to limit an amount of current drawn by the given power domain from the voltage supply node during a transition period, the switching circuitry further configured to consume zero dc power outside of the transition period. ... Freescale Semiconductor Inc

02/26/15 / #20150054096

Reducing mems stiction by introduction of a carbon barrier

A mechanism for reducing stiction in a mems device by decreasing an amount of carbon from teos-based silicon oxide films that can accumulate on polysilicon surfaces during fabrication is provided. A carbon barrier material film is deposited between one or more polysilicon layer in a mems device and the teos-based silicon oxide layer. ... Freescale Semiconductor Inc

02/26/15 / #20150054044

Method to form a polysilicon nanocrystal thin film storage bitcell within a high k metal gate platform technology using a gate last process to form transistor gates

A process integration is disclosed for fabricating non-volatile memory (nvm) cells (105-109, 113-115) on a first flash cell substrate area (111) which are encapsulated in one or more planar dielectric layers (116) prior to forming an elevated substrate (117) on a second cmos transistor area (112) on which high-k metal gate electrodes (119-120, 122-126, 132, 134) are formed using a gate-last hkmg cmos process flow without interfering with the operation or reliability of the nvm cells.. . ... Freescale Semiconductor Inc

02/19/15 / #20150049406

Electrostatic discharge protection circuit arrangement, electronic circuit and esd protection method

An electrostatic discharge, esd, protection circuit arrangement is connectable to a first pin and a second pin of an electronic circuit and arranged to at least partly absorb an esd current entering the electronic circuit through at least one of the first pin or the second pin during an esd stress event. The protection circuit arrangement comprises a first esd protection circuit arranged to absorb a first portion of the esd current during a first part of the esd stress event during which first part a level of the esd current exceeds a predetermined current threshold; and a second esd protection circuit arranged to absorb a second portion of the esd current, the second portion having a current level below the current threshold, at least during a second part of the esd stress event. ... Freescale Semiconductor Inc

02/19/15 / #20150048848

Test structure and methodology for estimating sensitivity of pressure sensors

A test structure includes two capacitor structures, wherein one of the capacitor structures has conductor plates spaced apart by a cavity, and the other capacitor structure does not include a cavity. Methodology entails forming the test structure and a pressure sensor on the same substrate using the same fabrication process techniques. ... Freescale Semiconductor Inc

02/19/15 / #20150048462

Sensor package and method of forming same

A method (70) of forming sensor packages (20) entails providing a sensor wafer (74) having sensors (30) formed on a side (26) positioned within areas (34) delineated by bonding perimeters (36), and providing a controller wafer (82) having control circuitry (42) at one side (38) and bonding perimeters (46) on an opposing side (40). The bonding perimeters (46) of the controller wafer (82) are bonded to corresponding bonding perimeters (36) of the sensor wafer (74) to form a stacked wafer structure (48) in which the control circuitry (42) faces outwardly. ... Freescale Semiconductor Inc

02/12/15 / #20150046893

Techniques for electromigration stress mitigation in interconnects of an integrated circuit design

A technique for electromigration stress mitigation in interconnects of an integrated circuit design includes generating a maximal spanning tree of a directed graph, which represents an interconnect network of an integrated circuit design. A first point on the spanning tree having a lowest stress and a second point on the spanning tree having a highest stress are located. ... Freescale Semiconductor Inc

02/12/15 / #20150046753

Embedded software debug system with partial hardware acceleration

An embedded software debug system with partial hardware acceleration includes a computer that executes a debug software stack. The debug software stack includes high level operations. ... Freescale Semiconductor Inc

02/12/15 / #20150046658

Cache organization and method

A method and information processing system with improved cache organization is provided. Each register capable of accessing memory has associated metadata, which contains the tag, way, and line for a corresponding cache entry, along with a valid bit, allowing a memory access which hits a location in the cache to go directly to the cache's data array, avoiding the need to look up the address in the cache's tag array. ... Freescale Semiconductor Inc

02/12/15 / #20150041927

Mems device with differential vertical sense electrodes

A mems device includes a first sense electrode and a first portion of a sense mass formed in a first structural layer, where the first sense electrode is fixedly coupled with the substrate and the first portion of the sense mass is suspended over the substrate. The mems device further includes a second sense electrode and a second portion of the sense mass formed in a second structural layer. ... Freescale Semiconductor Inc

02/05/15 / #20150040092

Stress migration mitigation

A computer-implemented method of configuring a semiconductor device includes identifying an interconnect having an interconnect path length greater than a stress-induced void formation characteristic length of the semiconductor device, and placing, with a processor, a conductive structure adjacent the interconnect to define a pair of segments of the interconnect. Each segment has a length no greater than the stress-induced void formation characteristic length of the interconnect, and the conductive structure is selected from the group consisting of a decoy via connected to the interconnect, a floating tile disposed along the interconnect, a tab that laterally extends outward from the interconnect, and a jumper from a first metal layer in which the interconnect is disposed to a second metal layer.. ... Freescale Semiconductor Inc

02/05/15 / #20150037958

Methods of making multi-state non-volatile memory cells

A semiconductor device includes a region in a semiconductor substrate having a top surface with a first charge storage layer on the top surface. A first conductive line is on the first charge storage layer. ... Freescale Semiconductor Inc

02/05/15 / #20150035604

Coupler with distributed feeding and compensation

The embodiments described herein can provide improved signal feeding between hybrid couplers and associated transistors. As such, these embodiments can improve the performance of amplifiers and other such rf devices that utilize these components. ... Freescale Semiconductor Inc

02/05/15 / #20150035151

Capping layer interface interruption for stress migration mitigation

A semiconductor device includes a substrate, a dielectric layer supported by the substrate, an interconnect adjacent the dielectric layer, the interconnect including a conduction material and a barrier material disposed along sidewalls of the interconnect between the conduction material and the dielectric layer, and a layer disposed over the interconnect to establish an interface between the conduction material, the barrier material, and the layer. A plate is disposed along a section of the interconnect to interrupt the interface.. ... Freescale Semiconductor Inc

01/29/15 / #20150029013

Method and system for facilitating viewing of information in a machine

Methods and systems for facilitating viewing of information by machine users associated with machines, such as vehicle users in vehicles, are disclosed. In one example embodiment, a method for facilitating viewing of first information comprises (a) determining second information concerning a viewing direction of the machine user, and (b) adapting at least one operation of at least one display device so as to display the first information. ... Freescale Semiconductor Inc

01/29/15 / #20150028948

Switch-mode amplifier

A device includes a doherty amplifier. The doherty amplifier has a carrier path and a peaking path. ... Freescale Semiconductor Inc

01/29/15 / #20150027767

System and method for lead frame package degating

A method of forming an electronic component includes masking a lead frame to form a mask defining an exposed area, oxidizing the exposed area of the lead frame, wherein the mask inhibits oxidation of an unexposed area, and removing the mask from the lead frame following oxidizing. A lead frame can include a metal sheet patterned to define a pad region and leads. ... Freescale Semiconductor Inc

01/29/15 / #20150027198

Mems parameter identification using modulated waveforms

A sensor system includes a microelectromechanical systems (mems) sensor, control circuit, signal evaluation circuitry, a digital to analog converter, signal filters, an amplifier, demodulation circuitry and memory. The system is configured to generate high and low-frequency signals, combine them, and provide the combined input signal to a mems sensor. ... Freescale Semiconductor Inc

01/22/15 / #20150026523

Debugging method and computer program product

A method for debugging a computer program is proposed. The method comprises: running at least part of said computer program on a computer, thereby prompting said computer to execute a sequence of instructions and to generate a trace corresponding to said executed sequence of instructions; and, when said program has generated an exception, selecting a set of one or more exception strings on the basis of said trace, so that each of said exception strings is a unique substring of said trace; and indicating said exception strings to a user or to a debugging tool. ... Freescale Semiconductor Inc

01/22/15 / #20150026410

Least recently used (lru) cache replacement implementation using a fifo

A method and apparatus for calculating a victim way that is always the least recently used way. More specifically, in an m-set, n-way set associative cache, each way a cache set comprises a valid bit that indicates that the way contains valid data. ... Freescale Semiconductor Inc

01/22/15 / #20150024535

Semiconductor sensor device with footed lid

A semiconductor sensor device is packaged using a footed lid instead of a pre-molded lead frame. A semiconductor sensor die is attached to a first side of a lead frame. ... Freescale Semiconductor Inc

01/22/15 / #20150021746

Backscattering for localized annealing

A method of fabricating an electronic apparatus includes forming an active layer over a wafer, forming a backscatter layer over the wafer, and directing radiation toward the wafer to anneal the active layer. The backscatter layer is not transparent to the radiation, more reflective than absorptive of the radiation, and positioned such that the backscatter layer inhibits exposure of the wafer to the radiation apart from the active layer.. ... Freescale Semiconductor Inc

01/22/15 / #20150021376

Wire bonding capillary with working tip protrusion

A method for bonding a wire to a substrate includes forming a wire ball at a working tip of a capillary and contacting the wire ball to a substrate via the capillary. The method also includes driving a protrusion at the working tip of the capillary into contact with a region of the substrate surrounding the wire ball. ... Freescale Semiconductor Inc

01/15/15 / #20150015240

Method of detecting irregular current flow in an integrated circuit device and apparatus therefor

A method of detecting irregular high current flow within an integrated circuit (ic) device is described. The method comprises obtaining infrared (ir) emission information for the ic device, identifying at least one functional component within the ic device comprising a high current flow, based at least partly on the obtained ir emission information, obtaining ir emission information for at least one reference component within the ic device, and determining whether the high current flow of the at least one functional component comprises an irregular high current flow based at least partly on a comparison of respective ir emission information for the at least one functional component and the at least one reference component.. ... Freescale Semiconductor Inc

01/08/15 / #20150011053

Semiconductor device and method of assembling same

A semiconductor device has a die support and external leads formed integrally from a single sheet of electrically conductive material. A die mounting substrate is mounted on the die support, with bonding pads coupled to respective external connection pads on an external connector side of the substrate. ... Freescale Semiconductor Inc

01/01/15 / #20150006869

Debug method and device for handling exceptions and interrupts

A method and information processing system provide trace compression for trace messages. In response to a branch of a conditional branch instruction having not been taken or having been taken, a flag of a history buffer is set or cleared. ... Freescale Semiconductor Inc

01/01/15 / #20150006863

Debug method and device for providing indexed trace messages

A method and information processing system provide trace compression for trace messages. In response to a branch of a conditional branch instruction having not been taken or having been taken, a flag of a history buffer is set or cleared. ... Freescale Semiconductor Inc

01/01/15 / #20150006827

Method for detecting bank collision at a memory and device therefor

A pipeline circuit determines a first effective address based a sum of a first value and a second value. The first effective address is based upon an actual value of a carry-in into a bit-wise region of the first and second values. ... Freescale Semiconductor Inc

01/01/15 / #20150004768

Drain-end drift diminution in semiconductor devices

A method of fabricating a transistor includes forming a field isolation region in a substrate. After forming the field isolation region, dopant is implanted in a first region of a substrate for formation of a drift region. ... Freescale Semiconductor Inc

01/01/15 / #20150004747

Reram device structure

A resistive random access memory (reram) includes a first metal layer having a first metal and a metal-oxide layer on the first metal layer. The metal-oxide layer includes the first metal. ... Freescale Semiconductor Inc

01/01/15 / #20150002229

Semiconductor packages having wire bond wall to reduce coupling

A device (e.g., a doherty amplifier) housed in an air cavity package includes one or more isolation structures over a surface of a substrate and defining an active circuit area. The device also includes first and second adjacent circuits within the active circuit area, first and second leads coupled to the isolation structure(s) between opposite sides of the package and electrically coupled to the first circuit, third and fourth leads coupled to the isolation structure(s) between the opposite sides of the package and electrically coupled to the second circuit, a first terminal over the first side of the package between the first lead and the third lead, a second terminal over the second side of the package between the second lead and the fourth lead, and an electronic component coupled to the package and electrically coupled to the first terminal, the second terminal, or both the first and second terminals.. ... Freescale Semiconductor Inc

01/01/15 / #20150002226

Semiconductor package having wire bond wall to reduce coupling

A system and method for a package including a wire bond wall to reduce coupling is presented. The package includes a substrate, and a first circuit on the substrate. ... Freescale Semiconductor Inc

01/01/15 / #20150002218

Device and method for compensating for voltage drops

A device that includes at least one current consuming component. The device is characterized by including a compensation circuit adapted to compare between a voltage level at a sensing point within an integrated circuit and between a reference voltage derived from a voltage peak level at the sensing point; and to selectively increase the voltage at the sensing point in response to the comparison. ... Freescale Semiconductor Inc

01/01/15 / #20150002183

Semiconductor device comprising an output driver circuitry, a packaged semiconductor device and associated methods

A semiconductor device comprises a plurality of output pads bondable to an output pin, a plurality of reference pads bondable to a reference pin, and output driver circuitry with a control terminal for receiving a control signal and arranged to drive the plurality of output pads relative to the plurality of reference pads in dependence on the control signal. The output driver circuitry includes driver sections and selection circuitry. ... Freescale Semiconductor Inc

01/01/15 / #20150002116

Dc to dc converter and method to operate a dc to dc converter

A dc to dc converter including a buck converter, a boost converter, and a control unit, wherein the control unit is arranged to calculate an error voltage of the buck converter verr_buck based on a feedback output voltage vout_fb of the dc to dc converter and a reference voltage of the buck converter vref_buck, and wherein the control unit is arranged to calculate an error voltage of the boost converter verr_boost based on the feedback output voltage vout_fb of the dc to dc converter and a reference voltage of the boost converter vref_boost, wherein the reference voltage of the boost converter vref_boost is shifted by an offset voffset as compared to the reference voltage of the buck converter vref_buck.. . ... Freescale Semiconductor Inc








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