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Freescale Semiconductor Inc patents (2016 archive)


Recent patent applications related to Freescale Semiconductor Inc. Freescale Semiconductor Inc is listed as an Agent/Assignee. Note: Freescale Semiconductor Inc may have other listings under different names/spellings. We're not affiliated with Freescale Semiconductor Inc, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "F" | Freescale Semiconductor Inc-related inventors


Carrier frequency offset estimation for wireless communication

Methods and system for carrier frequency offset (cfo) estimation are described. The method includes determining correlation values between a plurality of samples from a received signal and a plurality of reference signals corresponding to a plurality of cfo candidates. ... Freescale Semiconductor Inc

Low interference cellular data commnunication in unlicensed frequency spectrum

A cellular base station communicates data using both the licensed and unlicensed frequency spectrums. For each interval of a set of intervals (such as intervals corresponding to communication of lte frames), the base station first identifies whether signaling is detected on a specified unlicensed frequency channel (ufc). ... Freescale Semiconductor Inc

Systems and methods to dynamically calibrate and adjust gains in a direct conversion receiver

Method embodiments are provided herein for dynamically calibrating and adjusting a direct conversion receiver system. One embodiment includes applying one or more gain control signals to one or more gain elements of a receiver system, where the applying one or more gain control signals results in a gain change to the receiver system; in response to the gain change, determining whether the receiver system exhibits a dc (direct conversion) offset; and in response to a determination that the receiver system exhibits the dc offset, applying one or more dc offset correction control signals to one or more gain elements of the receiver system, where the one or more dc offset correction signals are configured to correct the dc offset.. ... Freescale Semiconductor Inc

Method and apparatus for secure recordation of time of attempted breach of ic package

An integrated circuit (ic) package includes a storage element and a protection component coupled to the storage element. The protection component includes a breach detection component configured to detect an attempted breach of the ic package. ... Freescale Semiconductor Inc

Devices with signal characteristic dependent control circuitry and methods of operation therefor

An embodiment of a device includes a terminal, an active transistor die electrically coupled to the terminal, a detector configured to sense a signal characteristic on the terminal, and control circuitry electrically coupled to the active transistor die and to the detector, wherein the active transistor die, detector, and control circuitry are coupled to a package. The control circuitry may include a control element and a control device. ... Freescale Semiconductor Inc

Semiconductor devices and methods for dead time optimization

Switching control devices and related operating methods are provided. An exemplary electronic device includes a semiconductor die, a driver arrangement on the semiconductor die to generate a switch control output signal based on an input switching command signal, and a timer arrangement on the semiconductor die and coupled to the driver arrangement to measure a time difference between a first change in the command signal and an exhibited response in the switch control signal, which can then be utilized to achieve a desired dead time.. ... Freescale Semiconductor Inc

Apparatus and method for verifying the origin of texture map in graphics pipeline processing

The present application relates to an apparatus for verifying the origin of texture data and a method of operating thereof. The apparatus comprises a frame buffer; at least one texture buffer; a graphics processing pipeline with a fragment shader unit; and a comparator unit. ... Freescale Semiconductor Inc

Apparatus and method for verifying fragment processing related data in graphics pipeline processing

The present application relates to an apparatus for verifying fragment processing related data and a method of operating thereof. The fragment shader unit is coupled to the at least one data buffer. ... Freescale Semiconductor Inc

Apparatus and method for verifying image data comprising mapped texture image data

The present application relates to an apparatus for verifying the integrity of image data comprising mapped texture data is provided and a method of operating thereof. A fragment shader unit is coupled to first and second frame buffers and at least one texture buffer. ... Freescale Semiconductor Inc

Apparatus and method for verifying the integrity of transformed vertex data in graphics pipeline processing

The present application relates to an apparatus for verifying the integrity of transformed vertex data and a method of operating thereof. The apparatus comprises a graphics processing pipeline with a vertex shader unit, a buffer and a comparator unit. ... Freescale Semiconductor Inc

Systems and methods for asymmetric memory access to memory banks within integrated circuit systems

Methods and systems are disclosed for asymmetric memory access to memory banks within integrated circuit (ic) systems. Disclosed embodiments include a memory and a memory controller within an integrated circuit. ... Freescale Semiconductor Inc

Ic module and method of decoding resource access requests

An integrated circuit (ic) module comprising at least one memory mapped resource, at least one port arranged to be coupled to a further ic module, and an address decoding component. Upon receipt of a resource access request by the ic module, the address decoding component is arranged to extract at least one position parameter from an address field of the received resource access request, determine if the at least one position parameter indicates a target resource as residing within the ic module, and if it is determined that the at least one position parameter indicates the target resource as not residing within the ic module, modify the at least one position parameter to represent a change of one position and forward the resource access request with the modified position parameter over the port to the further ic module.. ... Freescale Semiconductor Inc

Integrated circuit including overlapping scan domains

An integrated circuit includes overlapping scan domains, wherein at least one scan domain of the integrated circuit includes some, but not all, of the synchronous logic elements, logic gates, and signal paths of a different scan domain. Each scan domain includes a scan wrapper to receive test patterns generated to test the logic mix for that domain. ... Freescale Semiconductor Inc

Apparatus and method of performing a decimation on a signal for pattern detection

The present application relates to a receiver for performing a decimation on a signal for pattern detection and a method of operating thereof. A frequency-domain decimator component and a pattern detector component arranged at the receiver are provided. ... Freescale Semiconductor Inc

12/22/16 / #20160373102

Rail-to-rail comparator with built-in constant hysteresis

A comparator has an input stage having (i) resistor-coupled super source-follower circuits that convert differential input voltages into differential currents and (ii) hysteresis current-injection circuits that inject hysteresis currents into the differential currents. An output stage processes the differential currents to control the comparator output. ... Freescale Semiconductor Inc

12/22/16 / #20160373085

Rf circuit with multiple-definition rf substrate and conductive material void under a bias line

An rf circuit includes a first dielectric material, a signal line and a bias line over a first surface of the first dielectric material, a conductive layer over a second surface of the first dielectric material, and a second dielectric material over the conductive layer. The first and second dielectric materials have different dielectric constants. ... Freescale Semiconductor Inc

12/22/16 / #20160372575

Complementary gallium nitride integrated circuits and methods of their fabrication

An embodiment of a complementary gan integrated circuit includes a gan layer with a first bandgap. A second layer with a second bandgap is formed on the gan layer, resulting in a 2deg in a contact region between the gan layer and the second layer. ... Freescale Semiconductor Inc

12/22/16 / #20160372339

Semiconducitive catechol group encapsulant adhesion promoter for a packaged electronic device

A packaged electronic device includes a package substrate, an electronic component die mounted to the package substrate, and an encapsulant bonded to a portion of the package substrate at a catechol group adhesion promoted interface that includes benzene rings bonded with the package substrate and the encapsulant.. . ... Freescale Semiconductor Inc

12/22/16 / #20160372197

Ternary content addressable memory (tcam) with magnetic tunnel junction (mtj) devices

A ternary content addressable memory (tcam) cell is coupled to a first word line and a first match line and includes a first data storage portion coupled to a first search line, a second data storage portion coupled to a complement of the first search line, and a resistor divider portion including two resistive elements coupled in series with the first and second data storage portions of the first tcam cell. The first and second data storage portions of the first tcam cell are coupled to a first supply voltage and include two resistive elements coupled in parallel.. ... Freescale Semiconductor Inc

12/22/16 / #20160371182

Shared buffer management for variable length encoded data

A method and apparatus are provided for controlling data flow by storing variable length encoded information bits in a circular buffer in a write operation to a virtual write address comprising a first wrap bit value appended by a current write address within the buffer address range and generating an interrupt alarm if the virtual write address crosses a virtual alarm address comprising a second wrap bit value appended by an alarm address within the buffer address range, where the first and second wrap bit values each toggle between first and second values every time the current write address or alarm address, respectively, wraps around the circular buffer, thereby synchronizing data flow in the circular buffer and/or preventing buffer overflow.. . ... Freescale Semiconductor Inc

12/22/16 / #20160370894

Signal adaptive filtering for touch detection

A signal adaptive filtering technique for recognizing touch and release events as indicated from a measured capacitance signal received from a capacitive touch sensor device in order to improve electromagnetic noise immunity, event detection responses, adaptability to dynamically changing environments, and adaptability to signal sensitivity changes and signal offset over an extended period of time. A capacitive touch sensor system may include one or more capacitive touch sensor devices, each sending a measured capacitance signal that outputs a baseline capacitance signal during a release event, and outputs an increased capacitance signal during a touch event. ... Freescale Semiconductor Inc

12/22/16 / #20160370314

Protected sensor field effect transistors

Protected sensor field effect transistors (sfets). The sfets include a semiconductor substrate, a field effect transistor, and a sense electrode. ... Freescale Semiconductor Inc

12/22/16 / #20160370182

Mems device with common mode rejection structure

A mems device includes a drive spring system coupling a pair of drive masses and a sense spring system coupling a pair of sense masses. The drive spring system includes a constrained stiff beam and flexures interconnecting the pair of drive masses. ... Freescale Semiconductor Inc

12/22/16 / #20160370180

Inertial sensor with couple spring for common mode rejection

A mems device includes a two spring systems coupling a pair of movable masses. Each of the spring systems includes a constrained stiff beam and a pair of flexures, where one flexure is directly coupled to one end of the stiff beam and to one of the movable masses and the other flexure is directly coupled to the opposing end of the stiff beam and to the other movable mass. ... Freescale Semiconductor Inc

12/15/16 / #20160365422

Integrated circuit devices with counter-doped conductive gates

Integrated circuit devices with counter-doped conductive gates. The devices have a semiconductor substrate that has a substrate surface. ... Freescale Semiconductor Inc

12/15/16 / #20160365323

Electronic devices with attached die structures and methods of formation of such devices

An electronic device includes a semiconductor die having a lower surface, a sintered metallic layer underlying the lower surface of the semiconductor die, a conductive layer underlying the sintered metallic layer, and a conductive substrate underlying the conductive layer.. . ... Freescale Semiconductor Inc

12/15/16 / #20160365157

Method and apparatus for testing integrated circuit

An integrated circuit (ic) having a memory for storing data also has a memory built in self-test (mbist) unit coupled to the memory for testing an operation of the memory. A test interface provides test data. ... Freescale Semiconductor Inc

12/15/16 / #20160364343

Systems and methods for data encryption

A method of encrypting data on a memory device includes receiving a memory transaction request at an inline encryption engine coupled between a processing core and switch fabric in a system on a chip (soc). The memory transaction request includes a context component and a data component. ... Freescale Semiconductor Inc

12/15/16 / #20160364289

End-to-end error detection and correction

A technique for providing end-to-end error detection coding between a requesting module and a memory module have been disclosed. A method includes translating a first logical address of a memory request to a physical address. ... Freescale Semiconductor Inc

12/15/16 / #20160364264

Multiple processor core interrupt priority levels

A processor system includes at least two processor cores and an interrupt controller including interrupt priority registers configured for registering interrupt priorities of the respective processor cores. The processor system further includes at least two task timers associated with respective processor cores. ... Freescale Semiconductor Inc

12/15/16 / #20160364079

Capacitance sensor with noise rejection

In a touch interface, a sensor provides an output signal that is a function of a sensed capacitance. The sensor includes a charger for repetitively applying first and second voltages to charge the sensed capacitance to first and second charge values in first and second phases respectively. ... Freescale Semiconductor Inc

12/08/16 / #20160357695

System-level redundancy in pci express equipment

A data processing system is implemented with a backup pci express system, which is able to take over as the primary pci express system for ensuring that the endpoint devices continue to function in a desired manner when the initial primary root complex is no longer functioning correctly. Each of the endpoint devices is coupled to the initial primary root complex and a backup root complex through a multiplexer. ... Freescale Semiconductor Inc

12/08/16 / #20160357284

Capacitance sensor with noise rejection

A sensor for providing an output signal that is a function of a sensed capacitance, in a touch interface for example. The sensor includes a charger for repetitively applying first and second voltages to charge the sensed capacitance to first and second charge values in first and second phases respectively. ... Freescale Semiconductor Inc

12/08/16 / #20160356838

Systems and methods for testing a clamp function for insulated gate bipolar transistors

An integrated circuit includes an insulated gate bipolar transistor (“igbt”), a clamp element coupled to a control gate of the igbt to allow current flow in a first direction when voltage is applied to the control gate of the igbt, and a blocking element coupled to the control gate of the igbt and to the clamp element. The blocking element allows current flow in a second direction when voltage is removed from the control gate of the igbt, the second direction is opposite the first direction. ... Freescale Semiconductor Inc

12/08/16 / #20160356740

Protected sensor field effect transistors

Protected sensor field effect transistors (sfets). The sfets include a semiconductor substrate, a field effect transistor, and a sense electrode. ... Freescale Semiconductor Inc

12/01/16 / #20160352826

Multimedia system and method for streaming synchronization

A multimedia system includes a source device for providing a media stream and a sink device for playing the media stream. The source device encapsulates the media stream into data packets with corresponding timestamps associated with a first wall time, and transmits the data packets to the sink device based on the timestamps and the first wall time. ... Freescale Semiconductor Inc

12/01/16 / #20160352292

Amplfiers and related integrated circuits

Apparatus are provided for amplifier systems and related circuits are provided. An exemplary circuit includes a main amplifier arrangement, first impedance matching circuitry coupled between the output of the main amplifier arrangement and a first output of the circuit, a peaking amplifier arrangement, and second impedance matching circuitry coupled between the output of the peaking amplifier arrangement and a second output of the circuit. ... Freescale Semiconductor Inc

12/01/16 / #20160351522

Package-on-package device and cavity formation by solder removal for package interconnection

In an electronic package that includes an electronic component, a method of forming one or more cavities in the electronic package includes depositing solder material on at least one terminal of the electronic component, encapsulating the electronic component and the solder material in an encapsulant, exposing a top surface of the solder material from the encapsulant, and removing the solder material such that a cavity remains at a location in the encapsulant where the solder material was removed. The solder material can be removed by a hot air solder removal process to yield one or more cavities having a consistent size and shape. ... Freescale Semiconductor Inc

12/01/16 / #20160350536

Boot control systems and methods for vehicles

A hardware security module (hsm) transitions a first signal from a first state to a second state and transitions a second signal from a first state to a second state when a request to change boot code is received. In response to receipt of a boot request, the hsm, when the first signal is in the first state and the second signal is in the first state: does not execute the hash function; and maintains the second signal in the first state. ... Freescale Semiconductor Inc

12/01/16 / #20160350164

Data integrity check within a data processing system

A memory system includes a memory array, control circuitry, and comparator circuitry. The memory array includes a first section having a first plurality of programmed bitcells having a first threshold voltage distribution and a second section having a second plurality of programmed bitcells having a second threshold voltage distribution which has a lower average threshold voltage than the first threshold voltage distribution. ... Freescale Semiconductor Inc

12/01/16 / #20160350162

Detector for high frequency interrupts

High frequency detection of interrupts includes incrementing a count by a first number in response to at least one interrupt. The count is decremented by a second number in response to a clock if the count is greater than zero. ... Freescale Semiconductor Inc

11/24/16 / #20160344820

Method and apparatus for controlling wake events in a data processing system

A system and methods controlling wake events in a data processing system is described. A broadcast wake-up signal staggering order is determined in response to a first wake event. ... Freescale Semiconductor Inc

11/24/16 / #20160344375

Method and apparatus for modulating a clock signal

A clock modulation module and method for generating a modulated clock signal are provided. The clock modulation module comprises a comparator arranged to receive at a first input thereof a waveform signal, the waveform signal comprising a frequency representative of a frequency of a reference timing signal. ... Freescale Semiconductor Inc

11/24/16 / #20160344353

Rf amplifier output circuit device with integrated current path, and methods of manufacture thereof

A device includes multiple ceramic capacitors and a current path structure. A first ceramic capacitor includes a first ceramic material between first and second electrodes. ... Freescale Semiconductor Inc

11/24/16 / #20160343851

Semiconductor devices with vertical field floating rings and methods of fabrication thereof

A semiconductor device includes a semiconductor substrate having a first conductivity type. A gate structure is supported by a surface of the semiconductor substrate, and a current carrying region (e.g., a drain region of an ldmos transistor) is disposed in the semiconductor substrate at the surface. ... Freescale Semiconductor Inc

11/24/16 / #20160343833

Transistor with charge enhanced field plate structure and method

Transistors and methods of fabricating are described herein. These transistors include a field plate (108) and a charged dielectric layer (106) overlapping at least a portion of a gate electrode (102). ... Freescale Semiconductor Inc

11/24/16 / #20160343809

Device with a conductive feature formed over a cavity and method therefor

An embodiment of a device includes a semiconductor substrate, a transistor formed at the first substrate surface, a first conductive feature formed over the first substrate surface and electrically coupled to the transistor, and a second conductive feature covering only a portion of the second substrate surface to define a first conductor-less region. A cavity vertically aligned with the first conductive feature within the first conductor-less region extends into the semiconductor substrate. ... Freescale Semiconductor Inc

11/24/16 / #20160343696

Solar cell powered integrated circuit device and method therefor

A semiconductor device includes a circuitry die and a solar cell die. The circuitry die includes a plurality of interconnect layers on a front side of the circuitry die, a metallization layer on a back side of the circuitry die, and at least one tsv (through substrate via) that makes an electrical connection between a last metal interconnect layer on the front side of the circuitry die and the metallization layer on the back side of the circuitry die. ... Freescale Semiconductor Inc

11/24/16 / #20160343436

Systems and methods for sram with backup non-volatile memory that includes mtj resistive elements

A memory device has an sram that stores a logic state. A first mtj has two terminals. ... Freescale Semiconductor Inc

11/24/16 / #20160342421

Computer systems and methods for executing contexts with autonomous functional units

In a pipelined element configured to execute multiple contexts and including an instruction pipeline and a plurality of context modules each having a register file and a functional unit, a method includes scheduling a first context for execution in the instruction pipeline. The instruction pipeline includes an execution unit having a plurality of functional units. ... Freescale Semiconductor Inc

11/17/16 / #20160337154

Digital front-end channelization device

A digital front end channelization device for one or more carrier signals comprises a per carrier section and a composite section. The composite section may include signal processing units, each of which may include an inverse fourier transform unit for transforming a composite carrier signal into a time domain signal, a sample detection and selection unit for detecting and selecting a peak of the time domain signal, a clipping unit for clipping the time domain composite carrier signal to produce an error signal, a fourier transform unit for transforming the error signal into a frequency domain error signal, a frequency shaping unit for frequency shaping the frequency domain error signal, a summation unit for subtracting the frequency shaped frequency domain error signal from the composite carrier signal, and a phase selection unit for phase adjustment of the resulting signal.. ... Freescale Semiconductor Inc

11/17/16 / #20160337083

Method of offloading cyclic redundancy check on portions of a packet

A method and apparatus are provided for computing a crc value for a packet containing a data stream with a modified data unit data and one or more additional data units extending to the end of the data stream by computing a first crc value from the one or more additional data units, computing a second crc value from the modified data unit, adjusting the second crc value based on a shift length equal to a distance of the one or more additional data units to compute a perspective shifted second crc value by using fixed number of distance lookup table operations, and generating an updated crc value from the first crc value and perspective shifted second crc value, thereby avoiding recalculating a complete crc value based on an entirety of the modified data stream.. . ... Freescale Semiconductor Inc

11/17/16 / #20160336903

Phase correction in a doherty power amplifier

In various embodiments, a semiconductor package includes a carrier amplifier connected to a first output of a power divider, and a first output matching network connected to the carrier amplifier and an output combining node. The first output matching network exhibits a phase delay during operation of the carrier amplifier. ... Freescale Semiconductor Inc

11/17/16 / #20160336785

Bidirectional communication demodulation for wireless charging system

A system and method for demodulating a wireless power signal onto which binary data has been modulated involves processing the wireless power signal with analog circuitry to produce a modified power signal in accordance with the type of demodulation used, periodically capturing digital samples of the modified power signal to produce a series of digital samples, applying, with an mcu, at least two digital filtering algorithms to the digital samples to determine transitions associated with the modulation, and recovering, with the mcu, the binary data as a function of the determined transitions. The demodulator is applicable to bidirectional power transfer capable devices and includes algorithms that can be applied similarly to both ask and fsk demodulations with little or no modification.. ... Freescale Semiconductor Inc

11/17/16 / #20160334819

Voltage regulator with extended minimum to maximum load current ratio

Voltage regulator with extended minimum to maximum current ratio. In some embodiments, a low-dropout (ldo) voltage regulator disposed within a semiconductor package may include an inner loop; and an outer loop coupled to the inner loop, wherein: the inner loop is configured to control a load response of the ldo voltage regulator and to reduce at least one of: a printed circuit board (pcb) effect on the outer loop, a packaging effect on the outer loop, or a parasitic effect on the outer loop; the outer loop is configured to control a voltage at an output of the ldo voltage regulator; the output of the ldo voltage regulator is coupled to an integrated circuit within the semiconductor package; and the pcb, package, and parasitic effects comprise inductive or resistive effects caused by elements disposed outside of the semiconductor package.. ... Freescale Semiconductor Inc

11/17/16 / #20160334472

Corruption detection and smart reset of ferromagnetic structures in magnetic field sensors

A sensor package includes a magnetic field sensor and a corruption detection and reset subsystem. The magnetic field sensor has a magnetic sense element and a ferromagnetic structure characterized by a baseline magnetic state. ... Freescale Semiconductor Inc

11/10/16 / #20160329895

Package-aware state-based leakage power reduction

. . A multi-module integrated circuit (ic) can be configured in different types of packages having different modules enabled or disabled. A module that can be disabled has driven circuitry that is known a priori to have a low-power input vector that places the driven circuitry into a low leakage power state. ... Freescale Semiconductor Inc

11/10/16 / #20160329288

Semiconductor structure with sacrificial anode and method for forming

A packaged semiconductor device is made by forming a conductive pad on an external surface of an integrated circuit device, forming a passivation layer over the conductive pad, removing a portion of the passivation layer over a bond area on the conductive pad, forming a sacrificial anode around a majority of a periphery surrounding the bond area, forming a conductive bond in the bond area, and forming an encapsulating material around the conductive bond and an exposed portion of the sacrificial anode.. . ... Freescale Semiconductor Inc

11/10/16 / #20160328286

Memory reliability using error-correcting code

A method and system are provided for error correction in a memory. Error correction code (ecc) for data stored in a portion of the memory is enabled. ... Freescale Semiconductor Inc

11/10/16 / #20160328164

Method and apparatus for real-time blank page detection in data transmission

A device for reading data from a first memory to a second memory based on real-time blank page detection includes a memory controller for reading a page of data from the first memory, a buffer for buffering a portion of the page data, a blank page pre-detection unit for generating a pre-detection result that indicates whether the page is a blank page based on a pre-determined part of the page data, a data processing unit for processing all of the page data to identify a page type, and a control unit for signaling the memory controller to read the page of data from the first memory and enabling the data processing unit based on the pre-detection result.. . ... Freescale Semiconductor Inc

11/03/16 / #20160321118

Communication system, methods and apparatus for inter-partition communication

A communication system comprises a plurality of software partitions operably coupled to one another via at least one hardware module, wherein each of the plurality of software partitions comprises memory allocated to store data for use solely by the respective software partition, wherein the hardware module is arranged to copy data from a first memory location of a first software partition to second memory location of a second software partition wherein the second memory location is selected by the second software partition.. . ... Freescale Semiconductor Inc

11/03/16 / #20160320258

Multi-sensor system and method of forming same

A method for forming a multi-sensor system includes forming an inertial sensor fixed electrode of an inertial sensor and a movable electrode of a pressure sensor on a first substrate having through silicon vias (tsvs). A second substrate is fusion bonded to a bonding layer on the first substrate. ... Freescale Semiconductor Inc

11/03/16 / #20160320205

Counter based circuit for measuring movement of an object

An apparatus for measuring movement of an object has a quadrature incremental encoder for providing first and second phases of encoder pulses corresponding to incremental displacements of the object. A first counter counts edges of the encoder pulses according to the sense of the displacement. ... Freescale Semiconductor Inc

10/27/16 / #20160316226

Resource efficient video processing via prediction error computational adjustments

. . A video processing system dynamically adjusts video processing prediction error reduction computations in accordance with the amount of motion represented in a set of image data and/or available memory resources to store compressed video data. In at least one embodiment, video processing system adjusts utilization of prediction error computational resources based on the size of a prediction error between a first set of image data, such as current set of image data being processed, and a reference set of image data relative to an amount of motion in a current set of image data. ... Freescale Semiconductor Inc

10/27/16 / #20160316045

Method for coding packet classification key composition rules using variable length commands

A method and apparatus are provided for classifying received network frames (106) by using a key composition rule (134) having a header portion (nf) and multiple variable length key extract commands in a coded order sequence to sequentially generate multiple data fields (field 1-field n) using operands contained in the key extract commands to generate a lookup key (116) by combining multiple data fields in the same coded order sequence as the key extract commands.. . ... Freescale Semiconductor Inc

10/27/16 / #20160316044

Methods and systems to embed valid-field (vf) bits in classification keys for network packet frames

Methods and systems are disclosed to embed valid-field (vf) bits into classification keys for network packet frames. The embedded vf bits allow for extracted data from existing fields associated with frame data to be distinguished from default data used for missing fields where this extracted data and default data has been included within a frame classification key generated for a network packet frame. ... Freescale Semiconductor Inc

10/27/16 / #20160315617

Low-voltage differential signaling (differential signaling) driver circuit and method of enabling and disabling a differential signaling driver circuit

A low-voltage differential signaling (differential signaling) driver circuit (10) comprising enable circuitry for enabling and disabling the differential signaling driver circuit (10) in accordance with an control signal is described. The differential signaling driver circuit (10) comprises: a differential output (12, 13) connected or connectable to a differential signaling receiver circuit via a differential transmission line; current control circuitry (14) for driving a signal current through the differential output (12, 13) in accordance with a driver signal; feedback circuitry (16) for driving the current control circuitry (14) to counteract a difference between a common mode voltage of the differential output (12, 13) and a reference voltage from a reference voltage provider; and the enable circuitry (18). ... Freescale Semiconductor Inc

10/27/16 / #20160314846

Common source architecture for split gate memory

A memory system has an array of split gate non-volatile nvm cells that are in program sectors and the program sectors make up one or more erase sectors. The control gate of cells in a program sector are physically connected. ... Freescale Semiconductor Inc

10/27/16 / #20160314240

Method and apparatus for validating a test pattern

A method and apparatus of validating a test pattern for at-speed testing of at least one integrated circuit, ic, design. The method comprises calculating at least one weighted rise activity, wra, value for at least one region of the ic design based at least partly on rising gate transitions within the at least one region of the ic design when the test pattern is applied thereto, calculating at least one weighted fall activity, wfa, value for the at least one region of the ic design based at least partly on fall gate transitions within the at least one region of the ic design when the test pattern is applied thereto, and validating the test pattern based at least partly on the wra value and the wfa value.. ... Freescale Semiconductor Inc

10/27/16 / #20160314238

Systems and methods for via placement

A method for configuring a via in a semiconductor device includes determining time dependent dielectric breakdown failure rate as a function of distance between the via and a metal line, generating candidate via configurations with different sizes, rotation, and offset values for the via, determining tddb failure rate for the candidate via configurations, and selecting one of the candidate via configurations with an optimal tddb failure rate for the via.. . ... Freescale Semiconductor Inc

10/27/16 / #20160314038

Soft error detection in a memory system

In a memory having a memory array, a method includes reading read data from the memory array, and detecting a first bit error in the read data. The method further includes checking all bitcells in a radial search region about the first bit error. ... Freescale Semiconductor Inc

10/27/16 / #20160314030

Data processing system having messaging

A processing system includes a first processing system element, and a second processing system element configured to communicate with the first processing system. The second processing system element includes a set of messaging queues. ... Freescale Semiconductor Inc

10/27/16 / #20160313994

Data processing system with speculative fetching

A data processing system includes an instruction pipeline, a bus interface unit, and a cache. The instruction pipeline is configured to assert a discard signal when a speculative read request is determined to have been mispredicted. ... Freescale Semiconductor Inc

10/27/16 / #20160311676

Bonded wafer structure having cavities with low pressure and method for forming

A multi-wafer structure is formed by forming a cavity in a cap wafer and forming a first seal material around the cavity. A collapsible standoff structure is formed around the cavity. ... Freescale Semiconductor Inc

10/20/16 / #20160308537

Apparatus and method for generating a temperature-dependent control signal

A current-to-voltage converter receives a current which varies with temperature according to a selected one of two or more temperature coefficient factors and converts it to a temperature-dependent voltage to be used as a control signal to a varactor in a voltage controlled oscillator, vco, to compensate for temperature-induced frequency drift in the vco. A feedback arrangement with hysteresis is provided for controlling the selection of the temperature coefficient factor and operates by comparing the temperature-dependent voltage with a reference voltage. ... Freescale Semiconductor Inc

10/20/16 / #20160308497

Low drop out voltage regulator and method therefor

A circuit and method for regulating an output voltage are provided. The circuit includes a fully differential first stage amplifier, a second stage amplifier, and a power output driver transistor. ... Freescale Semiconductor Inc

10/20/16 / #20160308442

Voltage level shifter

A level shifter in a primary voltage domain has a control module receiving an input signal from a secondary voltage domain for controlling operation of the level shifter. The control module includes a complementary pair of transistors and a first native transistor connected in a series current conduction path in the primary voltage domain. ... Freescale Semiconductor Inc

10/20/16 / #20160308010

Semiconductor devices with a thermally conductive layer

An embodiment of a semiconductor device includes a semiconductor substrate that includes a host substrate and an upper surface, an active area, a substrate opening in the semiconductor substrate that is partially defined by a recessed surface, and a thermally conductive layer disposed over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate within the active area. A method for fabricating the semiconductor device includes defining an active area, forming a gate electrode over a channel in the active area, forming a source electrode and a drain electrode in the active area on opposite sides of the gate electrode, etching a substrate opening in the semiconductor substrate that is partially defined by the recessed surface, and depositing a thermally conductive layer over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate over the channel.. ... Freescale Semiconductor Inc

10/20/16 / #20160307791

Method of forming inter-level dielectric structures on semiconductor devices

A semiconductor device and a method for making the semiconductor device are provided. The method of making the semiconductor device may include patterning a layer for a first conductor and a second conductor, plating patterned portions of the layer to form the first conductor and the second conductor, removing patterned material to form an air gap between the first conductor and the second conductor, applying a self-supporting film on top of the first conductor and the second conductor to enclose the air gap, and reacting the self-supporting film causing the self-supporting film to be substantially non-conductive.. ... Freescale Semiconductor Inc

10/20/16 / #20160307780

Structure and method to minimize warpage of packaged semiconductor devices

A packaged semiconductor device includes a substrate, an electronic device coupled to the substrate, encapsulant including a first major surface surrounding the electronic device, and an oxygen barrier layer within fifty percent of a thickness of the encapsulant from a second major surface of the encapsulant. The oxygen barrier covers at least a portion of an area of the second major surface of the encapsulant to help reduce or eliminate warping of the encapsulant and/or the substrate of the packaged semiconductor device due to oxidation. ... Freescale Semiconductor Inc

10/20/16 / #20160307346

Display controller, heads-up image display system and method thereof

The present application relates to a display controller and display system and a method of operating thereof. At a filtering stage display image data are generated on the basis of received pixel-mapped image data. ... Freescale Semiconductor Inc

10/20/16 / #20160306913

Method and apparatus for system design verification

An apparatus for system design verification has a test case module for compiling a test case in a scripting language (such as tcl) and a testbench including the design under test and operating with a hardware descriptor language (such as systemverilog). A stimulus generated by the test case module is applied to the testbench through an interface gasket based on ‘c’.. ... Freescale Semiconductor Inc

10/20/16 / #20160306593

Method for reading data from nonvolatile memory

A memory system capable of running a variety of different read retry sequences includes a memory controller that has a boot rom with stored code for executing a read retry sequence. A non-volatile memory device such as a nand flash includes a read retry register and receives command instructions including a read retry instruction from the memory controller and in response provides read data. ... Freescale Semiconductor Inc

10/20/16 / #20160306007

Electric field sensor, system, and method for programming electronic devices on a wafer

An electric field sensor includes sense and reference cells. The sense cell produces a resistance that varies relative to an intensity of an electric field, and the reference cell produces a resistance that is invariable relative to the intensity of the electric field. ... Freescale Semiconductor Inc

10/13/16 / #20160301403

Filtered sampling circuit and a method of controlling a filtered sampling circuit

A circuit comprises an amplifier, a first switch arranged between an amplifier input and an amplifier output, a first capacitor, a first resistor, a second switch, a third switch, a first converter coupled to the first amplifier output, a register storing a last digital value, a second converter converting the stored last digital value into a corresponding voltage value, and a control circuit. The control circuit charges the first capacitor to the corresponding voltage value by coupling a second converter output to a second capacitor terminal and switching on the first switch, or by coupling the second converter output to the first capacitor terminal and switching on the third switch; switches on the first switch and the second switch for providing the input voltage signal to the first capacitor; and switches on the third switch for determining a subsequent digital value of the converted output amplifier signal.. ... Freescale Semiconductor Inc

10/13/16 / #20160301392

Flip-flop structure

A flip-flop structure comprising a master latch and a slave latch. An output of an input stage of the master latch is coupled to the output of the master latch. ... Freescale Semiconductor Inc

10/13/16 / #20160300919

Method of forming split gate memory with improved reliability

A first doped region extends from a top surface of a substrate to a first depth. An implant into the first doped region forms a second doped region of a second conductivity type. ... Freescale Semiconductor Inc

10/13/16 / #20160300828

Esd protection device

An electrostatic discharge protection device includes a buried layer having a plurality of heavily doped regions of a first conductivity type and a laterally diffused region between adjacent heavily doped regions, a semiconductor region over the buried layer, and a first well of the first conductivity type extending from a surface of the semiconductor region to a heavily doped region. The device includes a first transistor in the semiconductor region having an emitter coupled to the first terminal, and a second transistor in the semiconductor region having an emitter coupled to the second terminal. ... Freescale Semiconductor Inc

10/13/16 / #20160300599

Mismatch-compensated sense amplifier for highly scaled technology

Circuits and methods are provided for compensating an offset voltage measured between a first transistor and a second transistor of a sense amplifier circuit that is configured to sense a bit line signal during a sensing phase. The first transistor and the second transistor are cross-coupled. ... Freescale Semiconductor Inc

10/13/16 / #20160299859

Apparatus and method for external access to core resources of a processor, semiconductor systems development tool comprising the apparatus, and computer program product and non-transitory computer-readable storage medium associated with the method

There is disclosed an apparatus for external access to core resources (211,212) of a processor (2) comprising a processing core (21), a shared memory (22), and a multiple paths direct memory access, dma, controller (23). Access to core critical resources can be performed while the core is executing an application program. ... Freescale Semiconductor Inc

10/13/16 / #20160299828

Code injection for conditional breakpoints

An apparatus for debugging operational code of a target program comprises a memory storing the operational code and a set of instructions representing a debugger program for debugging the operational code. A microprocessor is configured to execute the operational code and the debugger program. ... Freescale Semiconductor Inc

10/13/16 / #20160299824

System and method for providing diagnostic information

A data processing system has a system bus, an analog-to-digital converter (adc), a signal processor, a memory, compression and packing units, and a debug unit. The adc samples a baseband signal, and provides a digitized signal representative of the baseband signal the system bus. ... Freescale Semiconductor Inc

10/13/16 / #20160297673

Device with vertically integrated sensors and method of fabrication

A device includes vertically and laterally spaced sensors that sense different physical stimuli. Fabrication of the device entails forming a device structure having a first and second wafer layers with a signal routing layer interposed between them. ... Freescale Semiconductor Inc

10/06/16 / #20160295352

Multiple connection management for bluetooth low energy devices

. . Methods and systems are disclosed for multiple connection management for bluetooth (bt) devices, and more particularly for bt low energy (ble) devices, to multiple different bonded bt peer devices. A bt device database within a non-volatile memory (nvm) stores identification and persistent information for each bonded bt peer device. ... Freescale Semiconductor Inc

10/06/16 / #20160294378

Transmission gate circuit

A transmission gate circuit includes a pass gate and a control circuit and provides high voltage protection to a flash memory in a characterization mode and a low resistive path with true open-drain functionality in a normal mode. A native nmosfet in series with the pass gate provides overvoltage protection for additional circuitry. ... Freescale Semiconductor Inc

10/06/16 / #20160294330

Phase shift and attenuation circuits for use with multiple-path amplifiers

Embodiments of circuits for use with an amplifier that includes multiple amplifier paths include a first circuit and a second circuit in parallel with the first circuit. The first circuit includes a first input coupled to a first power divider output, a first output coupled to a first amplifier path of the multiple amplifier paths, and a first adjustable phase shifter and a first attenuator series coupled between the first input and the first output. ... Freescale Semiconductor Inc

10/06/16 / #20160294195

Power receiver for wireless charging system

A power receiver for a wireless power transmission system that includes a power transmitter has input circuitry that converts power received from the power transmitter into an input signal. A regulator regulates the input signal to generate a regulated output signal based on a current reference signal and a voltage reference signal, and a load receives the regulated output signal. ... Freescale Semiconductor Inc

10/06/16 / #20160293568

Methods for forming semiconductor device packages

A semiconductor device package that incorporates a combination of ceramic, organic, and metallic materials that are coupled using silver is provided. The silver is applied in the form of fine particles under pressure and a low temperature. ... Freescale Semiconductor Inc

10/06/16 / #20160293551

Integrated electronic package and stacked assembly thereof

A wafer level packaging method entails providing electronic devices and providing a platform structure having cavities extending through the platform structure. The platform structure is mounted to a temporary support. ... Freescale Semiconductor Inc

10/06/16 / #20160293526

Lead frame with deflecting tie bar for ic package

A packaged integrated circuit (ic) device having a heatsink mounted onto an ic die, itself mounted onto a die pad, is assembled using a lead frame having tie bars that deflect during an encapsulation phase of the device assembly, which enables the die pad, the die, and the heatsink to move relative to the lead frame support structure when compressive force is applied by the molding tool. This movement results in negligible relative displacement between the heatsink and the die during encapsulation, which reduces the probability of physical damage to the die. ... Freescale Semiconductor Inc

10/06/16 / #20160293508

Semiconductor device packages

A semiconductor device package that incorporates a combination of ceramic, organic, and metallic materials that are coupled using silver is provided. The silver is applied in the form of fine particles under pressure and a low temperature. ... Freescale Semiconductor Inc

10/06/16 / #20160292027

Systems and methods for managing task watchdog status register entries

The present disclosure provides system and method embodiments for a status register comprising a plurality of bits, where each of the plurality of bits of the status register is associated with one of a plurality of entities. A trigger mechanism is configured to write a trigger data pattern to the status register, where the trigger data pattern comprises a first state value for each of the plurality of bits of the status register. ... Freescale Semiconductor Inc

10/06/16 / #20160292014

Method, apparatus, and system for unambiguous parameter sampling in a heterogeneous multi-core or multi-threaded processor environment

Apparatuses, methods, and systems are configured to perform unambiguous parameter sampling in a heterogeneous multi-core or multi-threaded environment by masking one or more thread requests; and, in response to bus activity ceasing for the one or more masked thread requests and completing any routine being processed for the one or more masked threads, processing a command by executing at least one of a command routine or a command thread, wherein the command routine or the command thread reads the parameter using thread atomicity with deterministic synchronization. One or more thread requests may be selected for masking by monitoring thread activity for each of a plurality of threads.. ... Freescale Semiconductor Inc

10/06/16 / #20160290253

Ignition control device having an electronic fuel injection (efi) mode and a capacitive discharge ignition (cdi) mode

An ignition control device having an electronic fuel injection mode and a capacitive discharge ignition mode is described. The ignition control device comprises: an output for providing an output voltage, connected or connectable to a load, the load being a fuel injection actuator of an efi system or an ignition capacitor of a cdi system; and a driver unit connected to the output, for driving the output voltage from a low level a high level and from the high level to the low level in dependence on an input signal, each transition of the output voltage from the low level to the high level having a low-to-high transition time which is longer for the cdi mode than for the efi mode.. ... Freescale Semiconductor Inc

09/29/16 / #20160285658

Demodulating frequency shift keying modulated input signal

A method of demodulating an fsk modulated input signal whose frequency varies between first and second frequencies. The input signal is delayed by a plurality of cycles, providing a second signal. ... Freescale Semiconductor Inc

09/29/16 / #20160285420

Rf amplifier module and methods of manufacture thereof

An amplifier module includes a module substrate. Conductive interconnect structures and an amplifier device are coupled to a top surface of the module substrate. ... Freescale Semiconductor Inc

09/29/16 / #20160285418

Rf amplifier with conductor-less region underlying filter circuit inductor, and methods of manufacture thereof

An amplifier includes a semiconductor substrate. A first conductive feature partially covers the bottom substrate surface to define a conductor-less region of the bottom substrate surface. ... Freescale Semiconductor Inc

09/29/16 / #20160285261

Esd protection device

An electrostatic discharge (esd) device is disclosed having two pnp transistors. During a high-voltage esd event a parasitic npn transistor couples to one of the two pnp transistors to provide esd protection.. ... Freescale Semiconductor Inc

09/29/16 / #20160284967

Pulse generator for energizing an ultrasonic transducer, a method of operating the pulse generator and a ultrasonic distance sensing system

The present application relates to a pulse generator for energizing an ultrasonic transducer, a method of operating thereof and an ultrasonic distance sensing system comprising the pulse generator. The pulse generator is arranged to generate an excitation pulse sequence comprising a first number of pulses; to generate a cancellation pulse sequence comprising at least a fractional pulse, wherein the cancellation pulse sequence has a phase shift of about 180° in relation to the excitation pulse sequence; and to output at an output of the generator the excitation pulse sequence and the cancellation pulse sequence forming an energizing pulse sequence to the ultrasonic transducer.. ... Freescale Semiconductor Inc

09/29/16 / #20160284841

Composite semiconductor device with different channel widths

A device includes a semiconductor substrate, a first constituent transistor including a first plurality of transistor structures in the semiconductor substrate connected in parallel with one another, and a second constituent transistor including a second plurality of transistor structures in the semiconductor substrate connected in parallel with one another. The first and second constituent transistors are disposed laterally adjacent to one another and connected in parallel with one another. ... Freescale Semiconductor Inc

09/29/16 / #20160284838

Trench mosfet shield poly contact

A recess is formed at a semiconductor layer of a device to define a plurality of mesas. An active trench portion of the recess residing between adjacent mesas. ... Freescale Semiconductor Inc

09/29/16 / #20160283751

Data processing system with temperature monitoring for security

A processing system includes a processor and a temperature security module coupled to provide a temperature tamper signal to the processor. The temperature security module includes a shelf mode trim value, an operating mode trim value, and a programmable temperature trim value. ... Freescale Semiconductor Inc

09/29/16 / #20160283642

Method for verifying design rule checks

A method for design rule verification is provided. The method comprises: providing a design rule check (drc) deck based on a design rule manual (drm) having a plurality of design rules; providing a plurality of primitive objects; creating a plurality of collection objects, each collection object using one or more primitive objects; using the plurality of collection objects, creating a plurality of drm test cases; assigning names to each of the plurality of drm test cases, each of the names based on a rule name of the plurality of design rules and on an expected pass or fail indication; and using the plurality of named drm test cases to verify the drc deck.. ... Freescale Semiconductor Inc

09/29/16 / #20160283432

Protocol-tolerant communications in controller area networks

Systems and methods for protocol-tolerant communications in a controller area network (can) are described. In some embodiments, a method may include receiving a frame at a network node; identifying, by the network node, a bit in a selected field of the frame; and determining, by the network node, that the frame follows a second format despite the bit indicating that the frame follows a first format. ... Freescale Semiconductor Inc

09/29/16 / #20160283314

Multi-channel network-on-a-chip

In at least one embodiment of the disclosure, a method includes detecting an error in a local memory shared by redundant computing modules executing in delayed lockstep. The method includes pausing execution in the redundant computing modules and handling the error of the local memory. ... Freescale Semiconductor Inc

09/29/16 / #20160283313

System on chip and method of updating program code on a system on chip

In a system on chip soc, a memory control unit connected between the memory unit and the processing unit controls access to the memory unit. An update request received or generated by the processing unit triggers an update operation which comprises appending an update enabling record to a sequence of update records in the log region, writing new program code to the memory unit, and appending an update completion record to a sequence of update records. ... Freescale Semiconductor Inc

09/29/16 / #20160283233

Computer systems and methods for context switching

A data processing system includes a plurality of contexts, a current context indicator configured to indicate a context of the plurality of contexts as the current context, an instruction queue configured to store fetched instructions for execution using in the current context, and a scheduler coupled to the context selector. The scheduler is configured to, in response to a context switch event, save a current context instruction state from the instruction queue to the corresponding instruction buffer of the current context, select a next context of the plurality of contexts, restore a context instruction state from the corresponding instruction buffer of the next context to the instruction queue, and set the current context indicator to indicate the selected next context as the current context.. ... Freescale Semiconductor Inc

09/29/16 / #20160282896

State-based undervoltage hysteresis

A method of undervoltage detection includes detecting a voltage level for a power supply of a system, placing the system in an undervoltage state if the voltage level is below an undervoltage threshold, activating a load of the system at a first power level if the detected voltage level exceeds a first activation threshold and if the system resides in the undervoltage state, and activating the load at a second power level if the detected voltage level exceeds a second activation threshold.. . ... Freescale Semiconductor Inc

09/22/16 / #20160276475

Methods of manufacturing trench semiconductor devices with edge termination structures

. . Embodiments of semiconductor devices and methods of their formation include providing a semiconductor substrate having a top surface, a bottom surface, an active region, and an edge region, and forming a gate structure in a first trench in the active region of the semiconductor substrate. A termination structure is formed in a second trench in the edge region of the semiconductor substrate. ... Freescale Semiconductor Inc

09/22/16 / #20160276460

Esd protection structure and method of fabrication thereof

An esd protection structure comprising a first semiconductor region of a first doping type, a second semiconductor region of the first doping type, a semiconductor structure of a second doping type opposite to the first doping type formed to provide lateral isolation between the first and second semiconductor regions of the first doping type, and a first contact region of the second doping type formed within a surface of the second semiconductor region. A thyristor structure is formed within the esd protection structure comprising the first contact region of the second doping type, the second semiconductor region of the first doping type, the semiconductor structure of the second doping type, and the first semiconductor region of the first doping type. ... Freescale Semiconductor Inc

09/22/16 / #20160276332

Esd protection structure and method of fabrication thereof

An esd protection structure formed within an isolation trench and comprising a first peripheral semiconductor region of a first doping type, a second semiconductor region of the first doping type, and a semiconductor structure of a second doping type opposite to the first doping type formed to provide lateral isolation between the semiconductor regions of the first doping type and isolation between the further semiconductor region of the first doping type and the isolation trench. The semiconductor structure of the second doping type is formed such that no semiconductor region of the second doping type is formed between a peripheral side of the first semiconductor region of the first doping type and a wall of the isolation trench, and no semiconductor region of the first doping type is in contact with the isolation trench other than the first semiconductor region of the first doping type.. ... Freescale Semiconductor Inc

09/22/16 / #20160276231

Optical programming of electronic devices on a wafer

A system for programming integrated circuit (ic) dies formed on a wafer includes an optical transmitter that outputs a digital test program as an optical signal. At least one optical sensor (e.g., photodiode) is formed with the ic dies on the wafer. ... Freescale Semiconductor Inc

09/22/16 / #20160276029

Non-volatile memory using bi-directional resistive elements

A memory cell includes a first bidirectional resistive memory element (brme), and a second brme, a first storage node, and a second storage node. A resistive memory write to the cell includes placing the first brme and the second brme in complementary resistive states indicative of the value being written. ... Freescale Semiconductor Inc

09/22/16 / #20160276004

Magnetic field programming of electronic devices on a wafer

A system for programming integrated circuit (ic) dies formed on a wafer includes a magnetic field transmitter that outputs a digital test program as a magnetic signal. At least one digital magnetic sensor (e.g., hall effect sensor) is formed with the ic dies on the wafer. ... Freescale Semiconductor Inc

09/22/16 / #20160274188

Wafer-level magnetic field programming of magnetic field sensors

A system for programming magnetic field sensors formed on a wafer includes a magnetic field transmitter that outputs a digital test program as a magnetic signal. At least one digital magnetic sensor (e.g., magnetoresistive sensor) is formed with the magnetic field sensors on the wafer and is distinct from the magnetic field sensors. ... Freescale Semiconductor Inc

09/22/16 / #20160274180

Embedded stress test circuitry and method of operating thereof

The present application relates to an embedded stress test circuitry for being formed on a substrate together with an operating circuit, both forming an electronic circuit. The embedded stress test circuitry comprises a test controller, a stress voltage regulator, which is controllably coupled to the test controller and arranged to generate a stress voltage signal in accordance with a stress voltage profile, a sensor, which is coupled to a component of the operating circuit and a storage, which is coupled to the test controller for storing the stress voltage profile.. ... Freescale Semiconductor Inc

09/22/16 / #20160274141

Micro-electro-mechanical acceleration sensor device

A mems acceleration device for measurement of the acceleration along three axes. The device includes capacitors, which capacitance changes under the influence of an acceleration acting upon the device. ... Freescale Semiconductor Inc

09/22/16 / #20160272482

Fabrication method for suspended mems device

A microelectromechanical systems (mems) die includes a substrate having a first substrate layer, a second substrate layer, and an insulator layer interposed between the first and second substrate layers. A structure is formed in the first substrate layer and includes a platform upon which a mems device resides. ... Freescale Semiconductor Inc

09/15/16 / #20160269063

Radio frequency receiver capable of determining a noise estimate in case of received power unbalanced antennas and method of operating thereof

The present application suggests a receiver and a method of operating thereof for determining a noise estimate based on a radio frequency signal from an interference source over different propagation paths through a plurality of antennas. A covariance matrix estimator coupled through separate processing paths to a respective one of the plurality of antennas is arranged to determine an estimate of a covariance matrix based on the received radio frequency signal. ... Freescale Semiconductor Inc

09/15/16 / #20160269041

Digital-to-analog converter circuit

A digital to analog converter including a current source for providing a master current, a first sub digital to analog converter coupled to the current source which generates a plurality of currents, and a second sub digital to analog converter coupled to at least one of the plurality of currents from the first sub digital to analog converter which generates a second plurality of currents. The digital to analog converter also includes an overlap adjustment circuit coupled with the second sub digital to analog converter which adds current. ... Freescale Semiconductor Inc

09/15/16 / #20160269022

Adjustable losses of bond wire arrangement

The invention provides a bond wire arrangement comprising a signal bond wire (1) for operably connecting a first electronic device (6) to a second electronic device (8), and a control bond wire (2) being arranged alongside the signal bond wire at a distance so as to have a magnetic coupling with the signal bond wire (1), and having a first end (11) coupled to ground, and a second end (12) coupled to ground via a resistive element (14). The proposed solution allows the control of the q factor (losses) of wire bond inductors during assembly phase, which will save time and reduce overall design cycle as compared to known methods.. ... Freescale Semiconductor Inc

09/15/16 / #20160268842

Free-resonance analog ping for wireless power transmission

A wireless transmitter wirelessly charges/powers a wireless receiver. The transmitter performs an analog ping to tentatively detect a device. ... Freescale Semiconductor Inc

09/15/16 / #20160268169

Method of forming supra low threshold devices

A semiconductor device and a method for making the semiconductor device are provided. The semiconductor device includes a non-volatile memory cell having a gate dielectric and formed in a non-volatile memory well region; a first transistor type formed using a first gate oxide and formed in a first transistor well region; a second transistor type formed using a second gate oxide and formed in a second transistor well region; and a third transistor type formed using a third gate oxide and formed in a third transistor well region. ... Freescale Semiconductor Inc

09/15/16 / #20160267979

Method for integrating non-volatile memory cells with static random access memory cells and logic transistors

A method of making a semiconductor device is described. The method comprises depositing a first polysilicon layer in a non-volatile memory (nvm) region and a logic region of a substrate. ... Freescale Semiconductor Inc

09/15/16 / #20160266239

Radar system and method with saturation detection and reset

The embodiments described herein provide a radar device and method that can provide improved sensitivity. In general, the embodiments described herein provide a saturation detector and reset mechanism coupled to a radar receiver. ... Freescale Semiconductor Inc

09/15/16 / #20160266238

Signal processing unit and method for searching for peaks in a two-dimensional matrix

A signal processing unit and a method for searching for peaks in a two-dimensional matrix of numbers are described. The matrix is analyzed row by row and then column by column. ... Freescale Semiconductor Inc

09/15/16 / #20160266180

Low jitter pulse output for power meter

There is provided an energy consumption meter device (1) comprising the processor (8) arranged to receive input data from the sampling unit. The processor calculates at a calculation step [n] an energy contribution value using Δe using a sampled voltage value and a sampled current value. ... Freescale Semiconductor Inc

09/08/16 / #20160259001

Semiconductor storage device having synchronous and asynchronous modes

A method for performing scan testing using a scan chain having a plurality of storage elements is described. During a capture phase, each storage element of the scan chain stores data from a first data input of the storage element synchronously to a clock signal. ... Freescale Semiconductor Inc

09/01/16 / #20160254380

Method of manufacturing a device having a shield plate dopant region

Forming a transistor transistor includes forming a surface region, a gate, a source dopant region, a drain dopant region, a drift dopant region, a set of electrically conductive shield plates, and a shield plate dopant region. A sidewall of the gate aligns with a drain side boundary of the surface region. ... Freescale Semiconductor Inc

08/25/16 / #20160248430

Phase locked loop having fractional vco modulation

. . An integrated circuit comprises a dual port modulator and a voltage controlled oscillator (vco). The dual port modulator has a first input for receiving a transmitter modulation signal, a first output for providing a fractional portion of a high port modulation signal, a second output for providing a integer portion of the high port modulation signal, and a third output for providing a low port modulation signal. ... Freescale Semiconductor Inc

08/25/16 / #20160247916

Bidirectional power transistor with shallow body trench

A bi-directional trench field effect power transistor. A layer stack extends over the top surface of the substrate, in which vertical trenches are present. ... Freescale Semiconductor Inc

08/25/16 / #20160247744

Heat spreader and method for forming

The present disclosure provides embodiments for a semiconductor structure including a heat spreader that includes a graphene grid having a first major surface and a second major surface opposite the first major surface. The graphene grid has a plurality of holes, each hole having a first opening in the first major surface and a second opening in the second major surface. ... Freescale Semiconductor Inc

08/25/16 / #20160247738

Integrated circuit carrier coating

A device includes an integrated circuit (ic) carrier for a semiconductor device, and a coating on the ic carrier. In the presence of an electrical field or a magnetic field, the coating includes a first functional group that attracts anions and a second functional group that attracts cations.. ... Freescale Semiconductor Inc

08/25/16 / #20160247574

Method and apparatus for stressing a non-volatile memory

A method and memory for stressing a plurality of non-volatile memory cells is provided. The method includes entering a memory cell stressing mode and providing one or more erase stress pulses to the plurality of non-volatile memory cells; determining that a threshold voltage of at least a subset of the plurality of non-volatile memory cells has a first relationship that is either greater than or less than a first predetermined voltage; providing one or more program stress pulses to the plurality of memory cells; and determining that the threshold voltage of at least a subset of the plurality of memory cells has a second relationship to a second predetermined voltage that is different than the first relationship.. ... Freescale Semiconductor Inc

08/25/16 / #20160246664

Micro controller unit including an error indicator module

A micro controller unit including an error indicator hardware module, the error indicator module being arranged to respond to event signals representative of internal and external fault and error events perturbing the micro controller unit function by registering in non-volatile memory a record of the nature of each of the events, wherein the record of the events is inaccessible to alteration.. . ... Freescale Semiconductor Inc

08/25/16 / #20160246539

Memory device with combined non-volatile memory (nvm) and volatile memory

The present disclosure provides embodiments for methods and memory devices. One embodiment of a memory device includes a first volatile memory cell having a first volatile access transistor with a current electrode coupled with a first volatile bit line; a first non-volatile memory cell having a first non-volatile access transistor with a current electrode coupled with a first non-volatile bit line; and a transfer circuit coupled between the first volatile bit line and the first non-volatile bit line. ... Freescale Semiconductor Inc

08/25/16 / #20160246358

A selectively powered layered network and a method thereof

A layered network (10; 11; 12) to provide offload of data in a communication processor (100; 110; 120). The layered network (10; 11; 12) includes a first set (s1) of network elements at a first layer (l1) and a second set (s2) of one or more network elements at a second layer (l2). ... Freescale Semiconductor Inc

08/18/16 / #20160242103

Cell search in a wireless communication network

The present application relates to an orthogonal frequency division multiplexing (ofdm) receiver and a method of operating the receiver for performing a cell search. A coarse correlator block is provided to detect one cell out of a by plurality of wireless communication cells by determining first correlation metric values by applying a partial correlation comprising part-wise correlating sample data with each one of a first set of phase-rotated reference sequences and non-coherent combining. ... Freescale Semiconductor Inc

08/18/16 / #20160241492

Switch point having look-ahead bypass

A network having a plurality of switch points, each switch point having both a main multi-stage pipeline and a look-ahead pipeline between input ports and output ports of the plurality of switch points is described. The look-ahead pipeline has fewer pipeline stages than the main multi-stage pipeline. ... Freescale Semiconductor Inc

08/18/16 / #20160241435

Apparatus for optimising a configuration of a communications network device

Apparatus (110) for configuring network equipment or devices (101a-101n) during runtime is particularly applicable to network equipment based on qoriq (trade mark) communication platforms for dpaa (data path acceleration architecture) optimization purposes and provides a way maintaining an optimal configuration which can change over time acccording to real traffic conditions. The invention may be implemented with any kind of adaptation algorithm for targeting different dpaa features. ... Freescale Semiconductor Inc

08/18/16 / #20160240488

Semiconductor device with an isolation structure coupled to a cover of the semiconductor device

A system and method for packaging a semiconductor device that includes a structure to reduce electromagnetic coupling are presented. The semiconductor device is formed on a substrate. ... Freescale Semiconductor Inc

08/18/16 / #20160239525

Method and apparatus for coding a user defined constant into a key composition rule using variable length command

A method and apparatus are provided for classifying received network frames (234) by extracting frame header data (e.g., n-tuple) which is combined with a key insert value (e.g., embedded prefix value “op01, op02, . . ... Freescale Semiconductor Inc

08/18/16 / #20160239362

Fault detection apparatus and method

Apparatus suitable for detecting a fault in a processor comprises a monitor which receives input and output signals from the processor and generates a hash index key which is used to access entries in a hash table. The entries may include actions such as setting a timer so that the response of an output to a change of state of an input may be confirmed as valid within a specified time interval.. ... Freescale Semiconductor Inc

08/18/16 / #20160239038

Supply-side voltage regulator

A voltage regulator generates an output voltage that is a designed voltage level below the supply voltage. A reference voltage generator generates a reference voltage between ground and supply voltages. ... Freescale Semiconductor Inc

08/18/16 / #20160238658

Wetting current diagnostics

A circuit for diagnostic testing includes a current source coupled to a power source and configured to provide wetting current along a path to a load control switch, a current sensor connected in series with the current source along the path, the current sensor being configured to generate a current sensor signal indicative of a current level along the path, a voltage measurement unit having an input terminal coupled to a node along the path through which the wetting current flows to reach the load control switch, the voltage measurement unit being configured to detect a state of the load control switch based on a voltage at the node, and a controller coupled to the current sensor and the voltage measurement unit, the controller being configured to determine a wetting current diagnostic condition in accordance with the current level and the detected state.. . ... Freescale Semiconductor Inc

08/18/16 / #20160238655

Enhanced status monitor for scan testing

An integrated circuit receives test-control information that is phase encoded on a scan clock used for testing a scan chain within the ic. The phase encoding does not affect the normal use of the scan clock and scan test chain and allows additional test-related data such as power supply, clock, and additional global and specialized status data to be collected by a secondary test data storage system such as a shift register. ... Freescale Semiconductor Inc

08/18/16 / #20160238654

Systems and methods for concurrently testing master and slave devices in a system on a chip

An integrated circuit includes a substrate, a master system on the substrate, a slave system on the substrate that is coupled to communicate with the master system, a first clock signal coupled to the master system, and a second clock signal coupled to the slave system. The master system is configured to isolate the slave system from the master system while a first test of the master system is conducted in parallel with a second test of the slave system. ... Freescale Semiconductor Inc

08/18/16 / #20160238580

Systems and methods for detecting change in species in an environment

A method for determining the concentration of an analyte is provided. The method comprises: applying an alternating voltage to a first electrode and a second electrode of a sensor in the presence of the analyte; measuring a first capacitance of the sensor in presence of the analyte; irradiating the analyte for a predetermined time period at a discrete frequency within a predetermined frequency range; measuring a second capacitance of the sensor at an end of the predetermined time period; determining a difference between the first and second capacitances; and determining the concentration of the analyte based on the difference. ... Freescale Semiconductor Inc

08/18/16 / #20160238551

Systems and methods for detecting change in species in an environment

The present disclosure provides embodiments for diodes, devices, and methods for polar vapor sensing. One embodiment of a diode includes a first electrode to which an electric field is applied; a second electrode to which the electric field is applied; and a vapor gap region between the first electrode and the second electrode. ... Freescale Semiconductor Inc

08/11/16 / #20160234117

Can fd end-of-frame detector, can bit stream processing device, method for detecting the end of a can fd frame, and method of operating a can bit stream processor

A can fd frame comprises one or more portions provided at a normal bit rate an end-of-frame field consisting of a succession of at least seven recessive bits. A method for detecting the end-of-frame of a can fd frame in an input bit stream entails providing a recessive bit count; defining a stretched bit transmission time longer than the bit transmission time associated with the high data rate; stretching the bit transmission time of each dominant bit succeeding a recessive bit in the input bit stream to the stretched bit transmission time to generate a conditioned input bit stream; sampling the conditioned input bit stream at a bit counter rate to generate a sampled bit stream; resetting the recessive bit count in response to each dominant bit in the sampled bit stream; and incrementing the recessive bit count in response to each recessive bit in the sampled bit stream.. ... Freescale Semiconductor Inc

08/11/16 / #20160234038

A transceiver circuit and method for controller area networks

A transceiver circuit for operating in a controller area network (can), having a can bus network and a control unit, that supports a flexible data rate (can fd), is described. The transceiver circuit comprises: a transmit can path and a receive can path; an input node on the transmit can path; a detection module operably coupled to the input node on the transmit can path and arranged to receive an input frame from the control unit before the input frame is transmitted on the can bus network and determine whether the input frame on the transmit can path comprises a can fd frame; and at least one switching module, operably coupled to the detection module and coupleable to the can bus network, where the at least one switching module is operable to impart a first voltage value on the can bus network in response to the input frame being determined as comprising a can fd frame.. ... Freescale Semiconductor Inc

08/11/16 / #20160233296

Deep trench isolation

An integrated semiconductor device includes a substrate of a first conductivity type, a buried layer located over the substrate, an isolated region located over a first portion of the buried layer, and an isolation trench located around the isolated region. A punch-through structure is located around at least a portion of the isolation trench. ... Freescale Semiconductor Inc

08/11/16 / #20160232123

Configurable serial and pulse width modulation interface

A reconfigurable register device includes an arrangement of storage elements arranged sequentially in a chain structure. Each storage element stores a state of a binary signal. ... Freescale Semiconductor Inc

08/11/16 / #20160232008

Method of resetting a processor

The invention relates to a method of resetting a processor, the method comprising the receiving of a reset signal indicating that one or more parts of said processor need to be reset, and forwarding of said reset signal to said parts to be reset. The forwarding of the reset signal is delayed for a period of time for at least one of the parts to be reset. ... Freescale Semiconductor Inc

08/11/16 / #20160231937

Hardware interface component and method therefor

A hardware interface component arranged to operably couple at least one arithmetic unit to a an interconnect component of a processing system. The hardware interface component comprises a plurality of program-visible registers and at least one operation decoder component. ... Freescale Semiconductor Inc

08/11/16 / #20160231806

Initial operational mode for integrated circuit

An integrated circuit (ic) and associated method support using a pre-use configuration for determining an initial/preferred operational mode for the ic from plural operational modes that may be entered following power-up cycles of the ic. The initial/preferred operational mode can be determined after the design phase of the ic so that, during ic operation, wasted power or delay are not incurred by first requiring that the ic power up in a default operational mode and subsequently run executive code to reprogram the ic to enter an operational mode that is preferred for the application for which the ic is being used by the ic integrator/user. ... Freescale Semiconductor Inc

08/11/16 / #20160231805

Electronic device and apparatus and method for power management of an electronic device

An electronic device, typically a microcontroller, which is divided into a multiplicity of power domains comprising one or more intelligent peripherals, is provided with an on-board power management module for switching power to one or more domains for pre-determined time periods and in a predetermined sequence. The values of the predetermined time periods and sequence may be pre-programmed by the design engineer or user of the device. ... Freescale Semiconductor Inc

08/11/16 / #20160231378

Apparatus and method for self-testing an integrated circuit

An integrated circuit and a method of self-testing the integrated circuit are provided. The method comprises: generating a reference voltage at an output of a reference circuit; initiating a test of the reference circuit during a test mode; determining whether the test of the reference circuit passes; and comparing, if the test of the reference circuit passes, a first voltage with the reference voltage. ... Freescale Semiconductor Inc

08/11/16 / #20160231369

Mems device positioning apparatus, test system, and test method

A positioning apparatus includes a support structure, a positioning structure, and a fixture for retaining mems devices. A shaft spans between the support structure and the positioning structure, and is configured to rotate about a first axis relative to the support structure in order to rotate the positioning structure and the fixture about the first axis. ... Freescale Semiconductor Inc

08/11/16 / #20160231119

System comprising a mechanical resonator and method therefor

A system is provided that includes a mechanical resonator, and an analog circuit coupled to the mechanical resonator. The analog circuit is arranged to receive a mechanical resonator measurement signal having a quadrature error from the mechanical resonator, and to extract a quadrature error signal from the mechanical resonator measurement signal using a quadrature clock. ... Freescale Semiconductor Inc

08/04/16 / #20160226492

Programmable buffer system

A programmable buffer system includes a plurality of programmable resources. Each of the programmable resources includes, in an unconfigured state, a buffer with multiple entries, an input multiplexer, and an output multiplexer. ... Freescale Semiconductor Inc

08/04/16 / #20160225713

Semiconductor package design providing reduced electromagnetic coupling between circuit components

A single semiconductor device package that reduces electromagnetic coupling between elements of a semiconductor device embodied within the package is provided. For a dual-path amplifier, such as a doherty power amplifier, an isolation feature that separates carrier amplifier elements from peaking amplifier elements is included within the semiconductor device package. ... Freescale Semiconductor Inc

08/04/16 / #20160224468

Efficient coherency response mechanism

A plurality of processing units are interconnected by a coherency network in accordance with a directed spanning tree. Each processing unit that is a leaf of the directed spanning tree includes processing circuitry to provide a coherency response in response to a snoop request. ... Freescale Semiconductor Inc

08/04/16 / #20160224454

Method of testing software

A method of testing software uses a debugger and a breakpoint handler. The debugger inserts a breakpoint in a target application and enters at least one filtering condition associated with the breakpoint in a data structure. ... Freescale Semiconductor Inc

08/04/16 / #20160224343

Method and apparatus for performing register allocation

A method of performing register allocation for at least one program code module. The method comprises constructing a restriction graph for program variables within at least one program instruction, and determining whether the constructed restriction graph is colourable. ... Freescale Semiconductor Inc

07/28/16 / #20160218893

Dc offset tracking of wireless receivers

. . A receiver system includes a dc (direct current) offset estimation block configured to capture a plurality of sample pairs, each sample pair including a first sample of a first signal and a second sample of a second signal. The first and second signals are passed through one or more gain elements. ... Freescale Semiconductor Inc

07/28/16 / #20160218526

Method for battery equalization

A battery equalization circuit is provided, including: a positive battery node connecting to a positive node of a battery cell in a battery circuit with a plurality of other battery cells; a negative battery node connected to a negative node of the battery cell; a transformer winding receiving an ac voltage, the transformer winding having an upper transformer node and a lower transformer node; an upper triac connected between the positive battery node and the upper transformer node; a lower triac connected between the negative battery node and the lower transformer node; a control circuit for controlling the upper triac and the lower triac based on a measured cell voltage between the positive battery node and the negative battery node, and a total battery voltage of the battery circuit; and an isolation element connected between the control circuit and a data bus.. . ... Freescale Semiconductor Inc

07/28/16 / #20160218112

Non-volatile memory (nvm) cell and device structure integration

A dielectric layer is formed over the substrate in the capacitor region and the memory region and a select gate layer is formed over the dielectric layer. A select gate is formed over the memory region and a plurality of lines of electrodes over the capacitor region from the select gate layer. ... Freescale Semiconductor Inc

07/28/16 / #20160218045

Glass frit wafer bond protective structure

A bonded semiconductor device comprising a support substrate, a semiconductor device located with respect to one side of the support substrate, a cap substrate overlying the support substrate and the device, a glass frit bond ring between the support substrate and the cap substrate, an electrically conductive ring between the support substrate and the cap substrate. The electrically conductive ring forms an inner ring around the semiconductor device and the glass frit bond ring forms an outer bond ring around the semiconductor device.. ... Freescale Semiconductor Inc

07/28/16 / #20160216318

Circuit for monitoring metal degradation on integrated circuit

An integrated circuit (ic) having a heat-generating element, such as a power mosfet, a current-carrying conductor coupled to the heat-generating element, a sense conductor adjacent the current-carrying conductor, and a failure-detection circuit coupled to the sense conductor. When thermal cycling of the ic causes the resistance of the sense conductor to become greater than a temperature-dependent threshold value, the failure-detection circuit generates a signal indicating that the integrated circuit will soon fail. ... Freescale Semiconductor Inc

07/28/16 / #20160216290

Mems device with over-travel stop structure and method of fabrication

A mems device comprises a substrate, a proof mass spaced apart from a surface of the substrate, and an over-travel stop structure. The over-travel stop structure includes a lateral stop structure and a cap coupled to the lateral stop structure. ... Freescale Semiconductor Inc

07/21/16 / #20160212644

Method of estimating ber values in a wireless communication system

There is provided a method of estimating a bit error rate in a transport channel of a wireless communication system. The method comprises the receiving a signal from a remote transmitter of the wireless communication system via a physical channel, the signal comprising data and noise forming a plurality of soft bits. ... Freescale Semiconductor Inc

07/21/16 / #20160211843

Low-power open-circuit detection system

An open-circuit detection system for an integrated circuit (ic) includes a wire (e.g., part of a wire mesh for device protection) and circuitry for detecting open-circuit conditions in the wire. A first signal generator (e.g., a linear-feedback shift register) applies a binary sequence to a first end of the wire. ... Freescale Semiconductor Inc

07/21/16 / #20160211222

Semiconductor packages having wire bond wall to reduce coupling

A device (e.g., a doherty amplifier) housed in an air cavity package includes one or more isolation structures over a surface of a substrate and defining an active circuit area. The device also includes first and second adjacent circuits within the active circuit area, first and second leads coupled to the isolation structure(s) between opposite sides of the package and electrically coupled to the first circuit, third and fourth leads coupled to the isolation structure(s) between the opposite sides of the package and electrically coupled to the second circuit, a first terminal over the first side of the package between the first lead and the third lead, a second terminal over the second side of the package between the second lead and the fourth lead, and an electronic component coupled to the package and electrically coupled to the first terminal, the second terminal, or both the first and second terminals.. ... Freescale Semiconductor Inc

07/21/16 / #20160210260

Resource domain partioning in a data processing system

A resource domain controller in a data processing system stores information that is used to group various resources, such as bus masters and peripherals, into common domains. Each group can be referred to as a resource domain and can include one or more data processor and peripheral devices. ... Freescale Semiconductor Inc

07/14/16 / #20160204089

Package with low stress region for an electronic component

A device package includes a substrate having an active surface. Electrical connection bumps are deposited on the active surface and are arranged in an array having a perimeter. ... Freescale Semiconductor Inc

07/07/16 / #20160197589

Inverse class f amplifiers with intrinsic capacitance compensation

. . The embodiments described herein provide inverse class f (class f−1) amplifiers. In general, the inverse class f amplifiers are implemented with a transistor, an output inductance and a transmission line configured to approximate inverse class f voltage and current output waveforms by compensating the effects of the transistor's intrinsic output capacitance for some even harmonic signals while providing a low impedance for some odd harmonic signals. ... Freescale Semiconductor Inc

07/07/16 / #20160197176

Semiconductor device and method of manufacture therefor

A semiconductor device comprises a first contact layer, a first drift layer adjacent the first contact layer, a buried body layer adjacent the first drift layer and a second contact layer. A first vertical trench and a second vertical trench are provided, the first and second vertical trenches being spaced with respect to each other and extending from the second contact layer to substantially beyond the buried body layer. ... Freescale Semiconductor Inc

07/07/16 / #20160195454

System and method for temperature sensing in an internal combustion engine

A system for determining a temperature of a first portion of an engine, and related circuit, and related method of operation, are disclosed. In one example embodiment, the system includes a wheel having a plurality of magnetic teeth, and an electrical circuit including a variable reluctance sensor (vrs) including at least one winding, the vrs being positioned proximate the wheel, where the vrs is in thermal contact with the first portion, and a comparator having first and second input terminals and an output terminal, where the comparator is configured to output an output signal at the output terminal. ... Freescale Semiconductor Inc

06/16/16 / #20160174218

Device for multiple pan access

. . . . . . A networking device for connection to a plurality of personal area networks is described which operates according to a layer model having a phy layer, at least a first mac layer and a second mac layer, and a third layer situated functionally between the phy layer and the at least first and second mac layers. The first and second mac layers are arranged to support first and second protocol stacks, respectively, to access first and second respective pans using frequency hopping spread spectrum techniques and first and second sets of parameters respectively. ... Freescale Semiconductor Inc

06/16/16 / #20160174094

Radio frequency transceiver loopback testing

An integrated circuit includes a receiver portion, a transmitter portion, and a modulated phase locked loop. The receiver portion is for receiving a radio frequency (rf) signal at a receiver input of the receiver portion. ... Freescale Semiconductor Inc

06/16/16 / #20160173847

Video processing unit and method of buffering a source video stream

In a video system, a video source, e.g., a camera, provides a source video stream. The source video stream comprises a stream of image data units. ... Freescale Semiconductor Inc

06/16/16 / #20160173416

Method and apparatus for implementing deterministic response frame transmission

There is provided a network interface module, and a method of implementing deterministic response frame transmission therein. The network interface module comprises a processor core arranged to execute a set of threads, the set of threads comprising at least one transmit thread arranged to cause a response frame to be transmitted upon expiry of a minimum response period from a response triggering event occurring. ... Freescale Semiconductor Inc

06/16/16 / #20160173335

Network interface module and a method of changing network configuration parameters within a network device

The invention relates to network interface module and a method of changing network configuration parameters on-the-fly within a network device. The network interface module comprises: a processor core arranged to execute a set of threads, the set of threads comprising a port servicing thread arranged to service requests received from a network port of the network interface module; and a task scheduling component arranged to schedule the execution of threads by the processor core. ... Freescale Semiconductor Inc

06/16/16 / #20160173121

Circuit generating an analog signal using a part of a sigma-delta adc

The circuit generates an analog output signal which may be used to test a sigma-delta adc. A digital waveform generator supplies a digital signal to a dac to convert the digital signal into an analog signal. ... Freescale Semiconductor Inc

06/16/16 / #20160173120

Test signal generator for sigma-delta adc

The test signal generator generates an analog and digital test signals to test a sigma-delta adc which has an analog portion succeeded by a digital decimation filter. The test signal generator supplies a first digital test signal having a first particular number of bits n and a first particular bit rate rn corresponding to digital signals occurring after the digital decimation filter. ... Freescale Semiconductor Inc

06/16/16 / #20160173109

Xor phase detector, phase-locked loop, and method of operating a pll

An xor phase detector for a phase-locked loop pll comprises an xor gate which has an input for a periodic reference signal and another input connected to a frequency divider of the pll. A level shifter has a level shifter input connected to an output of the xor gate and a level shifter output connectable to a voltage-controlled oscillator vco of the pll. ... Freescale Semiconductor Inc

06/16/16 / #20160173091

Lvds with idle state

A low voltage differential signaling generating circuit, which comprises a current source a pair of output nodes for providing a differential signal by virtue of a voltage difference therebetween, first and second differential switch circuitries and a bypass circuitry. The first differential switch circuitry selectively connects the current source to the first output node based on a control signal to cause a current flow from the first output node to the second one. ... Freescale Semiconductor Inc

06/16/16 / #20160173076

Production test trimming acceleration

Systems and methods for production test trimming acceleration. In an illustrative, non-limiting embodiment, a method may include providing a first trim code to a reference circuit, where the reference circuit is configured to output a first signal in response to the first trim code; integrating a difference between the first signal and a target voltage value into a first integrated value; providing a second trim code to the reference circuit, where the reference circuit is configured to output a second signal in response to the second trim code; integrating a difference between the second signal and the target voltage value into a second integrated value; and adjusting at least one of the first or second trim codes in response to a comparison between the first and second integrated values.. ... Freescale Semiconductor Inc

06/16/16 / #20160173067

System and method for enhanced clocking operation

A circuit, integrated circuit, system tor implementation in an integrated circuit, and method of operating such a circuit, integrated circuit, or system are disclosed herein. In one example embodiment, the such a circuit includes a multiplier circuit portion, a first duty cycle correction (dcc) circuit portion, and a clock gating circuit portion. ... Freescale Semiconductor Inc

06/16/16 / #20160173048

Dc offset calibration of wireless receivers

A receiver system includes an automatic gain control (agc) module configured to control a first gain control signal to a first gain element having variable gain control. The receiver system also includes a dc (direct current) offset correction block coupled to the agc module, the dc offset correction block configured to trigger the agc module to output a set of calibration gain control signals to the first gain element and capture a set of dc offset measurements of a first signal received at the dc offset correction block, where the first signal is passed by the first gain element. ... Freescale Semiconductor Inc

06/16/16 / #20160173039

Amplifiers with a short phase path, packaged rf devices for use therein, and methods of manufacture thereof

An embodiment of a packaged radio frequency (rf) amplifier device includes a transistor and an inverse class-f circuit configured to harmonically terminate the device. The transistor has a control terminal and first and second current carrying terminals. ... Freescale Semiconductor Inc

06/16/16 / #20160172867

Control of power transfer

An apparatus comprising: a first transmitter configured to transmit in a first channel defined by a first frequency band; a second transmitter configured to transmit in a second channel defined by a second frequency band; and a controller configured to control power transfer via the first channel in dependence upon an impedance of the first channel and an impedance of the second channel.. . ... Freescale Semiconductor Inc

06/16/16 / #20160172318

Semiconductor devices with impedance matching-circuits

Embodiments of semiconductor devices (e.g., rf devices) include a substrate, an isolation structure, an active device, a lead, and a circuit. The isolation structure is coupled to the substrate, and includes an opening. ... Freescale Semiconductor Inc

06/16/16 / #20160172309

Emi/rfi shielding for semiconductor device packages

An encapsulated semiconductor device package with an overlying conductive emi or rfi shield in contact with an end of a grounded conductive component at a lateral side of the package, and methods of making the semiconductor device package.. . ... Freescale Semiconductor Inc

06/16/16 / #20160172240

Method for forming a coupling layer

Molecules of a coupling layer composition in a semiconductor device are bidimensionally polymerized in order to provide enhanced moisture blocking effect, particularly when the coupling layer is formed on a porous layer, such as a porous dielectric layer. The deposition of the coupling layer on the underlying structure and/or the cross-polymerization of the coupling layer composition and/or a final metallization can be photo-activated, especially, but not only, using an ultraviolet light.. ... Freescale Semiconductor Inc

06/16/16 / #20160172199

Nanocrystal memory and methods for forming same

A charge-storing device includes a charge-storing layer including nanocrystals. The nanocrystals are formed by a deposition technique incorporating deuterated hydrides. ... Freescale Semiconductor Inc

06/16/16 / #20160172052

Memory array with read only cells having multiple states and method of programming thereof

A read only memory (rom) having a first row of rom cells, a first conductive line along the first row of rom cells, and a second conductive line along the first row of rom cells. The rom cells of the first row of rom cells are selectively coupled during programming to the first conductive line and the second conductive line so that in a first mode of the rom the first row of rom cells provide a first combination of logic highs and logic lows and in a second mode of the memory the first row of rom cells provide a second combination of logic highs and lows independent of the first combination of logic highs and logic lows.. ... Freescale Semiconductor Inc

06/16/16 / #20160172035

Pseudo sram using resistive elements for non-volatile storage

A memory device includes a first select transistor having a first current electrode coupled to a first bit line, a control electrode and a second current electrode. A second select transistor has a first current electrode coupled to a second bit line, a control electrode and a second current electrode. ... Freescale Semiconductor Inc

06/16/16 / #20160171645

Display controller and a method thereof

A display controller comprises a plurality of channels for fetching data from a memory, a plurality of buffers coupled to the channels for receiving the fetched data from the channels, a buffer controller for controlling the buffers and the channels, and a processing unit coupled to the buffers, the display and buffer controller for receiving the data from the buffers, outputting a control signal to the display based on the received data, and controlling the buffer controller, respectively. Each buffer has a respective fixed memory capacity for storing the fetched data. ... Freescale Semiconductor Inc

06/16/16 / #20160171223

Systems and methods for secure provisioning of production electronic circuits

To securely configure an electronic circuit and provision a product that includes the electronic circuit, a first entity (e.g., a chip manufacturer) embeds one or more secret values into copies of the circuit. A second entity (e.g., an oem): 1) derives a trust anchor from a code signing public key; 2) embeds the trust anchor in a first circuit copy; 3) causes the first circuit copy to generate a secret key derived from the trust anchor and the embedded secret value(s); 4) signs provisioning code using a code signing private key; and 5) sends the code signing public key, the trust anchor, and the signed provisioning code to a third entity (e.g., a product manufacturer). ... Freescale Semiconductor Inc

06/16/16 / #20160171140

Method and system for determining minimum operational voltage for transistor memory-based devices

A mechanism is provided by which a failure analysis during design of one or more memory arrays used in a system on a chip can take into account an operational voltage use profile over the projected life of the chip. The failure analysis is then used in chip redesign decision-making or modification of the use profile. ... Freescale Semiconductor Inc

06/16/16 / #20160170916

Coherent memory interleaving with uniform latency

A data processing system includes a network of interconnected switch points having a plurality of edge switch points located at an edge of the network; a plurality of network interface controllers, wherein each edge switch point of the plurality of edge points is coupled to a corresponding network interface controller of the plurality of network interface controllers; a plurality of target controllers; and a crossbar switch coupled between the plurality of network interface controllers and the plurality of target controllers. The crossbar switch is configured to communicate read/write signals between any one of the plurality of network interface controllers and any one of the plurality of target controllers.. ... Freescale Semiconductor Inc

06/16/16 / #20160170472

Low power configuration for usb (universal serial bus) devices

The present disclosure provides for a method and semiconductor device for low power configuration. In one embodiment, a method includes receiving a packet from a host device, where the packet is received at a usb (universal serial bus) device. ... Freescale Semiconductor Inc

06/16/16 / #20160170433

Method and circuit for generating a proportional-to-absolute-temperature current source

A proportional-to-absolute-temperature (“ptat”) circuit includes a bias component; first, second, third, and fourth transistors; an output transistor; and a first resistive component. A first terminal of the bias component is coupled to a voltage supply node. ... Freescale Semiconductor Inc

06/16/16 / #20160169965

Scan testing with staggered clocks

The present disclosure provides system and method embodiments for generation of capture clock signals. A first and second test circuit receive a first test pattern and a functional clock signal. ... Freescale Semiconductor Inc

06/16/16 / #20160169760

Pressure sensor with differential capacitive output

A mems pressure sensor device is provided that can provide both a linear output with regard to external pressure, and a differential capacitance output so as to improve the signal amplitude level. These benefits are provided through use of a rotating proof mass that generates capacitive output from electrodes configured at both ends of the rotating proof mass. ... Freescale Semiconductor Inc

06/16/16 / #20160169758

Stress isolated differential pressure sensor

A package includes a mems die and a cap element coupled to and stacked with the mems die. The mems die includes at least two physically isolated pressure sensors, each of which resides on its individual cantilevered platform structure. ... Freescale Semiconductor Inc

06/16/16 / #20160167961

Compensation and calibration for mems devices

A sensor system includes a microelectromechanical systems (mems) sensor, processing circuitry, measurement circuitry, stimulus circuitry and memory. The system is configured to provide an output responsive to physical displacement within the mems sensor to the measurement circuitry. ... Freescale Semiconductor Inc

06/16/16 / #20160167944

Reducing mems stiction by deposition of nanoclusters

A mechanism for reducing stiction in a mems device by decreasing surface area between two surfaces that can come into close contact is provided. Reduction in contact surface area is achieved by increasing surface roughness of one or both of the surfaces. ... Freescale Semiconductor Inc

06/16/16 / #20160166200

Glucose monitoring system as control input to adjustable focal length lenses

A mechanism to adjust variable focus lenses using monitored glucose levels is provided. A glucose sensor provides current blood glucose levels to a controller for the variable focus lenses. ... Freescale Semiconductor Inc

06/09/16 / #20160164471

Radio frequency devices with surface-mountable capacitors for decoupling and methods thereof

An embodiment of a radio-frequency (rf) device includes at least one transistor, a package, and a surface-mountable capacitor. The package contains the at least one transistor and includes at least one termination. ... Freescale Semiconductor Inc

06/09/16 / #20160163849

Semiconductor device and method of manufacture therefor

A semiconductor product comprising: a first semiconductor electrode, a second semiconductor electrode and an interconnecting semiconductor electrode defining a third semiconductor electrode; a first switch, between the first semiconductor electrode and the third semiconductor electrode, provided by a first vertical insulated-gate field-effect-transistor; and a second switch, between the second semiconductor electrode and the third semiconductor electrode, provided by a second vertical insulated-gate field-effect-transistor, wherein the interconnecting semiconductor electrode interconnects the first vertical insulated gate field-effect-transistor and the second vertical insulated gate field-effect-transistor.. . ... Freescale Semiconductor Inc

06/09/16 / #20160163671

Integrated circuit package with power plates

A surface-mounted integrated circuit package containing a semiconductor die has at least two conductive plates on its lower surface for contacting power and ground areas of a printed circuit board (pcb). The conductive plates are electrically connected to metal studs encapsulated within the package and which link the plates to the power and ground grids of the semiconductor die. ... Freescale Semiconductor Inc

06/09/16 / #20160163623

System, method and apparatus for leadless surface mounted semiconductor package

A packaged semiconductor device may include a termination surface having terminations configured as leadless interconnects to be surface mounted to a printed circuit board. A first flange has a first surface and a second surface. ... Freescale Semiconductor Inc

06/09/16 / #20160163290

Display system, a method of displaying an image on a screen and an associated computer program product

A display system and a method of displaying an image are hereby presented. The display system is arranged to display an image on a screen which has at least one useful screen area which is intended to be seen by a user and at least one non-useful screen area which the user cannot see. ... Freescale Semiconductor Inc

06/09/16 / #20160162709

3d graphics system

A 3d graphics system uses encryption keys to decrypt received and stored texture tiles of a texture in accordance with received and stored texture tile status data which indicates whether a texture tiles is encrypted or not and which one of the encryption keys is used. The decrypted texture tiles are rendered and at least a plurality of the rendered tiles is encrypted. ... Freescale Semiconductor Inc

06/09/16 / #20160161562

Apparatus and method for determining impedance characteristics of an electrical load

Apparatus (103) suitable for determining the resistance and inductance of an electric motor (101) estimates the phase shift between a voltage applied to the motor and motor current. Estimation of the phase shift employs a heterodyne technique. ... Freescale Semiconductor Inc

06/09/16 / #20160161544

Testing of semiconductor devices

A method comprising: recording test code defined in a high-level test specification language; and automated analysis of the test code defined in the high-level test specification language before a conversion of the high-level test specification language to a low-level test implementation language configured to enable testing of a target by a test module.. . ... Freescale Semiconductor Inc

06/09/16 / #20160161355

Packaged sensor with integrated offset calibration

A mechanism is provided to field adjust offset values for packaged sensors incorporated in devices. Embodiments provide for a processor in the sensor package to measure current environmental conditions and set a zero offset for the sensors in the package in light of those current environmental conditions. ... Freescale Semiconductor Inc

06/09/16 / #20160160833

Radiation devices

A radiation device and related method are presented. The radiation device includes a body. ... Freescale Semiconductor Inc

06/09/16 / #20160159642

Stress isolated mems device with asic as cap

A package includes a mems die and an integrated circuit (ic) die coupled to and stacked with the mems die. The mems die includes a substrate having a recess formed therein. ... Freescale Semiconductor Inc

06/02/16 / #20160156632

System on chip and method therefor

. . A system on chip comprises a responder unit comprising a set of responder elements and an access control unit 484 associated with an authorization list and the responder unit. An entry of the authorization list defines a set of access requirements in relation to an address space identifying at least part of the responder unit. ... Freescale Semiconductor Inc

06/02/16 / #20160156492

Radio signal decoding and decoder

A radio signal decoder (100) is provided. The radio signal decoder (100) comprises a receiver configured to receive a digitized radio signal (122), the radio signal having modulated subcarrier frequencies encoding digital information, a first set of the subcarrier frequencies having a first subcarrier spacing (pusch; pucch; srs), a second set of the subcarrier frequencies having a second subcarrier spacing (rach), a first transformer (130, fft) configured to transform the digitized radio signal from a time domain into a frequency domain, the transformer being configured with the first subcarrier spacing, an a first decoder (140, pusch; pucch; srs) configured to reconstruct digital information from the output of the first transformer, and an inverse transformer (220, ifft) configured to receive as input at least a part of the output (132) of the first transformer representing a frequency range overlapping the second set of subcarrier frequencies, and to transform the input from the frequency domain back to the time domain, the first inverse transformer being configured with the first subcarrier spacing, a second transformer (160, fft) configured to transform the output of inverse transformer from the time domain to a frequency domain, the second transformer being configured with the second subcarrier spacing, a second decoder (170, 180, zc) reconstructing digital information from the output of the second transformer.. ... Freescale Semiconductor Inc

06/02/16 / #20160156180

Electrostatic discharge protection

An electrostatic discharge protection circuit comprises at least two electrostatic discharge protection units connected in series between respective pairs of at least three input terminals, one of the input terminals being a reference input terminal. Each of the units comprises a silicon controlled rectifier and a current mirror. ... Freescale Semiconductor Inc

06/02/16 / #20160155813

Methods and structures for split gate memory cell scaling with merged control gates

A memory device has first and second memory cells in and over a substrate. A first doped region is in a first active region. ... Freescale Semiconductor Inc

06/02/16 / #20160154092

Integrated circuit for saturation detection, wireless device and method of detecting saturation

An integrated circuit for saturation detection comprises: a plurality of gain components; a plurality of saturation detectors with each saturation detector operably coupled to an output of one of the gain components; a plurality of logic elements with a first input of each logic element associated with an output of one of the saturation detectors; and a controller operably coupled to the plurality of logic elements. The controller is arranged to apply a signal to a second input of individual ones of the plurality of logic elements such that an output of the respective logic element identifies a saturation event of the saturation detector associated with that respective logic element.. ... Freescale Semiconductor Inc

06/02/16 / #20160154047

Sensor circuit, vehicle and method therefor

A sensor circuit, comprising at least: a first sensor arranged to selectively receive a first test current; a first digital-to-analog converter, dac, arranged to receive a first signal from the first sensor and output a first compensation signal in response thereto; a second dac arranged to receive a second signal from a second sensor and output a second compensation signal in response thereto; and a controller operably coupled to the first and second dacs and operable to determine from at least one of: the first compensation signal and second compensation signal whether a short condition exists between the first sensor and the second sensor.. . ... Freescale Semiconductor Inc

06/02/16 / #20160154045

Sensor circuit, vehicle and method therefor

A sensor circuit, comprising: at least one signal processing circuit connectable to at least one sensor operable on a channel and configured to receive and process a periodic sensor signal therefrom; a switching device coupled between the signal processing circuit and the at least one sensor, at least one switch coupled to the switching device; and a controller connected to the at least one switch and an output of the signal processing circuit. The controller is operable to re-configure the switching device via control of the switch and determine whether a short condition exists on the at least one sensor or channel based on the output from the signal processing circuit.. ... Freescale Semiconductor Inc

06/02/16 / #20160152464

Mems parameter identification using modulated waveforms

A sensor system includes a microelectromechanical systems (mems) sensor, control circuit, signal evaluation circuitry, a digital to analog converter, signal filters, an amplifier, demodulation circuitry and memory. The system is configured to generate high and low-frequency signals, combine them, and provide the combined input signal to a mems sensor. ... Freescale Semiconductor Inc

05/26/16 / #20160150654

Methods of forming oscillator systems having annular resonant circuitry

. . Systems and apparatus are provided for solid-state oscillators and related resonant circuitry. An exemplary oscillator system includes an amplifier having an amplifier input and an amplifier output and resonant circuitry coupled between the amplifier output and the amplifier input. ... Freescale Semiconductor Inc

05/26/16 / #20160150632

Packaged electronic devices with top terminations, and methods of manufacture thereof

An embodiment of an electronic device includes a circuit component (e.g., a transistor or other component) coupled to the top surface of a substrate. Encapsulation is formed over the substrate and the component. ... Freescale Semiconductor Inc

05/26/16 / #20160150164

System controller, multi-camera view system and a method of processing images

A system controller controls a multi-camera view system for displaying an output image on a display. The output image is a view from a selected viewpoint. ... Freescale Semiconductor Inc

05/26/16 / #20160149781

Network node, a communication system and associated methods

A first network node for communicating with a second network node over a first communication network is described. The second network node is arranged to communicate over the first communication network in a first part of a communication period and arranged to not communicate over the first communication network in a second part of the communication period. ... Freescale Semiconductor Inc

05/26/16 / #20160149773

Multi-partition networking device

A device is described for operating a multi-partition networking system, the device comprising hardware resources for the operation of a primary partition for performing tasks, a primary buffer for holding packets for processing within a partition of the multi-partition system and a reserve buffer. The device is arranged to allocate the primary buffer for use by the primary partition and allocate the reserve buffer for use by the primary partition when at least a suspicious condition is detected in the primary partition. ... Freescale Semiconductor Inc

05/26/16 / #20160149668

Turbo decoders with extrinsic addressing and associated methods

A plurality of turbo decoder engines store extrinsic values when concurrently decoding a received signal encoded within rows and columns of an interleaving matrix where interleaved values stay in a same re-ordered row during interleaving. An extrinsic reader and extrinsic writer accesses extrinsic memories using extrinsic addresses. ... Freescale Semiconductor Inc

05/26/16 / #20160149596

Turbo decoder with a low-power input format and associated method

A turbo decoder stores received data in words in systematic memory and parity memory in a way that is known that it will be used for later iterations by turbo decoder engines arranged to operate in parallel. A loader receives and separates llrs into systematic and parity data and stores them into a portion of a word per cycle until a word is full in a corresponding one of the systematic memory and parity memory. ... Freescale Semiconductor Inc

05/26/16 / #20160149591

Turbo decoders with stored column indexes for interleaver address generation and out-of-bounds detection and associated methods

A turbo decoder decodes encoded data using a regenerated interleaver sequence. An addressable column index memory stores column indexes of the encoded data during an input phase of a turbo decode operation. ... Freescale Semiconductor Inc

05/26/16 / #20160149569

A gate drive circuit and a method for setting up a gate drive circuit

A gate drive circuit includes a first switch and a first capacitor. A first terminal of the first capacitor is electrically coupled to the first switch. ... Freescale Semiconductor Inc

05/26/16 / #20160149515

A gate drive circuit and a method for controlling a power transistor

A gate drive circuit to drive a gate terminal of a power transistor. The gate drive circuit includes a first capacitor, a first switch, a measurement circuit and a reference source to generate a reference voltage. ... Freescale Semiconductor Inc

05/26/16 / #20160148685

Resistive memory with program verify and erase verify capability

A resistive non-volatile memory cell is programmed. A programming voltage is applied to a first terminal of the resistive non-volatile memory cell. ... Freescale Semiconductor Inc

05/26/16 / #20160148000

Method and apparatus for encoding image data

The present invention relates to a method and apparatus for encoding image data defining a graphics object. The method comprises partitioning the graphics object into a plurality of sub-images, deriving digital image data for each sub-image, the digital image data defining the respective sub-image, deriving sub-image position data defining the relative positioning of the sub-images within the graphics object, scrambling the digital image data for the plurality of sub-images, encrypting sub-image position data, and outputting encoded image data defining the graphics object comprising the scrambled sub-image data and the encrypted sub-image position data.. ... Freescale Semiconductor Inc

05/26/16 / #20160147672

Device having memory access protection

A device has a protection unit for controlling access to a memory. Indirect memory access requests have control data indicative of a memory access control register to be written to provide indirect access to a target memory and requested address data indicative of at least one memory address of the target memory to be accessed. ... Freescale Semiconductor Inc

05/26/16 / #20160147660

Access extent monitoring for data transfer reduction

A data processor system includes a local memory, a processor core, and an extent monitor. The local memory stores a block of data at a task memory location that is exclusive to a particular task during a duration of time. ... Freescale Semiconductor Inc

05/26/16 / #20160147586

Device and method for executing a program, and method for storing a program

A device and a method for executing a program, and a method for storing a program are described. The method of executing a program includes a sequence of instruction cycles, wherein each instruction cycle comprises: updating the program counter value; reading a data word from a memory location identified by the updated program counter value, wherein the data word comprises an instruction and a protection signature; determining a verification signature by applying a signature function associated with the program counter value to the instruction; executing the instruction if the verification signature and the protection signature are consistent with each other; and initiating an error action if they are inconsistent with each other. ... Freescale Semiconductor Inc

05/26/16 / #20160147517

Method and computer program product for disassembling a mixed machine code

A method and a computer program product for disassembling a mixed machine code are described. The machine code is provided as a sequence of code items including one or more instructions and one or more data items. ... Freescale Semiconductor Inc

05/26/16 / #20160147125

Electronic devices wth transparent conducting electrodes, and methods of manufacture thereof

An embodiment of a transparent conducting electrode includes a first non-conductive layer formed from a first non-conductive material, a conductive layer, and a second non-conductive layer formed from a second non-conductive material that is different from the first non-conductive material. One or more of the transparent conducting electrodes may be incorporated into electronic devices such as solar cells, light emitting diodes, electrochromic devices, liquid crystal displays, and other devices.. ... Freescale Semiconductor Inc

05/19/16 / #20160143012

Carrier aggregation controller and method

A carrier aggregation controller for providing an aggregated baseband signal from a plurality of baseband signals is provided. The controller comprises an accumulating memory, a selector and a time domain transformer. ... Freescale Semiconductor Inc

05/19/16 / #20160142674

Teleconferencing environment having auditory and visual cues

A teleconferencing environment is provided in which both audio and visual cues are used to identify active participants and presenters. Embodiments provide an artificial environment, configurable by each participant in a teleconference, that directs the attention of a user to an identifier of an active participant or presenter. ... Freescale Semiconductor Inc

05/19/16 / #20160142458

Method and device for data streaming in a mobile communication system

Interfacing between radio units in a base station in a mobile communication system uses a common public radio interface cpri for streaming iq data samples arranged in lanes. A separate serial interface srio is now additionally used for transferring selected data samples arranged in packets, the selected samples corresponding to selected lanes streamed between other radio units via the common public radio interface. ... Freescale Semiconductor Inc

05/19/16 / #20160142175

Adaptive cyclic channel coding for orthogonal frequency division multiplexed (ofdm) systems

A method and apparatus for an orthogonal frequency division multiplexed (ofdm) communication system for communication in the presence of cyclostationary noise is provided. A receiver receives from a medium a channel measurement packet of a communication channel. ... Freescale Semiconductor Inc

05/19/16 / #20160142025

Integrated matching circuit for a high frequency amplifier

An integrated matching circuits for a high frequency amplifier transistor having an input terminal, an output terminal and a reference terminal. The reference terminal is coupled to a reference potential. ... Freescale Semiconductor Inc

05/19/16 / #20160142015

High frequency amplifier

A high frequency amplifier includes a high frequency amplifier transistor integrated in a first die of a first semiconductor technology and a matching circuit. The high frequency amplifier transistor has an input terminal, an output terminal and a reference terminal. ... Freescale Semiconductor Inc

05/19/16 / #20160140063

Message filtering in a data processing system

A data processing system includes a plurality of processors, each processor configured to execute instructions, including a message send instruction, and a message filtering unit. The message filtering system is configured to receive messages from one or more of the plurality of processors in response to execution of message send instructions, each message indicating a message type and a message payload. ... Freescale Semiconductor Inc

05/19/16 / #20160140062

Message filtering in a data processing system

Each processor of a plurality of processors is configured to execute an interrupt message instruction. A message filtering unit includes storage circuitry configured to store captured identifier information from each processor. ... Freescale Semiconductor Inc

05/19/16 / #20160139944

Method and apparatus for combined hardware/software vm migration

A method and apparatus are provided for migrating one or more hardware devices (105) associated with a virtual machine (103) from a source machine (101) to a destination machine (111) by capturing, formatting, storing, and transferring hardware context information from the hardware device(s) at the source machine during the virtual machine migration process using a defined handshake protocol at each associated hardware driver (105) to capture the hardware context information from an associated hardware device (105) being migrated.. . ... Freescale Semiconductor Inc

05/19/16 / #20160139837

Error recovery in a data processing system which implements partial writes

A data processing system includes a command buffer and control circuitry. The command buffer is configured to store pending write requests to a memory in which each pending write request has corresponding write data. ... Freescale Semiconductor Inc

05/19/16 / #20160139174

Trimming circuit for a sensor and trimming method

An on-board trimming circuit suitable for trimming an accelerometer provides offset trim and gain trim modules for determining correct trim codes for subsequent programming into the trimming circuit. The correct trim codes may be determined by comparing sensor outputs which have been adjusted by successive trim codes, with a reference voltage in a comparator until the comparator toggles or by using a successive approximation technique. ... Freescale Semiconductor Inc

05/19/16 / #20160138968

Apparatus and method for checking the integrity of visual display information

The invention provides an apparatus and method for checking the integrity of visual display information and has particular application to checking images displayed in an automotive vehicle, such images containing safety critical information. The image intensity is checked only to an extent commensurate with a human being able to interpret its correct meaning. ... Freescale Semiconductor Inc

05/19/16 / #20160137151

Object restraint systems and methods of operation thereof

Embodiments include object restraint systems and methods of their operation. The system is contained in a vehicle with a passenger compartment, and includes sensor and processing subsystems, a vessel, a restraint mechanism, and an actuator. ... Freescale Semiconductor Inc

05/12/16 / #20160135223

Efficient scheduling in asynchronous contention-based system

. . In an operation scheduler adapted to schedule in an asynchronous contention-based system a first fifo queue is adapted to store one trigger message or one operation request. A message router is coupled to the first fifo queue and is adapted to route instructions to a second fifo queue or a memory and locate in the memory the instructions of a suspended operation associated with a trigger message and authorise execution of the suspended operation. ... Freescale Semiconductor Inc

05/12/16 / #20160134521

Device and method for processing in a mobile communication system

A processor device processes data samples of a radio signal in a mobile communication system. A fast flow process is executed for all samples and a batch process is executed at intervals on a subset of the samples. ... Freescale Semiconductor Inc

05/12/16 / #20160134279

Method and circuit for recharging a bootstrap capacitor using a transfer capacitor

A circuit including and a method utilizing an improved bootstrap topology provide power to a high side (hs) driver for high efficiency applications. The improved bootstrap topology includes a transfer capacitor to store charge and to recharge a bootstrap capacitor, which provides power to the hs driver. ... Freescale Semiconductor Inc

05/12/16 / #20160134273

Emitter follower buffer with reverse-bias protection

The invention relates to a buffer circuit for a receiver device including a transconductance stage and an output stage coupled in parallel to output stages of other channels of the device. The output of the transconductance stage is connected to a base of a bipolar transistor in the output stage. ... Freescale Semiconductor Inc

05/12/16 / #20160133608

Devices and stacked microelectronic packages with package surface conductors and methods of their fabrication

Embodiments of methods for forming a device include performing an oxidation inhibiting treatment to exposed ends of first and second device-to-edge conductors, and forming a package surface conductor to electrically couple the exposed ends of the first and second device-to-edge conductors. Performing the oxidation inhibiting treatment may include applying an organic solderability protectant coating to the exposed ends, or plating the exposed ends with a conductive plating material. ... Freescale Semiconductor Inc

05/12/16 / #20160133574

Though-substrate vias (tsvs) and method therefor

A semiconductor device includes a semiconductor substrate having a first major surface and a second major surface opposite the first major surface. A via extends through the substrate. ... Freescale Semiconductor Inc

05/12/16 / #20160132374

Detection of data corruption in a data processing device

A method of operating a data processing system comprises: processing data words and switching between contexts; assigning a context signature sig to any pair formed of a data word and a context; reading, within a current context, a data record from a memory unit, the data record comprising a payload data word and a protection signature; providing, as a verification signature, the context signature sig of the payload data word and the current context; checking the verification signature against the protection signature; and generating an error signal if the verification signature differs from the protection signature.. . ... Freescale Semiconductor Inc

05/12/16 / #20160132332

Signal processing device and method of performing a bit-expand operation

A signal processing device comprising at least one control unit arranged to receive at least one bit-expand instruction, decode the received at least one bit-expand instruction, and output at least one control signal in accordance with the received at least one bit-expand instruction. The signal processing device further includes at least one execution unit component arranged to receive at least one source register value comprising at least one data bit to be expanded, extract at least one data bit from the at least one source register value located at an offset position according to the at least one control signal, expand the at least one extracted data bit into at least one multi-bit data type, and output the at least one multi-bit data type to at least one destination register.. ... Freescale Semiconductor Inc

05/12/16 / #20160132093

Method and apparatus for controlling an operating mode of a processing module

A method of controlling an operating mode of at least one processing module. The method comprises receiving an indication of the execution of at least one background task by the at least one processing module, aggregating an execution duration for the at least one background task on the at least one processing module, and configuring a lower power mode for the at least one processing module when the at least one background task is allocated to the at least one processing module for execution thereon if the aggregated execution duration for the at least one background task exceeds a threshold duration within an evaluation period.. ... Freescale Semiconductor Inc

05/12/16 / #20160132070

Oscillator circuit and method of generating a clock signal

An oscillator circuit of the type comprising a flip-flop for generating a clock signal and two comparators for comparing a reference voltage with the voltage across a first capacitor which is charged during a first cycle of the clock signal and the voltage across a second capacitor which is charged during a second cycle of a clock signal provides a means for removing the effects of any offset in either comparator. This is achieved by reversing the inputs of the comparators for each cycle of the output frequency. ... Freescale Semiconductor Inc

05/12/16 / #20160131713

Systems and methods for switch health determination

The embodiments described herein provide systems and methods for determining the health status of a sensed switch. In general, the embodiments described herein determine a measure of a health status of the sensed switch by comparing a voltage on the sensed switch, ascertaining a first comparator state under one test condition and ascertaining a second comparator state under a second test condition. ... Freescale Semiconductor Inc

05/12/16 / #20160131552

Shock sensor with latch mechanism and method of shock detection

A micromechanical shock sensor includes a proof mass coupled to a surface of a substrate and a projection element extending laterally from the proof mass. The shock sensor further includes a latch mechanism and a retention anchor. ... Freescale Semiconductor Inc

05/12/16 / #20160130136

Environmental sensor structure

A device in which an electronic circuit positioned within a cavity of a package housing is encased by a bubble restrictor material, with a media resistant material overlaying the bubble restrictor material. The bubble restrictor material functions to inhibit the formation and growth of moisture-related bubbles within the material, including at the interfaces of the material and surfaces within the package housing. ... Freescale Semiconductor Inc

05/05/16 / #20160128040

Method and device for interfacing in a mobile communication system

Interfacing according to a common public radio interface in a base station in a mobile communication system is described. The interfacing comprises a conversion process for rate-converting legacy data samples. ... Freescale Semiconductor Inc

05/05/16 / #20160126963

Phase detector and phase-locked loop

A phase detector for generating a phase difference signal indicative of a phase difference between a first bi-level signal of frequency f1 and a second bi-level signal of frequency f2 is proposed. The phase detector may include first and second detector inputs first and second flip-flops, a nand gate, and a first and second overphase detection units. ... Freescale Semiconductor Inc

05/05/16 / #20160126905

Broadband radio frequency power amplifiers, and methods of manufacture thereof

An embodiment of an amplifier has a bandwidth defined by low and upper cutoff frequencies. The amplifier includes an input impedance matching circuit and a transistor. ... Freescale Semiconductor Inc

05/05/16 / #20160126841

Buck converter and method of operating a buck converter

A buck converter has an output node and a ground node, wherein a load is connected between the output node and the ground node and is arranged to drive an output current i_out through the output node, generating an output voltage v_out. A current control unit arranged to control the output current i_out in dependence on a control voltage v_ctl provided at a control node; and a voltage control unit arranged to provide the control voltage v_ctl. ... Freescale Semiconductor Inc

05/05/16 / #20160126729

Shared esd circuitry

An integrated circuit including esd circuitry that is shared among more than one terminal segment of the integrated circuit to discharge current from an esd event on any of the terminal segments. The shared esd circuitry includes a clamp circuit that is coupled to power buses of each segment to discharge current from esd events on each segment. ... Freescale Semiconductor Inc

05/05/16 / #20160126327

Method of making a split gate memory cell

A method includes forming a first dielectric layer over a memory region and a second dielectric layer over a logic region. A first polysilicon layer is formed over the first and second dielectric layers. ... Freescale Semiconductor Inc

05/05/16 / #20160126208

Coated bonding wire and methods for bonding using same

A semiconductor device includes a bond formed on a bond pad. The bond is formed of a wire that includes a central core of conductive metal, a first coating over the central core of conductive metal that is more chemically active than the conductive metal, and a second coating over the central core of conductive metal that is less chemically active than the central core of conductive metal.. ... Freescale Semiconductor Inc

05/05/16 / #20160126206

Thick-silver layer interface

A semiconductor device and a method of manufacturing the same include a die and a planar thermal layer, and a thick-silver layer having a thickness of at least four (4) micrometers disposed directly onto a first planar side of the planar thermal layer, as well as a metallurgical die-attach disposed between the thick-silver layer and the die, the metallurgical die-attach directly contacting the thick-silver layer.. . ... Freescale Semiconductor Inc

05/05/16 / #20160124904

Processing device and method for performing a round of a fast fourier transform

A data processing device and a method for performing a round of an n point fast fourier transform are described. The round comprises computing n output operands on the basis of n input operands by applying a set of n/p radix-p butterflies to the n input operands, wherein p is greater or equal two and the input operands are representable as n/(m*p)̂2 input operand matrices, wherein m is greater or equal one, each input operand matrix is a square matrix with m*p lines and m*p columns, and each column of each input operand matrix contains the input operands for m of said butterflies.. ... Freescale Semiconductor Inc

05/05/16 / #20160124853

Diagnostic apparatus, control unit, integrated circuit, vehicle and method of recording diagnostic data

A diagnostic apparatus comprises a diagnostic data buffer constituting a volatile memory, and a non-volatile memory capable of receiving data from the buffer. A data buffer controller is also provided and is operably coupled to the buffer and has an event alert input and a data channel monitoring input for receiving diagnostic data. ... Freescale Semiconductor Inc

05/05/16 / #20160124800

Microcontroller unit and method of operating a microcontroller unit

A microcontroller unit (mcu) having a functional state, a reset state, and one or more assertable fault sources is described. Each fault source has its own fault source assertion count and its own fault source assertion limit; the mcu is arranged to perform the following sequence of operations in a cyclic manner: if one or more of the fault sources are asserted, pass from the functional state to the reset state and increase the respective fault source assertion counts by one increment; if one or more of the fault source assertion counts exceeds the respective fault source assertion limit, disable the respective fault source; and pass from the reset state to the functional state. ... Freescale Semiconductor Inc

05/05/16 / #20160124521

Remote customization of sensor system performance

A mechanism is provided to customize response of devices to inputs received by a variety of sensors on those devices. Data samples of a desired input event are gathered and then those data samples are transmitted to a remote server computer for analysis. ... Freescale Semiconductor Inc

04/28/16 / #20160119887

Signal processing method for uplink in small cell base station

A base station and method of synchronizing with a user equipment (ue) in a cell of the base station. The base station signals to the ue an indication relating to a subset of preambles chosen for synchronization with the cell from a set of preambles derivable from one or more given root sequences. ... Freescale Semiconductor Inc

04/28/16 / #20160118705

Packaged integrated circuit waveguide interface and methods thereof

The embodiments described herein provide for the formation of circuit waveguide interfaces during a wafer-scale die packaging (wsdp) process. Specifically, during the packaging process singulated die are arranged on a wafer-like panel and covered with molding compound that will provide the bodies of the packages. ... Freescale Semiconductor Inc

04/28/16 / #20160118495

Integrated breakdown protection

A device includes a semiconductor substrate having a first conductivity type, a device isolating region in the semiconductor substrate, defining an active area, and having a second conductivity type, a body region in the active area and having the first conductivity type, and a drain region in the active area and spaced from the body region to define a conduction path of the device, the drain region having the second conductivity type. At least one of the body region and the device isolating region includes a plurality of peripheral, constituent regions disposed along a lateral periphery of the active area, each peripheral, constituent region defining a non-uniform spacing between the device isolating region and the body region. ... Freescale Semiconductor Inc

04/28/16 / #20160118469

Integrated circuit devices with counter-doped conductive gates

Integrated circuit devices with counter-doped conductive gates. The devices have a semiconductor substrate that has a substrate surface. ... Freescale Semiconductor Inc

04/28/16 / #20160118373

Multiple die lead frame packaging

First and second semiconductor die are mounted to first and second die pads of a lead frame disposed in a lead frame sheet. With a plurality of wire bonds, each post of a plurality of posts of the lead frame is connected to the first and second semiconductor die. ... Freescale Semiconductor Inc

04/28/16 / #20160118365

Die attachment for packaged semiconductor device

A method for forming a packaged semiconductor device includes attaching a first major surface of a semiconductor die to a plurality of protrusions extending from a package substrate. A top surface of each protrusion has a die attach material, and the plurality of protrusions define an open region between the first major surface of the semiconductor die and the package substrate. ... Freescale Semiconductor Inc

04/28/16 / #20160118313

Fan-out wafer level packages containing embedded ground plane interconnect structures and methods for the fabrication thereof

Fan-out wafer level packages (fo-wlps) and methods for fabricating fo-wlps containing embedded ground planes (egps) and backside egp interconnect structures are provided. In one embodiment, the method includes electrically coupling an egp to a backside terminal of a first microelectronic device through a backside egp interconnect structure. ... Freescale Semiconductor Inc

04/28/16 / #20160118095

Die stack address bus having a programmable width

The dies of a stacked die integrated circuit (ic) employ the address bus to indicate the particular die, or set of dies, targeted by data on a data bus. During manufacture of the stacked die ic, the ic is programmed with information indicating a width of the address bus. ... Freescale Semiconductor Inc

04/28/16 / #20160117255

Device having a cache memory

A device has a cache memory for temporarily storing contents of a buffer memory. The device has a mirror unit coupled between the cache memory and the buffer memory. ... Freescale Semiconductor Inc

04/28/16 / #20160117183

System-on-chip device, method of peripheral access and integrated circuit

A system-on-chip device comprises a core supporting a first virtual machine image and a virtual machine monitoring unit capable of communicating with the first virtual machine image. A shareable resource is also provided as well as a conflict detection unit capable of communicating with the virtual machine monitoring unit and the first virtual machine image. ... Freescale Semiconductor Inc

04/28/16 / #20160117007

Visual display content source identifier and method

The invention provides an apparatus and method which allows identification of the system which provided images for each pixel of a touchscreen display which displays merged images of arbitrary shapes supplied from a plurality of systems. It further allows routing of user inputs to the appropriate system for further processing. ... Freescale Semiconductor Inc

04/28/16 / #20160116361

System for wafer-level testing of mems pressure sensors

A system for testing pressure sensors on a device wafer includes a tray for holding the device wafer. The tray includes a base having a surface, a spacer extending from the surface, and a tacky material disposed on the surface. ... Freescale Semiconductor Inc

04/07/16 / #20160100367

Power management module and method therefor

A power management module comprising a client monitoring component arranged to monitor idle periods for a client component, and derive at least one idle period characteristic value for the client component based at least partly on the monitoring of the idle periods therefore. The power management module further comprises a power mode control component arranged to receive an indication of the client component entering an idle state, cause the client component to be put into a reduced power mode upon expiry of a first period of time, and cause the client component to be brought out of the reduced power mode upon expiry of a second period of time. ... Freescale Semiconductor Inc

04/07/16 / #20160099709

Current mode logic circuit for high speed input/output applications

A cml latch includes an input stage including input nodes to receive a differential input signal and output nodes to provide a differential intermediate output signal, and a negative output node to provide a negative side of the differential intermediate output signal, a negative resistance stage including an input node connected to a first voltage source and output nodes connected to the output nodes of the input stage, and a latch stage including input nodes connected to the output nodes of the input stage and output nodes to provide a differential output signal. The negative resistance stage increases a current gain of the input stage.. ... Freescale Semiconductor Inc

04/07/16 / #20160099656

Non-isolated ac-dc conversion power supply

A non-isolated capacitive ac-dc conversion power supply includes a current limiting input module that receives ac input power and has an output capacitor that supplies dc power. Charge storage stages have charge storage capacitors, a rectifier supplying rectified current from the input module to charge the charge storage capacitors and the output capacitor during a first part-cycle of the ac input power. ... Freescale Semiconductor Inc

04/07/16 / #20160099349

Semiconductor device with non-isolated power transistor with integrated diode protection

A semiconductor device configured with one or more integrated breakdown protection diodes in non-isolated power transistor devices and electronic apparatus, and methods for fabricating the devices.. . ... Freescale Semiconductor Inc

04/07/16 / #20160099341

High breakdown voltage ldmos device

A multi-region (81, 83) lateral-diffused-metal-oxide-semiconductor (ldmos) device (40) has a semiconductor-on-insulator (soi) support structure (21) on or over which are formed a substantially symmetrical, laterally internal, first ldmos region (81) and a substantially asymmetric, laterally edge-proximate, second ldmos region (83). A deep trench isolation (dti) wall (60) substantially laterally terminates the laterally edge-proximate second ldmos region (83). ... Freescale Semiconductor Inc

04/07/16 / #20160099212

Through package circuit in fan-out wafer level package

A method and apparatus are provided for manufacturing a packaged electronic device (3) having pre-formed and placed through package circuit devices (35) which include an embedded circuit component (39) and conductor terminals (37a, 37b) extending from a molded package (38) embedding the circuit component (39). The through package circuit devices (35) are placed on end with integrated circuit die (34) and encapsulated in a molded device package (32) which leaves exposed the one or more conductor terminals (37a, 37b) positioned on first and second surfaces of the through package circuit device, where the conductor terminals (37a, 37b) and embedded circuit component (39) form a circuit path through the molded device package.. ... Freescale Semiconductor Inc

04/07/16 / #20160099199

Electronic devices with solderable die structures and methods of formation of such devices

An electronic device includes a semiconductor die having a lower surface, a sintered metallic layer underlying the lower surface of the semiconductor die, a thermally conductive flow layer underlying the sintered metallic layer, and a thermally conductive substrate underlying the thermally conductive flow layer.. . ... Freescale Semiconductor Inc

04/07/16 / #20160099153

Split-gate non-volatile memory (nvm) cell and method therefor

A split gate memory device includes a semiconductor substrate and a select gate over the substrate. The select gate has a bottom portion and a top portion over the bottom portion, wherein the top portion has a top sidewall and the bottom portion has a bottom sidewall, and wherein the bottom sidewall extends beyond the top sidewall. ... Freescale Semiconductor Inc

04/07/16 / #20160098551

Optical authentication of operations for a mobile device

An operation at a mobile device is authenticated by using a random visual presentation displayed at the device for the authentication. The mobile device generates and displays the random visual presentation which is optically captured (e.g., by a camera) at a capturing device. ... Freescale Semiconductor Inc

04/07/16 / #20160098506

Signal delay flip-flop cell for fixing hold time violation

A signal delay cell for use in resolving hold time violations in an ic has a first multiplexer having a first functional data input node and a scan data input node ti and a second multiplexer having a second functional data input node, a second input node connected to the output of the first multiplexer and a flip-flop module. The propagation of a data input signal applied to the first multiplexer is delayed, and the hold margin of the flip-flop module is increased by transit through the first multiplexer. ... Freescale Semiconductor Inc

04/07/16 / #20160098326

Method and apparatus for enabling temporal alignment of debug information

A signal processing device includes at least one timestamp generation component arranged to generate at least one local timestamp value, and to provide the at least one local timestamp value to at least one data link layer module for timestamping of data packets. The signal processing device further includes at least one debug module arranged to receive the at least one local timestamp value and to timestamp debug information based at least partly on the at least one local timestamp value.. ... Freescale Semiconductor Inc

04/07/16 / #20160098313

Watchdog method and device

Each task assigned to a core can be considered an “active” task. Sequential strobe signals of a watchdog signal can be spaced apart in time by a certain duration. ... Freescale Semiconductor Inc

04/07/16 / #20160098050

Voltage regulator, application-specific integrated circuit and method for providing a load with a regulated voltage

A voltage regulator for digital loads combines a closed loop regulation circuit with an open loop topology. A transistor and a bank of transistors share the same voltage source vdd and gate control current. ... Freescale Semiconductor Inc

04/07/16 / #20160098047

Voltage monitoring system

An integrated circuit (ic) includes a digital-to-analog converter (dac), a voltage monitoring circuit, and a controller. The voltage monitoring circuit includes low voltage detect (lvd) and low voltage warning (lvw) circuits that generate lvd and lvw reference voltage signals. ... Freescale Semiconductor Inc

04/07/16 / #20160097792

Three-axis microelectromechanical systems device with single proof mass

A microelectromechanical systems (mems) device, such as a three-axis mems device can sense acceleration in three orthogonal axes. The mems device includes a single proof mass and suspension spring systems that movably couple the proof mass to a substrate. ... Freescale Semiconductor Inc

04/07/16 / #20160096724

Stress isolation for mems device

A microelectromechanical systems (mems) die includes a substrate having a recess formed therein and a cantilevered platform structure. The cantilevered platform structure has a platform and an arm extending from the platform, wherein the platform and arm are suspended over the recess. ... Freescale Semiconductor Inc

03/31/16 / #20160094766

Orientation determination for devices generating electromagnetic interference

. . A mechanism is provided to determine orientation of a device that includes sources of electromagnetic interference. Data generated by one or more gyroscopes in the device, in conjunction with data generated by one or more accelerometers, can be used to generate an estimate of the change of orientation of the device from the time of a last accurate magnetometer reading. ... Freescale Semiconductor Inc

03/31/16 / #20160094187

Modifiable signal adjustment devices for power amplifiers and corresponding methods & apparatus

An embodiment of an amplifier system includes a modifiable signal adjustment device with an rf signal adjustment circuit coupled between first and second nodes. The rf signal adjustment circuit includes an adjustable phase shifter and an adjustable attenuator coupled in series with each other. ... Freescale Semiconductor Inc

03/31/16 / #20160093671

Non-volatile random access memory (nvram)

A semiconductor device and methods for making the same are disclosed. The device may include: a first transistor structure; a second transistor structure; a capacitor structure comprising a trench in the substrate between the first and second transistor structures, the capacitor structure further comprising a doped layer over the substrate, a dielectric layer over the doped layer, and a conductive fill material over the dielectric layer; a first conductive contact from the first transistor structure to a first bit line; a second conductive contact from the second transistor to a non-volatile memory element; and a third conductive contact from the non-volatile memory element to a second bit line.. ... Freescale Semiconductor Inc

03/31/16 / #20160093587

Flexible circuit leads in packaging for radio frequency devices and methods thereof

A packaged rf device is provided that can provide improved performance and flexibility though the use of flexible circuit leads. The rf device includes at least one integrated circuit (ic) die configured to implement the rf device. ... Freescale Semiconductor Inc

03/31/16 / #20160093549

Integrated circuit heater for reducing stress in the integrated circuit material and chip leads of the integrated circit, and for optimizing performance of devices of the integrated circuit

A device comprising a first detector, comprising an output, disposed at a first location of an integrated circuit chip and configured to determine a first temperature information, a chip heater, comprising an input to receive a control signal, disposed at a second location of the integrated circuit and configured to heat an area of the integrated circuit device that includes the first location and the second location, based upon the control signal, and a heater controller comprising a first input coupled to the output of the first detector to receive the first temperature information, and an output coupled to the input of the chip heater, the heater controller configured to generate the control signal based upon the first temperature information.. . ... Freescale Semiconductor Inc

03/31/16 / #20160093533

Substrate for alternative semiconductor die configurations

A method of assembling semiconductor devices with semiconductor dies of alternative different configurations uses the same substrate panel. The dies of the selected configuration are placed in an array, mounted, and connected to internal electrical contact pads on a first face of the panel using main fiducial markings and an array of subsidiary fiducial markings corresponding universally to arrays of semiconductor dies of the different alternative configurations. ... Freescale Semiconductor Inc

03/31/16 / #20160092329

Final result checking for system with pre-verified cores

Provided are a system and method for generating final result checking for a test case. A test case is executed for a coherent memory system having a processor core. ... Freescale Semiconductor Inc

03/31/16 / #20160092323

Multi-partition networking device and method therefor

A multi-partition networking device comprising a primary partition running on a first set of hardware resources and a secondary partition running on a further set of hardware resources. The multi-partition networking device is arranged to operate in a first operating state, whereby the first set of hardware resources are in an active state and the primary partition is arranged to process network traffic, and the further set of hardware resources are in a standby state. ... Freescale Semiconductor Inc

03/31/16 / #20160092320

Electronic fault detection unit

An electronic fault detection unit is provided that has a first register, a second register, a comparator circuit, and a timer circuit. The first and second register can be written from a first software portion, and a second software portion, respectively. ... Freescale Semiconductor Inc

03/31/16 / #20160092229

Systems and methods for managing return stacks in a multi-threaded data processing system

A processor is configured to execute instructions of a first thread and a second thread. A first return stack corresponds to the first thread, and a second return stack to the second thread. ... Freescale Semiconductor Inc

03/31/16 / #20160091908

Sensed switch current control

A circuit includes an evaluation node through which current flows from a voltage source node to a sensed switch when the sensed switch is closed. First and second control switches are disposed between the voltage source node and the evaluation node to switch between first and second current paths for the current. ... Freescale Semiconductor Inc

03/31/16 / #20160091561

Secure low voltage testing

An integrated circuit includes a normal voltage detector configured to detect a normal voltage at which the integrated circuit being fully functional. A first voltage detector detects a first voltage that is less than the normal voltage. ... Freescale Semiconductor Inc

03/31/16 / #20160091529

Accelerometer calibration in a rotating member

To calibrate an accelerometer, a rotating member is rotated over multiple periods, thereby causing the accelerometer attached to the rotating member to repeatedly turn over. A processor obtains acceleration measurements as the accelerometer turns and determines a set of local minima and maxima of the acceleration measurements. ... Freescale Semiconductor Inc

03/24/16 / #20160087737

A network receiver for a network using distributed clock synchronization and a method of sampling a signal received from the network

. . A network receiver receives from a network an input signal which is sampled by a data sampler of the network receiver at sampling moments. Sampling moments have a relative position in time within a period of time of a single bit. ... Freescale Semiconductor Inc

03/24/16 / #20160087588

Packaged rf amplifier devices with grounded isolation structures and methods of manufacture thereof

An embodiment of a packaged rf amplifier device includes a device substrate, a transistor die coupled to the device substrate, and an isolation structure coupled to the transistor die. The transistor die has a top die surface, a bottom die surface, a semiconductor substrate, first and second transistors formed in the semiconductor substrate, a conductive structure at the top die surface and positioned between the first and second transistors, and a low resistance path that extends vertically through the semiconductor substrate between the conductive structure and the bottom die surface. ... Freescale Semiconductor Inc

03/24/16 / #20160087586

Packaged rf amplifier devices and methods of manufacture thereof

An embodiment of a packaged radio frequency (rf) device includes a device substrate with a voltage reference plane, a first input lead coupled to the device substrate, a first output lead coupled to the device substrate, a first transistor die coupled to a top surface of the device substrate with a solder bond, a second die coupled to the top surface of the device substrate with a conductive epoxy that electrically couples at least one component of the second die to the voltage reference plane, and non-conductive molding compound over the top surface of the device substrate and encompassing the first transistor die, the second die, a portion of the first input lead, and a portion of the first output lead.. . ... Freescale Semiconductor Inc

03/24/16 / #20160087333

Integrated circuit package

An integrated circuit package has a first side and an opposite second side. The integrated circuit package comprises: a stack of layers comprising at least a first and second electrically isolating layers, a dielectric material arranged on the stack of layers at the second side for encapsulating the integrated circuit package, a first integrated antenna structure for transmitting and/or receiving a first radio frequency signal, and a first array of electrically conductive vias extending through at least the first electrically isolating layer and the dielectric material. ... Freescale Semiconductor Inc

03/24/16 / #20160087057

Low resistance polysilicon strap

A low resistance polysilicon (poly) structure includes a first poly coupled to a substrate and having a sidewall. A second poly is separated from the sidewall of the first poly and the substrate by a programming oxide. ... Freescale Semiconductor Inc

03/24/16 / #20160086930

Fan-out wafer level package containing back-to-back embedded microelectronic components and assembly method therefor

Fan-out wafer level packages (fo-wlps) include double-sided molded package bodies in which first and second layers of components are embedded in a back-to-back relationship. In one embodiment, the fo-wlp fabrication method includes positioning a first microelectronic component carried by a first temporary substrate in a back-to-back relationship with a second microelectronic component carried by a second temporary substrate. ... Freescale Semiconductor Inc

03/24/16 / #20160086880

Copper wire through silicon via connection

A semiconductor device includes a semiconductor substrate having opposing first and second main surfaces, a via (tsv) extending from the first main surface of the substrate to the second main surface of the substrate, first electrical connectors formed near the first main surface and second electrical connectors formed near the second main surface. There are insulated bond wires, each extending through the via and having a first end bonded to a respective one of the first electrical connectors and a second end bonded to a respective one of the second electrical connectors. ... Freescale Semiconductor Inc

03/24/16 / #20160085687

Memory management component

A memory management component arranged to receive memory access transactions and provide memory management functionality therefor, and a method of providing memory management functionality within a processing system are disclosed. The memory management component comprises a first memory management module arranged to provide memory management functionality for received memory access transactions in accordance with a paging memory management scheme, and at least one further memory management module arranged to provide memory management functionality for received memory access transactions in accordance with an address range memory management scheme.. ... Freescale Semiconductor Inc

03/24/16 / #20160085618

Electronic device having a runtime integrity checker

An electronic device has a runtime integrity checker for monitoring contents of storage locations in an address range. The runtime integrity checker has a location selector for selecting the storage locations by generating addresses within the address range for locations to be checked, an interface unit coupled to the location selector for receiving the addresses for accessing the locations to be checked via a bus interface, and a processor coupled to the interface unit for retrieving the contents from the locations to be checked. ... Freescale Semiconductor Inc

03/24/16 / #20160085545

Method and apparatus for implementing inter-component function calls

A method of implementing inter-component function calls. The method comprises generating a lower tier indirection data structure comprising an entry indicating a location in memory of a function within a first software component, a higher tier indirection data structure comprising an entry indicating a location in memory of the lower tier indirection data structure, and a configuration data structure comprising an entry defining an active version of the first software component. ... Freescale Semiconductor Inc

03/24/16 / #20160085479

Interface system and method

An interface system has a first media access controller having a first mac buffer for storing at least one first-type frame in a first frame format according to a first communication protocol. A time synchronization module is arranged to, upon detecting the start of the first-type frame, determine a first timestamp from a master clock signal and latch the first timestamp into a first timestamp register. ... Freescale Semiconductor Inc

03/24/16 / #20160085279

Method for resetting an electronic device having independent device domains

A reset state control circuit adapted to reset independent device domains of an electronic device, said reset state control circuit comprising a capturing unit adapted to capture reset events; and a reset shaping logic adapted to change dynamically a reset control flow to reset device domains of said electronic device depending on a sequence of the reset events captured by said capturing unit.. . ... Freescale Semiconductor Inc

03/24/16 / #20160085261

Low voltage swing buffer

An apparatus includes a first circuit of a first type that couples an output node to a first power supply node in response to a first value of a control signal. The apparatus includes a second circuit of a second type to couple the output node to the first power supply node in response to a first value of a first signal having a first voltage swing. ... Freescale Semiconductor Inc

03/24/16 / #20160084913

Cell monitoring apparatus, battery monitoring apparatus, integrated circuit and method of monitoring a rechargeable cell

A cell monitoring apparatus includes a processor and memory arranged to execute code representing a linear time-invariant state transition model and a non-linear observation model are provided to model a rechargeable cell using at least a non-linear open circuit voltage, an internal resistance, a time-invariant distortion voltage across a reactive component block, and a distortion current component constituting an error of measurement of current flowing through the reactive component block. An estimator unit performs extended kalman filtering in respect of the state transition model and the observation model using the input state data in order to generate output state data. ... Freescale Semiconductor Inc

03/24/16 / #20160084903

Integrated circuit and method of operating an integrated circuit

An integrated circuit comprises a first functional unit and one or more other functional units. The first functional unit has an input for receiving data and an output for providing data. ... Freescale Semiconductor Inc

03/24/16 / #20160084872

Three-axis microelectromechanical systems devices

The embodiments described herein provide microelectromechanical systems (mems) devices, such as three-axis mems devices that can sense acceleration in three orthogonal axes (e.g., x-axis, y-axis, and z-axis). In general, the embodiments described can provide decoupling between the sense motions of all three axes from each other. ... Freescale Semiconductor Inc

03/24/16 / #20160084722

Differential pressure sensor assembly

A differential pressure sensor assembly includes a transducer having a first sensing surface and a second sensing surface. The second sensing surface is contained in a cavity. ... Freescale Semiconductor Inc

03/24/16 / #20160083249

Mems device with differential vertical sense electrodes

A mems device includes a first sense electrode and a first portion of a sense mass formed in a first structural layer, where the first sense electrode is fixedly coupled with the substrate and the first portion of the sense mass is suspended over the substrate. The mems device further includes a second sense electrode and a second portion of the sense mass formed in a second structural layer. ... Freescale Semiconductor Inc

03/17/16 / #20160080262

Domain name collaboration service using domain name dependency server

A domain name dependency server (dds) stores known relationships between domain names. In response to a domain relationship query from a local dns server for a given domain name, the dds supplies the domain names that are related to the given domain name. ... Freescale Semiconductor Inc

03/17/16 / #20160080140

A network receiver for a network using distributed clock synchronization and a method of adjusting a frequency of an internal clock of the network receiver

A network receiver for a network using distributed clock synchronization and a method of adjusting a frequency of an internal clock of the network receiver are provided. The network receiver receives from the network an input signal and has an internal clock for generating a clock signal. ... Freescale Semiconductor Inc

03/17/16 / #20160080002

Adaptive error correction codes (eccs) for electronic memories

Systems and methods for adaptive error correction codes (eccs) for electronic memories. In some embodiments, a memory device, may include a first memory having a plurality of address locations, each of the plurality of address locations having a number of storage bits configured to store data and one or more error correction bits corresponding to the data; and a second memory distinct from the first memory, the second memory having a plurality of entries, each of the plurality of entries configured to store one or more operation code bits relating to data stored at a corresponding address location in the first memory, the one or more operation code bits identifying an error correction scheme used to generate the one or more error correction bits at the corresponding address location in the first memory.. ... Freescale Semiconductor Inc

03/17/16 / #20160078253

Device having a security module

A device securely accesses data in a memory via an addressing unit which provides a memory interface for interfacing to a memory, a core interface for interfacing to a core processor and a first and second security interface. The device includes a security processor hsm for performing at least one security operation on the data and a remapping unit mmap. ... Freescale Semiconductor Inc

03/17/16 / #20160078251

Key storage and revocation in a secure memory system

A technique for providing access to a first storage structure of a system includes exposing a first key of a plurality of first keys stored in a second storage structure in response to a select code based on a plurality of corresponding select records stored in one-time programmable storage elements of the second memory structure. The technique includes providing the first key as a current first key of a memory access controller. ... Freescale Semiconductor Inc

03/17/16 / #20160077984

Mechanism for managing access to at least one shared integrated peripheral of a processing unit and a method of operating thereof

The present application relates to a mechanism for managing access to at least one shared integrated peripheral of a processing unit and a method of operating thereof. The mechanism is operative in an available state and a locked state. ... Freescale Semiconductor Inc

03/17/16 / #20160077904

Integrated circuit and method of detecting a data integrity error

An integrated circuit comprises a write bus coupled to a register for storing control data. A storage unit is arranged to store reference signature data encoding a reference collective state of the register. ... Freescale Semiconductor Inc

03/17/16 / #20160077870

Starvation control in a data processing system

A data processing system (100) includes a main list (126) of tasks, main scheduling scheme, a starvation list (128) of tasks, and a secondary scheduling scheme. A method identifies tasks in the main list that are potentially-starving tasks and places the potentially-starving tasks in the starvation list. ... Freescale Semiconductor Inc

03/17/16 / #20160077542

Method and apparatus for control of a switched current circuit

An apparatus and corresponding method are provided to control a switched current circuit by switching the switched current circuit into an on-state, waiting an amount of waiting an amount of time tb after the current within the switched current circuit increases above a current threshold, and switching the switched current circuit into an off-state after waiting the time tb. Further, a duration of time ta1 between switching the switched current circuit in the off-state and the point at which the current within the switched current circuit decreases below the current threshold is determined, and the method includes waiting a time ta2 after the current within the switched current circuit decreased below the current threshold, the time ta2 based at least in part on the time ta1, after which the switched current circuit is switched into the on-state.. ... Freescale Semiconductor Inc

03/17/16 / #20160077537

A low drop-out voltage regulator and a method of providing a regulated voltage

A low drop-out voltage regulator, an integrated circuit, a sensor and a method of providing a regulated voltage are provided. The low drop-out voltage regulator comprises a regulated voltage driver for providing the regulated voltage in response to a control voltage, a feedback-loop circuit for generating the control signal such that the regulated voltage driving circuit provides the regulated voltage, and a pull-up circuit for pulling up the regulated voltage to a supply voltage when a difference between the supply voltage and the control voltage is smaller than a predetermined threshold value. ... Freescale Semiconductor Inc

03/17/16 / #20160077533

Voltage regulation system for integrated circuit

An integrated circuit (ic) includes a power grid having first, second, third, and fourth nodes for receiving first supply, first ground, second supply, and second ground voltage signals, respectively. A feedback circuit is connected to the second and fourth nodes for receiving the second supply and second ground voltage signals and generating a feedback voltage signal based on a difference between the second supply and second ground voltage signals. ... Freescale Semiconductor Inc

03/17/16 / #20160077196

Receiver system and method for receiver testing

A receiver system which may be implemented in an integrated circuit device and suitable for use in automotive radar systems such as collision avoidance systems, includes self test circuitry whereby a local oscillator test signal is generated by an on-board frequency multiplier and mixed in a down-conversion mixer with an rf test signal. The rf test signal is generated on the device by up-conversion of an externally generated low-frequency test signal with the local oscillator test signal. ... Freescale Semiconductor Inc

03/17/16 / #20160075553

Sensor protective coating

A microelectromechanical system (mems) sensor device includes a substrate, a support structure supported by the substrate, a membrane supported by the support structure and spaced from the substrate, and a polymer layer covering the membrane.. . ... Freescale Semiconductor Inc

03/10/16 / #20160072488

Voltage-driver circuit with dynamic slew rate control

A system for circuit for generating an output signal with a dynamically adjustable slew rate includes a sampler, an envelope detector, an envelope comparison and control circuit, and a voltage-driver circuit that includes output buffers for generating the output signal. The sampler generates a sampled signal indicative of the slew rate of the output signal. ... Freescale Semiconductor Inc

03/10/16 / #20160072484

Low swing flip-flop with reduced leakage slave latch

A data processing system includes first and second power distribution networks to provide power at first and second voltages, and a flip-flop. The second voltage is less than the first voltage. ... Freescale Semiconductor Inc

03/10/16 / #20160072451

Rf power transistor circuits

A radio frequency (rf) power transistor circuit includes a power transistor and a decoupling circuit. The power transistor has a control electrode coupled to an input terminal for receiving an rf input signal, a first current electrode for providing an rf output signal at an output terminal, and a second current electrode coupled to a voltage reference. ... Freescale Semiconductor Inc

03/10/16 / #20160072413

Method, computer program product and controller for starting-up a switched reluctance motor, and electrical apparatus implementing same

A method of starting-up a switched reluctance, sr, motor is provided. The method comprises simultaneously energizing a plurality of phases at a first time point with respective phase voltages that are substantially the same, until the motor rotor is stabilized in alignment with either one of the plurality of phases; simultaneously de-energizing the plurality of phases at a second time point that follows the first time point; monitoring a decrease of respective phase currents in the plurality of phases from a third time point that follows the second time point by a first predetermined time interval; determining a phase of alignment of the rotor using evaluation of the decrease of the phase currents following simultaneous de-energizing of the plurality of phases; and, initiating rotation of the rotor from the determined phase of alignment of the rotor.. ... Freescale Semiconductor Inc

03/10/16 / #20160071960

Non-volatile memory (nvm) cell and a method of making

A method of forming a flash memory cell includes forming a first hard mask and a second hard mask on a substrate. A select gate is formed as a spacer around the first hard mask. ... Freescale Semiconductor Inc

03/10/16 / #20160071943

Method to form self-aligned high density nanocrystals

Methods for fabricating dense arrays of electrically conductive nanocrystals that are self-aligned in depressions at target locations on a substrate, and semiconductor devices configured with nanocrystals situated within a gate stack as a charge storage area for a nonvolatile memory (nvm) device, are provided.. . ... Freescale Semiconductor Inc

03/10/16 / #20160071789

Molded interposer for packaged semiconductor device

A method for forming a pass-through layer of an interposer of a packaged semiconductor device in which conducting structures are extended between first and second ends of a casing. The conducting structures are subsequently encapsulated in a molding compound to form a molded bar, and the molded bar is sliced to obtain the pass-through layer. ... Freescale Semiconductor Inc

03/10/16 / #20160071495

Display controller device having a debug interface

A display controller device for processing image data has a data processor for generating a display signal. The device has a writeback unit having an input coupled to the display signal and an output coupled to a debug interface. ... Freescale Semiconductor Inc

03/10/16 / #20160071228

Data logging system and method

A data logging system for logging input data received from a data source is described. The data logging system has a data storage memory. ... Freescale Semiconductor Inc

03/10/16 / #20160070934

Memory controller

A memory controller used to verify authenticity of data stored in a first memory unit. The memory controller includes a secure memory unit which stores a pre-stored value representative of the authenticity of the data to be written in the first memory unit. ... Freescale Semiconductor Inc

03/10/16 / #20160070846

System for testing ic design

A method for testing an integrated circuit design exercises the design using a set of simulation signals, and partitions a representation of the design into a first set of active elements and a second set of inactive elements. Only the active elements of the first set are exercised using a second set of simulation signals during verification of the integrated circuit design.. ... Freescale Semiconductor Inc

03/10/16 / #20160070669

Multi-port transmitter device for transmitting at least partly redundant data, an associated control system, an associated method and an associated computer program product

A multi-port transmitter device for transmitting at least partly redundant data is described. The multi-port transmitter device comprises at least two transmitters comprising respective transmitter buffers. ... Freescale Semiconductor Inc

03/10/16 / #20160070666

Method of controlling direct memory access of a peripheral memory of a peripheral by a master, an associated circuitry, an associated device and an associated computer program product

A method of controlling direct memory access of a peripheral memory of a peripheral by a master is described. The method includes checking whether there is a pending request from the peripheral for a direct memory access service, establishing whether an access condition is satisfied in dependence on at least whether there is a pending request, and, if the access condition is satisfied, granting access to the master. ... Freescale Semiconductor Inc

03/10/16 / #20160070619

Method and apparatus for configuring i/o cells of a signal processing ic device into a safe state

A peripheral integrated circuit (ic) device for providing support to a data processing ic device. The peripheral ic device comprises a fault detection component arranged to detect an occurrence of fault conditions within the data processing ic device. ... Freescale Semiconductor Inc

03/10/16 / #20160069986

Radar device and method of operating a radar device

A radar device includes a rf signal source, two or more antenna interface units, a feed network, and a control unit. The rf signal source is arranged to provide a rf signal; each of the antenna interface units includes an antenna port and one of the following an amplifier and a mixer; the feed network includes two or more buffers, each buffer has an active and an inactive state; the control unit is arranged to generate or receive a selection signal which specifies none, one, or more of the antenna interface units as active antenna interface units and the remaining antenna interface units as inactive antenna interface units; the control unit is arranged to activate and deactivate the buffers in dependence on the selection signal so as to feed the rf signal to the none, one, or more active antenna interface units and not to the inactive antenna interface units.. ... Freescale Semiconductor Inc

03/10/16 / #20160069763

Semiconductor sensor device formed with gel sheet

A method for assembling a pressure sensor device uses a pressure-sensitive gel material that is applied to an active region of a pressure-sensing integrated circuit (ic) die. A molding compound is dispensed over the pressure-sensitive gel material to encapsulate the gel material. ... Freescale Semiconductor Inc

03/03/16 / #20160066052

Television receiver, television set, and method for updating program schedule information in a television receiver

. . A television receiver, comprising a television signal input, a tuner, a frame buffer, a control input, a pattern recognition unit, and an electronic program guide unit. In operation, the television signal input receives a television signal. ... Freescale Semiconductor Inc

03/03/16 / #20160065250

Wireless communication unit, integrated circuits and method for linearizing a transmitter signal

A wireless communication unit comprising a transmitter comprises: a linearization circuit arranged to receive and digitally distort an input signal; a radio frequency power amplifier operably coupled to the linearization circuit and arranged to amplify a radio frequency representation of the digitally distorted input signal; a feedback path arranged to feed back a portion of the amplified digitally distorted output of the received input signal to the linearization circuit; a bypass circuit comprising a plurality of energy storage elements operably coupled between an output of the radio frequency power amplifier and ground; and a first connector arranged to provide a representation of at least one electrical memory effect of at least one of the plurality of energy storage elements to the linearization circuit, wherein the linearization circuit is arranged to use the representation of the at least one electrical memory effect when digitally distorting the input signal.. . ... Freescale Semiconductor Inc

03/03/16 / #20160065225

Method for re-centering a vco, integrated circuit and wireless device

A method of re-centering a voltage controlled oscillator of a wireless device comprising a phase locked loop circuit is described. The method comprises receiving an input frequency signal at a phase detector of the phase locked loop circuit from a frequency source; generating an oscillator signal based on the received frequency signal; selectably opening a feedback loop of the phase locked loop circuit when in a calibration mode of operation, performing coarse frequency tuning of the oscillator output signal; performing fine frequency tuning of a coarsely adjusted oscillator output signal; and closing the feedback loop.. ... Freescale Semiconductor Inc

03/03/16 / #20160065131

Integrated circuit comprising a frequency dependent circuit, wireless device and method of adjusting a frequency

An integrated circuit comprises a frequency dependent circuit comprising an input node, an output node and a main bank of selectable first capacitive elements that affect a frequency characteristic of the frequency dependent circuit. The frequency dependent circuit further comprises at least one shunt bank of selectable second capacitive elements located between ground and one of the input node or the output node, wherein at least one selectable second capacitive element switched out of the frequency dependent circuit is based on a number of the selectable first capacitive elements that are switched into the frequency dependent circuit.. ... Freescale Semiconductor Inc

03/03/16 / #20160065114

Device for controlling a multi-phase motor

An electronic device is for controlling motor drive circuits for driving a multi-phase motor in a force assisted system. Each motor drive circuit selectively permitting current to flow into or out of a respective phase of the multi-phase motor connected to the motor drive circuit in response to being driven by respective control signals. ... Freescale Semiconductor Inc

03/03/16 / #20160064792

Radio frequency coupling structure and a method of manufacturing thereof

A radio frequency transmission structure couples a rf signal between a first and a second radiating elements arranged at a first and a second sides of a first dielectric substrate, respectively. The rf coupling structure comprises: a hole arranged through the first dielectric substrate, a first electrically conductive layer arranged on a first wall of the hole to electrically connect a first and a second signal terminals, a second electrically conductive layer arranged on a second wall of the hole opposite to the first wall to electrically connect a first and a second reference terminals. ... Freescale Semiconductor Inc

03/03/16 / #20160064556

Trench gate fet with self-aligned source contact

A semiconductor device includes a substrate and a semiconductor layer having a first conductivity type. The semiconductor device further includes first and second trenches extending into the semiconductor layer from a surface of the semiconductor layer, each of the first and second trenches including a corresponding gate electrode. ... Freescale Semiconductor Inc

03/03/16 / #20160064546

Edge termination for trench gate fet

A semiconductor device includes a semiconductor layer disposed at a substrate and a plurality of active cells disposed at the semiconductor layer. Each active cell includes a trench extending into the semiconductor layer and a body region disposed in the semiconductor layer adjacent to a sidewall of the trench and at a first depth below the surface of the semiconductor layer. ... Freescale Semiconductor Inc

03/03/16 / #20160064356

Semiconductor device package with organic interposer

A method of making an integrated circuit package, such as a ball grid array, includes providing a flexible tape that has first and second sets of bond pads on respective first and second surfaces thereof. A carrier is attached to the first surface of the flexible tape. ... Freescale Semiconductor Inc

03/03/16 / #20160064324

Semiconductor package with embedded capacitor and methods of manufacturing same

A semiconductor package with an embedded capacitor and corresponding manufacturing methods are described. The semiconductor package with the embedded capacitor includes a semiconductor die having a first metal layer extending across at least a portion of a first side of the semiconductor die and a package structure formed on the first side of the semiconductor die. ... Freescale Semiconductor Inc

03/03/16 / #20160063149

Design tool apparatus, method and computer program for designing an integrated circuit

An integrated circuit design tool apparatus includes a processing resource configured to support a circuit simulator, a circuit sensitivity optimiser and a circuit sensitivity calculator. The circuit sensitivity optimiser is adapted to communicate to the circuit simulator a first dynamic list of selected devices of the circuit; and a second dynamic list of selected process parameters associated with the selected devices of the first dynamic list. ... Freescale Semiconductor Inc

03/03/16 / #20160062874

Debug architecture for multithreaded processors

Debug architecture for multithreaded processors. In some embodiments, a method includes, in response to receiving a halt command, saving a context of a thread being executed by a processor core to a context memory distinct from the processor core; suspending execution of the thread; and initiating a debug of the thread using the context stored in the context memory. ... Freescale Semiconductor Inc

03/03/16 / #20160062862

Data processing system with debug control

A data processing system includes a processor configured to execute processor instructions and a memory. The memory has a data array and a checkbit array wherein each entry of the checkbit array includes a plurality of checkbits and corresponds to a storage location of the data array. ... Freescale Semiconductor Inc

03/03/16 / #20160062810

Methods and apparatus for detecting software inteference

The present application relates to an apparatus for detecting software interference and the method of operating thereof. A processor and at least one shared resource form a computing shell to execute a first, functional safety critical application and at least one second application in time-shared operation. ... Freescale Semiconductor Inc

03/03/16 / #20160062806

Method and device for detecting a race condition and a computer program product

A method is provided for detecting a race condition of a parallel task when accessing a shared resource in a multi-core processing system. The method requires that a core requires only a read access to the data set of another core thereby ensuring better decoupling of the tasks. ... Freescale Semiconductor Inc

03/03/16 / #20160062797

System and method for dynamically managed task switch lookahead

A processing system includes a processor pipeline, a detector circuit, and a task scheduler. The detector circuit includes a basic block detector circuit to determine that the processor pipeline received a first instruction of a first instance of a basic block, and to determine that a last-in-order instruction of the first instance of the basic block is a resource switch instruction (rswi), and an indicator circuit to provide an indication in response to determining that the processor pipeline received the first instruction of a second instance of the basic block. ... Freescale Semiconductor Inc

03/03/16 / #20160062751

Method and apparatus for optimising computer program code

A method and apparatus for optimising computer program code. The method comprises identifying at least one set of candidate instructions within the computer program code, each candidate instruction comprising an instruction for writing a constant value to memory and the at least one set comprising a plurality of candidate instructions. ... Freescale Semiconductor Inc

03/03/16 / #20160062656

Command set extension for non-volatile memory

A method and apparatus are provided for generating an adjusted internal electrical parameter for accessing a nand flash memory array based on an adjustment control parameter conveyed by a memory access instruction, where the memory access instruction is compliant with an open nand flash interface (onfi) protocol to include a two command cycle sequence to specify a command for accessing the nand flash memory with the adjusted internal electrical parameter.. . ... Freescale Semiconductor Inc

03/03/16 / #20160062331

Apparatus and method for validating the integrity of control signals in timing domain

The present application relates to a signal integrity module for validating one or more control signals in time domain and a method thereof. The one or more control signals are received via a signal input from at least one control signal generating unit. ... Freescale Semiconductor Inc

03/03/16 / #20160061898

Wetting current diagnostics

A method of providing wetting current diagnostics for a load control switch includes changing test switch settings of a detection circuit from an operational configuration to a testing configuration. The test switch settings specify respective states of first and second test switches of the detection circuit. ... Freescale Semiconductor Inc

03/03/16 / #20160061891

Mixed mode integrated circuit, method of providing a controllable test clock signal to a sub-circuitry of the mixed-mode integrated circuit and method of detecting current paths causing violations of electromagnetic compatibility standards in the mixed mode integrated circuit

A mixed mode integrated circuit, a method of providing a controllable test clock signal to a sub-circuitry of the mixed-mode integrated circuit and a method of detecting current paths causing violations of electromagnetic compatibility standards in the mixed mode integrated circuit are provided. The mixed mode integrated circuit 100 comprises in addition to a clock network 110 an integrated test clock signal generator 140 to generate test clock signals that are provided via controllable multiplexers 150, 160 to an analogue and digital sub-circuitry, respectively, of the mixed-mode integrated circuit. ... Freescale Semiconductor Inc

03/03/16 / #20160061890

Integrated circuit device and method of performing self-testing within an integrated circuit device

Ic device comprising a plurality of functional components arranged into self-test cells. The ic device is configurable into a first self-test configuration comprising a first set of self-test partitions. ... Freescale Semiconductor Inc

03/03/16 / #20160061870

Electric power meter

An electric power meter for measuring electric power is provided. The power meter has a frequency domain converter arranged to convert a sequence of digital voltage samples from the time domain to a frequency domain obtaining digital voltage frequency components, and to convert a sequence of digital current samples from the time domain to the frequency domain obtaining digital current frequency components. ... Freescale Semiconductor Inc

03/03/16 / #20160061867

Method and apparatus for metering a voltage signal

A voltage metering module for metering a voltage signal at least one analogue to digital converter (adc) component arranged to receive at an input thereof a voltage signal and to generate a digital signal representative of the received voltage signal. The at least one adc component includes at least one sampling network controllable to sample the received voltage signal for conversion to a digital signal representative of the received voltage signal and at least one compensation network operably coupled in parallel with the sampling network and controllable to sample the received voltage signal such that an input current of the compensation network at least partially compensates for a component of an input current of the sampling network.. ... Freescale Semiconductor Inc

02/25/16 / #20160056811

Testable power-on-reset circuit

An integrated circuit with a testable power-on-reset (por) circuit includes a voltage divider, an inverter, a level-shifter, a buffer and a flip-flop. The voltage divider receives a first supply voltage and generates a second supply voltage. ... Freescale Semiconductor Inc

02/25/16 / #20160056765

Frequency selective isolation circuit and method for suppressing parametric oscillation

In a system comprising a plurality of gain elements configured in parallel to one another, a harmonically tuned filter provides an isolation circuit to prevent odd-mode differential oscillations. A harmonically tuned filter comprises resistors, inductors, and capacitors (rlc) to selectively allow one or more specific harmonics to pass through the isolation circuit to suppress the odd-mode oscillation. ... Freescale Semiconductor Inc

02/25/16 / #20160056741

Device for determining a position of a rotor of an electric motor

A device for determining a rotor position in a polyphase electric motor has a power control unit for applying drive voltages according to a pulse width modulation scheme so as to synchronously drive the motor. A measurement unit is arranged for measuring a voltage value on a respective phase by determining a zero-crossing interval where the phase current is around zero, disconnecting the phase from the respective drive voltage during the zero-crossing interval, and measuring the voltage value when the drive voltage of a first other phase is the supply voltage and the drive voltage of a second other phase is the zero voltage. ... Freescale Semiconductor Inc

02/25/16 / #20160056234

Deep trench isolation structures and systems and methods including the same

Deep trench isolation structures and systems and methods including the same are disclosed herein. The systems include a semiconductor device. ... Freescale Semiconductor Inc

02/25/16 / #20160056114

Trenched faraday shielding

A device includes a semiconductor substrate having a surface with a trench, first and second conduction terminals supported by the semiconductor substrate, a control electrode supported by the semiconductor substrate between the first and second conduction terminals and configured to control flow of charge carriers during operation between the first and second conduction terminals, and a faraday shield supported by the semiconductor substrate and disposed between the control electrode and the second conduction terminal. At least a portion of the faraday shield is disposed in the trench.. ... Freescale Semiconductor Inc

02/25/16 / #20160056099

Integrated circuit with on-die decoupling capacitors

A semiconductor device has an on-die decoupling capacitor that is shared between alternative high-speed interfaces. A capacitance pad is connected to the decoupling capacitor and internal connection pads are connected respectively to the alternative interfaces. ... Freescale Semiconductor Inc

02/25/16 / #20160056094

Ball grid array package with more signal routing structures

A semiconductor package includes a substrate, a die mounted on a first side of the substrate, an array of solder balls mounted on a second, opposite side of the substrate, and a signal-routing structure mounted on the first side of the substrate and adjacent to the die. The substrate and the signal-routing structure provide electrical connections between die pads on the die and some of the solder balls.. ... Freescale Semiconductor Inc

02/25/16 / #20160054995

Single-instruction multiple data processor

In accordance with at least one embodiment, a processor system is disclosed having a simd processor device that has a plurality of subsidiary processing elements that are controlled to process multiple data concurrently. In accordance with at least one embodiment, the simd processor is a vector processor (vpu) having a plurality of vector arithmetic units (aus) as subsidiary processing elements, and the vpu executes an instruction to transfer table information from a global memory of the vpu to a plurality of local memories accessible by each au. ... Freescale Semiconductor Inc

02/25/16 / #20160054746

Voltage regulation system for integrated circuit

An integrated circuit (ic) includes a power grid having first, through fourth nodes for receiving first supply, first ground, second supply, and second ground voltage signals, respectively, a voltage regulator, a reference voltage calibration circuit, a dual-rail sense circuit, and a voltage monitor circuit. The reference voltage calibration circuit receives the first supply, first ground, second supply, and second ground voltage signals and generates a reference voltage signal based on differences between voltage levels of the first supply and ground voltage signals, and the second supply and ground voltage signals. ... Freescale Semiconductor Inc

02/18/16 / #20160049905

Oscillator circuit and method of providing temperature compensation therefor

An oscillator circuit comprising at least a first component arranged to be statically calibrated to calibrate the oscillator circuit to achieve a symmetrical frequency/temperature profile for the oscillator circuit. The oscillator circuit further comprises at least one further component arranged to be dynamically calibrated to enable an oscillating frequency of the oscillator circuit to be dynamically adjusted, and at least one temperature compensation component arranged to receive at least one temperature indication for the oscillator circuit and to dynamically adjust the at least one further component based at least partly on the at least one received temperature indication. ... Freescale Semiconductor Inc

02/18/16 / #20160049508

Bidirectional trench fet with gate-based resurf

A device includes a semiconductor substrate having a surface, a trench in the semiconductor substrate extending vertically from the surface, a body region laterally adjacent the trench, spaced from the surface, having a first conductivity type, and in which a channel is formed during operation, a drift region between the body region and the surface, and having a second conductivity type, a gate structure disposed in the trench alongside the body region, recessed from the surface, and configured to receive a control voltage is applied to control formation of the channel, and a gate dielectric layer disposed along a sidewall of the trench between the gate structure and the body region. The gate structure and the gate dielectric layer have a substantial vertical overlap with the drift region such that electric field magnitudes in the drift region are reduced through application of the control voltage.. ... Freescale Semiconductor Inc

02/18/16 / #20160049303

Method for forming a memory structure having nanocrystals

A method of forming a semiconductor structure uses a substrate. A first insulating layer is formed over the substrate. ... Freescale Semiconductor Inc

02/18/16 / #20160048629

Automatic generation of test layouts for testing a design rule checking tool

A method of automatically generating a set of test layouts for testing a design rule checking tool is described. A layout is a point in a space of several coordinates, and the design rule comprises n design constraints numbered 1 to n, wherein n is greater or equal two and each design constraint is a boolean-valued function of one or more of the coordinates. ... Freescale Semiconductor Inc

02/18/16 / #20160048390

Method for automated managing of the usage of alternative code and a processing system of operating thereof

The present application relates to a method and a processing system for automated managing of the usage of alternative code. Code sections including original code and alternative code are retrieved from a code basis and the retrieved code is analyzed to detect an alternative code section. ... Freescale Semiconductor Inc

02/18/16 / #20160048155

Reset circuitry for integrated circuit

An on-board reset circuit for a system-on-chip (soc) addresses the problem of meta-stability in flip-flops on asynchronous reset that arises when different power domains or reset domains receive resets from different sources. To ameliorate the problem, a reset signal is asserted and de-asserted while the clocks are gated. ... Freescale Semiconductor Inc

02/18/16 / #20160048147

Voltage regulation subsystem

A voltage regulation subsystem for a microprocessor has both internal and external regulation modes. An internal auxiliary voltage regulator is selectively enabled to overdrive the voltage. ... Freescale Semiconductor Inc

02/18/16 / #20160047696

Temperature sensor circuit

A temperature sensor circuit implemented in electronic circuitry that senses the temperature at a site, digitizes the sensed temperature, and then outputs a signal representing such a sensed temperature. The temperature sensor circuit converts a voltage signal that is proportional to the temperature to a first digital value. ... Freescale Semiconductor Inc

02/11/16 / #20160043039

Semiconductor device with an isolation structure coupled to a cover of the semiconductor device

A system and method for packaging a semiconductor device that includes a structure to reduce electromagnetic coupling are presented. The semiconductor device is formed on a substrate. ... Freescale Semiconductor Inc

02/11/16 / #20160042246

A haar calculation system, an image classification system, associated methods and associated computer program products

A compute engine is arranged to retrieve a block of image data corresponding to a rectangular image region; calculate integral image values for all pixels of the block of image data to obtain an integral image of the block of image data; and store the integral image of the block in the one or more memories. The main processor determines which blocks of image data comprise pixels of the predefined rectangular region of the image, and defines a respective rectangular region part as the pixels of the block that belong to the predefined rectangular region of the image; calculate a haar feature of the rectangular region part for each block of image data that comprise pixels of the predefined rectangular region of the image; and add the haar features of the rectangular region parts to obtain the haar feature of the predefined rectangular region of the image.. ... Freescale Semiconductor Inc

02/11/16 / #20160041579

Timing synchronization circuit for wireless communication apparatus

A transmission node includes a digital front-end device that provides functional clocks for jesd204b based data transmission. The front-end device includes a pll for generating a phase locked clock based on a device clock of the front-end device, a clock dividing unit for generating the functional clocks by dividing the phase locked clock, a clock gating unit connected between the pll and the clock dividing unit, and a system reference signal sampling unit for timing radio frame boundaries. ... Freescale Semiconductor Inc

02/11/16 / #20160041571

Current generator circuit and method of calibration thereof

A current generator circuit includes at least one current generation component arranged to generate an output current of the current generator circuit, at least one absolute current calibration component arranged to enable calibration of an absolute current value of the output current, and at least one temperature coefficient calibration component arranged to enable calibration of a temperature coefficient characteristic of the output current. The at least one temperature coefficient calibration component is further arranged to be in a passive state at a reference temperature.. ... Freescale Semiconductor Inc

02/04/16 / #20160037186

Method and video system for freeze-frame detection

A method for detecting a freeze-frame condition comprises receiving a sequence of images from at least one digital device; selectively encoding a first subset of the sequence of images using a first coding scheme that causes an adjustment to an image characteristic of the selected images being encoded; selectively encoding a second subset of the sequence of images using a second coding scheme; storing the first encoded subset and second encoded subset; retrieving the stored first encoded subset and second encoded subset; selectively decoding the first subset of the selected images using the first coding scheme and selectively decoding the second subset of the selected images using the second coding scheme to re-create the sequence of images. A freeze-frame condition in the re-created sequence of images is identifiable based on a plurality of decoded images being different with respect to the image characteristic across multiple decoded image frames.. ... Freescale Semiconductor Inc

02/04/16 / #20160036463

Data storage device and method for protecting a data item against unauthorized access

A method for protecting a data item against unauthorized access and a data processing device is disclosed comprising a memory unit and a memory control unit to protect data items stored in the memory unit against prohibited access. Upon a write access the memory control unit forms a first data word comprising a data item and a first key; computes a first error-detection code; and stores the data item along with the first error-detection code. ... Freescale Semiconductor Inc

02/04/16 / #20160035822

High voltage semiconductor devices and methods for their fabrication

Semiconductor devices include: (a) a semiconductor substrate containing a source region and a drain region; (b) a gate structure supported by the semiconductor substrate between the source region and the drain region; (c) a composite drift region in the semiconductor substrate, the composite drift region extending laterally from the drain region to at least an edge of the gate structure, the composite drift region including dopant having a first conductivity type, wherein at least a portion of the dopant is buried beneath the drain region at a depth exceeding an ion implantation range; and (d) a well region in the semiconductor substrate, wherein the well region has a second conductivity type and wherein the well region is configured to form a channel therein under the gate structure during operation of the semiconductor device. Methods for the fabrication of semiconductor devices are described.. ... Freescale Semiconductor Inc

02/04/16 / #20160035433

Memory array with ram and embedded rom

A memory array with ram and embedded rom including multiple ram cells, a rom cell, and a rom enable circuit. Each ram cell has a ram cell structure with a first and second power terminals and configured to operate as a ram cell when the memory array is in a ram mode. ... Freescale Semiconductor Inc

02/04/16 / #20160035415

Non-volatile memory using bi-directional resistive elements

A memory cell includes a single bi-directional resistive memory element (brme) having a first terminal directly connected to a first power rail and a second terminal coupled to an internal node; and a first transistor having a control electrode coupled to the internal node, and a first current electrode coupled to a first bitline, and a second current electrode coupled to one of a group consisting of: a read wordline and the first power rail.. . ... Freescale Semiconductor Inc

02/04/16 / #20160034398

Cache-coherent multiprocessor system and a method for detecting failures in a cache-coherent multiprocessor system

A cache-coherent multiprocessor system comprising processing units, a shared memory resource accessible by the processing units, the shared memory resource being divided into at least one shared region, at least one first region, and at least one second region, a first cache, a second cache, a coherency unit, and a monitor unit, wherein the monitor unit is adapted to generate an error signal, when the coherency unit affects the at least one first region due to a memory access from the second processing unit and/or when the coherency unit affects the at least one second region due to a memory access from the first processing unit, and a method for detecting failures in a such a cache-coherent multiprocessor system.. . ... Freescale Semiconductor Inc

02/04/16 / #20160034344

Error repair location cache

A method for repairing a memory includes executing an error correction code (ecc) for a page of the memory. The page includes a plurality of bits having an inherent number of failed bits equal to or greater than zero. ... Freescale Semiconductor Inc

02/04/16 / #20160034291

System on a chip and method for a controller supported virtual machine monitor

A system on a chip comprising: a first communication controller; at least one second communication controller operably coupled to the first communication controller; at least one processing core operably coupled to the first communication controller and arranged to support software running on a first partition and a second partition; and a virtual machine monitor located between the first and second partitions, and the at least one processing core and arranged to support communications there between. The first communication controller is arranged to: generate or receive at least one data frame; and communicate the at least one data frame to the at least one second communication controller; such that the at least one second communication controller is capable of routing the at least one data frame to the second partition bypassing the virtual machine monitor.. ... Freescale Semiconductor Inc

02/04/16 / #20160033567

Crystal oscillator monitoring circuit

In an integrated circuit, a clock monitor circuit detects when an analog clock signal output by an on-chip crystal oscillator has stabilized. The clock monitor circuit uses an envelope follower circuit to monitor the envelope of the analog clock signal and compare the amplitude of the envelope with a predetermined amplitude value. ... Freescale Semiconductor Inc

02/04/16 / #20160033560

Mode-controlled voltage excursion detector apparatus and a method of operating thereof

The present application relates to a mode-controlled voltage excursion detector apparatus for monitoring a supply voltage of a power supply applied to a load and a method of operating thereof. A voltage monitor is configured to detect an excursion event if the supply voltage exceeds or falls below at least one defined threshold, to generate an excursion event signal upon detection of the excursion event and to provide the generated excursion event signal to the excursion event output for being outputted via an excursion event output. ... Freescale Semiconductor Inc

02/04/16 / #20160032852

Method of calibrating a crank angle of a combustion engine

The present application provides a calibration device for calibrating a crank angle of a calibrateable combustion engine, the calibrateable combustion engine and a method for calibrating. The calibration device is provided to determine a trigger wheel angle offset from a combustionless driving of the combustion engine in that an in-cylinder pressure profile is recorded, on the basis of which a trigger wheel angle offset is determined and stored at an offset memory of the combustion engine. ... Freescale Semiconductor Inc

01/28/16 / #20160028385

System and method for clocking integrated circuit

A system and method of clocking an integrated circuit (ic) includes determining operating characteristics of the ic. The ic has multiple domains and each domain receives a respective domain clock signal. ... Freescale Semiconductor Inc

01/28/16 / #20160028377

Resistance detection for integrated circuit driver

An ic driver includes a resistor detector to detect whether at least a threshold resistance is present between a pin of the ic driver and the gate of an igbt. The resistor detector can include a comparator that compares a voltage at the collector of the igbt to a threshold reference voltage (e.g., ground). ... Freescale Semiconductor Inc

01/28/16 / #20160027992

Package-in-package semiconductor sensor device

A semiconductor sensor device includes a device substrate, a micro-controller unit (mcu) die attached to the substrate, and a packaged pressure sensor having a sensor substrate and a pressure sensor die. The sensor substrate has a front side with the pressure sensor die attached to it, a back side, and an opening from the front side to the back side. ... Freescale Semiconductor Inc

01/28/16 / #20160027768

Synthesis of complex cells

Hierarchical layout synthesis of complex cells. In some embodiments, a method may include partitioning a cell into a plurality of subcells, where the cell represents a set of electronic components in an integrated circuit; identifying, among the plurality of subcells, a most complex subcell; synthesizing a layout of the most complex subcell for each of one or more side-port configurations; selecting a side-port configuration based upon the layout of the most complex subcell; and synthesizing a layout of one or more of the plurality of subcells neighboring the most complex subcell by propagating one or more constraints associated with the selected side-port configuration.. ... Freescale Semiconductor Inc

01/28/16 / #20160027529

Address fault detection circuit

A semiconductor memory device and method of operation are provided for a multi-bank memory array (100) with an address fault detector circuit (24, 28) connected to split word lines (wln-wlm) across multiple banks, where the address fault detector circuit includes at least a first mosfet transistor (51-54) connected to each word line for detecting an error-free operation mode and a plurality of different transient address faults including a “no word line select,” “false word line select,” and “multiple word line select” failure mode at one of the first and second memory banks. In selected embodiments, the address fault detector provides resistive coupling (33-40) between split word lines across multiple banks to create interaction or contention between split word lines to create a unique voltage level on a fault detection bit line during an address fault depending on the fault type.. ... Freescale Semiconductor Inc

01/28/16 / #20160026829

Tamper detector with hardware-based random number generator

A system includes a tamper detector that includes a linear feedback shift register (lfsr) for generating pseudorandom coded detection signals as a function of seed values and a generator polynomial. The generator polynomial is loaded from a controller to the lfsr via software, and the seed values are directly loaded from a hardware-based random number generator to the lfsr. ... Freescale Semiconductor Inc

01/28/16 / #20160026203

Current source, an integrated circuit and a method

The present invention provides a current source comprising a first bias current control element, the first bias current control element being configured to generate a first current if the control value is lower than a reference value and configured to generate a second current if the control value equal to or higher than the reference value. In addition or alternatively the bias current source comprises a second bias current control element, the second bias current control element being configured to generate a third current if the control value is lower than or equal to the reference value and configured to generate a fourth current if the control value is higher than the reference value. ... Freescale Semiconductor Inc

01/28/16 / #20160025808

Method and system for logic built-in self-test

A controller executes a first lbist test on a device at a first shift frequency on a plurality of partitions and detects any voltage drop at sense points in each partition during the test. If a voltage drop is detected, then the test is re-run for those partitions that failed the first test. ... Freescale Semiconductor Inc

01/21/16 / #20160021734

Semiconductor device with active shielding of leads

A semiconductor device has a multi-wire lead and a die having a multi-site bond pad. A shielding wire and a guarded wire both extend from the multi-wire lead to the multi-site bond pad. ... Freescale Semiconductor Inc

01/21/16 / #20160020278

Applications for nanopillar structures

A disclosed method of fabricating a hybrid nanopillar device includes forming a mask on a substrate and a layer of nanoclusters on the hard mask. The hard mask is then etched to transfer a pattern formed by the first layer of nanoclusters into a first region of the hard mask. ... Freescale Semiconductor Inc

01/21/16 / #20160020189

Flexible packaged integrated circuit

A method for assembling a thin, flexible integrated circuit (ic) device includes using an etched contoured lead frame having raised features. A die is attached to the lead frame to form a sub-assembly that is then selectively coated with a low-modulus gel. ... Freescale Semiconductor Inc

01/21/16 / #20160020182

Wire bond mold lock method and structure

A method and apparatus are described for fabricating a microchip structure (70) which protects interior electrical integrated circuits and components (120) attached to a lead frame die flag (104) using a molding compound (124) that mechanically interlocks with one or more positive mold lock structures formed as dummy wire loops (114) or stud bumps (214) that are attached to the lead frame (100) and/or die flag (104).. . ... Freescale Semiconductor Inc

01/14/16 / #20160013182

Semiconductor device and driver circuit with an active device and isolation structure interconnected through a diode circuit, and method of manufacture thereof

Embodiments of semiconductor devices and driver circuits include a semiconductor substrate having a first conductivity type, an isolation structure (including a sinker region and a buried layer), an active device within area of the substrate contained by the isolation structure, and a diode circuit. The buried layer is positioned below the top substrate surface, and has a second conductivity type. ... Freescale Semiconductor Inc

01/14/16 / #20160012254

Apparatus, a method and machine readable instructions for controlling performance of a process in response to a detected processing event

An apparatus including: circuitry configured to enable a delay of a process performed responsive to a detected processing event; and an configuration interface configured to enable pre-configuration by a user of at least one of one or more attributes of the delay, the process or the processing event.. . ... Freescale Semiconductor Inc

01/14/16 / #20160011259

Integrated circuit device and method therefor

An integrated circuit device comprising at least one self-test component arranged to execute self-testing within at least one self-test structure during a self-test execution phase of the ic device, and at least one clock control component arranged to provide at least one clock signal to the at least one self-test component at least during the self-test execution phase of the ic device. The at least one clock control component is further arranged to receive at least one indication of at least one power dissipation parameter for at least a part of the ic device, and modulate the at least one clock signal provided to the at least one self-test component based at least partly on the received at least one power dissipation parameter for at least a part of the ic device.. ... Freescale Semiconductor Inc

01/07/16 / #20160006399

Doherty amplifier

A two-way doherty amplifier for amplifying a modulated or non-modulated carrier signal, said carrier signal having a carrier frequency; wherein the doherty amplifier comprises a first amplifier having a first amplifier output node, a second amplifier having a second amplifier output node, a combining node connected or connectable to a load, a first amplifier output line connecting the first amplifier output node to the combining node, and a second amplifier output line connecting the second amplifier output node to the combining node, and wherein the first amplifier output line has an electrical length of substantially one quarter wavelength of the carrier signal and the second amplifier output line has an electrical length of substantially one half wavelength of the carrier signal.. . ... Freescale Semiconductor Inc

01/07/16 / #20160005730

Esd protection with asymmetrical bipolar-based device

An esd protection device is fabricated in a semiconductor substrate that includes a semiconductor layer having a first conductivity type. A first well implantation procedure implants dopant of a second conductivity type in the semiconductor layer to form inner and outer sinker regions. ... Freescale Semiconductor Inc

01/07/16 / #20160005682

Matrix lid heatspreader for flip chip package

A method and apparatus are provided for manufacturing a lead frame based thermally enhanced flip chip package with an exposed heat spreader lid array (310) designed for direct attachment to an array of integrated circuit die (306) by including a thermal interface adhesion layer (308) to each die (306) and encapsulating the attached heat spreader lid array (310) and array of integrated circuit die (306) with mold compound (321) except for planar upper lid surfaces of the heat spreader lids (312).. . ... Freescale Semiconductor Inc

01/07/16 / #20160004661

Usb transceiver

A universal serial bus (usb) controller includes a usb transceiver to detect a high-speed (hs) disconnect between the usb controller and a device connected to it. The usb transceiver includes a reference-voltage generation circuit, a hs current driver, first and second comparators, and a multiplexer. ... Freescale Semiconductor Inc

01/07/16 / #20160004654

System for migrating stash transactions

A system for migrating stash transactions includes first and second cores, an input/output memory management unit (iommu), an iommu mapping table, an input/output (i/o) device, a stash transaction migration management unit (stmmu), a queue manager and an operating system (os) scheduler. The i/o device generates a first stash transaction request for a first data frame. ... Freescale Semiconductor Inc

01/07/16 / #20160004536

Systems and methods for processing inline constants

Disclosed is a digital processor comprising an instruction memory having a first input, a second input, a first output, and a second output. A program counter register is in communication with the first input of the instruction memory. ... Freescale Semiconductor Inc

01/07/16 / #20160004292

Microcontroller with multiple power modes

A microcontroller operable in a high power mode and a low power unit (lpu) run mode includes primary and lpu domains, primary and lpu mode controllers, and primary and lpu clock generator modules. The primary domain includes a first set of circuits and a first set of cores. ... Freescale Semiconductor Inc

01/07/16 / #20160004274

Apparatus, a method and machine readable instructions for querying timers

An apparatus including: an input interface configured to enable user configuration of a future time window; and a report interface configured to produce a report relating to a first sub-set of a plurality of active timers that expire at programmed future points in time, wherein the first sub-set of the plurality of active timers expire during the user-configured future time window.. . ... Freescale Semiconductor Inc

01/07/16 / #20160003908

Method for testing comparator and device therefor

An integrated circuit facilitates a self test routine that verifies proper operation of an analog comparator. In response to entering the self test routine, the voltage provided to an input of a comparator is changed from being at an operating voltage supply to being at a self test voltage that is used to verify operation of the comparator. ... Freescale Semiconductor Inc








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