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Freescale Semiconductor Inc patents (2017 archive)


Recent patent applications related to Freescale Semiconductor Inc. Freescale Semiconductor Inc is listed as an Agent/Assignee. Note: Freescale Semiconductor Inc may have other listings under different names/spellings. We're not affiliated with Freescale Semiconductor Inc, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "F" | Freescale Semiconductor Inc-related inventors


Esd protection structure

An esd protection structure formed within a semiconductor substrate of an integrated circuit device. The esd protection structure comprises a thyristor structure being formed from a first p-doped section forming an anode of the thyristor structure, a first n-doped section forming a collector node of the thyristor structure, a second p-doped section, and a second n-doped section forming a cathode of the thyristor structure. ... Freescale Semiconductor Inc

Controlled pulse generation methods and apparatuses for evaluating stiction in microelectromechanical systems devices

Methods and apparatuses are provided for evaluating or testing stiction in microelectromechanical systems (mems) devices utilizing a mechanized shock pulse generation approach. In one embodiment, the method includes the step or process of loading a mems device, such as a multi-axis mems accelerometer, into a socket provided on a device-under-test (dut) board. ... Freescale Semiconductor Inc

Communication link adjustments in wireless networks based upon composite lqi measurements

Methods and systems are disclosed to adjust communication links within wireless networks based upon composite link quality indicators (lqis). Packet communications are received by a network node through a communication link from a separate network node within a wireless network. ... Freescale Semiconductor Inc

Clear channel assessment

Circuits and methods concerning signal detection are disclosed. In some example embodiments, an apparatus is configured to detect presence of a spreading sequence in a sample data sequence. ... Freescale Semiconductor Inc

Shielded and packaged electronic devices, electronic assemblies, and methods

Shielded and packaged electronic devices, electronic assemblies, and methods are disclosed herein. The shielded and packaged electronic devices include a packaged electronic device with a package surface and a plurality of electrically conductive package pads arranged on the package surface, a shielding dielectric layer extending in contact with the package surface and having a shielding layer surface and a plurality of openings that extends between the shielding layer surface and the plurality of electrically conductive package pads, and a plurality of electrical conductors that extends from the plurality of electrically conductive package pads and projects from the shielding layer surface. ... Freescale Semiconductor Inc

Method and apparatus for performing distributed computation of precoding estimates

A method and apparatus for performing distributed computation of precoding estimates within a das. An rrh comprises a receiver component arranged to receive uplink signals from active user devices. ... Freescale Semiconductor Inc

Method of wafer dicing for backside metallization

Method embodiments of wafer dicing for backside metallization are provided. One method includes: applying dicing tape to a front side of a semiconductor wafer, wherein the front side of the semiconductor wafer includes active circuitry; cutting a back side of the semiconductor wafer, the back side opposite the front side, wherein the cutting forms a retrograde cavity in a street of the semiconductor wafer, the retrograde cavity has a gap width at the back side of the semiconductor wafer, and the retrograde cavity has sidewalls with negative slope; depositing a metal layer on the back side of the semiconductor wafer, wherein the gap width is large enough to prevent formation of the metal layer over the retrograde cavity; and cutting through the street of the semiconductor wafer subsequent to the depositing the metal layer.. ... Freescale Semiconductor Inc

Mass storage system and method of storing mass data

A mass storage system for storing mass data generated by a mass data source. The system includes a data buffer coupled to the mass data source, and a file system and command generator. ... Freescale Semiconductor Inc

Kernel based cluster fault analysis

A fault analysis method comprises: receiving fault data from wafer level testing that identifies locations and test results of a plurality of die; applying a kernel transform to the fault data to produce cluster data, where the kernel transform defines a fault impact distribution that defines fault contribution from the failed die to local die within an outer radial boundary of the fault impact distribution. Applying the kernel transform comprises: centering the fault impact distribution at a location of each die that failed wafer level testing, associating each local die that falls within the outer radial boundary with a respective fault contribution value according to the fault impact distribution, and accruing fault contribution values associated with each respective die of the plurality of die to produce a cluster value for the respective die, which correlates to a probability of failure of the respective die at a future time.. ... Freescale Semiconductor Inc

Conversion rate control for analog to digital conversion

A method, apparatus, and energy metering system obtains mains samples of a mains power line signal, performs non-white noise (nwn) filtering of the mains power line signal, obtains adjustable clock source samples of an adjustable clock signal of an adjustable clock oscillator, determines a difference based on the mains samples and the adjustable clock source samples, adjusts an adjustable clock source frequency of the adjustable clock oscillator based on the difference, and applies the adjustable clock source frequency to an analog to digital converter (adc) to determine a conversion rate of the adc.. . ... Freescale Semiconductor Inc

Application specific low-power secure key

A key generator including a low-power key adjust circuit, and a high-power key adjust circuit. The low-power key adjust circuit including a storage location to store an original key, a shifter to shift the original key by a number of steps to shift to create a first key, and an output to provide the first key. ... Freescale Semiconductor Inc

Semiconductor device and method of making

A semiconductor device is disclosed that includes a first region of a first conductivity type that includes a drain, a region of a second conductivity type abutting the first region in a lateral direction and a vertical direction to form an interface between the first conductivity type and the second conductivity type, wherein the drain region is spaced apart from the interface. A source region of the first conductivity type abuts the second region in the lateral direction and vertical directions. ... Freescale Semiconductor Inc

Method and apparatus for managing mismatches within a multi-threaded lockstep processing system

A processing system comprising a first processing domain and a second processing domain. Each of the first processing domain and the second processing domain comprises a multi-threaded processor core arranged to output a set of internal state signals representative of current states of internal components of the respective processor core. ... Freescale Semiconductor Inc

Mems gyroscope device

A microelectromechanical system (mems) gyroscope device includes a substrate having a surface parallel to a plane; first and second proof masses driven to slide back and forth past one another in a first directional axis of the plane, where the first and second proof masses respectively have a first and second recess in a respective side closest to the other proof mass; a pivot structure coupled to the first proof mass within the first recess and to the second proof mass within the second recess; an anchor between the first and second recesses and coupled to a mid-point of the pivot structure; and third and fourth proof masses driven to move toward and away from one another in a second directional axis of the plane that is perpendicular to the first directional axis; where the proof masses move in response to angular velocity in one or more directional axes.. . ... Freescale Semiconductor Inc

11/30/17 / #20170346664

Communicaton unit, circuit for quadrature sampling error estimation and compensation and method therefor

A communication unit comprises a modem configured to generate a first and second test digital quadrature signal. The modem is configured to: estimate a first sampling error performance associated with a first quadrature path from the first received test digital quadrature signal; estimate a second sampling error performance associated with a second quadrature path from the second received test digital quadrature signal; and generate at least one sampling error compensation signal based on the first estimated sampling error performance and second estimated sampling error performance to be applied to at least one of the receiver and transmitter.. ... Freescale Semiconductor Inc

11/30/17 / #20170346579

Communicaton unit receiver, integrated circuit and method for adc dynamic range selection

A communication unit receiver comprising: a multi-section analogue to digital converter, adc, configured to receive an analogue signal and convert at least a first portion of the analogue signal into a digital signal using a first adc dynamic range. A modem, coupled to the multi-section adc, is configured to: process the digital signal; determine a signal-to-noise ratio, snr, for sub-carriers of the analogue signal; and output an adc selection signal to the multi-section adc that selects a subset of sections of the multi-section adc, where the selection signal is based at least partly on the determined snr. ... Freescale Semiconductor Inc

11/30/17 / #20170346280

Sensing and detection of esd and other transient overstress events

An integrated circuit includes an i/o pad and a protection device coupled to the i/o pad and a first supply node. A transient event detector includes a latch; a first transistor having a first current electrode coupled to the i/o pad, a control electrode coupled to a first supply node, and a second current electrode coupled to a data input of the latch, wherein the latch is configured to store an indication that a transient event occurred. ... Freescale Semiconductor Inc

11/30/17 / #20170345746

Integrated circuit package with solder balls on two sides

An integrated circuit package with solder balls on two major sides of the package and a method of making. The integrated circuit package includes at least one die encapsulated in an encapsulant. ... Freescale Semiconductor Inc

11/30/17 / #20170345491

Systems and methods for non-volatile flip flops

An integrated circuit includes a first plurality of flip flops; a first bank of resistive memory cells, wherein each flip flop of the first plurality of flip flops uniquely corresponds to a resistive memory cell of the first bank of resistive memory cells; write circuitry configured to store data from the first plurality of flip flops to the first bank of resistive memory cells; and read circuitry configured to read data from the first bank of resistive memory cells and provide the data from the first bank for storage into the first plurality of flip flops.. . ... Freescale Semiconductor Inc

11/30/17 / #20170343350

Angular rate sensor

A mems sensor for measuring rotational motion about a first axis includes a frame, a base structure under the frame, a drive mass mounted in the frame for rotational movement about a second axis perpendicular to the first axis, and a first drive paddle in the drive mass. A first link includes a first end coupled to a first spring that movably couples the first drive paddle to the drive mass and a second end coupled to a second spring that movably couples the first link to the frame. ... Freescale Semiconductor Inc

11/23/17 / #20170337142

Compiler global memory access optimization in code regions using most appropriate base pointer registers

A processing device includes a target processor instruction memory to store a plurality of target processor instructions that include a plurality of global memory access instructions. The processing device further includes a compiler to communicate with the target processor instruction memory, the compiler including: a global variable candidate detection module to identify a global memory access instruction within a set of code regions that use a set of global variable candidates to access a global memory, and a memory access optimization module to modify the global memory access instruction, wherein the modified global memory access instruction utilizes an unused base pointer register of a set of unused base pointer register candidates within the set of code regions, a global variable from the set of global variable candidates to be used as a base address, and an offset relative to the base address to access the global memory.. ... Freescale Semiconductor Inc

11/23/17 / #20170336973

Memory interleave system and method therefor

Methods and systems for accessing a memory are provided. One method of accessing a memory includes generating a memory access profile for accesses to a memory array. ... Freescale Semiconductor Inc

11/23/17 / #20170334306

Battery monitoring device

A battery monitoring device suitable for monitoring performance of one or more battery cells, such as with respect to a battery pack powering a vehicle. The battery monitoring device includes a signal injector configured to produce a replacement physical set that emulates one or more physical properties associated with the one or more battery cells, a multiplexer configured to selectively output, during different periods of time, the replacement physical set received from the signal injector or a physical set of physical properties received from the one or more battery cells, a sensor circuit configured to separately convert the physical set to a first signal set representing a first digitized measurement of the physical set and the replacement physical set to a second signal set representing a second digitized measurement of the replacement physical set, and a controller configured to compare the first signal set to the second signal set for a variance outside of a predetermined threshold. ... Freescale Semiconductor Inc

11/09/17 / #20170324716

Autonomous key update mechanism with blacklisting of compromised nodes for mesh networks

Various embodiments described herein relate to network key manager which is configured to manage keys in nodes in the network, wherein the network key manager including a memory configured to store an update data structure; a processor configured to: determine which nodes are blacklisted; generate the update data structure of volatile private keys for each node that is not blacklisted, wherein the volatile private key is based upon secret information associated with the node and an index, wherein the volatile private key is used for the indexth key update; determine a neighbor node of the network key manager; remove the volatile private key for the neighbor node from the update data structure; encrypt the resulting update data structure and a new network key with the private key for the neighbor node to produce an encrypted message; and send the encrypted message to the neighbor node.. . ... Freescale Semiconductor Inc

11/09/17 / #20170324715

Light-weight key update mechanism with blacklisting based on secret sharing algorithm in wireless sensor networks

Various embodiments include a network manager for managing network keys in a network having a plurality of nodes, the device including: a memory; and a processor configured to: determine n nodes to blacklist, wherein n is an integer; select a polynomial function from a plurality of polynomial functions of degree k and wherein the polynomial functions define plurality of secret network keys; generate k-n random abscissa values, wherein none of the random abscissa values are not found in a list of node abscissa values; calculate k-n polynomial function values for the k-n random abscissa values; calculate n polynomial function values for n node abscissa values associated with the n blacklisted nodes; transmit a message to nodes in the network including an indication of the selected polynomial function, the k-n random abscissa values, the n node abscissa values associated with the n blacklisted nodes, the k-n calculated polynomial function values, and the n calculated polynomial function values.. . ... Freescale Semiconductor Inc

11/09/17 / #20170324377

Amplitude detection with compensation

A circuit including an amplitude detector. The amplitude detector includes an input to receive a signal having an amplitude voltage and a first pair of transistors configured in parallel. ... Freescale Semiconductor Inc

11/09/17 / #20170322891

Device and method for secure data storage

A device for secure data storage has a host unit that obtains data stored on an external device at an external storage address; a user signal generator that generates a user defined security signal based on the external storage address of the data that indicates a security level of the data; a storage address determining unit that determines an internal storage address for the data based on the security level of the data; and a storage unit that stores the data at the internal storage address corresponding to the security level.. . ... Freescale Semiconductor Inc

11/09/17 / #20170322098

Pressure sensor device and method for testing the pressure sensor device

A pressure sensor device and a method for testing the pressure sensor device is provided. The pressure sensor device includes a first pressure sensor cell having a first capacitance value, and a second pressure sensor cell having a second capacitance value, the second capacitance value being different from the first capacitance value. ... Freescale Semiconductor Inc

10/26/17 / #20170310307

Systems and methods for supplying different voltage levels with shared current

An integrated circuit includes a first portion of a stacked ring oscillator coupled between a first supply voltage node and a common node, wherein the first supply voltage node provides a local supply voltage for the first portion and the common node provides a local ground for the first portion. The integrated circuit includes a second portion of the stacked ring oscillator coupled between the common node and a second supply voltage node wherein the common node provides a local supply voltage for the second portion and the second supply voltage node provides a local ground for the second portion. ... Freescale Semiconductor Inc

10/26/17 / #20170308404

Data processing system having a coherency interconnect

A processing system includes a first processor configured to issue a first request in a first format, an adapter configured to receive the first request in the first format and send the first request in a second format, and a memory coherency interconnect configured to receive the first request in the second format and determine whether the first request in the second format is for a translation lookaside buffer (tlb) operation or a non-tlb operation based on information in the first request in the second format. When the first request in the second format is for a tlb operation, the interconnect routes the first request in the second format to a tlb global ordering point (gop). ... Freescale Semiconductor Inc

10/26/17 / #20170308108

Voltage supply regulator with overshoot protection

A voltage supply regulator includes a first output resistor including a first terminal coupled to an output voltage of the voltage supply regulator and a second terminal; a first comparator including a first input coupled to a reference voltage, a second input coupled to the second terminal of the first output resistor, and an output coupled to a base of a first regulator transistor; a current mirror coupled to a collector of the first regulator transistor; and an slew rate detector coupled to the current mirror that includes a first terminal coupled to control electrodes of first and second transistors in the current mirror, and a detection bipolar junction transistor having a collector coupled to the control electrodes of the first and second transistors in the current mirror, and a base coupled to a second terminal of the capacitor.. . ... Freescale Semiconductor Inc

10/26/17 / #20170307697

Magnetic field sensor with multiple axis sense capability

A sensor for sensing an external magnetic field along a sensing direction comprises a sensor bridge. The sensor bridge has a first sensor leg that includes a first magnetoresistive sense element and a second sensor leg that includes a second magnetoresistive sense element. ... Freescale Semiconductor Inc

10/12/17 / #20170295097

System and method for creating session entry

A system for creating a session entry and forwarding an ip packet includes memories that store session and session template tables, and first and second processors in communication with the memories. When the first processor receives the ip packet, it determines whether the session table includes a session entry corresponding to the ip packet. ... Freescale Semiconductor Inc

10/12/17 / #20170294994

Common public radio interface, cpri, lane controller and method of operating thereof

The present application relates to a common public radio interface, cpri, lane controller and a method of operating thereof. The cpri lane controller comprises a transaction counter, a symbol counter and a comparator. ... Freescale Semiconductor Inc

10/12/17 / #20170294393

Pre-plated substrate for die attachment

A method for attaching a semiconductor die to a substrate includes providing a substrate that includes an attachment layer at a surface of the substrate. The attachment layer is covered by a protective flash plating layer. ... Freescale Semiconductor Inc

10/12/17 / #20170293516

Temporal relationship extension of state machine observer

A method includes receiving a first progress request from a first state machine associated with execution of a first thread on a processor. The method includes updating a current state of a temporal relationship state machine based on the current state, the first progress request, and a predetermined temporal relationship between progress of the first state machine to a first state machine state and progress to a second state. ... Freescale Semiconductor Inc

10/12/17 / #20170293375

Capacitive sensor device and method of operation

A capacitive sensor system includes a capacitive sensor device having a sense electrode that includes a first capacitor, a first supply voltage in , a first switch operable to couple the sense electrode to the first supply voltage during a first mode and an analog to digital converter during a second mode, a second switch operable to couple a second capacitor to a second supply voltage during the first mode and to an open circuit during the second mode, and a resistive element that includes a first terminal coupled between the first capacitor and the first switch, and a second terminal coupled between the second capacitor and the second switch.. . ... Freescale Semiconductor Inc

10/12/17 / #20170293001

Magnetic field sensor with permanent magnet biasing

A magnetic field sensor for sensing an external magnetic field along a sensing direction oriented perpendicular to a plane of the magnetic field sensor comprises a sensor bridge. The sensor bridge has a first sensor leg that includes a first magnetoresistive sense element and a second sensor leg that includes a second magnetoresistive sense element. ... Freescale Semiconductor Inc

10/12/17 / #20170292995

Multi-bit data flip-flop with scan initialization

Multi-bit data flip-flops are disclosed that provide bit initialization through propagation of scan bits. Input multiplexers are configured to select between input data bits and input scan bits based upon mode select signals. ... Freescale Semiconductor Inc

10/05/17 / #20170289842

Method and system for processing lower nfft lte rates over cpri link

A method including receiving, by a radio equipment control (rec) device of a wireless communication system over an interface link, time domain compressed data from a radio equipment (re) device at a first data transmission rate. The method further including transforming, by the rec device, the time domain compressed data to frequency domain decompressed full rate data for a second transmission data rate utilizing a fast fourier processing engine of the rec device.. ... Freescale Semiconductor Inc

10/05/17 / #20170286587

Systems and methods for creating block constraints in integrated circuit designs

Methods for generating constraints associated with an integrated circuit design are provided. The method includes identifying, with a processor, a plurality of paths based on a floor-plan data set, each of the paths specifying a first block, a second block, and a first interconnect between the first block and the second block. ... Freescale Semiconductor Inc

09/28/17 / #20170279268

Power switch module, smart grid power supply arrangement and method therefor

A power switch module comprising a control component. Upon an indicated operating condition fulfilling a protection condition, the control component is arranged to transition the power switch module from an on state to a latched-off state in which the control component is arranged to configure the switching device to be turned off to decouple the load node from the power supply node. ... Freescale Semiconductor Inc

09/28/17 / #20170278961

Semiconductor devices with an enhanced resistivity region and methods of fabrication therefor

Embodiments of a semiconductor device include a base substrate including an upper surface, a nucleation layer disposed over the upper surface of the base substrate, a first semiconductor layer disposed over the nucleation layer, a second semiconductor layer disposed over the first semiconductor layer, a channel within the second semiconductor layer and proximate to an upper surface of the second semiconductor layer, and an enhanced resistivity region with an upper boundary proximate to an upper surface of the first semiconductor layer. The enhanced resistivity region has an upper boundary located a distance below the channel. ... Freescale Semiconductor Inc

09/28/17 / #20170278937

Split gate device with doped region and method therefor

A method of forming a semiconductor device using a substrate includes forming a first select gate over the substrate, a charge storage layer over the first select gate, over the second select gate, and over the substrate in a region between the first select gate and the second select gate, wherein the charge storage layer is conformal, and a control gate layer over the charge storage layer, wherein the control gate layer is conformal. The method further includes performing a first implant that penetrates through the control gate layer in a middle portion of the region between the first select gate and the second select gate to the substrate to form a doped region in the substrate in a first portion of the region between the first select gate and the second select gate that does not reach the first select gate and does not reach the second select gate.. ... Freescale Semiconductor Inc

09/28/17 / #20170278825

Apparatus and methods for multi-die packaging

A packaged semiconductor device includes a first package substrate having a first plurality of lead fingers, a first die attached to a first major surface of the first package substrate, a second package substrate having a second plurality of lead fingers, wherein each of the second plurality of lead fingers extends over the first die and the second package substrate is electrically isolated from the first package substrate. The device also includes a second die attached to a first major surface of the second package substrate, over the first die, and an encapsulant surrounding the first die, the first package substrate, the second die, and the second package substrate, wherein the encapsulant exposes a portion of the first package substrate and a portion of the second package substrate.. ... Freescale Semiconductor Inc

09/28/17 / #20170278768

Packaged device with extended structure for forming an opening in the encapsualant

A packaged device includes an extended structure located at a major side of the packaged device. The extended structure defines an outer area that includes encapsulated material on the major side and an inner area where there is a lack of encapsulant over a portion of the device at the major side. ... Freescale Semiconductor Inc

09/28/17 / #20170278763

Semiconductor device package and methods of manufacture thereof

A method of manufacturing a packaged semiconductor device includes forming an assembly by placing a semiconductor die over a substrate with a die attach material between the semiconductor die and the substrate. A conformal structure which includes a pressure transmissive material contacts at least a portion of a top surface of the semiconductor die. ... Freescale Semiconductor Inc

09/28/17 / #20170277647

Integrated circuit with pin level access to io pins

An integrated circuit (ic) having multiple cores controls write access to its input/output (i/o) pins. The ic includes a pin-control circuit, a memory, and a set of i/o pins. ... Freescale Semiconductor Inc

09/28/17 / #20170276738

Multiple axis magnetic sensor

A magnetic field sensor for sensing an external magnetic field along a sensing direction comprises a sensor bridge. The sensor bridge has a first sensor leg that includes a first magnetoresistive sense element and a second sensor leg that includes a second magnetoresistive sense element. ... Freescale Semiconductor Inc

09/14/17 / #20170265228

Linear combination for rach detection

A method including receiving, by an antenna combiner of a wireless communication system, a set of random access channel (rach) sequences of a first rach signal from a first antenna and a set of rach sequences of a second rach signal from a second antenna. The method further including selecting, by the antenna combiner, each rach sequence of the set of rach sequences of a selected rach signal from a selected antenna that has a best signal to interference plus noise ratio (sinr) from each rach sequence of the set of rach sequences of the first rach signal from the first antenna that has a first sinr and each rach sequence of the set of rach sequences of the second rach signal from the second antenna that has a second sinr.. ... Freescale Semiconductor Inc

09/14/17 / #20170264124

Regulation circuit having analog and digital feedback and method therefor

A regulation circuit for powering a device while charging a battery is provided. The regulation circuit includes at least one analog feedback loop, and a digitally controlled feedback loop. ... Freescale Semiconductor Inc

09/14/17 / #20170263538

Packaged semiconductor device having bent leads and method for forming

A package device has a first lead frame having a first flag. A first integrated circuit is on the first flag. ... Freescale Semiconductor Inc

09/14/17 / #20170263324

Sector retirement for split-gate memory

A memory is provided. The memory includes an array of non-volatile memory (nvm) cells arranged in a plurality sectors. ... Freescale Semiconductor Inc

09/07/17 / #20170257466

System and method for adaptive learning time based network traffic manager

Data packets are received at a media access control interface. An arbitration policy at a traffic management controller adapts to changes in network traffic characteristics by implementing a learning phase during which processing time information based upon individual packets is updated. ... Freescale Semiconductor Inc

09/07/17 / #20170255485

Data processing system having dynamic thread control

A method for managing thread execution in a processing system is provided. The method includes setting a first watchpoint, and generating a first watchpoint trigger corresponding to the first watchpoint. ... Freescale Semiconductor Inc

08/31/17 / #20170250730

Passive equalizer capable of use in high-speed data communication

A passive equalizer is provided. The passive equalizer includes a first resistive element, a first inductive element, a second resistive element, and a first variable capacitor. ... Freescale Semiconductor Inc

08/31/17 / #20170250656

Multiple path amplifier with pre-cancellation

A device includes a first amplifier coupled to a first signal conduction path and a second amplifier coupled to a second signal conduction path. A first coupler is coupled to the first signal conduction path. ... Freescale Semiconductor Inc

08/31/17 / #20170249993

Memory repair system and method therefor

A memory system includes a main memory array, a redundant memory array, and a content addressable memory (cam). The cam includes a plurality of entries, wherein each entry includes a plurality of column address bits and a plurality of maskable row address bits. ... Freescale Semiconductor Inc

08/31/17 / #20170249103

Data processing system having a write request network and a write data network

A data processing system includes a plurality of switch points interconnected by a write data network and a write request network. Each switch point includes write request switch circuitry having write request ingress ports and write request egress ports coupled to the write request network and arbitration circuitry configured to grant a write request received at one of the write request ingress ports access to one of the write request egress ports. ... Freescale Semiconductor Inc

08/31/17 / #20170247247

Integrated capacitive humidity sensor

A semiconductor device composed of a capacitive humidity sensor comprised of a moisture-sensitive polymer layer electrografted to an electrically conductive metal layer situated on an cmos substrate or a combined mems and cmos substrate, and exposed within an opening through a passivation layer, packages composed of the encapsulated device, and methods of forming the capacitive humidity sensor within the semiconductor device, are provided.. . ... Freescale Semiconductor Inc

08/24/17 / #20170244582

Fixed-point conjugate gradient digital pre-distortion (dpd) adaptation

A predistortion method and apparatus are provided which use a dpd actuator (225) to apply a memory polynomial formed with first dpd coefficients to a first input signal x[n], thereby generating a first pre-distorted input signal y[n] which is provided to the non-linear electronic device (253) to produce the output signal, where the memory polynomial may be adaptively modified with a digital predistortion adapter (224) which computes second dpd coefficients u[n] with an iterative fixed-point conjugate gradient method which uses n received digital samples of the first pre-distorted input signal y[n] and a feedback signal z[n] captured from the output signal to process a set of conjugate gradient parameters (u, b, v, r, ω, α, β) at each predetermined interval, thereby updating the first dpd coefficients with the second dpd coefficients u[n] generate a second pre-distorted input signal which is provided to the non-linear electronic device.. . ... Freescale Semiconductor Inc

08/24/17 / #20170244395

Circuit for reducing negative glitches in voltage regulator

A circuit that stabilizes an output signal of a voltage regulator includes a glitch amplifier, a pulse generator, and a transistor. The glitch amplifier amplifies glitches in the output signal and generates a glitch amplifier output signal. ... Freescale Semiconductor Inc

08/10/17 / #20170230311

Buffer allocation and use for packet cloning and mangling

A method of cloning and mangling a received data packet in which an unused space of a receiving buffer can be used to accommodate at least some generated clone packets. Additional memory-use efficiencies can be realized by employing scatter-gather lists in the process of clone-packet generation when the size of the received data packet exceeds a predetermined threshold size. ... Freescale Semiconductor Inc

08/10/17 / #20170229444

Esd protection circuit

Electrostatic discharge (esd) protection circuitry in an integrated circuit is provided. The protection circuitry includes a trigger circuit coupled between a first power supply bus and a second power supply bus. ... Freescale Semiconductor Inc

08/10/17 / #20170227982

Secure clock switch circuit

An integrated circuit (ic) having a clock switch that switches the system clock between an internal clock and an external clock based on whether or not the ic has finished downloading device configuration at boot and on whether or not the internal clock is functional. Further restrictions on the use of the external clock are imposed by the clock switch based on a life-cycle state of the ic. ... Freescale Semiconductor Inc

08/10/17 / #20170227409

On-die temperature sensor for integrated circuit

An on-die temperature sensor measures temperature during a temperature-measurement session. A ptat (proportional-to-absolute-temperature) generator generates an analog ptat voltage that is dependent on temperature. ... Freescale Semiconductor Inc

08/03/17 / #20170223637

Receiver removal detection in wireless charging systems

A wireless charging system has a transmitter and a receiver. The transmitter has (i) a tx coil that wirelessly transfers power to the receiver and (ii) tx circuitry that powers the tx coil and detects receiver removal by comparing tx input power and tx power loss. ... Freescale Semiconductor Inc

08/03/17 / #20170223152

Network application verification at a network processor

A network application is verified at a network processor by selecting network application functions based on a field of an ingress packet. The network application is composed of a set of network application functions, with each function carrying out a corresponding packet processing operation, such as packet parsing, statistical gathering, and the like. ... Freescale Semiconductor Inc

08/03/17 / #20170220491

Direct interface between sram and non-volatile memory

A memory system comprises an sram array and a nvm array. The sram array and nvm array are both organized in rows and columns. ... Freescale Semiconductor Inc

08/03/17 / #20170220414

Multi-dimensional parity checker (mdpc) systems and related methods for external memories

Multi-dimensional parity checker (mdpc) systems and related methods are disclosed to check parity of data regions within external memories. In one embodiment, the mdpc system includes a control register and a parity checker. ... Freescale Semiconductor Inc

07/27/17 / #20170213601

Full address coverage during memory array built-in self-test with minimum transitions

A method and apparatus for generating an address sequence in a memory device is provided. The method includes providing a memory array having a set of unique addresses, storing one of a first subset of the set of unique addresses in a first storage element, storing one of a second subset of the set of unique addresses in a second storage element, and generating a sequence of addresses to test the memory array. ... Freescale Semiconductor Inc

07/27/17 / #20170212800

System and method for performing bus transactions

A system that performs a bus transaction includes a transaction controller and a protection code processing circuit. The transaction controller identifies a set of parameters corresponding to the bus transaction based on address and received control information, and modifies at least one parameter or splits the bus transaction into sub-transactions depending on the parameter values to map the bus transaction to a memory address space. ... Freescale Semiconductor Inc

07/27/17 / #20170212189

Magnetic field sensor with permanent magnet biasing

A magnetic field sensor comprises a sensor bridge having multiple sensor legs. Each sensor leg includes magnetoresistive sense elements located in a plane of the magnetic field sensor. ... Freescale Semiconductor Inc

07/27/17 / #20170212176

Magnetic field sensor with skewed sense magnetization of sense layer

A magnetic field sensor comprises a sensor bridge having multiple sensor legs. Each sensor leg includes magnetoresistive sense elements, each comprising a pinned layer having a reference magnetization parallel to a plane of the sensor and a sense layer having a sense magnetization that is skewed away from three orthogonal axes. ... Freescale Semiconductor Inc

07/27/17 / #20170212175

Magnetic field sensor with multiple sense layer magnetization orientations

A magnetic field sensor comprises a sensor bridge having multiple sensor legs. Each sensor leg includes magnetoresistive sense elements, each comprising a pinned layer having a reference magnetization parallel to a plane of the sensor and a sense layer having a sense magnetization. ... Freescale Semiconductor Inc

07/06/17 / #20170195981

System and method for automatic delay compensation in a radio base station system

A method including performing a delay measurement of a first round trip delay value of an interface link, the first round trip delay value based on a transmission of a first rec synchronization signal to a re and when a rec receives a first re synchronization signal back, wherein frames transmitted by the rec are synchronized based upon the first rec synchronization signal, and frames transmitted by the re are synchronized based upon the first re synchronization signal. Calculating a first delay change value between the first round trip delay value and a previous round trip delay value, in response to determining that the first delay change value violates a delay tolerance value, transmitting an offset indicator that indicates an amount of offset the re is to shift the first re synchronization signal at a future time, and transmitting frames from the rec after shifting the first rec synchronization signal.. ... Freescale Semiconductor Inc

07/06/17 / #20170194488

Semiconductor device with floating field plates

A semiconductor device with a current terminal region located in a device active area of a substrate of the device. A guard region is located in a termination area of the device. ... Freescale Semiconductor Inc

07/06/17 / #20170192790

Providing task-triggered determinisitic operational mode for simultaneous multi-threaded superscalar processor

A task identifier-based mechanism is configured to temporarily disable a dual-issue capability of one or more threads in a superscalar simultaneous multi-threaded core. The core executes a first thread and a second thread which are each provided with a dual-issue capability wherein up to two instructions may be issued in parallel. ... Freescale Semiconductor Inc

07/06/17 / #20170192040

Current sensing circuit and method

The present application relates to a circuit arrangement for sensing a current. The circuit arrangement comprises a current sense circuit configured to cause the sense current through a sense transistor, wherein the sense current is representative of a load current through a load transistor. ... Freescale Semiconductor Inc

06/29/17 / #20170187399

Transmitter output driver circuits for high data rate applications, and methods of their operation

Embodiments of single-ended and differential output driver circuits include one or more complementary data switch pairs, each coupled to a t-coil. Each complementary data switch pair is coupled between a voltage source and a ground reference node, and each complementary data switch pair includes complementary transistors, each with a control terminal, a first current conducting terminal, and a second current conducting terminal. ... Freescale Semiconductor Inc

06/29/17 / #20170185519

Computing system with a cache invalidation unit, a cache invalidation unit and a method of operating a cache invalidation unit in a computing system

The present application relates to a cache invalidation unit for a computing system having a processor unit, cpu, with a cache memory, a main memory and at least one an alternate bus master unit. The cpu, the main memory and the at least one an alternate bus master unit are coupled via an interconnect for data communications between them. ... Freescale Semiconductor Inc

06/22/17 / #20170181192

Apparatus for reception and detection of random access channel (rach) data

An apparatus for reception and detection of rach data in an lte input signal includes a hardware accelerator that has a decimator that filters and down-samples the input signal, a first fourier transform circuit that transforms the decimated signal from the time domain to the frequency domain, and a second transform circuit that multiplies the resulting signal by a complex z-c sequence and performs an inverse fourier transform (ift) operation to transform the multiplied signal from the frequency domain to the time domain. A dsp performs a delay profile analysis operation on the signal resulting from the ift operation.. ... Freescale Semiconductor Inc

06/22/17 / #20170180253

Hash-based packet classification with multiple algorithms at a network processor

A network processor has a “bi-level” architecture including a classification algorithm level and a single-record search level to search a hash database that stores packet classification information based on packet field values. The classification algorithm level implements multiple different classification algorithm engines, wherein the individual algorithm applied to a received packet can be selected based on a field of the packet, a port at which the packet was received, or other criteria. ... Freescale Semiconductor Inc

06/22/17 / #20170179898

Amplifier devices with in-package bias modulation buffer

The embodiments described herein include amplifiers that are typically used in radio frequency (rf) applications. The amplifiers described herein use a buffer that is implemented inside the device package. ... Freescale Semiconductor Inc

06/22/17 / #20170179279

Partial, self-biased isolation in semiconductor devices

A device includes a semiconductor substrate, a buried doped isolation layer disposed in the semiconductor substrate to isolate the device, a drain region disposed in the semiconductor substrate and to which a voltage is applied during operation, and a depletion region disposed in the semiconductor substrate and having a conductivity type in common with the buried doped isolation barrier and the drain region. The depletion region reaches a depth in the semiconductor substrate to be in contact with the buried doped isolation layer. ... Freescale Semiconductor Inc

06/22/17 / #20170179049

Power grid balancing apparatus, system and method

A semiconductor apparatus for power distribution on a die, the semiconductor apparatus, comprising a first die, wherein the first die comprises a first integrated circuit, a dam coupled to the first die, wherein the dam is a metal ring, a second die, wherein the second die comprises a second integrated circuit, wherein the first and second dies are stacked together and are electrically connected, and a pair of metal connectors coupled to the dam and an edge of the first die, wherein power and ground wires are coupled to the dam, wherein the power transmitted through the power and ground wires is distributed through the dam and metal connectors to the first die and wherein the power transmitted to the first die is distributed to the to the second die.. . ... Freescale Semiconductor Inc

06/22/17 / #20170177432

Memory controller and method of operating a memory controller

The present application relates to a memory controller and a method of operating thereof. The memory controller comprises a transaction interface arranged to be coupled to a transaction interconnect to receive a write transaction comprising write data; a mode controller arranged to obtain context information and to select a data protection scheme out of a plurality of data protection schemes based on the obtained context information; at least one data protection module to apply the selected data protection scheme by generating one or more protection code sequences from at least the write data in accordance with the selected data protection scheme; and a physical memory interface coupled to at least one memory device to store the write data and the one or more protection code sequences in the at least one memory device.. ... Freescale Semiconductor Inc

06/22/17 / #20170177428

Memory error detection system

An error detection system detects errors in data packets stored in a memory. A read signature generation circuit generates a read signature of a first data packet. ... Freescale Semiconductor Inc

06/22/17 / #20170176535

Clock gating for x-bounding timing exceptions in ic testing

An integrated circuit includes a clock gate that is used to prevent timing exception paths from affecting data being captured by scan chain registers during at-speed scan testing. A single clock gate can be used to control multiple timing-exception paths, so the amount of x-bounding circuitry inserted into the ic can be drastically reduced compared to that required by conventional x-bounding methodologies.. ... Freescale Semiconductor Inc

06/15/17 / #20170171343

Method and apparatus to accelerate session creation using historical session cache

A method and apparatus receive packets, wherein the packets comprise headers, and the headers comprise session parameter values, route the packets in response to the session parameter values matching an active traffic session entry of the active traffic session entries in an active traffic session cache memory, match the session parameter values against historical session entries in an historical session cache memory in response to the session parameter values not matching any active traffic session entry of the active traffic session entries in the active traffic session cache memory, wherein the historical session entries for traffic sessions in the historical session cache memory persist after the traffic sessions are no longer active, and, in response to the session parameter values not matching any historical session entry of the historical session entries in the historical session cache memory, performing a packet security check on the packets.. . ... Freescale Semiconductor Inc

06/15/17 / #20170171268

System and method for on-the-fly modification of the properties on an active antenna carrier in radio base station communication operation

A method performed by a radio base station, the method including receiving streaming data information, the data information includes a first portion from a first set of antenna carriers and a second portion from a second set of antenna carriers, wherein the first portion is to be processed prior to the second portion. The method further including streaming the first portion of the data information from a radio equipment control device in a first data frame over an interface link that is configured to operate based on a first mapping configuration that indicates a set of locations of the first data frame at which the first portion of information is to be streamed, and streaming the second portion of the data information from the rec device in a second data frame over the interface link that is configured to operate based on a second mapping configuration.. ... Freescale Semiconductor Inc

06/15/17 / #20170171088

System and method for automatic load adaptive antenna carrier bandwidth dynamic reconfiguration in radio base station system

A method performed by a radio base station, the method including determining that one of a direct memory access (dma) buffers of a communication link for a service provider has gone beyond a dma buffer limit (empty or full), the communication link between a radio equipment control (rec) device and a radio equipment (re) device that is operating based on a first bandwidth configuration of the communication link. The method further including in response to determining that the communication link is to change operation (due to reaching the dma buffer limit) based on a second bandwidth configuration of the communication link, instead of the first bandwidth configuration, continuing operation of the communication link based on the second bandwidth configuration. ... Freescale Semiconductor Inc

06/15/17 / #20170171064

Adapative message caches for replay/flood protection in mesh network devices

Adaptive message caches are disclosed for packet replay and/or flood protection in mesh network devices. The adaptive message cache includes a replay protection area (rpa) and a flood protection area (fpa). ... Freescale Semiconductor Inc

06/15/17 / #20170169156

Designing a density driven integrated circuit

A design tool system includes a schematic design tool that computes a total number of devices in an analog circuit schematic based on information extracted from the analog circuit schematic. The schematic design tool selects an optimal row/column device configuration for the total number of devices and creates a temporary layout based upon the optimal row/column device configuration. ... Freescale Semiconductor Inc

06/15/17 / #20170168934

Memory controller with interleaving and arbitration scheme

A memory controller that implements an interleaving and arbitration scheme includes an address decoder that selects a memory bank for an access request based on a set of address least significant bits included in the access request. A core requiring sequential access to memory is routed to consecutive memory banks of the memory for consecutive access requests. ... Freescale Semiconductor Inc

06/15/17 / #20170168745

System and method for modulo addressing vectorization with invariant code motion

A processing device includes a target processor instruction memory to store a plurality of memory access instructions, and a compiler. A vector invariant candidate detection module of the compiler to determine whether the memory access instruction is to be replaced by vector invariant access code, and in response: the complier to generate first replacement code that vectorizes the memory access instruction using vector invariant access code, and to replace the memory access instruction with the first replacement code. ... Freescale Semiconductor Inc

06/08/17 / #20170164333

Base transceiver station for reducing congestion in communcation network

A base transceiver station (bts) includes dedicated memories to store uplink real-time (rt) data received by way of an antenna of the bts and downlink rt data generated by processors of the bts. The dedicated memories serve a dedicated number of processors, which prevents over-run and under-run of antenna buffers and provides deterministic data flow necessary to stream time-critical uplink and downlink rt data. ... Freescale Semiconductor Inc

06/08/17 / #20170163274

Low-power clock repeaters and injection locking protection for high-frequency clock distributions

A low power clock distribution circuit system (200) includes a clock generator (201) for generating a high frequency clock signal that is supplied to a clock interconnect running to multiple lanes of an integrated circuit, each lane including a passive clock repeater circuit (e.g., 203) having a differential-mode rlc network (e.g., 301) that is shielded by an active guard ring structure (e.g., 511) and that is coupled to receive first and second input clock signals (vip, vin) to provide clock signal gain boosting at a predetermined frequency range and clock signal attenuation out of the operating frequency range, thereby generating the first and second output clock signals (vop, von) that are provided to a clocked circuit (e.g., 211).. . ... Freescale Semiconductor Inc

06/08/17 / #20170162168

Adaptive instrument cluster

An adaptive instrument cluster (aic) is employed in a device, such as an automobile, wherein the aic adjusts a display of instrumentation information based on one or more of captured imagery, user eye position, and device conditions. Based on these factors the aic can adjust the appearance, position, information display format, and other aspects of one or more instrument gauges. ... Freescale Semiconductor Inc

06/08/17 / #20170160788

Low power state retention mode for processor

A method for conserving power in a computing device including a processor connected to an volatile system memory and having a processing core, always-on non-wakeup (aonw) resources, and a system memory controller, includes receiving a request at the processor to enter a low power state retention mode, saving, in the volatile system memory, control register settings for each of the aonw resources, placing the volatile system memory in a self-refresh mode to maintain all data stored in the volatile system memory, placing the system memory controller in a low power state, and turning off power to the processing core and all of the aonw resources.. . ... Freescale Semiconductor Inc

06/01/17 / #20170154859

Antenna assembly for wafer level packaging

Embodiments are provided for a packaged semiconductor device that includes a package substrate that in turn includes an embedded die configured to process a radio frequency (rf) signal; a printed circuit board (pcb) attached to a front side of the package substrate, where the pcb includes a cavity; and an antenna enabling element attached to the front side of the package substrate within the cavity, the antenna enabling element configured to convey the rf signal through the cavity.. . ... Freescale Semiconductor Inc

06/01/17 / #20170153847

System and method for removing hash table entries

A data processing device includes a hash table management module that sequentially steps through linear address space of the hash table to identify hash chain in sequential address order. Each identified hash chain is evaluated, before identifying a next hash chain, to remove any entries marked for deletion.. ... Freescale Semiconductor Inc

05/18/17 / #20170141087

Packaged devices with multiple planes of embedded electronic devices

A packaged semiconductor structure includes an interconnect layer and a first microelectronic device on a first major surface of the interconnect layer. The structure also includes a substrate having a cavity, wherein the cavity is defined by a vertical portion and a horizontal portion, wherein the vertical portion surrounds the first device, the horizontal portion is over the first device, and the first device is between the horizontal portion and the first major surface of the interconnect layer such that the first device is in the cavity. ... Freescale Semiconductor Inc

05/18/17 / #20170141057

Semiconductor device package, electronic device and method of manufacturing electronic devices using wafer level chip scale package technology

A semiconductor device package comprising a circuit chip and a wafer level chip scale package is designed for reducing capacitive interactions which exist between electrically conducting portions of the circuit chip and under-bump metallization areas of the package. Such design is beneficial in particular for under-bump metallization areas which are dedicated to transferring signals having frequencies above 30 ghz.. ... Freescale Semiconductor Inc

05/18/17 / #20170139863

Interrupt controlled prefetching and caching mechanism for enhanced processor throughput

An interrupt controlled prefetching and caching technique includes transferring peripheral data from a peripheral to a peripheral cache via direct memory access in response to receiving an interrupt request from the peripheral. The technique includes executing an interrupt service routine prologue in response to completion of transferring of peripheral data. ... Freescale Semiconductor Inc

05/18/17 / #20170139772

Protecting embedded nonvolatile memory from interference

Electromagnetic compatibility (emc) of a system-on-a-chip (soc) is enhanced by encoding at least a subset of control signals before the control signals are transmitted over a bus (e.g., a bus internal to a soc) from a controller to an embedded nonvolatile memory (nvm). The error-detection code used causes an emc event to introduce errors into the transmitted codewords with relatively high probability. ... Freescale Semiconductor Inc

05/18/17 / #20170139744

Systems and methods for frame presentation and modification in a networking environment

A data processing system can comprise a first module having a workspace and configured to execute a task that can request access to a frame in a system memory, a queue manager configured to store a frame descriptor which identifies the frame in the system memory, and a memory access engine coupled to the first module and the queue manager. The memory access engine copies requested segments of the frame to the workspace and has a working frame unit to store a segment handle identifying a location and size of each requested segment copied to the workspace of the first module. ... Freescale Semiconductor Inc

05/18/17 / #20170138734

Mems device with capacitance enhancement on quadrature compensation electrode

A mems device includes a mass system capable of undergoing oscillatory drive motion along a drive axis and oscillatory sense motion along a sense axis perpendicular to the drive axis. A quadrature correction unit includes a fixed electrode and a movable electrode coupled to the movable mass system, each being lengthwise oriented along the drive axis. ... Freescale Semiconductor Inc

05/11/17 / #20170133349

Method of packaging integrated circuit die and device

A package substrate having an opening and through-substrate interconnect structures is attached to a temporary carrier such as an adhesive film. The active surface of an ic die is placed in contact with the carrier substrate within the opening, to temporarily attach the die to the carrier substrate. ... Freescale Semiconductor Inc

05/11/17 / #20170132307

Data clustering employing mapping and merging

A data-clustering method generates data clusters for a set of data points. A region of interest containing the data points and a center matrix for the region of interest are defined, where the center matrix includes an array of center points defining centers of overlapping circles. ... Freescale Semiconductor Inc

05/11/17 / #20170132175

Fft device and method for performing a fast fourier transform

An fft device for performing a fast fourier transform (fft) of an operand vector of length n is described. The fft device comprises: a control unit arranged to control a sequence of transformation rounds, the transformation rounds including two or more fft rounds, wherein the fft rounds include a window-fft round or the transformation rounds further include a window round, wherein each transformation round is arranged to be carried out in a sequence of n/m successive operations, each operation transforming a subvector of length m of said operand vector into a corresponding transformed subvector of length m; and a coefficient unit for providing transformation data; and a transformation unit arranged to receive, for each of said transformation rounds, transformation data from the coefficient unit, the transformation data depending on whether the respective transformation round is an fft round, a window-fft round, or said window round, and to perform the respective linear transformation on the basis of the transformation data. ... Freescale Semiconductor Inc

05/11/17 / #20170131351

Testing multi-core integrated circuit with parallel scan test data inputs and outputs

Testing an integrated circuit (ic) that has a set of nominally similar cores and pairs of test data input (tdi) and test data output (tdo) pads common to the different cores. Similar scan chains in parallel in the different cores provide response signals as functions of corresponding tdi signals. ... Freescale Semiconductor Inc

05/11/17 / #20170129769

Mems device with isolation sub-frame structure

An embodiment of a microelectromechanical systems (mems) device is provided, which includes a substrate; a proof mass positioned in space above a surface of the substrate, wherein the proof mass is configured to pivot on a rotational axis parallel to the substrate; an anchor structure that includes two or more separated anchors mounted to the surface of the substrate, wherein the anchor structure is aligned with the rotational axis; and an isolation sub-frame structure that surrounds the anchor structure and is flexibly connected to each of the two or more separated anchors of the anchor structure, where the proof mass is flexibly connected to the isolation sub-frame structure.. . ... Freescale Semiconductor Inc

05/04/17 / #20170127297

Systems and methods for managing high network data rates

A wireless communication device includes a physical (phy) layer module, a media access control (mac) layer module (102) coupled to the phy layer module. The mac layer module is configured to generate a limited acknowledgement (lack) response that indicates successful receipt of a data transmission, and to reduce a data rate used to transmit data to the wireless communication device.. ... Freescale Semiconductor Inc

05/04/17 / #20170126533

Multi-rate overlay mode in wireless communication systems

A method is provided, which includes identifying a data transfer rate associated with a wireless communication device. The data transfer rate is identified from a group including a legacy data transfer rate and a plurality of non-legacy data transfer rates. ... Freescale Semiconductor Inc

05/04/17 / #20170126237

Method and apparatus for calibrating a digitally controlled oscillator

A method of calibrating a digitally controlled oscillator (dco). The method comprises configuring a fine tuning capacitive component of the dco into a minimum capacitance configuration therefor, configuring a coarse tuning capacitive component of the dco into a first configuration therefor and determining a resulting first output frequency of the dco. ... Freescale Semiconductor Inc

05/04/17 / #20170126181

Reconfigurable power splitters and amplifiers, and corresponding methods

A reconfigurable doherty power amplifier includes a packaged power splitter device, main and peaking amplifiers, and a combiner circuit. The power splitter device includes a power divider, input terminals coupled to first and second ports of the power divider, and output terminals coupled to third and fourth ports of the power divider. ... Freescale Semiconductor Inc

05/04/17 / #20170126153

Method and apparatus for motor lock or stall detection

A method and apparatus are provided for detecting a rotor lock condition in a sensorless permanent magnet synchronous motor. A bemf observer determines an estimated rotor speed {circumflex over (ω)} and a first bemf voltage value in an estimated rotor-related γ,δ reference frame. ... Freescale Semiconductor Inc

05/04/17 / #20170125584

Self-adjusted isolation bias in semiconductor devices

A device includes a semiconductor substrate, a doped isolation barrier disposed in the semiconductor substrate to isolate the device, a drain region disposed in the semiconductor substrate and to which a voltage is applied during operation, and a depleted well region disposed in the semiconductor substrate, and having a conductivity type in common with the doped isolation barrier and the drain region. The depleted well region is positioned between the doped isolation barrier and the drain region to electrically couple the doped isolation barrier and the drain region such that the doped isolation barrier is biased at a voltage level lower than the voltage applied to the drain region.. ... Freescale Semiconductor Inc

05/04/17 / #20170125336

Substrate with routing

A substrate having an edge; a first and second active trace, wherein the first active trace corresponds to a first signal of a differential pair and the second active trace corresponds to a second signal of the differential pair; and a first and second conductive via which are located at different distances from the edge. The first active trace is routed to the first conductive via, and the second active trace is routed around the first conductive via to the second conductive via such that the second active trace is between the first conductive via and the edge. ... Freescale Semiconductor Inc

05/04/17 / #20170125293

Substrate array for packaging integrated circuits

A method for packaging integrated circuits includes providing a substrate array having (i) multiple individual substrates, each of which has bottom contact pads and corresponding conductive traces and (ii) plating busses located between adjoining ones of the substrates and electrically connected to the bottom contact pads by way of the traces. The method further includes (i) forming slots in the substrate array by removing portions of the plating busses connected to the traces while leaving corner attachment zones connecting adjacent individual substrates, (ii) attaching and electrically connecting dies to the substrates, (iii) encapsulating the dies, (iv) electrically and functionally testing the assemblies, and then, after the testing, (v) singulating the assemblies, which yields individual ic devices corresponding to the individual substrates.. ... Freescale Semiconductor Inc

05/04/17 / #20170124354

Integrated circuit lifecycle security with redundant and overlapping crosschecks

An integrated circuit includes a security module with multiple stages arranged in a pipeline, with each stage executing a different operation for accessing stored lifecycle (lc) information. For each portion of lc being accessed, each stage performs n iterations of its corresponding operation, whereby n is an integer greater than two, and crosschecks the results of successive iterations to ensure that the results of the operation are consistent. ... Freescale Semiconductor Inc

05/04/17 / #20170122825

Pressure sensor with variable sense gap

A sensor device includes a substrate having a port extending through it and a membrane including a first electrode spanning across the port. The port exposes the membrane to a pressure stimulus from an external environment. ... Freescale Semiconductor Inc

04/27/17 / #20170118113

System and method for processing data packets by caching instructions

A system for processing data packets includes memories with cache buffers that store flow tables and a flow index table, and a processor in communication with the memories. When the processor receives a data packet, it determines whether the flow index table includes a flow index table entry corresponding to the data packet. ... Freescale Semiconductor Inc

04/27/17 / #20170117880

Rail-to-rail comparator with shared active load

A rail-to-rail comparator circuit includes nmos and pmos differential input stages with associated loads that are coupled to a shared-load stage. The shared-load stage is coupled to an output stage that includes two active devices. ... Freescale Semiconductor Inc

04/27/17 / #20170117856

Rf power transistors with video bandwidth circuits, and methods of manufacture thereof

Embodiments of rf amplifiers and packaged rf amplifier devices each include a transistor, an impedance matching circuit, and a video bandwidth circuit. The impedance matching circuit is coupled between the transistor and an rf i/o (e.g., an input or output lead). ... Freescale Semiconductor Inc

04/27/17 / #20170117239

Output impedance matching circuit for rf amplifier devices, and methods of manufacture thereof

A packaged rf amplifier device includes a transistor and an output circuit. The transistor includes a control terminal and first and second current carrying terminals. ... Freescale Semiconductor Inc

04/27/17 / #20170117028

Sense path circuitry suitable for magnetic tunnel junction memories

A memory includes a first memory cell; and a second memory cell. A selectable current path is coupled between the first memory cell and the second memory cell. ... Freescale Semiconductor Inc

04/27/17 / #20170116365

Integrated circuit using standard cells from two or more libraries

An integrated circuit (ic) has a block of instances of cells aligned in rows of at least first and second heights. The instances of cells are selected from at least two different libraries of standard cells that have heights that are integer multiples of the first and second heights respectively as a function of performance criteria of the instances of cells. ... Freescale Semiconductor Inc

04/27/17 / #20170115879

Non-volatile ram system

A data processing system includes a backup nonvolatile memory (nvm), a random access memory (ram), and a controller. The ram includes a plurality of partitions, each partition having a different corresponding backup frequency. ... Freescale Semiconductor Inc

04/27/17 / #20170115723

Multi-port power prediction for power management of data storage devices

Multi-port power prediction for power management of data storage devices is disclosed. For certain embodiments, a host interface within a port multiplier receives host messages from a host device for a plurality of data storage devices. ... Freescale Semiconductor Inc

04/27/17 / #20170115322

Mems sensor device having integrated multiple stimulus sensing

A sensor device comprises a device structure and a cap coupled with the device structure to produce a cavity in which components of the sensor device are located. The device structure includes a substrate and a movable element spaced apart from a surface of the substrate. ... Freescale Semiconductor Inc

04/20/17 / #20170110451

Integrated circuits and devices with interleaved transistor elements, and methods of their fabrication

A monolithic integrated circuit includes first and second pluralities of parallel-connected transistor elements (e.g., transistor fingers). To spread heat in the ic, the first and second pluralities of transistor elements are interleaved with each other and arranged in a first row. ... Freescale Semiconductor Inc

04/20/17 / #20170110339

Ic device having patterned, non-conductive substrate

A patterned, non-conductive substrate for an integrated circuit (ic) package has a die side configured to receive a die and a lead side opposite the die side. A pattern formed in the substrate defines openings (e.g., holes, steps, grooves, and/or cavities) that extend between the die side and the lead side of the substrate. ... Freescale Semiconductor Inc

04/20/17 / #20170109305

Slave device alert signal in inter-integrated circuit (i2c) bus system

A system having master and slave devices and communicating over an i2c bus has sda and a scl lines that are normally high unless a device pulls the voltage of the line low. Normal data signals on the sda line are set during the low phase of the clock signals on the scl line and transferred to a receiver during the high phase of the clock signals. ... Freescale Semiconductor Inc

04/20/17 / #20170109079

Partitioned memory having pipeline writes

A memory device includes a non-volatile memory (nvm) array and a memory controller. The nvm array has four partitions in which each partition has as plurality of groups of nvm cells. ... Freescale Semiconductor Inc

04/20/17 / #20170108980

Mutual capacitance sensing circuit

An electronic device includes a transmit module and a receive module connected, respectively, to touch pad transmit and receive electrodes. The receive module includes a non-linear voltage-to-current converter, a pre-charge voltage generator, and an integrator. ... Freescale Semiconductor Inc

04/13/17 / #20170104653

Packet loss debug system and method

A mechanism is provided for debugging of system-wide packet loss issues in network devices by automatically identifying packet loss conditions at runtime of the network device and by logging and analyzing relevant data to help diagnose the issues resulting in lost packets. A network programmer defines a path through the communications processor that identified packets should follow, and then hardware mechanisms within the modules of the communications processor are used to determine whether the packets are indeed following the defined path. ... Freescale Semiconductor Inc

04/13/17 / #20170103905

Method for packaging an integrated circuit device with stress buffer

A method of fabricating a plurality of semiconductor devices includes attaching a plurality of integrated circuit (ic) die to a substrate including forming electric connections between contacts on the ic die and contacts on the substrate. After the ic die is attached to the substrate, a first encapsulating material is placed over stress-sensitive areas of the ic die. ... Freescale Semiconductor Inc

04/06/17 / #20170099077

Configurable correlator for joint timing and frequency synchronization and demodulation

At least one embodiment of a correlator comprising a plurality of correlator taps is configurable to provide synchronization and symbol modulation for a plurality of modulation systems. Among other uses, at least one embodiment of the correlator can provide a coarse symbol timing value. ... Freescale Semiconductor Inc

04/06/17 / #20170098644

Esd protection device

An electrostatic protection includes a buried layer having an outer region and an inner region which are heavily doped regions of a first conductivity type. The inner region is surrounded by an undoped or lightly doped ring region. ... Freescale Semiconductor Inc

04/06/17 / #20170097388

Lbist debug controller

An integrated circuit (ic) includes a logic built-in self-test (lbist) system that includes scan chains. The scan chains receive a clock signal and test pattern signals, and generate scan out signals. ... Freescale Semiconductor Inc

03/30/17 / #20170093914

Rule lookup using predictive tuples based rule lookup cache in the data plane

This disclosure describes an approach to handle packets that arrive at a network security device, such as a router. At a data plane of the security device, packet identifiers included in an incoming packet not currently belonging to an ip session of the device are compared to packet identifiers stored in a table stored in a memory of the security device. ... Freescale Semiconductor Inc

03/30/17 / #20170093856

Communication device identification

A peripheral device and central device in a communication network, such as a bluetooth low energy network, maintain privacy while establishing a connection. During the connection set-up, energy may be saved in the peripheral device by linking the advertising address of the peripheral device to the resolvable private address of the central device, thereby minimizing the search effort of the peripheral device.. ... Freescale Semiconductor Inc

03/30/17 / #20170093607

Methods and system for generating a waveform for transmitting data to a plurality of receivers and for decoding the received waveform

Methods and a system are described for generating a waveform for transmitting data over a channel divided into a plurality of adjacent frequency subcarriers. One method includes receiving a plurality of data bits, each destined for a different receiver of a plurality of receivers. ... Freescale Semiconductor Inc

03/30/17 / #20170093561

Denial-of-service attack protection for a communication device

A peripheral and central device in a wireless network, such as a bluetooth low energy network, may maintain privacy while connecting. During connecting energy in the peripheral device may be saved by linking an advertised address of the peripheral device to a resolvable private address of the central device, thereby providing an early indication if the central device is, according to the peripheral device, allowed to connect to the peripheral device. ... Freescale Semiconductor Inc

03/30/17 / #20170093151

Hot plugging protection

An overcharge protection circuit comprises a first series of first terminals a second series of second terminals, a first overvoltage protection device connected between each consecutive pair of first terminals, a current balancing device connected between each consecutive pair of second terminals, and a second overvoltage protection device connected between a first terminal and a second terminal. The second overvoltage protection device is configured to pass a current if a voltage over the second overvoltage protection device exceeds a threshold. ... Freescale Semiconductor Inc

03/30/17 / #20170092595

Methods to improve bga package isolation in radio frequency and millimeter wave products

A method and apparatus are provided for manufacturing a packaged electronic device (200) which includes a carrier substrate (120) in which conductive interconnect paths (122) extend between first and second opposed surfaces, an integrated circuit die (125) affixed to the first surface of the carrier substrate for electrical connection to the plurality of conductive interconnect paths, and an array of conductors (110), such as bga, lga, pga, c4 bump or flip chip conductors, affixed to the second surface of the carrier substrate for electrical connection to the plurality of conductive interconnect paths, where the array comprising a signal feed ball (112) and an array of shielding ground balls (111) surrounding the signal feed ball.. . ... Freescale Semiconductor Inc

03/30/17 / #20170092567

Microelectronic packages having mold-embedded traces and methods for the production thereof

Methods for fabricating microelectronic packages, such as fan-out wafer level packages, and microelectronic packages are provided. In one embodiment, the method includes placing a first semiconductor die on a temporary substrate, forming an electrically-conducive trace in contact with at least one of the first semiconductor die and the temporary substrate, and encapsulating the first semiconductor die and the electrically-conductive trace within a molded panel. ... Freescale Semiconductor Inc

03/30/17 / #20170092380

Full address coverage during memory array built-in self test with minimum transitions

Transitioning to all addresses of a memory array during bist includes arranging the addresses as a matrix with rows of the matrix corresponding one to one to the plurality of addresses of the memory array and columns of the matrix corresponding one to one to the plurality addresses of the memory array. A column of a selected current location can correspond to a destination address of a memory transition. ... Freescale Semiconductor Inc

03/30/17 / #20170092354

Memory with read circuitry and method of operating

A non-volatile memory includes a first bit cell having a programmable resistive element coupled to a write bit line wherein the programmable resistive element is programmable to one of two resistive states, a resistive element coupled to the programmable resistive element at a circuit node, and a first transistor configured to operate in saturation during a read operation. The first transistor has a control electrode coupled to the circuit node and a first current electrode coupled to a read bit line.. ... Freescale Semiconductor Inc

03/30/17 / #20170091372

Gate length upsizing for low leakage standard cells

This disclosure describes a library optimization system that creates modified standard cells with reduced leakage currents that meet predefined cell area, timing, and leakage requirements. The library optimization system selects transistors to upsize based upon the fact that transistors of a same type, such as p-channel or n-channel transistors, that are connected in series produce a small reverse bias between the gate and source, known as a stacking effect. ... Freescale Semiconductor Inc

03/30/17 / #20170091249

Systems and methods to access memory locations in exact match keyed lookup tables using auxiliary keys

Methods and systems are disclosed to access memory locations using auxiliary keys in addition to primary keys. Commands are received by a memory management unit to insert or access records in an exact match keyed lookup table where records include keys (i.e., primary keys), auxiliary keys, and data. ... Freescale Semiconductor Inc

03/30/17 / #20170091139

Interconnect sharing with integrated control for reduced pinout

A method and apparatus provide an ability to selectively couple one of the output of the buffer or the output of the digital driver to a data terminal based upon a state of a storage location in which a stored first select indicator is stored and based upon a state of a selection signal. An external serial interface, at a semiconductor die, includes the data terminal, a selection terminal to receive the selection signal, and a clock terminal to receive a clock signal. ... Freescale Semiconductor Inc

03/30/17 / #20170091096

Shared cache protocol for parallel search and replacement

A method includes generating least-recently-used location information for a shared set-associative multi-access cache and next-to least-recently-used location information for the shared set-associative multi-access cache. The method includes concurrently accessing a shared set-associative multi-access cache in response to a first memory request from a first memory requestor and a second memory request from a second memory requestor based on the least-recently-used location information and the next-to least-recently-used location information. ... Freescale Semiconductor Inc

03/30/17 / #20170090983

Data processing unit having a memory protection unit

In a data processing system having a processor and a memory protection unit (mpu), a method includes scheduling, in the processor, a new process to be executed; writing a process identifier (pid) corresponding to the new process into storage circuitry of the mpu; in response to updating the storage circuitry with the pid, configuring the mpu with region descriptors corresponding to the new process; configuring, by an operating system of the processor, the processor to execute the new process in parallel with the configuring the mpu with the region descriptors; and when the configuring the mpu is complete, giving control to the new process to execute on the processor.. . ... Freescale Semiconductor Inc

03/30/17 / #20170089978

Integrated circuit with secure scan enable

An integrated circuit senses attempts to access security-related data stored in registers connectable into a scan chain when the attempt includes locally and selectively asserting a scan-enable signal at a corresponding branch of the scan-enable tree when the integrated circuit is in a secure functional mode. When such an attempt is detected, the integrated circuit (i) generates a security warning that causes a reset of the security-related data and/or (ii) engages a bypass switch to disconnect the scan chain from the respective output terminal to preclude the security-related data from being shifted out of the ic via the scan chain.. ... Freescale Semiconductor Inc

03/30/17 / #20170089945

Mems sensor with reduced cross-axis sensitivity

A mems sensor includes a movable element positioned in spaced apart relationship above a surface of a substrate and a single centrally located suspension anchor formed on the surface of the substrate. First and second rigid beams are coupled to opposing sides of the suspension anchor and are suspended above the surface of the substrate. ... Freescale Semiconductor Inc

03/23/17 / #20170085470

Creating and utilizing customized network applications

This disclosure describes a network flow framework that generates customized network applications based upon user inputs that invokes various software building block functions to process ingress data packets. The network flow framework creates a network application pointer that points to the customized network application, and stores the network application pointer with application classification keys in a classification entry. ... Freescale Semiconductor Inc

03/23/17 / #20170085294

System and method for large dimension equalization using small dimension equalizers

An equalizer comprises an equalizer circuit including a signal input to receive a first frequency-domain signal, another signal input to receive a second frequency-domain signal, and an equalized signal output to provide a first equalized signal based upon the first and second frequency-domain signals. Another equalizer circuit includes a signal input to receive a third frequency-domain signal, another signal input to receive a fourth frequency-domain signal, and an equalized signal output to provide a second equalized signal based upon the third and fourth frequency-domain signals. ... Freescale Semiconductor Inc

03/23/17 / #20170085228

Encapsulated semiconductor device package with heatsink opening, and methods of manufacture thereof

Embodiments include packaged semiconductor devices and methods of manufacturing packaged semiconductor devices. A semiconductor die includes a conductive feature coupled to a bottom surface of the die. ... Freescale Semiconductor Inc

03/23/17 / #20170084786

Electronic devices with nanorings, and methods of manufacture thereof

Systems and methods for electronic devices are presented. A device includes a substrate. ... Freescale Semiconductor Inc

03/23/17 / #20170084599

Electrostatic discharge protection devices and methods

Electrostatic discharge (esd) protection devices and methods. The esd protection devices include a semiconductor substrate, a buried semiconducting layer, and an overlying semiconducting layer. ... Freescale Semiconductor Inc

03/23/17 / #20170084591

Localized redistribution layer structure for embedded component package and method

An embedded component package includes an embedded component substrate. The embedded component substrate includes an electronic component having an active surface including bond pads and a package body encapsulating the electronic component. ... Freescale Semiconductor Inc

03/23/17 / #20170084535

Integrated circuit with power saving feature

An integrated circuit includes a first transistor including a first current electrode, a second current electrode, and a bulk tie; a first conductive line coupled between the first current electrode and a first supply voltage; and a second conductive line coupled to the second current electrode. A resistance of the second conductive line is at least 5 percent greater than a resistance of the first conductive line. ... Freescale Semiconductor Inc

03/23/17 / #20170084524

Terminal structure for active power device

A semiconductor die comprising a terminal structure for an active power device. The terminal structure comprises a metallic layer arranged to be electrically coupled between the active power device and an external contact of an integrated circuit package, a conductive sub-structure extending in parallel with the metallic layer, and located such that, when mounted within an integrated circuit device, the conductive sub-structure lies between the metallic layer and a reference voltage plane, and interconnecting elements extending between the metallic layer and the conductive sub-structure and electrically coupling the metallic layer to the conductive sub-structure. ... Freescale Semiconductor Inc

03/23/17 / #20170084519

Semiconductor package and method of manufacturing same

A semiconductor die is electrically connected to the leads of a flagless lead frame and is fully encapsulated by encapsulant to form a semiconductor package. A method of manufacturing the semiconductor package entails encapsulating a flagless lead frame with a first encapsulant such that a top surface of the leads of the flagless lead frame are exposed from the first encapsulant. ... Freescale Semiconductor Inc

03/23/17 / #20170084491

Wafer level chip scale package with encapsulant

A method of processing a semiconductor wafer includes forming a plurality of die in the semiconductor wafer. The semiconductor wafer has a first brittleness. ... Freescale Semiconductor Inc

03/23/17 / #20170084484

Semiconductor device with graphene encapsulated metal and method therefor

A method for forming a semiconductor structure includes forming a first metal layer over a first dielectric layer, forming a first graphene layer on at least one major surface of the first metal layer, and forming a second dielectric layer over the first metal layer and the first graphene layer. The method further includes forming an opening in the second dielectric layer which exposes the first metal layer, forming a second metal layer over the second dielectric layer and within the opening, and forming a second graphene layer on at least one major surface of the second metal layer, wherein the second graphene layer is also formed within the opening.. ... Freescale Semiconductor Inc

03/23/17 / #20170083554

Tree-search temporal-miss handling

A temporal-miss handler includes updating a data leaf in a tree-structured database of a communications processor with a plurality of threads. A search for the data leaf includes generating at least one search result for one of the plurality of threads. ... Freescale Semiconductor Inc

03/23/17 / #20170083418

Handling defective non-volatile memory

A non-volatile memory (nvm) system has a main nvm sector with multiple memory segments, a redundant nvm sector for storing recovery records, an address-matching circuit having multiple memory sections, each adapted to store a pair of main and substitute addresses, and an nvm controller. The nvm controller is configured to determine if a first memory segment of the main nvm sector is no longer usable and, consequently (i) create a recovery record for storage in the redundant nvm sector that includes the address of the first memory segment and the data associated with the first memory segment, and (ii) add a pair of main and substitute addresses to the address-matching circuit, where the main address is the address of the first memory segment and the substitute address identifies a substitute location for the data associated with the first memory segment.. ... Freescale Semiconductor Inc

03/23/17 / #20170083392

System and method for error detection in a critical system

A system includes a processor having first and second processing units and a memory coupled to the processor. The memory includes processor executable code to implement an application to execute a first process to provide first application output information and to execute a second process to provide second application output information, a selector to provide a first indication that the first process is a critical process and a second indication that the second process is a non-critical process, and an application program interface (api) to run on the first processing unit. ... Freescale Semiconductor Inc

03/23/17 / #20170083391

Safety level specific error response scheme for mixed criticality systems

An error response method for a mixed criticality system includes assigning a safety level to an application executed by a processor. Executing the application includes a transaction between the processor and a resource. ... Freescale Semiconductor Inc

03/23/17 / #20170082686

Data processing system with built-in self-test and method therefor

A scan circuit and methods of operating a scan circuit are provided. The method for operating a scan circuit includes providing a first scan flip-flop which includes an overwrite feature. ... Freescale Semiconductor Inc

03/23/17 / #20170081179

Mems sensor with side port and method of fabricating same

A mems sensor package comprises a mems die that includes a substrate having a sensor formed thereon and a cap layer coupled to the substrate. The cap layer has a cavity overlying a substrate region at which the sensor resides. ... Freescale Semiconductor Inc

03/23/17 / #20170081178

Semiconductor device package with seal structure

A packaged semiconductor device includes a first semiconductor die including interconnect pads and a seal ring pad surrounding at least some of the interconnect pads, a first portion of an plated seal ring structure formed on the seal ring pad, and a second semiconductor die including a second portion of the plated seal ring structure formed on a major surface of the second semiconductor die. The second portion of the plated seal ring structure is coupled to the first portion of the plated seal ring structure to form a seal around a cavity between the first and second semiconductor die. ... Freescale Semiconductor Inc

03/23/17 / #20170081174

Integrating diverse sensors in a single semiconductor device

In some embodiments a method of manufacturing a sensor system can comprise forming a first structure having a substrate layer and a first sensor that is positioned on a first side of the substrate layer, bonding a cap structure over the first sensor on the first side of the substrate layer, and depositing a first dielectric layer over the cap structure. After bonding the cap structure and depositing the first dielectric layer, a second sensor is fabricated on the first dielectric layer. ... Freescale Semiconductor Inc

03/16/17 / #20170078996

Method for determining and recovering from loss of synchronization, communication units and integrated circuits therefor

A method of recovery from a time-synchronization loss in a communication unit between a first processor supporting physical layer communications and a second processor supporting layer-2 communications is described. The method comprises: detecting, by the first processor, that a loss of sync has occurred between the first and second processors; in response to said detecting, stopping sending subsequent physical layer messages from the first processor to the second processor, for example to allow the second processor to consume any old pending messages; re-starting a messaging process by the first processor by sending at least one new message to the second processor with updated system frame number, sfn, and sub-frame, sf, counter value; and receiving at the first processor at least one subsequent response message from the second processor acknowledging receipt of at least one new message with an indication of the received and updated sfn and sf counter value of that message thereby confirming synchronization being restored.. ... Freescale Semiconductor Inc

03/16/17 / #20170077874

Phase shift and attenuation circuits for use with multiple-path amplifiers

Embodiments of circuits for use with an amplifier that includes multiple amplifier paths include a first circuit and a second circuit in parallel with the first circuit. The first circuit includes a first input coupled to a first power divider output, a first output coupled to a first amplifier path of the multiple amplifier paths, and a first adjustable phase shifter and a first attenuator series coupled between the first input and the first output. ... Freescale Semiconductor Inc

03/16/17 / #20170077872

Low power circuit for amplifying a voltage without using resistors

A resistor-less amplifying circuit includes a plurality of resistor-less cells. Each cell includes a plurality of mos transistors. ... Freescale Semiconductor Inc

03/16/17 / #20170077805

High power driver

A transistor circuit includes a transistor having a control electrode, a first current electrode, and a second current electrode. A turn off mode change circuit has a signal input that receives a series of pulses, an output coupled to the control electrode of the transistor, and a control input. ... Freescale Semiconductor Inc

03/16/17 / #20170077740

Wireless power transmitters with wide input voltage range and methods of their operation

The embodiments described herein provide a power transmitter for wireless charging of an electronic device and methods of its operation. The power transmitter uses an inverter configured to generate a square wave from a potentially wide ranging dc input voltage. ... Freescale Semiconductor Inc

03/16/17 / #20170077295

Partially biased isolation in semiconductor devices

A device includes a semiconductor substrate, a doped isolation barrier disposed in the semiconductor substrate and defining a core device area within the doped isolation barrier, an isolation contact region disposed in the semiconductor substrate outside of the core device area and to which a voltage is applied during operation, and a depleted well region disposed in the semiconductor substrate outside of the core device area. The depleted well region electrically couples the isolation contact region and the doped isolation barrier such that the doped isolation barrier is biased at a voltage level lower than the voltage applied to the isolation contact region.. ... Freescale Semiconductor Inc

03/16/17 / #20170077245

Segmented field plate structure

A device includes a transistor formed over a substrate. The transistor includes a source structure, a drain structure, and a gate structure. ... Freescale Semiconductor Inc

03/16/17 / #20170077233

Multi-gate semiconductor devices with improved hot-carrier injection immunity

A semiconductor device includes a substrate having a first dopant type, a first gate electrode and second gate electrode formed over the substrate and spatially separated from each other, a first region of a second dopant type, having a pocket of the first dopant type, formed in the substrate between the first and second gate electrodes, the pocket being spaced apart from the first and second gate electrodes, a silicide block over the first region, a source region formed in the substrate on an opposing side of the first gate electrode from the first region and having the second dopant type, a drain region formed in the substrate on an opposing side of the second gate electrode from the first region, the drain region having the second dopant type, and a second pocket of the first dopant type formed in the drain region adjacent to the second gate electrode.. . ... Freescale Semiconductor Inc

03/16/17 / #20170077219

Partially biased isolation in semiconductor devices

A device includes a semiconductor substrate, a doped isolation barrier disposed in the semiconductor substrate and defining a core device area within the doped isolation barrier, an isolation contact region disposed in the semiconductor substrate outside of the core device area, and a body region disposed in the semiconductor substrate within the core device area, and in which a channel is formed during operation. The body region is electrically tied to the isolation contact region. ... Freescale Semiconductor Inc

03/16/17 / #20170077072

System-in-packages containing preassembled surface mount device modules and methods for the production thereof

Methods for producing system-in-packages (sips) containing embedded surface mount device (smd) modules are provided, as sips containing smd modules. In one embodiment, the fabrication method includes positioning a semiconductor die and first preassembled smd module, which contains a plurality of smds soldered to an interposer substrate, in predetermined spatial relationship. ... Freescale Semiconductor Inc

03/16/17 / #20170077051

Monolithic microwave integrated circuits

Low q associated with passive components of monolithic integrated circuits (ics) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., ≧100 ohm-cm) semiconductor substrates and lower resistance inductors for the ic. This eliminates significant in-substrate electromagnetic coupling losses from planar inductors and interconnections overlying the substrate. ... Freescale Semiconductor Inc

03/16/17 / #20170076702

Systems and methods for graphical layer blending

The embodiments described herein provide devices and methods for image processing. Specifically, the embodiments described herein provide techniques for blending graphical layers together into an image for display. ... Freescale Semiconductor Inc

03/16/17 / #20170076116

Model-based runtime detection of insecure behavior for system on chip with security requirements

A runtime classifier hardware circuit is incorporated into an electronic device for implementing hardware security by storing a support vector model in memory which is derived from pre-silicon verification data to define secure behavior for a first circuit on the electronic device; monitoring input and/or output signals associated with the first circuit using the runtime classifier hardware circuit which compares the input and/or output signals to the support vector model to detect an outlier input signal and/or outlier output signal for the first circuit; and blocking the outlier input and/or output signal from being input to or output from the first circuit.. . ... Freescale Semiconductor Inc

03/16/17 / #20170075825

Automatic memory security

A computing device has a security module that (i) receives a request to decrypt encrypted data; (ii) sets up an uninterruptible timer based on a specified time interval; (iii) decrypts the encrypted data to generate and stores corresponding decrypted data in a memory within the computing device; and (iv) provides a trigger signal to delete the decrypted data from the memory after expiration of the specified time interval as determined by the timer. The security module limits the duration that the decrypted data is stored in the memory and thus reduces the chance the data can be subject to unauthorized accessed.. ... Freescale Semiconductor Inc

03/16/17 / #20170075792

Method and system to display and browse program trace using source code decoration

A method and apparatus are provided for navigating source code (112) by capturing a program trace data history (134) from a target (150) in response to execution of application executable code (123) thereon and decorating the source code blocks (252) on a graphical user interface viewer (251) by displaying an execution instance control indicator (253-255) corresponding to each detected execution instance, where an execution instance control enables control of which execution instance is displayed and an execution instance indicator displays information about the sequence of instructions that were executed at runtime in that execution instance.. . ... Freescale Semiconductor Inc

03/16/17 / #20170074738

Differential capacitive output pressure sensor and method

A differential capacitive output pressure sensor device includes a pressure sensor diaphragm layer comprising a pressure sensing diaphragm portion, a movable electrode on the pressure sensing diaphragm portion, a fixed electrode, and a device layer electrode. The pressure sensor device further includes a device layer including a fixed element connected to the device layer electrode and a movable element connected to the movable electrode. ... Freescale Semiconductor Inc

03/09/17 / #20170070768

Video stream decoder

A video stream decoder for decoding a multiple parallel-input video streams from multiple video cameras permits continuance of the decoding process even if one of the streams has stalled or if a start code of a currently active stream has become corrupted. A counter triggers a stream switching module to switch to a different input video stream on a round-robin or priority basis after a preset time period elapsed if no start code of a currently active stream has been detected.. ... Freescale Semiconductor Inc

03/09/17 / #20170070265

Wireless charger using frequency aliasing fsk demodulation

A frequency shift keying (fsk) demodulation component having of a sampler that receives an fsk modulated signal, samples the received fsk modulated signal, and outputs the sampled signal. The fsk demodulation component further includes a low pass filter that filters the sampled signal, and a frequency shift detector that detects shifts in frequency of the low pass filtered sampled signal. ... Freescale Semiconductor Inc

03/09/17 / #20170070213

Input buffer with selectable hysteresis and speed

A buffer provides a signal at an output node as a function of an input signal. First and second buffer stages have respective current conduction paths for asserting the output signal. ... Freescale Semiconductor Inc

03/09/17 / #20170070202

Impedance matching device with coupled resonator structure

An impedance matching device is presented. The device includes an input terminal configured to receive a radio frequency signal, and an output terminal configured to couple to an amplifier. ... Freescale Semiconductor Inc

03/09/17 / #20170070137

Charge pump circuit for providing multiplied voltage

A charge pump comprises one or more pump stages for providing a negative boosted output voltage. Each of the one or more pump stages comprises a p-channel transistor formed in an isolated p-well and an n-channel transistor coupled in series with the p-channel transistor. ... Freescale Semiconductor Inc

03/09/17 / #20170069607

Stacked microelectronic package assemblies and methods for the fabrication thereof

Stacked microelectronic package assemblies are provided, as are methods for producing stacked microelectronic package assemblies. In one embodiment, the stacked microelectronic package assembly includes a base package layer onto which a stacked bridge device is stacked. ... Freescale Semiconductor Inc

03/09/17 / #20170069572

Apparatus and method for placing stressors within an integrated circuit device to manage electromigration failures

An integrated circuit device includes a first line in a first metal layer of the integrated circuit device, wherein the first line forms at least a portion of an interconnect, a second line in a second metal layer of the integrated circuit device, and a first via that couples the first line to the second line. The integrated circuit device further includes a first stressor disposed at a first area of the interconnect, wherein the first area at least partially overlaps the first via, wherein the first stressor alters an electromigration stress profile for the interconnect by altering a stress at the first area to be less tensile.. ... Freescale Semiconductor Inc

03/09/17 / #20170067932

Compensation and calibration of multiple mass mems sensor

A system includes a mems sensor having dual proof masses capable of moving independently from one another in response to forces imposed upon the proof masses. Each proof mass includes an independent set of sense contacts configured to provide output signals corresponding to the physical displacement of the corresponding sense mass. ... Freescale Semiconductor Inc

03/02/17 / #20170064300

Video encoder with adjustable intra-refresh rate

An encoding system for converting video data to a media stream based on a given intra-refresh rate includes an encoder for encoding the video data to frames based on the given intra-refresh rate, a decoder for reconstructing the encoded frames, and an evaluation unit for scoring macro blocks (mbs) of a current frame being decoded. A score of an intra-mb is defined as a predetermined value, and a score of an inter-mb is generated based on the scores of mbs of previous frames. ... Freescale Semiconductor Inc

03/02/17 / #20170063546

Data processing system with secure key generation

A method of secure key generation includes writing a predetermined write pattern to a particular address of volatile memory, wherein the volatile memory includes bit lines; reading data from the particular address while applying a first set of operating variables to the volatile memory, subsequent to the writing; sensing a first plurality of timing mismatches during the reading, wherein sense amplifiers are coupled to the bit lines, each latch of a plurality of latches is coupled between a respective pair of sense amplifiers, and each latch is configured to output a data value that indicates a respective timing mismatch between outputs of the respective pair of sense amplifiers; and determining an entropy ratio for the particular address, wherein the entropy ratio is equivalent to a ratio of a first number of latches that output a first data value to a second number of latches that output a second data value.. . ... Freescale Semiconductor Inc

03/02/17 / #20170063371

Substrate bias circuit and method for biasing a substrate

A substrate bias circuit and method for biasing a substrate are provided. A substrate bias circuit includes a first voltage source, a second voltage source, a diode coupled between the first voltage source and the second voltage source, and a plurality of transistors, each transistor in the plurality of transistors having a substrate terminal. ... Freescale Semiconductor Inc

03/02/17 / #20170063350

Multi-bit flip-flop with shared clock switch

A multi-bit flip-flop has first and second one-bit flip-flops. The multi-bit flip-flop employs inter-cell clock switch (csw) sharing in which the first and second one-bit flip-flops share at least one clock switch. ... Freescale Semiconductor Inc

03/02/17 / #20170063348

Programmable resistive elements as variable tuning elements

The present disclosure provides circuit and method embodiments for calibrating a signal of an integrated circuit. A programmable resistive element is coupled in series with a node of the integrated circuit, where at least part of the integrated circuit is formed in at least one front end of line (feol) device level. ... Freescale Semiconductor Inc

03/02/17 / #20170063346

Configurable fir filter with segmented cells

A fir filter includes segment cells, each of which is configurable as an interpolation filter, a decimation filter, a symmetric filter, or an asymmetric filter. Two or more of the segment cells are configurable to be cascaded to form an interpolation filter, a decimation filter, a symmetric filter, an asymmetric filter, a complex symmetric filter, or a complex asymmetric filter. ... Freescale Semiconductor Inc

03/02/17 / #20170062320

Universal bga substrate

A universal substrate for assembling ball grid array (bga) type integrated circuit packages has a non-conducting matrix, an array of conducting vias extending between top and bottom surfaces of the matrix, and one or more instances of each of two or more different types of fiducial pairs on the top surface of the matrix. Each instance of each different fiducial pair indicates a location of a different via sub-array of the substrate for a different bga package of a particular package size. ... Freescale Semiconductor Inc

03/02/17 / #20170062311

Integrated circuit with on-die power distribution bars

A packaged ic device has a power bar assembly with one or more power distribution bars, mounted on top of the ic die, which enables assembly using a lead frame that does not include any power distribution bars. External power supply voltages are brought to the ic die by (i) a corresponding first bond wire that connects a lead frame lead to a corresponding die-mounted power distribution bar and (ii) a corresponding second bond wire that connects the power distribution bar to a corresponding bond pad on the ic die. ... Freescale Semiconductor Inc

03/02/17 / #20170062052

Ternary content addressable memory (tcam) with programmable resistive elements

A content addressable memory device includes a first memory cell having three programmable resistive elements coupled in parallel. The first terminals of the first, second, and third programmable resistive elements are coupled to a first node, the second terminal of the first programmable resistive element coupled to a first source line voltage, the second terminal of the second programmable resistive element coupled to a second source line voltage, and the second terminal of the third programmable resistive element coupled to a first supply voltage. ... Freescale Semiconductor Inc

03/02/17 / #20170062049

Static random access memory (sram) with programmable resistive elements

A memory device includes a volatile memory cell and a non-volatile memory cell. The non-volatile memory cell includes a first resistive element having a first terminal and a second terminal and a second resistive element having a first terminal and a second terminal. ... Freescale Semiconductor Inc

03/02/17 / #20170060786

Multiple request notification network for global ordering in a coherent mesh interconnect

A data processing system includes a plurality of processing unit. Each processing unit includes notification storage circuitry configured to store a notification indicator corresponding to each processing unit which indicates whether the processing unit has an outstanding coherent memory request, and multiple request storage circuitry configured to store a multiple request indicator corresponding to each processing unit which indicates whether the processing unit has more than one outstanding request. ... Freescale Semiconductor Inc

03/02/17 / #20170060781

Fast secure boot from embedded flash memory

A technique that reduces the startup time of a processing system authenticates a proxy for an image stored in tracked memory instead of authenticating the image stored in the tracked memory. A controller generates an alteration log authentication code based on an alteration log that is updated prior to programming the image stored in tracked memory. ... Freescale Semiconductor Inc

03/02/17 / #20170060669

Safe secure bit storage with validation

A bit storage device, integrated circuit, and method are provided. The bit storage device comprises registers to store an actual value, an inverse value, a differential actual value, and a differential inverse value, a validation circuit including validation inputs coupled to outputs of the registers and including a validity output to provide a validity indication, and a write circuit including write circuit inputs coupled to the registers, the write circuit configured to cause, at a first clock edge, the first register to store the actual value and either the second register to store the inverse value or the fourth register to store the differential inverse value, and, at a second clock edge, the third register to store the differential actual value and the other of the second register and the fourth register to store to store the inverse value or the differential inverse value, respectively.. ... Freescale Semiconductor Inc

03/02/17 / #20170060582

Arbitrary instruction execution from context memory

Arbitrary instruction execution from context memory. In some embodiments, an integrated circuit includes a processor core; a context management circuit coupled to the processor core; and a debug support circuit coupled to the context management circuit, where: the context management circuit is configured to halt a thread running on the processor core and save a halted thread context for that thread into a context memory distinct from the processor core, where the halted thread context comprises a fetched instruction as the next instruction in the execution pipeline; the debug support circuit is configured instruct the context management circuit to modify the halted thread context in the context memory by replacing the fetched instruction with an arbitrary instruction; and the context management circuit is further configured to cause the thread to resume using the modified thread context to execute the arbitrary instruction.. ... Freescale Semiconductor Inc

03/02/17 / #20170059650

High capacity i/o (input/output) cells

A wafer structure has a plurality of semiconductor die. Each semiconductor die includes circuitry, a test pad for use in testing the circuitry, and a plurality of external pins. ... Freescale Semiconductor Inc

02/23/17 / #20170055045

Recovering from discontinuities in time synchronization in audio/video decoder

A decoder for decoding compressed video and audio data. The demultiplexer provides a prediction of a presentation timestamp (pts) after a discontinuity occurs that is conditional on whether data of the elementary bit stream is still present in the demultiplexer and control decoder module when the discontinuity is detected. ... Freescale Semiconductor Inc

02/23/17 / #20170054993

Media display system

A display system for displaying a media stream based on a given access point includes a decoder for decoding frames of the media stream, and an evaluation unit for scoring macro blocks (mbs) of a current frame. A score of an intra-mb is defined as a predetermined value, and a score of an inter-mb is generated based on scores of mbs in previously decoded frames. ... Freescale Semiconductor Inc

02/23/17 / #20170054419

Output impedance-matching network having harmonic-prevention circuitry

An output impedance-matching network for an rf power amplifier die includes a harmonic-prevention circuit that functions like a short circuit at a fundamental frequency of the amplifier and an open circuit at a second harmonic frequency of the amplifier. In certain implementations, the harmonic-prevention circuit has one or more parallel, reactive (lc) legs that resonate at the fundamental frequency and a parallel, reactive (capacitive) leg that causes the harmonic-prevention circuit to resonate at the second harmonic frequency. ... Freescale Semiconductor Inc

02/23/17 / #20170053999

Semiconductor device with enhanced 3d resurf

A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate and spaced from one another along a first lateral dimension, and a drift region in the semiconductor substrate and through which charge carriers drift during operation upon application of a bias voltage between the source and drain regions. The drift region has a notched dopant profile in a second lateral dimension along an interface between the drift region and the drain region.. ... Freescale Semiconductor Inc

02/23/17 / #20170053930

Semiconductor device having a metal oxide metal (mom) capacitor and a plurality of series capacitors and method for forming

A capacitor module includes a semiconductor substrate of a first polarity. The substrate includes a deep well of a second polarity, a first well of the first polarity over the deep well, a second well of the second polarity over at least a portion of the deep well, a first capacitor including the first well as a first electrode, a dielectric layer over the first electrode, and an electrically conductive layer as a second electrode over the dielectric layer, and a second capacitor including the second well as a first electrode, a dielectric layer over the first electrode, and an electrically conductive layer as a second electrode over the dielectric layer. ... Freescale Semiconductor Inc

02/23/17 / #20170053862

Three-dimensional integrated circuit systems in a package and methods therefor

A method for making a packaged semiconductor device includes dispensing a first adhesive into a first cavity of a substrate having a first major surface and a second major surface. The first cavity extends into the substrate from the second major surface. ... Freescale Semiconductor Inc

02/23/17 / #20170053710

Storage element with storage and clock tree monitoring circuit and methods therefor

A storage element with monitoring circuit, comprising a previous state information storage element configured to record a previous state of a monitored state information storage element, a state change indication unit having a clock input terminal coupled to the clock signal input interface, a state change indication unit being configured to generate a state change indication signal indicative of whether the monitored state information storage element shall have performed a state change by observing the data at a data input interface and a data output terminal, and a state change confirmation unit configured to generate a storage fault indicator by observing the data output terminal of the monitored state information storage element and the data output of the previous state information storage element and checking whether the result of this observation is in line with the state change indicator.. . ... Freescale Semiconductor Inc

02/23/17 / #20170052859

Fast write mechanism for emulated electrically erasable (eee) system

A method of operating an emulated electrically erasable (eee) memory system includes entering a quick write mode for a predetermined amount of time, upon detection of imminent power loss of the eee memory system. A first write request is received immediately subsequent to entering the quick write mode, where the first write request includes a first address of an emulated memory of the eee memory system and associated first data to be written at the first address. ... Freescale Semiconductor Inc

02/23/17 / #20170052834

Data processing system having messaging

A method of handling requests between contexts in a processing system includes, in a current context of a source processing system element (pse): executing a send-and rendezvous instruction that specifies a destination pse, a queue address in the destination pse, a set of source registers, and a set of receive registers; and sending a send-and-rendezvous message (srm) to the destination pse, wherein the srm includes an address of the destination pse, a destination queue address, a source pse address, and an identifier of the current context in the source pse.. . ... Freescale Semiconductor Inc

02/23/17 / #20170052082

Electrically conductive barriers for integrated circuits

Electrically conductive barriers for integrated circuits and integrated circuits and methods including the electrically conductive barriers. The integrated circuits include a semiconductor substrate, a semiconductor device supported by a device portion of the substrate, and a plurality of bond pads supported by a bond pad portion of the substrate. ... Freescale Semiconductor Inc

02/16/17 / #20170048969

Radio frequency coupling and transition structure

A radio frequency transmission structure couples a rf signal between a first and a second radiating elements arranged at a first and a second sides of a first dielectric substrate, respectively. The rf coupling structure comprises first and second coupling structures. ... Freescale Semiconductor Inc

02/16/17 / #20170048915

System and method for radio base station device hot reconnection (hot plugging)

A method performed by a radio equipment control (rec) device, including storing values of link configuration registers of a radio equipment control (rec) device at shadow registers of the rec device in response to determining that a synchronization of a current communication link between the rec device and a radio equipment (re) device has been lost. The method further including re-establishing the current communication link based on the values of the link configuration registers stored at the shadow registers of the rec device.. ... Freescale Semiconductor Inc

02/16/17 / #20170048910

System and method for radio base station device hot switching and hot swapping

A method performed by a radio base station, the method including determining a link configuration of a first communication link, the first communication link being a current communication link between a first radio equipment control (rec) device and a radio equipment (re) device. The method further including in response to determining that a second communication link between a second rec device and the re device is to replace the current communication link, instead of the first communication link, establishing, by the second rec device, the second communication link based on the determined link configuration of the first communication link.. ... Freescale Semiconductor Inc

02/16/17 / #20170047933

Phase locked loop circuit, integrated circuit, communication unit and method therefor

A phase locked loop circuit includes a voltage controlled oscillator, vco, configured to receive an oscillator tuning voltage; a phase detector configured to receive an input signal and a reference signal and generate a phase difference pulse signal that is varied in accordance with the oscillator tuning voltage; a loop filter having an input and an output; and a level shifter circuit coupled to an output of the phase detector and the loop filter input and configured to apply a level shift to the phase difference pulse signal such that the level shift is configured to compensate vco gain and the loop filter averages the phase difference pulse signal to output an averaged signal to the vco.. . ... Freescale Semiconductor Inc

02/16/17 / #20170047840

Zero-current crossing detection circuits

Systems and methods for zero-current crossing detection circuits. In some embodiments, a circuit may include a buck converter comprising a high-side switch, a low-side switch, and an inductor; a zero-current crossing detection circuit comprising a reference switch coupled to a current source, where the reference switch is controllable conjointly with the low-side switch; an amplifier coupled to: (a) a first node between the current source and reference switch, where in operation the first node has a positive voltage value during an interval of interest, and a (b) second node between the low-side switch and the inductor, where in operation the second node has a negative voltage value during the interval of interest; and a comparator coupled to the amplifier, the comparator configured to output a flag in response to a detection that a decreasing current through the inductor has reached a predetermined value.. ... Freescale Semiconductor Inc

02/16/17 / #20170047271

Method for making a semiconductor device having an interposer

A semiconductor device and a method for making the semiconductor device are provided. The semiconductor device comprises a leadframe and a metal interposer. ... Freescale Semiconductor Inc

02/16/17 / #20170047101

Sensing and reference voltage scheme for random access memory

A method uses a memory that includes a plurality of non-volatile memory (nvm) cells; a plurality of word lines; a plurality of bit lines; and an amplifier having an inverting input, a non-inverting input, and an output; and a capacitance coupled to the inverting input includes. A reference is coupled to the non-inverting input. ... Freescale Semiconductor Inc

02/16/17 / #20170047098

Non-volatile dynamic random access memory (nvdram) with programming line

A memory circuit includes a first bit line, a second bit line, and a memory cell that is coupled to first bit line and the second bit line. The memory cell includes a capacitor, a first pass gate transistor, a non-volatile (nv) element, and a second pass gate transistor. ... Freescale Semiconductor Inc

02/16/17 / #20170046271

Tagged cache for data coherency in multi-domain debug operations

A tagged cache is disclosed for data coherency in multi-domain debug operations. Access requests to a memory within a target device are received for data views associated with debug operations, and access requests include virtual addresses associated with virtual address spaces and client identifiers associated with requesting data views. ... Freescale Semiconductor Inc

02/16/17 / #20170045467

Systems and methods for detecting change in species in an environment

One embodiment of making a diode includes forming a first electrode to which an electric field is applied; forming a second electrode to which the electric field is applied; and forming a vapor gap region between the first electrode and the second electrode. A total capacitance measured between the first electrode and the second electrode varies based on presence of a polar vapor species on at least a portion of an electrode surface of at least one of the first electrode and the second electrode.. ... Freescale Semiconductor Inc

02/16/17 / #20170044005

Microelectronic packages having axially-partitioned hermetic cavities and methods for the fabrication thereof

Microelectronic packages and methods for producing microelectronic packages are provided. In one embodiment, the method includes bonding a first microelectromechanical systems (mems) die having a first mems transducer structure thereon to a cap piece. ... Freescale Semiconductor Inc

02/09/17 / #20170040943

Electronic device with capacitor bank linearization and a linearization method

An electronic device comprises a controllable capacitor bank and a capacitive divider arranged in parallel with the capacitor bank and configured to linearize the capacitor bank in a linearization frequency range of a frequency characteristic of the electronic device. The capacitive divider comprises a series arrangement of a first series capacitance, and a main capacitor bank. ... Freescale Semiconductor Inc

02/09/17 / #20170040911

Electrical energy generation within a vehicle tire

An apparatus for installation within a tire for a vehicle includes a flexible arm and a power generating element coupled to the flexible arm for generating electrical energy. One end of the flexible arm is coupled to a rim of the tire. ... Freescale Semiconductor Inc

02/09/17 / #20170040826

Wireless power source and method for simultaneous, non-radiative, inductive, wireless power transfer to two or more devices to be charged

A wireless power source 1 for simultaneous, non-radiative, inductive, wireless power transfer to two or more devices to be charged. The wireless power source 1 comprises a set of transmitter coils for generating an electromagnetic field 3 in a three-dimensional charging space 2 and a controller connected to the set of transmitter coils for controlling the set of transmitter coils to rotate the electromagnetic field 3 in the charging space around a rotational axis.. ... Freescale Semiconductor Inc

02/09/17 / #20170040282

Semiconductor device with protective material and method for encapsulating

A semiconductor device includes a plurality of wire bonds formed on a surface of the semiconductor device by bonding each of a plurality of copper wires onto corresponding ones of a plurality of aluminum pads; a protective material is applied around the plurality of wire bonds, the protective material having a first ph; and at least a portion of the semiconductor device and the protective material are encapsulated with an encapsulating material having a second ph, wherein the first ph of the protective material is for neutralizing the second ph of the encapsulating material around the plurality of wire bonds.. . ... Freescale Semiconductor Inc

02/09/17 / #20170039932

Display control apparatus and method of configuring an interface bandwidth for image data flow

A display control apparatus comprising at least one memory element within which image data is stored, at least one display controller arranged to read from the, or each, memory element the image data and to output display data generated from the read image data to at least one display device. The display control apparatus further comprises at least one interface component via which the display controller is arranged to read image data from the memory element. ... Freescale Semiconductor Inc

02/02/17 / #20170034522

Workload balancing in multi-core video decoder

A multi-core decoder for decoding compressed video picture data decodes compressed video picture data. Multi-core processing resources parse compressed video picture data, and decode structures of picture data stored in a temporary storage. ... Freescale Semiconductor Inc

02/02/17 / #20170034069

Reduction of silicon area for ethernet pfc protocol implementation in queue based network processors

In a pipelined network processor, a first stage in the pipeline is responsive to receipt of a pause indication from a third stage. The pause indication is associated with one of a plurality of ports and priority classes of frames advancing through the pipeline. ... Freescale Semiconductor Inc

01/26/17 / #20170026696

Interconnecting system, video signal transmitter and video signal receiver for transmitting an n-symbol data signal

The present application relates to an interconnect system comprising a video signal transmitter and video signal receiver for transmitting a stream of n-symbol data signals over an error prone wired parallel bus having at least n data signal lines. A line scrambler at the video signal transmitter is configured to accept an n-symbol data signal having a sequence of data symbols in a predefined order and to output a permuted sequence of data symbols in accordance with a permutation. ... Freescale Semiconductor Inc

01/26/17 / #20170026605

Interconnecting system, video signal transmitter and video signal receiver for transmitting an n-symbol data signal

The present application relates to an interconnect system for transmitting a stream of n-symbol data signals, which comprises a parallel data signal line bus, a line scrambler, a line de-scrambler and a defect detector. The defect detector is configured to detect one or more defective data signal lines. ... Freescale Semiconductor Inc

01/26/17 / #20170026266

Bandwidth estimation circuit, computer system, method for estimating and predicting the bandwidth and computer readable program product

The present invention relates to a bandwidth estimation circuit for estimating and predicting the bandwidth of a computer system, the bandwidth estimation circuit comprising: a memory unit which is configured to store multiple predetermined bandwidth envelopes, wherein each one of the predetermined bandwidth envelopes is assigned to a feature of a code of an application program; a bandwidth measurement unit which is configured to online measure the bandwidth of a data transaction based on the code; a selection unit coupled either to the memory unit and the bandwidth measurement unit and configured to find the nearest bandwidth envelopes in the memory unit for the measured bandwidth; a calculation unit which is configured to calculate a ratio between the selected bandwidth envelopes, to construct a new bandwidth envelope by applying an interpolation function based on the calculated ratio and to calculate an estimated bandwidth by applying the new bandwidth envelope. The present invention also relates to a computer system, a method for estimating and predicting the bandwidth and a computer readable program product.. ... Freescale Semiconductor Inc

01/26/17 / #20170026023

Balun transformer

A balun includes a dielectric layer having first and second sides, an electrically conductive plate on the second side of the dielectric layer, a first electrically conductive line on the first side and comprising a first end electrically connected to a first terminal and a second end, a second electrically conductive line on the second side and comprising a third end electrically coupled to a second terminal and a fourth end connected to an unbalanced terminal and a micro strip line comprising a fifth end electrically connected to the third end and a sixth end. The first electrically conductive line overlaps the second electrically conductive line. ... Freescale Semiconductor Inc

01/26/17 / #20170025349

Semiconductor wafers with through substrate vias and back metal, and methods of fabrication thereof

An embodiment of a semiconductor wafer includes a semiconductor substrate, a plurality of through substrate vias (tsvs), and a conductive layer. The tsvs extend between first and second substrate surfaces. ... Freescale Semiconductor Inc

01/26/17 / #20170024502

Simulation of hierarchical circuit element arrays

This disclosure describes a design tool that iteratively performs simulation sets on an integrated circuit design, each corresponding to a different hierarchical level with each of the simulation sets producing a different set of simulation results. Each of the simulation sets utilizes a different set of local parameter values that include extreme instance local parameter values based on the set of simulation results of a preceding simulation set. ... Freescale Semiconductor Inc

01/26/17 / #20170024342

Interrupt management system for deferring low priority interrupts in real-time system

An interrupt management system for managing multiple interrupts includes a timer and an interrupt management sub-system. The interrupt management sub-system receives first and second interrupts, determines the first interrupt to be a real-time interrupt and the second interrupt to be a non-real-time interrupt, initializes the timer for a predetermined time period on reception of the first interrupt, and determines whether the second interrupt is either a maskable or non-maskable interrupt. ... Freescale Semiconductor Inc

01/26/17 / #20170024270

Dma controller for a data processing system, a data processing system and a method of operating a dma controller

The present application relates to a direct memory access, dma, controller for a data processing system and a method of operating the dma controller is provided. The dma controller comprises a transfer table, a data path processing block and a comparator logic block. ... Freescale Semiconductor Inc

01/26/17 / #20170023958

Linear voltage regulator

A voltage regulator includes an error amplifier, a voltage buffer, a transistor, a frequency compensation circuit, a capacitor, and a resistive network. The error amplifier receives a reference signal and a feedback signal, and generates an intermediate control signal. ... Freescale Semiconductor Inc

01/26/17 / #20170023608

Multi-axis inertial sensor with dual mass and integrated damping structure

An inertial sensor includes first and second movable elements suspended from a substrate and interconnected by a beam. The second movable element is positioned laterally adjacent to the first movable element, and each of the movable elements has a mass that is asymmetric relative to a rotational axis. ... Freescale Semiconductor Inc

01/26/17 / #20170023606

Mems device with flexible travel stops and method of fabrication

A microelectromechanical systems (mems) device is provided, which includes a substrate; a proof mass positioned in space above a surface of the substrate, where the proof mass is configured to move relative to the substrate; a flexible travel stop structure formed within the proof mass, where the flexible travel stop structure includes a contact lever connected to the proof mass via flexible elements; and a bumper formed on the surface of the substrate, where the contact lever is aligned to make contact with the bumper when the proof mass moves toward the substrate.. . ... Freescale Semiconductor Inc

01/26/17 / #20170023427

Self test for capacitive pressure sensors

During a first cycle of operation, first and second bottom electrodes of a split bottom electrode are electrically connected together. A total capacitance between the split bottom electrode and a top electrode layer is measured to determine the ambient pressure. ... Freescale Semiconductor Inc

01/19/17 / #20170019675

Parallel decoder with inter-prediction of video pictures

A parallel decoder for decoding compressed video picture data including inter-coded picture item data with motion vector data. A decoding module decodes picture data stored in a temporary storage. ... Freescale Semiconductor Inc

01/19/17 / #20170017485

System and method for updating firmware in real-time

A system controlled by firmware includes a memory and a processor. The memory includes a first memory block for storing non-programmable code used for performing key functions, and second and third memory blocks for storing programmable code used for performing normal functions. ... Freescale Semiconductor Inc

01/19/17 / #20170017260

Timer rings having different time unit granularities

In a processing system, a method includes selecting, at a timer management component of a processor, a timer ring of a set of timer rings for a requested timer based on a time unit granularity associated with the requested timer, wherein each timer ring of the set has a different time unit granularity. The method further includes instantiating the requested timer in a selected entry of the selected timer ring. ... Freescale Semiconductor Inc

01/19/17 / #20170017259

Coherent timer management in a multicore or multithreaded system

In a processing system, a method includes transmitting a timer expiration notification from a timer management component of a processor to one or more other components of the processor in response to expiration of a timer. The method further includes transmitting, from a component of the processor that requested instantiation of the timer, a timer release confirmation message to the timer management component in response to the timer expiration notification, the timer release confirmation message confirming that the component has released the timer. ... Freescale Semiconductor Inc

01/19/17 / #20170016423

Method and apparatus for determining a value of a variable parameter

A control methodology and apparatus for an engine suitable for use in capacitor discharge ignition systems for internal combustion engines or brushless dc motors is provided, which make use of a simple logic block to determine for instance an ignition timing advance angle or duty cycle signal based on actual engine speed versus engine control parameter data stored in a table, which is a read-only memory, preferably configurable. To minimise memory space, a small number of values of engine control parameter versus engine speed are stored in the table and the logic block determines the required engine control signal for a measured value of engine speed by an interpolation process, preferably linear interpolation.. ... Freescale Semiconductor Inc

01/12/17 / #20170011905

Method of making a packaged semiconductor device

A method of removing metal oxide from electrically conductive contacts of a packaged semiconductor device includes mixing a solution including vinegar and nitric acid, applying the solution to the contacts for a time sufficient to remove the metal oxide from the contacts, and rinsing the solution from the contacts.. . ... Freescale Semiconductor Inc

01/12/17 / #20170009387

Woven signal-routing substrate for wearable electronic devices

A woven signal-routing substrate for a wearable electronic devoce has conductive warps and wefts that are woven with each other and with insulative warps and wefts. Woven electrical cross-connections are formed at some of the intersections of the conductive warps and wefts, while no electrical cross-connections are formed at other intersections, to provide a signal-routing architecture for the substrate that can be used to route signals between electronic components of the wearable device. ... Freescale Semiconductor Inc

01/05/17 / #20170006257

Video buffering and frame rate doubling device and method

. . A frame buffer having a size of one video frame of a video stream is provided. The video stream has a source frame rate. ... Freescale Semiconductor Inc

01/05/17 / #20170005650

Noise suppression circuit for a switchable transistor

A noise suppression circuit comprises a switchable transistor and an amplifier having a first amplifier input terminal electrically coupled to an output terminal of the switchable transistor for sensing a voltage thereat, and an amplifier output terminal electrically coupled to a control terminal of the switchable transistor for outputting a control voltage thereto. The amplifier is configured, based on the sensed voltage and a transition mode threshold voltage of the switchable transistor which defines a boundary between operation modes of the switchable transistor, to set the voltage at the transistor output terminal to at least the transition mode threshold voltage such that for noise frequencies below or corresponding to the switching frequency of the switchable transistor a resistive path is provided between the transistor output terminal and the transistor reference terminal and for noise frequencies above the switching frequency of the switchable transistor the resistive path is substantially interrupted.. ... Freescale Semiconductor Inc

01/05/17 / #20170005621

Semiconductor package having an isolation wall to reduce electromagnetic coupling

A system and method for packaging a semiconductor device that includes a wall to reduce electromagnetic coupling is presented. A semiconductor device has a substrate on which a first circuit and a second circuit are formed proximate to each other. ... Freescale Semiconductor Inc

01/05/17 / #20170005081

Esd protection structure

An esd protection structure comprising a thyristor structure. The thyristor structure is formed from a first p-doped section comprising a first p-doped well formed within a first region of a p-doped epitaxial layer, a first n-doped section comprising a deep n-well structure, a second p-doped section comprising a second p-doped well formed within a second region of the epitaxial layer, and a second n-doped section comprising an n-doped contact region formed within a surface of the second p-doped well. ... Freescale Semiconductor Inc

01/05/17 / #20170004867

Non-volatile random access memory (nvram)

A non-volatile memory device includes an array of non-volatile memory cells. A memory cell in the array of memory cells includes a first resistive element including a first terminal and a second terminal, a second resistive element including a first terminal and a second terminal, and a select transistor including a gate electrode coupled to a word line, a first current electrode coupled to the first terminal of the first resistive element and the first terminal of the second resistive element, and a second current electrode coupled to a bit line. ... Freescale Semiconductor Inc

01/05/17 / #20170004791

Display system, an integrated circuit for use in the display system, and a method of displaying at least two images on at least two screens

A display system and a method of displaying a separate image on each one of at least two n-bit screens simultaneously, are hereby presented. The display system comprises at least two data processing units arranged for controlling the display of pixels on the corresponding n-bit screen, and a single merger block arranged for receiving pixel data from each respective data processing unit and for transmitting said pixel data to the corresponding n-bit screen. ... Freescale Semiconductor Inc

01/05/17 / #20170004063

Flash memory controller, data processing system with flash memory controller and method of operating a flash memory controller

The present application relates to a flash memory controller and a method of operating thereof. A system bus interface is provided to interface with a system bus and a debug bus interface is provided to interface with a debug bus. ... Freescale Semiconductor Inc

01/05/17 / #20170003732

Electronic device with demonstration mode

An electronic device includes a plurality of modules coupled to a charge storage node. A method for operating the electronic device includes starting up the electronic device and entering a demonstration mode. ... Freescale Semiconductor Inc

01/05/17 / #20170003315

Mems sensor devices having a self-test mode

A micro-electro-mechanical system (mems) device comprises a micro-electro-mechanical system (mems) sensor; a detector circuit; a controller circuit coupled with the mems sensor; a first connection arranged between a first output of the mems sensor and a first input of the detector circuit; a second connection arranged between a second output of the mems sensor and a second input of the detector circuit; and a first switch arranged in the first connection. The controller circuit is configured to open the first switch during a first test mode so as to connect only a single input of the detector circuit with an output of the mems sensor. ... Freescale Semiconductor Inc








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