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Freescale Semiconductor Inc patents (2018 archive)


Recent patent applications related to Freescale Semiconductor Inc. Freescale Semiconductor Inc is listed as an Agent/Assignee. Note: Freescale Semiconductor Inc may have other listings under different names/spellings. We're not affiliated with Freescale Semiconductor Inc, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "F" | Freescale Semiconductor Inc-related inventors


Inertial sensor with motion limit structure

An inertial sensor includes a substrate, a movable mass, and a motion limit structure. The motion limit structure includes a rigid element interposed between first and second spring beams. ... Freescale Semiconductor Inc

Amplifier architecture reconfiguration

An amplifier includes first, second, and third inputs to receive an rf signal, first and second amplifiers, and an input phase adjustment circuit coupling the first, second, and third inputs to the first and second amplifiers, the input phase adjustment circuit having first and second outputs coupled to the first and second amplifiers, respectively. The input phase adjustment circuit includes a pair of inputs, where the pair of inputs includes the first and second inputs, for the first output and a pair of phase adjustment paths coupling the pair of inputs to the first output, respectively. ... Freescale Semiconductor Inc

Through substrate via (tsv) and method therefor

A through substrate via (tsv) and method of forming the same are provided. The method of making the tsv may include etching a via opening into the backside of semiconductor substrate, the via opening exposing a surface of a metal landing structure. ... Freescale Semiconductor Inc

Systems and methods for testing package assemblies

A method for stress testing a device under test (dut) having a plurality of pins includes generating a stress test pattern which independently stresses each pin of the plurality of pins, wherein the stress test pattern includes a plurality of test vector, and applying each test vector to the plurality of pins for a predetermined amount of time. The method further includes, after applying all the test vectors of the stress test pattern, applying a programmable load to each pin independently and after applying each programmable load, comparing an output voltage of each pin to a predetermined voltage range to form an output vector for each pin.. ... Freescale Semiconductor Inc

Microelectromechanical systems device test system and method

A system includes a rotary platform adapted to undergo oscillatory motion about a fixed point, a test fixture coupled to the rotary platform, the test fixture being adapted to receive a device-under-test, and an inertial sensor mounted to the rotary platform for providing a motion output signal indicative of the oscillatory motion. A controller is in communication with the rotary platform and inertial sensor. ... Freescale Semiconductor Inc

Feedback directed program stack optimization

A processing device includes an instruction memory to store executable applications that are executable by a target processor, and a compiler. The compiler includes a builder module and a call graph generator. ... Freescale Semiconductor Inc

Method for link adaptation and power amplifier voltage control and system therefor

A method includes determining a quality indicator designating a quality of packet reception at a wireless local area network transceiver. A modulation and coding scheme (mcs) index value is selected based on the quality indicator. ... Freescale Semiconductor Inc

Operation amplifiers with offset cancellation

A semiconductor device includes an operational transconductance amplifier (ota) with a matched pair of transistors including a first transistor and a second transistor, and configuration units that include a first set of switches, a second set of switches, and an input transistor. Gain adjustment circuitry is coupled to adjust gain of the ota. ... Freescale Semiconductor Inc

Distributed reservation based coherency protocol

A method of operating a cache-coherent computing system includes storing first state information corresponding to a first reservation for a first exclusive access to a first memory address requested by a first thread executing on a first processor of a first plurality of processors. The method includes transmitting an output atomic response transaction indicating a status of the first reservation to a coherency interconnection in response to issuance of the first exclusive access to the coherency interconnection. ... Freescale Semiconductor Inc

Calibrating inertial navigation data using tire pressure monitoring system signals

A system includes a tire pressure monitoring system (tpms) module coupled with a wheel on a vehicle and a vehicle navigation system of the vehicle. A method entails determining a movement signal at the tpms module and receiving the movement signal at the vehicle navigation system. ... Freescale Semiconductor Inc

Integrated circuit with protection from transient electrical stress events and method therefor

An integrated circuit for protecting against transient electrical stress events includes a rail clamp device, and a trigger circuit including a resistive-capacitive (rc) filter, a drive circuit including a first inverter stage receiving an input signal from the rc filter, the drive circuit is configured to enable the rail clamp device during a transient electrical stress event, and a stress event detection circuit coupled to the rc filter. The drive circuit includes a configurable activation voltage which is controlled by the stress event detection circuit, wherein the activation voltage is reduced when the transient electrical stress event is detected.. ... Freescale Semiconductor Inc

Integrated circuit with protection from transient electrical stress events and method therefor

An integrated circuit with protection against transient electrical stress events includes a trigger circuit having a first detection circuit coupled to a first supply voltage, a second detection circuit coupled to a second supply voltage, and a rail clamp device. During a first type of electrical stress event, the rail clamp device is activated in response to a first output signal provided by the first detection circuit. ... Freescale Semiconductor Inc

Air cavity packages and methods for the production thereof

Air cavity packages and methods for producing air cavity packages containing sintered bonded components, multipart window frames, and/or other unique structural features are disclosed. In one embodiment, a method for fabricating an air cavity package includes the step or process of forming a first metal particle-containing precursor layer between a base flange and a window frame positioned over the base flange. ... Freescale Semiconductor Inc

System and method for adjusting boot interface frequency

A system-on-chip includes a processing core and a memory controller connected between the core and an external memory. A clock divider receives an internal clock signal and outputs a divided clock signal. ... Freescale Semiconductor Inc

03/22/18 / #20180081412

Configuration of default voltage level for dual-voltage input/output pad cell via voltage rail ramp up timing

An integrated circuit (ic) package of an electronic device includes a first input coupled to a first voltage rail and a second input coupled to a second voltage rail. The ic package further includes a set of one or more input/output (io) pad cells and a power sequence detector coupled to the first and second voltage rails. ... Freescale Semiconductor Inc

03/15/18 / #20180075258

Systems and methods for dynamically assigning domain identifiers for access control

A master domain assignment controller includes a first plurality of registers corresponding to a first processor including a first register corresponding to a first set of process identifiers (pids) and a second register corresponding to a second set of pids, and comparison circuitry. The comparison circuitry is coupled to receive an input pid from the first processor and is configured to determine if the input pid is one of the first set or the second set of pids. ... Freescale Semiconductor Inc

03/15/18 / #20180074532

Reference voltage generator

A reference voltage generator includes first through sixth transistors and an operational amplifier. The first and second transistors provide first and second voltages to the operational amplifier, respectively. ... Freescale Semiconductor Inc

03/15/18 / #20180074122

Circuit and method for testing flip flop state retention

An integrated circuit includes a plurality of state retention power gating (srpg) flip-flops coupled in a first chain, wherein the first chain has a first scan input and a first scan output; a pseudo random pattern generator (prpg) configured to generate test patterns in response to seeds; a multiplexer (mux) coupled between the prpg and the first scan input and coupled to receive a select signal; and response compression logic coupled to the first scan output and configured to generate a test signature in response to an output pattern provided at the first scan output. The mux is configured to, when the select signal has a first value, couple a first output of the prpg to the first scan input, and, when the select signal has a second value, couple an inversion of the first output of the prpg to the first scan input.. ... Freescale Semiconductor Inc

03/08/18 / #20180068980

Multiple interconnections between die

Embodiments of a semiconductor packaged device and method of making thereof are provided, the device including a substrate; a first flip chip die mounted to a first major surface of the substrate; a second flip chip die mounted to the first major surface of the substrate, the second flip chip die laterally adjacent to the first flip chip die on the first major surface; and a wire bond formed between a first bond pad on the first flip chip die and a second bond pad on the second flip chip die.. . ... Freescale Semiconductor Inc

03/01/18 / #20180062241

Power amplifier system with integrated antenna

A system with an integrated antenna includes a housing having a first surface and a second surface. The second surface of the housing defines a recess. ... Freescale Semiconductor Inc

03/01/18 / #20180061780

Active tamper detection circuit with bypass detection and method therefor

An active tamper detection circuit with bypass detection is provided. A bypass detection circuit is coupled to an active mesh loop. ... Freescale Semiconductor Inc

03/01/18 / #20180060164

Integrated circuits and methods for dynamic allocation of one-time programmable memory

An integrated circuit includes a one-time programmable (otp) memory having a plurality of pages and address translation circuitry. A first line of each page is configured to store error policy bits. ... Freescale Semiconductor Inc

03/01/18 / #20180059756

Multiprocessing system with peripheral power consumption control

An integrated circuit device includes a peripheral control circuit configured to receive a low power intent signal from a first processor, and a first control register in the peripheral control circuit. The first control register includes a peripheral enable indicator for each processor that can use a first peripheral. ... Freescale Semiconductor Inc

03/01/18 / #20180059290

Aluminum nitride protection of silver apparatus, system and method

A semiconductor apparatus including a wafer base with a top side and a bottom side, a silver base with a top side and a bottom side, wherein the bottom side of the silver base is attached to the top side of the wafer base and wherein the silver base provides a reflective surface, and an aluminum nitride protective layer attached to the top side of the silver base, wherein the aluminum nitride protective layer shields the silver base from the environment.. . ... Freescale Semiconductor Inc

03/01/18 / #20180059177

Scan circuitry with iddq verification

An integrated circuitry includes a first logic block coupled between a first power supply terminal and a second power supply terminal. The first logic block includes a first scan chain and a configurable defect coupled to a scan output node of the first scan chain. ... Freescale Semiconductor Inc

03/01/18 / #20180059052

Methods and sensor devices for sensing fluid properties

An ion sensor for sensing ions in a fluid includes a metal-oxide semiconductor (mos) varactor formed in and on a semiconductor substrate having a gate dielectric over the semiconductor substrate, a gate over the gate dielectric, a well region in the substrate under the gate dielectric, and source/drain regions in the well region, wherein the well region and the source/drain regions are of a same conductivity type; and a sense electrode coupled to the mos varactor, wherein the capacitance of the gate dielectric of the varactor changes when the sense electrode interacts with ions in the fluid. Alternatively, resistance of the well region changes when the sense electrode interacts with ions in the fluid, affecting a change in a quality factor of an inductor.. ... Freescale Semiconductor Inc

03/01/18 / #20180058970

System, test chamber, and method for response time measurement of a pressure sensor

A test chamber is used within a system for testing microelectromechanical systems (mems) pressure sensors. The system includes a processor, two air tanks pressurized to different air pressures, a high speed switch mechanism, and the test chamber. ... Freescale Semiconductor Inc

02/22/18 / #20180053753

Stackable molded packages and methods of manufacture thereof

A stackable package assembly and method of manufacturing is provided. The method includes attaching a plurality of interconnect balls to a first surface of a substrate, and encapsulating the first surface of the substrate and the plurality of interconnect balls with an encapsulant. ... Freescale Semiconductor Inc

02/22/18 / #20180053698

System and method for characterizing critical parameters resulting from a semiconductor device fabrication process

A system includes three related structures. A first structure includes a first finger interposed between a first pair of sidewalls. ... Freescale Semiconductor Inc

02/22/18 / #20180052615

Soft error detection in a memory system

An integrated circuit (ic) device including a first memory device, a second memory device stacked with the first memory device, and one or more memory controllers configured to detect a first error in data stored in the first memory device at a first physical location in the ic device, and upon detecting the first error, determine whether there is a second error in data stored in the second memory device in a second physical location in the ic device near the first physical location.. . ... Freescale Semiconductor Inc

02/22/18 / #20180052185

Methods and systems for electrically calibrating transducers

Devices, systems and methods are provided for calibrating a transducer. One exemplary method involves determining a transfer function for the transducer based on a measured response of the transducer to an applied electrical signal, determining a set of values for a plurality of response parameters associated with the transducer based on the transfer function, determining a calibration coefficient value associated with the transducer based at least in part on the set of values and a correlation between physical sensitivity and the plurality of response parameters, and storing the calibration coefficient value in association with the transducer.. ... Freescale Semiconductor Inc

02/15/18 / #20180048320

Switching power converter

Aspects of various embodiments of the present disclosure are directed to applications utilizing voltage regulation. In certain embodiments, an oscillator circuit is configured to generate an oscillating signal having a frequency specified by a frequency control signal. ... Freescale Semiconductor Inc

02/15/18 / #20180046392

Method for performing data transaction and memory device therefor

A system for performing a data transaction between a memory and a master via a bus based on a strobe signal. The memory includes at least one memory bank having first and second cuts. ... Freescale Semiconductor Inc

02/08/18 / #20180039589

Communication system for transmitting and receiving control frames

A communication system for communicating control data between a processor and an interface includes configuration registers, a packet processor, an interrupt processor, a timing monitor, a configuration sampler, a control-frame processor, a mode selector, and a transceiver. The processor, timing monitor, and configuration sampler generate control data, a timing signal and frame structure data, respectively. ... Freescale Semiconductor Inc

02/08/18 / #20180039552

Distributed baseboard management controller for multiple devices on server boards

A server board includes first and second devices. A first service processor of the first device operates as a master baseboard management controller of the server board, and monitors a communication channel for alive messages from a plurality service processors. ... Freescale Semiconductor Inc

02/01/18 / #20180033716

Sintered multilayer heat sinks for microelectronic packages and methods for the production thereof

Methods for producing multilayer heat sinks utilizing low temperature sintering processes are provided. In one embodiment, the method includes forming a metal particle-containing precursor layer over a first principal surface of a first metal layer. ... Freescale Semiconductor Inc

02/01/18 / #20180033472

Adaptable sense circuitry and method for read-only memory

Apparatus and methods for operating a read-only memory (rom) are disclosed. The method for operating the rom includes sensing a dummy bit line with a dummy sense amplifier coupled to the dummy bit line to generate a keeper adjust signal. ... Freescale Semiconductor Inc

01/25/18 / #20180024951

Heterogeneous multi-processor device and method of enabling coherent data access within a heterogeneous multi-processor device

A heterogeneous multi-processor device having a first processor component arranged to issue a data access command request, a second processor component arranged to execute a set of threads, a task scheduling component arranged to schedule the execution of threads by the second processor component, and an internal memory component. In response to the data access command request being issued by the first processor component, the task scheduling component is arranged to wait for activities relating to the indicated subset of threads to finish, and when the activities relating to the indicated subset of threads have finished to load a command thread for execution by the second processor component, the command thread being arranged to cause the second processor component to read the indicated data from the at least one region of memory and make the read data available to the first processor component.. ... Freescale Semiconductor Inc

01/18/18 / #20180020468

Scheduler for layer mapped code words

An enode-b includes push mapping hardware for improved performance. A scheduler schedules first and second code words of first and second respective user devices. ... Freescale Semiconductor Inc

01/18/18 / #20180019735

Systems and methods for non-volatile flip flops

A non-volatile flip flop integrated circuit includes a master latch circuit, a slave latch circuit coupled to the master latch circuit, and a non-volatile memory array coupled to the slave latch circuit. The non-volatile memory array includes a first pair of memory cells coupled to the slave latch circuit, and a second pair of memory cells coupled to the slave latch circuit in parallel with the first pair of memory cells. ... Freescale Semiconductor Inc

01/18/18 / #20180019020

Sample-and-hold circuit

A sample-and-hold circuit, which includes a hold capacitor at its output terminal and at least one intermediate capacitor, intermittently receives an input voltage, and a first value of a switch enable signal causes the sample-and-hold circuit to sample the input voltage and to charge the at least one intermediate capacitor and the hold capacitor to the input voltage, and when it is not receiving the input voltage, a second value of the switch enable signal causes the sample-and-hold circuit to hold, at its output terminal, the input voltage until the hold capacitor discharges, which starts to discharge only after the at least one intermediate capacitor has substantially discharged.. . ... Freescale Semiconductor Inc

01/18/18 / #20180018131

Memory controller for performing write transaction

A memory controller receives first and second write transactions from a processor and stores write data in a memory. The memory controller includes an address comparison circuit, a buffer, a level control circuit, a command generator, and a control circuit. ... Freescale Semiconductor Inc

01/18/18 / #20180018125

Breach detection in integrated circuits

An apparatus embodiment includes an integrated circuit (ic) and breach-detection circuitry. The ic includes data storage circuitry, a power grid configured to distribute power to the data storage circuitry, and a plurality of nodes distributed over at least one sensitive region of the ic. ... Freescale Semiconductor Inc

01/11/18 / #20180011736

Hardware controlled instruction pre-fetching

A task control circuit maintains, in response to task event information, a task information queue that includes task information for a plurality of tasks. Based upon the task information in the task information queue, a future task switch condition is identified as corresponding to a task switch time for a particular task of the plurality of tasks. ... Freescale Semiconductor Inc

01/11/18 / #20180011735

Instruction pre-fetching

Pre-fetching instructions for tasks of an operating system (os) is provided by calling a task scheduler that determines a load start time for a set of instructions for a particular task corresponding to a task switch condition. The os calls, and in response to the load start time, a loader entity module that generates a pre-fetch request that loads the set of instructions for the particular task from a non-volatile memory circuit into a random access memory circuit. ... Freescale Semiconductor Inc

01/11/18 / #20180010913

Vibration and shock robust gyroscope

A mems device includes a movable mass having a central region overlying a sense electrode and an opening in which a suspension structure and spring system are located. The suspension structure includes an anchor coupled to a substrate and rigid links extending from opposing sides of the anchor. ... Freescale Semiconductor Inc

01/04/18 / #20180007746

Solid state microwave heating apparatus with dielectric resonator antenna array, and methods of operation and manufacture

An embodiment of a microwave heating apparatus includes a solid state microwave energy source, a chamber, a dielectric resonator antenna with an exciter dielectric resonator and a feed structure, and one or more additional dielectric resonators each positioned within a distance of the exciter resonator to form a dielectric resonator antenna array. The distance is selected so that each additional resonator is closely capacitively coupled with the exciter resonator. ... Freescale Semiconductor Inc

01/04/18 / #20180007745

Solid state microwave heating apparatus with stacked dielectric resonator antenna array, and methods of operation and manufacture

An embodiment of a microwave heating apparatus includes a solid state microwave energy source, a first dielectric resonator antenna that includes a first exciter dielectric resonator and a first feed structure in proximity to the first exciter dielectric resonator, one or more additional dielectric resonators stacked above the top surface of the first exciter dielectric resonator to form a vertically-stacked dielectric resonator antenna array. The first feed structure is electrically coupled to the microwave energy source to receive a first excitation signal, and the first exciter dielectric resonator is configured to produce a first electric field in response to the excitation signal provided to the first feed structure.. ... Freescale Semiconductor Inc

01/04/18 / #20180005957

Shielded package with integrated antenna

A semiconductor structure includes a packaged semiconductor device having at least one device, a conductive pillar, an encapsulant over the at least one device and surrounding the conductive pillar, wherein the conductive pillar extends from a first major surface to a second major surface of the encapsulant, and is exposed at the second major surface and the at least one device is exposed at the first major surface. The packaged device also includes a conductive shield layer on the second major surface of the encapsulant and on minor surfaces of the encapsulant and an isolation region at the second major surface of the encapsulant between the encapsulant and the conductive pillar such that the conductive shield layer is electrically isolated from the conductive pillar. ... Freescale Semiconductor Inc

01/04/18 / #20180005925

Packaged semiconductor device having a lead frame and inner and outer leads and method for forming

A method of making a packaged integrated circuit device includes forming a lead frame with leads that have an inner portion and an outer portion, the inner portion of the lead is between a periphery of a die pad and extends to one end of openings around the die pad. The outer portion of the leads are separated along their length almost up to an opposite end of the openings. ... Freescale Semiconductor Inc

01/04/18 / #20180004692

Direct memory access (dma) unit with address alignment

Systems and methods for operating a dma unit with address alignment are disclosed. These may include configuring a bandwidth control setting for a read job that includes a data transfer size corresponding to a first number of bytes. ... Freescale Semiconductor Inc








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