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Fujitsu Semiconductor Limited patents


Recent patent applications related to Fujitsu Semiconductor Limited. Fujitsu Semiconductor Limited is listed as an Agent/Assignee. Note: Fujitsu Semiconductor Limited may have other listings under different names/spellings. We're not affiliated with Fujitsu Semiconductor Limited, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "F" | Fujitsu Semiconductor Limited-related inventors


Tipless transistors, short-tip transistors, and methods and circuits therefor

An integrated circuit can include a plurality of first transistors formed in a substrate and having gate lengths of less than one micron and at least one tipless transistor formed in the substrate and having a source-drain path coupled between a circuit node and a first power supply voltage. In addition or alternatively, an integrated circuit can include minimum feature size transistors; a signal driving circuit comprising a first transistor of a first conductivity type having a source-drain path coupled between a first power supply node and an output node, and a second transistor of a second conductivity type having a source-drain path coupled between a second power supply node and the output node, and a gate coupled to a gate of the first transistor, wherein the first or second transistor is a tipless transistor.. ... Fujitsu Semiconductor Limited

Semiconductor device and semiconductor device fabrication method

A multilayer wiring in a semiconductor device includes a first lower wiring formed in a first insulating layer, a via which is formed in a second insulating layer over the first insulating layer and which is connected to the first lower wiring, and an upper wiring connected to the via. The upper wiring has an outer edge at which a nick portion is formed beside a portion of the upper wiring to which the via is connected. ... Fujitsu Semiconductor Limited

Semiconductor device and method of manufacturing the same

A method of manufacturing a semiconductor device includes: forming an insulating film above a semiconductor substrate; forming a conductive film on the insulating film; forming a dielectric film on the conductive film; forming a plurality of upper electrodes at intervals on the dielectric film; forming a first protective insulating film on the upper electrodes and the dielectric film by a sputtering method; forming a second protective insulating film on the first protective insulating film by an atomic layer deposition method, thereby filling gaps of a grain boundary of the dielectric film with the second protective insulating film; and patterning the conductive film after the second protective insulating film is formed to provide a lower electrode.. . ... Fujitsu Semiconductor Limited

Semiconductor device manufacturing method

A method of manufacturing a semiconductor device includes the following processes. A metal film forming process in which a metal film including cobalt is formed on a surface of silicon. ... Fujitsu Semiconductor Limited

Semiconductor device including ferroelectric capacitor and method of manufacturing the same

A semiconductor device includes: a semiconductor substrate; a ferroelectric capacitor above the semiconductor substrate; a first guard ring around the ferroelectric capacitor above the semiconductor substrate. The ferroelectric capacitor includes a bottom electrode, a capacitor insulating film and a top electrode. ... Fujitsu Semiconductor Limited

Digital circuits having improved transistors, and methods therefor

Digital circuits are disclosed that may include multiple transistors having controllable current paths coupled between first and second logic nodes. One or more of the transistors may have a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region. ... Fujitsu Semiconductor Limited

Regulator circuit and semiconductor integrated circuit device

A regulator circuit includes a first transistor reducing an external supply voltage and outputting an internal active voltage to an output node; a first detector receiving a criteria level, detecting the internal active voltage based on an enable signal, controlling a gate voltage of the first transistor, and adjusting an output current thereof; a second transistor reducing the external supply voltage, and outputting an internal standby voltage corresponding to the internal active voltage to the output node; a second detector receiving a reference voltage, detecting the internal standby voltage regardless of the enable signal, controlling a gate voltage of the second transistor, and adjusting an output current thereof; a first switch controlling whether to output the reference voltage as the criteria level of the first detector; and a second switch controlling whether to output the voltage of the output node as the criteria level of the first detector.. . ... Fujitsu Semiconductor Limited

Semiconductor device and method of manufacturing the semiconductor device

A semiconductor device includes a transistor configuration including first and second gate electrodes, each of the first and second gate electrodes having at least a bottom layer and an upper layer including polycrystalline silicon grains, wherein the first gate electrode is a nmos gate electrode formed in an nmos region of the transistor configuration, wherein the polycrystalline silicon grains included in the bottom layer of the first gate electrode have a greater particle diameter than the polycrystalline grains included in the upper layer of the second gate electrode.. . ... Fujitsu Semiconductor Limited

Buried channel deeply depleted channel transistor

Semiconductor devices and methods of fabricating such devices are provided. The devices include source and drain regions on one conductivity type separated by a channel length and a gate structure. ... Fujitsu Semiconductor Limited

Semiconductor device

There is provided a semiconductor device including a memory region and a logic region. The memory region includes a transistor (memory transistor) that stores information by accumulating charge in a sidewall insulating film. ... Fujitsu Semiconductor Limited

Semiconductor integrated circuit and design method thereof

A semiconductor integrated circuit includes a bus signal line and a test signal line arranged adjacent to the bus signal line. The semiconductor integrated circuit has a system mode, which is an operation mode that uses the bus signal line, and a scan mode, which is an operation mode that uses the test signal line. ... Fujitsu Semiconductor Limited

Semiconductor device and manufacturing method for same

A semiconductor device and a manufacturing method for the same are provided in such a manner that the oxygen barrier film and the conductive plug in the base of a capacitor are prevented from being abnormally oxidized. A capacitor is formed by layering a lower electrode, a dielectric film including a ferroelectric substance or a high dielectric substance, and an upper electrode in this order on top of an interlayer insulation film with at least a conductive oxygen barrier film in between, and at least a portion of a side of the conductive oxygen barrier film is covered with an oxygen entering portion or an insulating oxygen barrier film.. ... Fujitsu Semiconductor Limited

Semiconductor device and manufacturing method of semiconductor device

A manufacturing method of a semiconductor device according to a disclosed embodiment includes: implanting a first impurity into a first region of a semiconductor substrate, forming a semiconductor layer on the semiconductor substrate, forming a trench in the semiconductor layer and the semiconductor substrate, forming an isolation insulating film in the trench, implanting a second impurity into a second region of the semiconductor layer, forming a first gate insulating film and a first gate electrode in the first region, forming a second gate insulating film and a second gate electrode in the second region, forming a first source region and a first drain region at both sides of the first gate electrode, and forming a second source region and a second drain region at both sides of the second gate electrode.. . ... Fujitsu Semiconductor Limited

Semiconductor intergrated curcuit apparatus and manufacturing method for same

A semiconductor integrated circuit apparatus and a manufacturing method for the same are provided in such a manner that a leak current caused by a ballast resistor is reduced, and at the same time, the inconsistency in the leak current is reduced. The peak impurity concentration of the ballast resistors is made smaller than the peak impurity concentration in the extension regions, and the depth of the ballast resistors is made greater than the depth of the extension regions.. ... Fujitsu Semiconductor Limited

08/24/17 / #20170243934

Semiconductor device and semiconductor device fabrication method

A semiconductor device includes as a resistance element a first polycrystalline silicon and a second polycrystalline silicon containing impurities, such as boron, of the same kind and having different widths. The first polycrystalline silicon contains the impurities at a concentration cx. ... Fujitsu Semiconductor Limited

08/03/17 / #20170221777

Method of manufacturing semiconductor device and method of forming mask

A first mask with a first pattern is formed above a substrate, a first portion is formed in or above the substrate using the first mask, a second mask with a second pattern is formed above the substrate, a first positional deviation between the first portion and the second pattern is measured, a second portion is formed in or above the substrate using the second mask, a third mask with a third pattern is formed above the substrate, and a third portion is formed in or above the substrate using the third mask. In the forming the third mask, the third pattern is formed in a material film for the third mask with alignment in consideration of the first positional deviation.. ... Fujitsu Semiconductor Limited

07/27/17 / #20170214404

Digital circuits having improved transistors, and methods therefor

Digital circuits are disclosed that may include multiple transistors having controllable current paths coupled between first and second logic nodes. One or more of the transistors may have a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region. ... Fujitsu Semiconductor Limited

06/29/17 / #20170186704

Method for manufacturing a semiconductor device having moisture-resistant rings being formed in a peripheral region

A semiconductor device includes a first moisture-resistant ring disposed in a peripheral region surrounding a circuit region on a semiconductor substrate in such a way as to surround the circuit region and a second moisture-resistant ring disposed in the peripheral region in such a way as to surround the first moisture-resistant ring.. . ... Fujitsu Semiconductor Limited

06/29/17 / #20170186649

Method of manufacturing semiconductor device

A semiconductor device manufacturing method includes forming a silicon layer by epitaxial growth over a semiconductor substrate having a first area and a second area; forming a first gate oxide film by oxidizing the silicon layer; removing the first gate oxide film from the second area, while maintaining the first gate oxide film in the first area; thereafter, increasing a thickness of the first gate oxide film in the first area and simultaneously forming a second gate oxide film by oxidizing the silicon layer in the second area; and forming a first gate electrode and a second gate electrode over the first gate oxide film and the second gate oxide film, respectively, wherein after the formation of the first and second gate electrodes, the silicon layer in the first area is thicker than the silicon layer in the second area.. . ... Fujitsu Semiconductor Limited

06/22/17 / #20170177370

Compressing detected current and preceding instructions with the same operation code and operand patterns

A processor accesses memory storing a compressed instruction sequence that includes compression information indicating that an instruction that with respect to the preceding instruction, has identical operation code and operand continuity is compressed. The processor includes a fetcher that fetches a bit string from the memory and determines whether the bit string is a non-compressed instruction, where if so, transfers the given bit string and if not, transfers the compression information; and a decoder that upon receiving the non-compressed instruction, holds in a buffer, instruction code and an operand pattern of the non-compressed instruction and executes processing to set to an initial value, the value of an instruction counter that indicates a count of consecutive instructions having identical operation code and operand continuity, and upon receiving the compression information, restores the instruction code based on the instruction code held in the buffer, the instruction counter value, and the operand pattern.. ... Fujitsu Semiconductor Limited

05/18/17 / #20170141209

Semiconductor structure with multiple transistors having various threshold voltages

A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. ... Fujitsu Semiconductor Limited

04/27/17 / #20170117366

Electronic devices and systems, and methods for making and using the same

Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk cmos process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a deeply depleted channel (ddc) design, allowing cmos based devices to have a reduced σvt compared to conventional bulk cmos and can allow the threshold voltage vt of fets having dopants in the channel region to be set much more precisely. ... Fujitsu Semiconductor Limited

04/27/17 / #20170117273

Tipless transistors, short-tip transistors, and methods and circuits therefor

An integrated circuit can include a plurality of first transistors formed in a substrate and having gate lengths of less than one micron and at least one tipless transistor formed in the substrate and having a source-drain path coupled between a circuit node and a first power supply voltage. In addition or alternatively, an integrated circuit can include minimum feature size transistors; a signal driving circuit comprising a first transistor of a first conductivity type having a source-drain path coupled between a first power supply node and an output node, and a second transistor of a second conductivity type having a source-drain path coupled between a second power supply node and the output node, and a gate coupled to a gate of the first transistor, wherein the first or second transistor is a tipless transistor.. ... Fujitsu Semiconductor Limited

03/02/17 / #20170062283

Semiconductor device and manufacturing method thereof

There are included: forming element isolation regions in a semiconductor substrate; introducing a first impurity of a first conductivity type, to thereby form a first well and a second well of the first conductivity type; introducing a second impurity of a second conductivity type, to thereby form a third well of the second conductivity type and introducing the second impurity into a region between the first well and the second well, to thereby form a separation well of the second conductivity type; and further introducing a third impurity of the second conductivity type into the region between the first well and the second well.. . ... Fujitsu Semiconductor Limited

02/16/17 / #20170047246

Semiconductor device having insulating layers containing oxygen and a barrier layer containing manganese

A semiconductor device includes an insulating layer formed over a semiconductor substrate, the insulating layer including oxygen, a first wire formed in the insulating layer, and a second wire formed in the insulating layer over the first wire and containing manganese, oxygen, and copper, the second wire having a projection portion formed in the insulating layer and extending downwardly but spaced apart from the first wire.. . ... Fujitsu Semiconductor Limited

02/16/17 / #20170047100

Integrated circuit device body boas circuits and methods

A system having an integrated circuit (ic) device can include a die formed on a semiconductor substrate and having a plurality of first wells formed therein, the first wells being doped to at least a first conductivity type; a global network configured to supply a first global body bias voltage to the first wells; and a first bias circuit corresponding to each first well and configured to generate a first local body bias for its well having a smaller setting voltage than the first global body bias voltage; wherein at least one of the first wells is coupled to a transistor having a strong body coefficient formed therein, which transistor may be a transistor having a highly doped region formed below a substantially undoped channel, the highly doped region having a dopant concentration greater than that the corresponding well.. . ... Fujitsu Semiconductor Limited

02/09/17 / #20170040419

Advanced transistors with punch through suppression

An advanced transistor with punch through suppression includes a gate with length lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×1018 dopant atoms per cm3. ... Fujitsu Semiconductor Limited

02/09/17 / #20170040225

Reducing or eliminating pre-amorphization in transistor manufacture

A method for fabricating field effect transistors using carbon doped silicon layers to substantially reduce the diffusion of a doped screen layer formed below a substantially undoped channel layer includes forming an in-situ epitaxial carbon doped silicon substrate that is doped to form the screen layer in the carbon doped silicon substrate and forming the substantially undoped silicon layer above the carbon doped silicon substrate. The method may include implanting carbon below the screen layer and forming a thin layer of in-situ epitaxial carbon doped silicon above the screen layer. ... Fujitsu Semiconductor Limited

02/09/17 / #20170040064

Semiconductor storage device and data read method

A semiconductor storage device including plural bit lines, plural select gate lines that intersect with the plural bit lines, and plural memory cells that each include a p-channel memory transistor. The semiconductor storage device includes plural p-channel charging transistors that are respectively connected to the plural bit lines, and a charging line that is connected to each of the plurality of charging transistors. ... Fujitsu Semiconductor Limited

02/02/17 / #20170033005

Semiconductor device having groove-shaped via-hole

The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. ... Fujitsu Semiconductor Limited

01/26/17 / #20170025501

Method for fabricating a transistor device with a tuned dopant profile

A transistor device with a tuned dopant profile is fabricated by implanting one or more dopant migrating mitigating material such as carbon. The process conditions for the carbon implant are selected to achieve a desired peak location and height of the dopant profile for each dopant implant, such as boron. ... Fujitsu Semiconductor Limited

01/26/17 / #20170025457

Buried channel deeply depleted channel transistor

Semiconductor devices and methods of fabricating such devices are provided. The devices include source and drain regions on one conductivity type separated by a channel length and a gate structure. ... Fujitsu Semiconductor Limited

01/12/17 / #20170012044

Low power semiconductor transistor structure and method of fabrication thereof

A structure and method of fabrication thereof relate to a deeply depleted channel (ddc) design, allowing cmos based devices to have a reduced σvt compared to conventional bulk cmos and can allow the threshold voltage vt of fets having dopants in the channel region to be set much more precisely. The ddc design also can have a strong body effect compared to conventional bulk cmos transistors, which can allow for significant dynamic control of power consumption in ddc transistors. ... Fujitsu Semiconductor Limited








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