Fujitsu Semiconductor Limited patents

Tipless transistors, short-tip transistors, and methods and circuits therefor

An integrated circuit can include a plurality of first transistors formed in a substrate and having gate lengths of less than one micron and at least one tipless transistor formed in the substrate and having a source-drain path coupled between a circuit node and a first power supply voltage. In addition or alternatively, an integrated circuit can include minimum feature size transistors; a signal driving circuit comprising a first transistor of a first conductivity type having a source-drain path coupled between a first power supply node and an output node, and a second transistor of a second conductivity type having a source-drain path coupled between a second power supply node and the output node, and a gate coupled to a gate of the first transistor, wherein the first or second transistor is a tipless transistor.. ... Fujitsu Semiconductor Limited

Semiconductor device and semiconductor device fabrication method

A multilayer wiring in a semiconductor device includes a first lower wiring formed in a first insulating layer, a via which is formed in a second insulating layer over the first insulating layer and which is connected to the first lower wiring, and an upper wiring connected to the via. The upper wiring has an outer edge at which a nick portion is formed beside a portion of the upper wiring to which the via is connected. ... Fujitsu Semiconductor Limited

Semiconductor device and method of manufacturing the same

A method of manufacturing a semiconductor device includes: forming an insulating film above a semiconductor substrate; forming a conductive film on the insulating film; forming a dielectric film on the conductive film; forming a plurality of upper electrodes at intervals on the dielectric film; forming a first protective insulating film on the upper electrodes and the dielectric film by a sputtering method; forming a second protective insulating film on the first protective insulating film by an atomic layer deposition method, thereby filling gaps of a grain boundary of the dielectric film with the second protective insulating film; and patterning the conductive film after the second protective insulating film is formed to provide a lower electrode.. . ... Fujitsu Semiconductor Limited

Semiconductor device manufacturing method

A method of manufacturing a semiconductor device includes the following processes. A metal film forming process in which a metal film including cobalt is formed on a surface of silicon. ... Fujitsu Semiconductor Limited

Semiconductor device including ferroelectric capacitor and method of manufacturing the same

A semiconductor device includes: a semiconductor substrate; a ferroelectric capacitor above the semiconductor substrate; a first guard ring around the ferroelectric capacitor above the semiconductor substrate. The ferroelectric capacitor includes a bottom electrode, a capacitor insulating film and a top electrode. ... Fujitsu Semiconductor Limited

Digital circuits having improved transistors, and methods therefor

Digital circuits are disclosed that may include multiple transistors having controllable current paths coupled between first and second logic nodes. One or more of the transistors may have a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region. ... Fujitsu Semiconductor Limited

Regulator circuit and semiconductor integrated circuit device

A regulator circuit includes a first transistor reducing an external supply voltage and outputting an internal active voltage to an output node; a first detector receiving a criteria level, detecting the internal active voltage based on an enable signal, controlling a gate voltage of the first transistor, and adjusting an output current thereof; a second transistor reducing the external supply voltage, and outputting an internal standby voltage corresponding to the internal active voltage to the output node; a second detector receiving a reference voltage, detecting the internal standby voltage regardless of the enable signal, controlling a gate voltage of the second transistor, and adjusting an output current thereof; a first switch controlling whether to output the reference voltage as the criteria level of the first detector; and a second switch controlling whether to output the voltage of the output node as the criteria level of the first detector.. . ... Fujitsu Semiconductor Limited

Semiconductor device and method of manufacturing the semiconductor device

A semiconductor device includes a transistor configuration including first and second gate electrodes, each of the first and second gate electrodes having at least a bottom layer and an upper layer including polycrystalline silicon grains, wherein the first gate electrode is a nmos gate electrode formed in an nmos region of the transistor configuration, wherein the polycrystalline silicon grains included in the bottom layer of the first gate electrode have a greater particle diameter than the polycrystalline grains included in the upper layer of the second gate electrode.. . ... Fujitsu Semiconductor Limited

Buried channel deeply depleted channel transistor

Semiconductor devices and methods of fabricating such devices are provided. The devices include source and drain regions on one conductivity type separated by a channel length and a gate structure. ... Fujitsu Semiconductor Limited

Semiconductor device

There is provided a semiconductor device including a memory region and a logic region. The memory region includes a transistor (memory transistor) that stores information by accumulating charge in a sidewall insulating film. ... Fujitsu Semiconductor Limited

Semiconductor integrated circuit and design method thereof

A semiconductor integrated circuit includes a bus signal line and a test signal line arranged adjacent to the bus signal line. The semiconductor integrated circuit has a system mode, which is an operation mode that uses the bus signal line, and a scan mode, which is an operation mode that uses the test signal line. ... Fujitsu Semiconductor Limited

Semiconductor device and manufacturing method for same

A semiconductor device and a manufacturing method for the same are provided in such a manner that the oxygen barrier film and the conductive plug in the base of a capacitor are prevented from being abnormally oxidized. A capacitor is formed by layering a lower electrode, a dielectric film including a ferroelectric substance or a high dielectric substance, and an upper electrode in this order on top of an interlayer insulation film with at least a conductive oxygen barrier film in between, and at least a portion of a side of the conductive oxygen barrier film is covered with an oxygen entering portion or an insulating oxygen barrier film.. ... Fujitsu Semiconductor Limited

Semiconductor device and manufacturing method of semiconductor device

A manufacturing method of a semiconductor device according to a disclosed embodiment includes: implanting a first impurity into a first region of a semiconductor substrate, forming a semiconductor layer on the semiconductor substrate, forming a trench in the semiconductor layer and the semiconductor substrate, forming an isolation insulating film in the trench, implanting a second impurity into a second region of the semiconductor layer, forming a first gate insulating film and a first gate electrode in the first region, forming a second gate insulating film and a second gate electrode in the second region, forming a first source region and a first drain region at both sides of the first gate electrode, and forming a second source region and a second drain region at both sides of the second gate electrode.. . ... Fujitsu Semiconductor Limited

Semiconductor intergrated curcuit apparatus and manufacturing method for same

A semiconductor integrated circuit apparatus and a manufacturing method for the same are provided in such a manner that a leak current caused by a ballast resistor is reduced, and at the same time, the inconsistency in the leak current is reduced. The peak impurity concentration of the ballast resistors is made smaller than the peak impurity concentration in the extension regions, and the depth of the ballast resistors is made greater than the depth of the extension regions.. ... Fujitsu Semiconductor Limited