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Fujitsu Semiconductor Limited patents (2015 archive)


Recent patent applications related to Fujitsu Semiconductor Limited. Fujitsu Semiconductor Limited is listed as an Agent/Assignee. Note: Fujitsu Semiconductor Limited may have other listings under different names/spellings. We're not affiliated with Fujitsu Semiconductor Limited, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "F" | Fujitsu Semiconductor Limited-related inventors


12/31/15 / #20150378776

Scheduling in a multicore architecture

This invention relates to scheduling threads in a multicore processor. Executable transactions may be scheduled using at least one distribution queue, which lists executable transactions in order of eligibility for execution, and multilevel scheduler which comprises a plurality of linked individual executable transaction schedulers. ... Fujitsu Semiconductor Limited

12/17/15 / #20150364484

Method of manufacturing semiconductor device

A semiconductor device manufacturing method includes forming a silicon layer by epitaxial growth over a semiconductor substrate having a first area and a second area; forming a first gate oxide film by oxidizing the silicon layer; removing the first gate oxide film from the second area, while maintaining the first gate oxide film in the first area; thereafter, increasing a thickness of the first gate oxide film in the first area and simultaneously forming a second gate oxide film by oxidizing the silicon layer in the second area; and forming a first gate electrode and a second gate electrode over the first gate oxide film and the second gate oxide film, respectively, wherein after the formation of the first and second gate electrodes, the silicon layer in the first area is thicker than the silicon layer in the second area.. . ... Fujitsu Semiconductor Limited

12/10/15 / #20150357330

Semiconductor device and manufacturing method of semiconductor device

A manufacturing method of a semiconductor device according to a disclosed embodiment includes: implanting a first impurity into a first region of a semiconductor substrate, forming a semiconductor layer on the semiconductor substrate, forming a trench in the semiconductor layer and the semiconductor substrate, forming an isolation insulating film in the trench, implanting a second impurity into a second region of the semiconductor layer, forming a first gate insulating film and a first gate electrode in the first region, forming a second gate insulating film and a second gate electrode in the second region, forming a first source region and a first drain region at both sides of the first gate electrode, and forming a second source region and a second drain region at both sides of the second gate electrode.. . ... Fujitsu Semiconductor Limited

11/26/15 / #20150340466

Method for manufacturing semiconductor device and device

A method for manufacturing a semiconductor device includes: forming a temporary gate electrode and a first dummy gate electrode located on a first side of the temporary gate electrode, on a semiconductor region with a first lattice constant; forming a first semiconductor layer with a second lattice constant different from the first lattice constant, between the temporary gate electrode and the first dummy gate electrode; removing the temporary gate electrode while leaving the first dummy gate electrode intact; and forming a gate electrode in a region from which the temporary gate electrode is removed.. . ... Fujitsu Semiconductor Limited

11/26/15 / #20150340460

Advanced transistors with threshold voltage set dopant structures

An advanced transistor with threshold voltage set dopant structure includes a gate with length lg and a well doped to have a first concentration of a dopant. A screening region is positioned between the well and the gate and has a second concentration of dopant greater than 5×1018 dopant atoms per cm3. ... Fujitsu Semiconductor Limited

11/19/15 / #20150333738

Integrated circuit process and bias monitors and related methods

An integrated circuit device can include at least one oscillator stage having a current mirror circuit comprising first and second mirror transistors of a first conductivity type, and configured to mirror current on two mirror paths, at least one reference transistor of a second conductivity type having a source-drain path coupled to a first of the mirror paths, and a switching circuit coupled to a second of the mirror paths and configured to generate a transition in a stage output signal in response to a stage input signal received from another oscillator stage, wherein the channel lengths of the first and second mirror transistors are larger than that of the at least one reference transistor.. . ... Fujitsu Semiconductor Limited

11/19/15 / #20150333144

High uniformity screen and epitaxial layers for cmos devices

A transistor and method of fabrication thereof includes a screening layer formed at least in part in the semiconductor substrate beneath a channel layer and a gate stack, the gate stack including spacer structures on either side of the gate stack. The transistor includes a shallow lightly doped drain region in the channel layer and a deeply lightly doped drain region at the depth relative to the bottom of the screening layer for reducing junction leakage current. ... Fujitsu Semiconductor Limited

11/05/15 / #20150318026

Integrated circuit device body bias circuits and methods

A system having an integrated circuit (ic) device can include a die formed on a semiconductor substrate and having a plurality of first wells formed therein, the first wells being doped to at least a first conductivity type; a global network configured to supply a first global body bias voltage to the first wells; and a first bias circuit corresponding to each first well and configured to generate a first local body bias for its well having a smaller setting voltage than the first global body bias voltage; wherein at least one of the first wells is coupled to a transistor having a strong body coefficient formed therein, which transistor may be a transistor having a highly doped region formed below a substantially undoped channel, the highly doped region having a dopant concentration greater than that the corresponding well.. . ... Fujitsu Semiconductor Limited

10/29/15 / #20150311164

Semiconductor device and method of producing semiconductor device

A semiconductor device provided on a semiconductor substrate includes an element region including an element, a moisture-resistant frame surrounding the element region, an insulating layer provided between the moisture-resistant frame and an outer peripheral edge of the semiconductor device and on the semiconductor substrate, a first metal line extending along the outer peripheral edge and provided in the insulating layer, and a groove provided in the insulating layer.. . ... Fujitsu Semiconductor Limited

10/22/15 / #20150303905

Slew based process and bias monitors and related methods

An integrated circuit can include at least one slew generator circuit comprising at least one body biasable reference transistor, the slew generator circuit configured to generate at least a first signal having a slew rate that varies according to characteristics of the reference transistor; a pulse generator circuit configured to generate a pulse signal having a first pulse with a duration corresponding to the slew rate of the first signal; and a counter configured to generate a count value corresponding to a duration of the first pulse.. . ... Fujitsu Semiconductor Limited

10/22/15 / #20150303743

Power switching circuit, semiconductor integrated circuit, radio apparatus, radio system, and power switching method

A power switching circuit includes a current mirror circuit to generate mirror currents, by transferring, at different mirror ratios, monitored currents that are obtained by monitoring power supply voltages, a selector to select the mirror currents with a combination having the different mirror ratios for the monitored currents, according to a switching state of the power supply voltages, a comparator to compare the mirror currents selected by the selector and output a comparison result, and a switching circuit to switch a supply voltage to be supplied to a load to one of the power supply voltages, based on the comparison result.. . ... Fujitsu Semiconductor Limited

10/01/15 / #20150280666

Differential amplification circuit and semiconductor integrated circuit

A differential amplification circuit includes: a first transistor and a second transistor of a differential pair; first and second loads; current sources; and a resistor circuit, wherein the resistor circuit includes: a coarse adjustment part and a fine adjustment part, one of the coarse adjustment part and the fine adjustment part includes a first lateral adjustment part and a second lateral adjustment part which have the same configuration, the first lateral adjustment part and the second lateral adjustment part are connected symmetrically to both sides of a central adjustment part, and the central adjustment part has a circuit configuration symmetrical with respect to two connection nodes with the first lateral adjustment part and the second lateral adjustment part.. . ... Fujitsu Semiconductor Limited

10/01/15 / #20150279449

Semiconductor device and semiconductor storage device

A semiconductor device includes a circuit block that is switchable between selection and non-selection, and a leakage current control circuit disposed between the circuit block and a first power supply line. The leakage current control circuit includes a first transistor disposed between the circuit block and the first power supply line, and a resistor device disposed between the circuit block and the first power supply line.. ... Fujitsu Semiconductor Limited

10/01/15 / #20150278415

Design method and design apparatus

When a design apparatus adjusts clock skews, the design apparatus separates each of the power supply currents which flow through circuit sections that operate in synchronization with a clock signal into a plurality of frequency components, sets skew values of the clock signal which reaches the circuit sections, and performs, by changing the skew values, repetition of calculating a combined amplitude by combining, with respect to each of the frequency components, corresponding ones of the frequency components of the power supply currents which flow through the circuit sections and finds dependence of the combined amplitude on a skew.. . ... Fujitsu Semiconductor Limited

10/01/15 / #20150276497

Temperature measurement device, integrated circuit, and temperature measurement method

In a first sensing state in which a first current flows in a forward direction with respect to a pn junction of a first semiconductor element and a second current of a different magnitude from the first current flows in a forward direction with respect to a pn junction of a second semiconductor element, a difference between a forward direction voltage of the pn junction of the first semiconductor element and a forward direction voltage of the pn junction of the second semiconductor element is converted into a digital value by a computer and acquired as a first digital value. In a second sensing state in which the second current flows in the forward direction in the pn junction of the first semiconductor element and the first current flows in the forward direction in the pn junction of the second semiconductor element, a difference between the forward direction voltage of the pn junction of the first semiconductor element and the forward direction voltage of the pn junction of the second semiconductor element is converted into a digital value by the computer and acquired as a second digital value. ... Fujitsu Semiconductor Limited

09/24/15 / #20150271422

Defective pixel correcting apparatus, imaging apparatus, and method of correcting defective pixel

An apparatus for correcting a defective pixel includes a unit configured to obtain a first corrected value based on a maximum value or minimum value of values of surrounding pixels around a defective pixel, a unit configured to identify a direction in which a change in pixel values is the smallest based on the values of the surrounding pixels, and configured to obtain a second corrected value responsive to values of pixels situated in the identified direction among the surrounding pixels, and a selection unit configured to select the first corrected value when a difference between a value of the defective pixel and a representative value of the surrounding pixels is smaller than a first threshold value, configured to select the second corrected value when the difference is larger than or equal to a second threshold value that is larger than or equal to the first threshold value.. . ... Fujitsu Semiconductor Limited

09/10/15 / #20150256190

Analog-to-digital conversion circuit

An analog-to-digital conversion circuit includes capacitors coupled to a common line. Each capacitor has a capacitance less than or equal to a capacitance sum of lower order capacitors. ... Fujitsu Semiconductor Limited

09/10/15 / #20150255350

Electronic devices and systems, and methods for making and using same

Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk cmos process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a deeply depleted channel (ddc) design, allowing cmos based devices to have a reduced sigma vt compared to conventional bulk cmos and can allow the threshold voltage vt of fets having dopants in the channel region to be set much more precisely. ... Fujitsu Semiconductor Limited

09/10/15 / #20150254392

Layout verification method and verification apparatus

A method of verifying a layout of a semiconductor integrated circuit is disclosed. The method includes executing a timing analysis of the semiconductor integrated circuit based on first layout information acquired after execution of a layout process, executing layout correction with respect to the first layout information, comparing the first layout information acquired before the execution of the layout correction and second layout information acquired after the execution of the layout correction to acquire information indicating an rc difference in wires, and adding, by a computer, an effect due to an increase in delay in the wires resulting from the rc difference to timing information obtained by the timing analysis.. ... Fujitsu Semiconductor Limited

08/20/15 / #20150236711

Capacitor array, ad converter and semiconductor device

A capacitor array includes a plural capacitors provided separated at intervals from each other. A first wiring line is connected to the first electrode of each of the plurality of capacitors, and is provided so as to pass through the intervals between the plurality of capacitors. ... Fujitsu Semiconductor Limited

08/20/15 / #20150236678

Semiconductor integrated circuit

There are provided: a first buffer circuit which includes buffers being circuits to be measured connected in series, whose output and input are connected to a first input terminal and a second output terminal of a control circuit, respectively; a second buffer circuit which includes buffers being circuits to be measured connected in series whose number is the same as a number of the buffers included in the first buffer circuit, whose output and input are connected to a second input terminal and a first output terminal of the control circuit, respectively; and the control circuit which makes the entire circuit is a negative logic when a first operation is set, and simultaneously outputs signals with different logics from the output terminals at a time of a start of an oscillation operation and makes the entire circuit is a positive logic when a second operation is set.. . ... Fujitsu Semiconductor Limited

08/20/15 / #20150235901

Semiconductor device and manufacturing method of semiconductor device

A semiconductor device has a semiconductor substrate having a first surface and a second surface, a through electrode penetrating through the semiconductor substrate and having a protrusion protruding from the second surface, and an insulation layer on the second surface, which covers the side surface of the protrusion, has an opening through which to expose the end surface of the protrusion, and has a thickness greater than the length of the protrusion.. . ... Fujitsu Semiconductor Limited

08/20/15 / #20150235690

Semiconductor memory device and control method thereof

When a voltage monitoring circuit detects that a supplied voltage is in a state of being less than a certain voltage at a time of performing writing of data with respect to a memory cell of a memory core having a refresh function, a flag is set in a register circuit, an address at which the writing is performed is held, and the memory core is made to execute rewriting by a refresh operation with respect to the held address, in accordance with the flag set in the register circuit, thereby enabling an increase in speed of operation while securing a retention life of memory data, and enabling a reduction in power consumption without lowering a processing capability even if the supplied voltage is lowered.. . ... Fujitsu Semiconductor Limited

08/20/15 / #20150235689

Semiconductor memory device and control method thereof

A semiconductor memory device includes: a memory cell array including a memory cell, which includes a ferroelectric capacitor and an access transistor which is a first conductive type transistor formed in a second conductive type well and includes a source or a drain connected to one electrode of the ferroelectric capacitor; and a control circuit which controls a potential applied to the second conductive type well. The control circuit applies a fixed potential to another electrode of the ferroelectric capacitor and applies a second potential being a forward voltage with respect to a junction between the first conductive type source and drain and the second conductive type well when erasing data in the memory cell, and applies a third potential not being the forward voltage with respect to the junction between the first conductive type source and drain and the second conductive type well in a normal operation.. ... Fujitsu Semiconductor Limited

08/13/15 / #20150227475

Arbitration circuit and processing method of arbitration circuit

In an arbitration circuit, transactions output from a plurality of master circuits are stored in a first-in-first-out type first buffer, and when a high-priority transaction higher in priority than one of the stored transactions is output from one of the plural master circuits, a cancel request of a low-priority transaction lower in priority than the high-priority transaction, out of the stored transactions, is output to a second buffer in a slave circuit, and when the cancel request is successful, the high-priority transaction is output to the slave circuit, and after the high-priority transaction is output to the slave circuit, the low-priority transaction whose cancel request is successful is output to the slave circuit.. . ... Fujitsu Semiconductor Limited

08/06/15 / #20150221659

Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device includes: forming a conductive film over a semiconductor substrate; forming a first ferroelectric film over the conductive film; forming an amorphous second ferroelectric film over the first ferroelectric film; forming a transition metal oxide material film containing ruthenium over the second ferroelectric film; forming a first conductive metal oxide film over the transition metal oxide material film without exposing the transition metal oxide material film to the air; annealing and crystallizing the second ferroelectric film; and patterning the first conductive metal oxide film, the first ferroelectric film, the second ferroelectric film, and the conductive film to form a ferroelectric capacitor.. . ... Fujitsu Semiconductor Limited

08/06/15 / #20150221658

Semiconductor device and manufacturing method for same

A semiconductor device and a manufacturing method for the same are provided in such a manner that the oxygen barrier film and the conductive plug in the base of a capacitor are prevented from being abnormally oxidized. A capacitor is formed by layering a lower electrode, a dielectric film including a ferroelectric substance or a high dielectric substance, and an upper electrode in this order on top of an interlayer insulation film with at least a conductive oxygen barrier film in between, and at least a portion of a side of the conductive oxygen barrier film is covered with an oxygen entering portion or an insulating oxygen barrier film.. ... Fujitsu Semiconductor Limited

08/06/15 / #20150221657

Semiconductor device and method of manufacturing the same

An embodiment of a semiconductor device includes a plate line that is connected to ferroelectric capacitors selected from a plurality of ferroelectric capacitors and covers the selected ferroelectric capacitors and regions between the selected ferroelectric capacitors from above top electrodes.. . ... Fujitsu Semiconductor Limited

07/30/15 / #20150214151

Semiconductor device and method of manufacturing semiconductor device

A semiconductor device includes a first insulating film formed above a semiconductor substrate, a fuse formed above the first insulating film, a second insulating film formed above the first insulating film and the fuse and including an opening reaching the fuse, and a third insulating film formed above the second insulating film and in the opening.. . ... Fujitsu Semiconductor Limited

07/23/15 / #20150205908

Verification method and verification apparatus

A verification apparatus detects a first delay circuit connected to an output side of a second isolator in a first netlist including first and second isolators, in which the first isolator is inserted into a first path between first and second power domains under first rule, and the second isolator is inserted into a second path between the first and third power domains under second rule. To verify whether the first and second isolators are inserted under the first and second rules respectively, the verification apparatus searches a second netlist generated by performing an optimization step including delay adjustment on the first netlist for a connection destination of the first power domain, and if the connection destination is not the first delay circuit, continues searching, and detects the second power domain, to thereby specify the first path at the time of the first rule being applied.. ... Fujitsu Semiconductor Limited

07/23/15 / #20150205898

Design method and design apparatus

A design apparatus preferentially selects a low coefficient in a range in which design conditions are met from a group of coefficients (coefficient library) indicative of an increase in delay time at the time of voltage drop for combinations of one of a plurality of clock buffers which differ in parameter and one of a plurality of wiring loads, which differ in parameter, connected to the one of the plurality of clock buffers, selects from the plurality of clock buffers and the plurality of wiring loads a clock buffer and a wiring load each having a parameter associated with the selected coefficient, and designs a clock path.. . ... Fujitsu Semiconductor Limited

07/16/15 / #20150200197

Semiconductor device and method of manufacturing the same

An embodiment of a compound semiconductor device includes: a first lower electrode; a first insulating film over the first lower electrode; a first upper electrode over the first insulating film; a second lower electrode separate from the first lower electrode; a second insulating film over the second lower electrode; a third insulating film over the second insulating film; and a second upper electrode over on the third insulating film. A thickness of the first insulating film is substantially the same as a thickness of the third insulating film, a contour of the third insulating film in planar view is outside a contour of the second insulating film in planar view, and a contour of the second upper electrode in planar view is inside the contour of the second insulating film in planar view.. ... Fujitsu Semiconductor Limited

07/16/15 / #20150200191

Semiconductor intergrated circuit apparatus and manufacturing method for same

A semiconductor integrated circuit apparatus and a manufacturing method for the same are provided in such a manner that a leak current caused by a ballast resistor is reduced, and at the same time, the inconsistency in the leak current is reduced. The peak impurity concentration of the ballast resistors is made smaller than the peak impurity concentration in the extension regions, and the depth of the ballast resistors is made greater than the depth of the extension regions.. ... Fujitsu Semiconductor Limited

07/16/15 / #20150199135

Memory control method, memory control program, and semiconductor integrated circuit device

A memory control method, which is configured to control data writing to a memory, includes securing a temporary write region in the memory; at the time of writing data to the memory, writing to the temporary write region based on a threshold time. The memory control method includes, when writing to a first portion of the temporary write region has not been completed by a time when the threshold time passed, canceling the writing to the first portion, and writing to a second portion that is different from the first portion of the temporary write region.. ... Fujitsu Semiconductor Limited

07/09/15 / #20150195089

Data scramble device, security device, security system, and data scramble method

A data scramble device includes an intermediate key generation unit configured to generate intermediate keys from random numbers, and an extended key generation unit configured to generate an extended key from intermediate keys generated by the intermediate key generation unit. Further, the data scramble device includes a scramble arithmetic operation unit configured to generate scramble data by performing a scramble arithmetic operation of target data and an extended key generated by the extended key generation unit.. ... Fujitsu Semiconductor Limited

07/09/15 / #20150194960

Output circuit

An output circuit includes a driver circuit and a node control circuit. The driver circuit includes a first transistor and a second transistor. ... Fujitsu Semiconductor Limited

07/09/15 / #20150194527

Semiconductor device, method of manufacturing the same, and method of evaluating semiconductor device

A semiconductor device has: a silicon (semiconductor) substrate; a gate insulating film and a gate electrode, which are formed on the silicon substrate in this order; and source/drain material layers formed in recesses (holes) in the silicon substrate, the recesses being located beside the gate electrode. Here, each of side surfaces of the recesses, which are closer to the gate electrode, is constituted of at least one crystal plane of the silicon substrate.. ... Fujitsu Semiconductor Limited

07/02/15 / #20150186679

Secure processor system without need for manufacturer and user to know encryption information of each other

A secure processor system capable of improving the security of processor processing by the addition of minimum modules without the need for a manufacturer and a user to know encryption information of each other has been disclosed. The secure processor system includes a secure processor having a cpu core that executes a instruction code, an encryption key hold part that holds a processor key, and an encryption processing part that encrypts or decrypts data input/output to/from the core with a processor key and a memory, and the encryption key hold part includes a hardware register that holds a hardwired encryption key, a write only register that stores an encryption key for instruction to be input and holds the stored encryption key for instruction so that it cannot be read, and the encryption key hold part outputs a hardware encryption key as a processor key at the time of activation and outputs a command encryption key as a processor key after a encryption key for instruction is written.. ... Fujitsu Semiconductor Limited

06/25/15 / #20150180671

Authentication system, method for authentication, authentication device and device to be authenticated

An authentication system includes a device to be authenticated and an authentication device. The device to be authenticated includes a first communication unit configured to transmit an instruction code and a first comparison value, and to receive a random number, a first memory unit, and a first control unit configured to create the first comparison value based on the random number, the common secret identification information and the instruction code. ... Fujitsu Semiconductor Limited

06/25/15 / #20150178311

Recording medium and method for file access

A method for file access includes accessing, by a processor, a file which is divided and stored in data area including a plurality of access units on the base of an access unit management table, the accessing including using a first table included in the access unit management table, the first table including a first management information corresponding to a first access unit and indicating that the first access unit and a second access unit following the first access unit in chains are located in continuous addresses and a second management information corresponding to the first access unit and indicating that the first access unit and the second access unit are located in discontinuous addresses, and using a second table included in the access unit management table, the second table including access unit identification information of the first and the second access units which are located in the discontinuous addresses.. . ... Fujitsu Semiconductor Limited

06/25/15 / #20150178159

Memory device and control method of memory device

A memory device includes: a memory including a first port and a second port that are accessible; an error check and correct encoding circuit that applies an error check and correct code to data and writes them into the first port of the memory; an error check and correct decoding circuit that receives input of the data and the error check and correct code read from the first port of the memory, and corrects the inputted data in case of an error in the inputted data is detected based on the inputted error check and correct code; and a control circuit that writes the corrected data and the error check and correct code into the second port of the memory in case of the error is detected and a current access address and a previous access address to the first port of the memory are different.. . ... Fujitsu Semiconductor Limited

06/11/15 / #20150160499

Semiconductor device and method for fabricating semiconductor device

A semiconductor device includes a first electrode layer and a second electrode layer disposed over a substrate, a first insulating layer disposed over the first electrode layer, and a reflective electrode layer disposed on the first insulating layer and electrically connected to the first electrode layer, wherein the second electrode layer is exposed externally, and a thickness of the second electrode layer is greater than a thickness of the reflective electrode layer.. . ... Fujitsu Semiconductor Limited

06/11/15 / #20150160274

Method and apparatus for power estimation

A power estimation method includes acquiring power values consumed by a power estimation target apparatus, each of the power values corresponding to a plurality of parameters; calculating magnitude of variation in the power values in relation to a mean thereof; creating, when the magnitude of variation is less than a first value, a first power prediction formula approximating power consumption of the power estimation target apparatus by a constant which is the mean; calculating a degree of influence of each of the parameters on the power consumption when the magnitude of variation is the first value or more; creating, by reducing the number of the parameters based on the degree of influence, a second power prediction formula approximating the power consumption by a linear equation; and estimating the power consumption using one of the first and the second power prediction formulae.. . ... Fujitsu Semiconductor Limited

06/04/15 / #20150155872

Semiconductor device and communication interface circuit

A communication interface circuit includes a register and a register setting circuit. The register holds a data value for controlling characteristics of an electronic circuit element included in the communication interface circuit. ... Fujitsu Semiconductor Limited

06/04/15 / #20150154129

Memory system having a plurality of types of memory chips and a memory controller for controlling the memory chips

A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. ... Fujitsu Semiconductor Limited

05/28/15 / #20150147855

Semiconductor device with high breakdown voltage and manufacture thereof

A semiconductor device includes: first and second n-type wells formed in p-type semiconductor substrate, the second n-type well being deeper than the first n-type well; first and second p-type backgate regions formed in the first and second n-type wells; first and second n-type source regions formed in the first and second p-type backgate regions; first and second n-type drain regions formed in the first and second n-type wells, at positions opposed to the first and second n-type source regions, sandwiching the first and the second p-type backgate regions; and field insulation films formed on the substrate, at positions between the first and second p-type backgate regions and the first and second n-type drain regions; whereby first transistor is formed in the first n-type well, and second transistor is formed in the second n-type well with a higher reverse voltage durability than the first transistor.. . ... Fujitsu Semiconductor Limited

05/21/15 / #20150140802

Semiconductor device and process for producing semiconductor device

A semiconductor device includes: a substrate in which a product region and scribe regions are defined; a 1st insulation film formed above the substrate; a metal film in the 1st insulation film, disposed within the scribe regions in such a manner as to surround the product region; a 2nd insulation film formed on the 1st insulation film and the metal film; a 1st groove disposed more inside than the metal film in such a manner as to surround the product region, and reaching from a top surface of the 2nd insulation film to a position deeper than a top surface of the metal film; and a 2nd groove disposed more outside than the metal film in such a manner as to surround the metal film, and reaching from the top surface of the 2nd insulation film to a position deeper than the top surface of the metal film.. . ... Fujitsu Semiconductor Limited

05/21/15 / #20150137211

Semiconductor device manufacturing method and semiconductor device

A semiconductor device manufacturing method includes: forming an element isolation insulating film in a semiconductor substrate; forming a first film on a surface of the semiconductor substrate; forming a second film on the element isolation insulating film and on the first film; forming a first resist pattern that includes a first open above the element isolation insulating film in a first region; removing the second film on the element isolation insulating film in the first region to separate the second film in the first region into a plurality of parts by performing first etching; forming a third film on the second film in the first region; forming a first gate electrode on the third film in the first region; and forming a first insulating film that includes the first to third films under the first gate electrode by patterning the first to third films.. . ... Fujitsu Semiconductor Limited

05/07/15 / #20150123187

Semiconductor device manufacturing method and semiconductor device

A semiconductor device manufacturing method includes: forming a first well of the first conductivity type in a substrate; forming a second well of the first conductivity type in a first region of the substrate; forming a third well of the second conductivity type underneath the second well in the first region of the substrate in a position overlapping with the first well located underneath the second well in the first region of the substrate; forming a fourth well, that surrounds the second well and has the second conductivity type, in the first region of the substrate; forming a fifth well of the first conductivity type above the first well in the second region of the substrate; and forming a sixth well of the second conductivity type above the first well in the second region of the substrate.. . ... Fujitsu Semiconductor Limited

04/30/15 / #20150120983

Direct memory access controller, control method thereof, and information processing system

Two channels of a main cpu channel and a sub cpu channel each including a reception channel and a transmission channel, and performing a data transfer by a dma in accordance with a descriptor are provided, a channel switching part selects the main cpu channel or the sub cpu channel in accordance with information set at a mode setting register, and performs a switching of channels at a boundary of a packet to be transferred to thereby enable the switching of channels without interrupting a dma operation.. . ... Fujitsu Semiconductor Limited

04/30/15 / #20150118841

Semiconductor device and method for manufacturing the same

A semiconductor device includes: an integrated circuit having an electrode pad; a first insulating layer disposed on the integrated circuit; a redistribution layer including a plurality of wirings and disposed on the first insulating layer, at least one of the plurality of wirings being electrically coupled to the electrode pad; a second insulating layer having a opening on at least a portion of the plurality of wirings; a metal film disposed on the opening and on the second insulating layer, and electrically coupled to at least one of the plurality of wirings; and a solder bump the solder bump overhanging at least one of the plurality of wirings not electrically coupled to the metal film.. . ... Fujitsu Semiconductor Limited

04/30/15 / #20150116140

Analog-to-digital converter circuit and method of controlling analog-to-digital converter circuit

An analog-to-digital converter circuit includes a plurality of conversion stages that are cascaded to be coupled in series. Each of the plurality of conversion stages includes a signal holding circuit configured to hold an input voltage, an analog-to-digital converter configured to convert the input voltage into a digital signal based on a first reference voltage, a digital-to-analog converter configured to generate a first voltage according to the digital signal, the first reference voltage, and the input voltage, an amplifier configured to amplify the first voltage to generate an output voltage, and a reference holding circuit configured to hold a holding voltage that is in proportion to the first reference voltage. ... Fujitsu Semiconductor Limited

04/23/15 / #20150111310

Semiconductor device and method of manufacturing the same

A lower electrode film, a ferroelectric film, and an upper electrode film are formed on an insulation film covering a transistor formed on a semiconductor substrate. Furthermore, a pt film is formed as a cap layer on the upper electrode film. ... Fujitsu Semiconductor Limited

04/23/15 / #20150109875

Semiconductor memory device

A semiconductor memory device includes a memory cell array, a word line decoder, a time determination signal generation circuit, and a timing circuit. The memory cell array is configured to include a plurality of memory cells, and the word line decoder is configured to control selection and a voltage level of a word line connected to each of the memory cells. ... Fujitsu Semiconductor Limited

04/16/15 / #20150106774

High-level synthesis data generation apparatus, high-level synthesis apparatus, and high-level synthesis data generation method

An analysis unit analyzes a source code representing design data of a semiconductor device, and generates information (cdfg information) indicating the data and control flow of the semiconductor device. A high-level synthesis data generation unit acquires intermediate data (an object file), which is obtained by compiling the source code, generates intermediate data (an object file) by incorporating the cdfg information generated by the analysis unit into the acquired intermediate data, and outputs the generated intermediate data as high-level synthesis data.. ... Fujitsu Semiconductor Limited

04/09/15 / #20150098263

Ferroelectric memory device

A ferroelectric memory device includes a memory array including a plurality of ferroelectric memory cells, a code generating circuit configured to multiply write data and a parity generator matrix to generate check bits, thereby producing a hamming code having information bits and the check bits arranged therein, the information bits being the write data, and a driver circuit configured to write the hamming code to the memory array, wherein the parity generator matrix has a plurality of rows, and a number of “1”s in each of the rows is an even number.. . ... Fujitsu Semiconductor Limited

04/09/15 / #20150097619

Amplifier

An amplifier includes two input terminals to receive a differential, two-tone transmission signal; two output terminals; a coil having terminals connected with the input terminals respectively, and a center tap; a first transistor having the gate connected with one terminal of the coil, and the output terminal connected with one output terminal; a second transistor having the gate connected with the other terminal of the coil, end the output terminal connected with the other output terminal; a diode having a terminal connected with the center tap; and a bias circuit connected with the other terminal of the diode to output a gate voltage to turn on the first and second transistors. The diode adjusts the terminal voltage depending on a signal level of a double harmonic wave of the transmission signal supplied to the terminal of the diode from the center tap.. ... Fujitsu Semiconductor Limited

04/02/15 / #20150091633

Design method and design device

A design method is executed by a computer. The design method includes grouping logical modules in each of power domains arranged on a chip; provisionally arranging regular cells in each of logical module groups formed by the grouping; and arranging power switches around each of the logical module groups.. ... Fujitsu Semiconductor Limited

03/26/15 / #20150084160

Semiconductor device and method of manufacturing the same

A ferroelectric capacitor formed above a semiconductor substrate includes a lower electrode, a dielectric film (ferroelectric film) having ferroelectric characteristics, and an upper electrode. The upper electrode includes a conductive oxide film made of a ferroelectric material to which conductivity is provided by adding a conductive material such as ir, and the conductive oxide film is in contact with the dielectric film.. ... Fujitsu Semiconductor Limited

03/19/15 / #20150081987

Data supply circuit, arithmetic processing circuit, and data supply method

An data supply circuit includes a buffer configured to store a plurality of data items each having a first width, a memory access unit configured to read source data stored in memory and to store the source data as one or more data items each having the first width in the buffer, and a selection control unit configured to repeat multiple times an operation of reading a data item having a second width shorter than or equal to the first width to read a plurality of data items each having the second width contiguously and sequentially from the buffer and configured to continue to read from a head end of the source data upon a read portion reaching a tail end of the source data.. . ... Fujitsu Semiconductor Limited

03/19/15 / #20150077278

Sampling

There is disclosed current-mode time-interleaved sampling circuitry configured to be driven by substantially sinusoidal clock signals. Such circuitry may be incorporated in adc circuitry, for example as integrated circuitry on an ic chip. ... Fujitsu Semiconductor Limited

03/12/15 / #20150074626

Determining method, computer product, and determining apparatus

A determining method includes obtaining terminal information indicating a first object terminal that is among terminals included among partial circuits and subject to determination of whether the first object terminal is an open terminal; obtaining for each terminal, connection information and first attribute information indicating an attribute of any one among an input terminal and an output terminal; generating, by a computer, for each terminal, second attribute information indicating an attribute opposite to the attribute indicated by the first attribute information; and determining, by the computer, whether a state of the first object terminal indicated by the terminal information becomes a high-impedance state, by simulating on the basis of the connection information and the second attribute information, a state of each terminal when a value of a terminal among the terminals and indicated as an output terminal by the second attribute information, is set at a first specified value.. . ... Fujitsu Semiconductor Limited

03/12/15 / #20150074384

Secure boot method, semiconductor device and recording medium

A secure boot method for a system, the system including a processor and a storage medium configured to store a program, a plurality of first partial hash values calculated based on a plurality of first partial programs into which the program is divided, and a first legitimate hash value which is a hash value calculated based on a plurality of first legitimate partial hash values, the plurality of first legitimate partial hash values being calculated based on a plurality of legitimate partial programs. The secure boot method includes calculating, a second calculated hash value based on the plurality of first partial hash values, and determining, whether or not the second calculated hash value matches the first legitimate hash value to continue the start-up processing of the system when the determination indicates match, and suspend the start-up processing of the system when the determination does not indicate match.. ... Fujitsu Semiconductor Limited

03/12/15 / #20150073745

Angle detection device and angle detection method

An angle detection device includes: first and second rotation measuring instruments; an anomaly detection unit detecting occurrences of anomalies in the first and second rotation measuring instruments; and a switching interpolation unit configured to select a first angle signal and a first angular speed signal and output as a third angle signal and a third angular speed signal when the first rotation measuring instrument is normal, and to perform switching so that a second angle signal and a second angular speed signal are output as the third angle signal and the third angular speed signal while performing interpolation so that the difference between the first angle signal and the second angle signal is reduced stepwise if the second rotation measuring instrument is normal when an anomaly has occurred in the first rotation measuring instrument.. . ... Fujitsu Semiconductor Limited

03/12/15 / #20150071396

Method for determining phase of clock used for reception of parallel data, receiving circuit, and electronic apparatus

For each of a plurality of delayed phases, one of the plurality of delayed phases being the same as a phase of a reference clock and the others of the plurality of delayed phases delayed with respect to the phase of the reference clock, test parallel data transmitted in synchronism with the reference clock is received in synchronism with a delayed clock having the delayed phase and an adjacent delayed clock having a delayed phase adjacent to the delayed phase of the delayed clock, respectively; and a phase range containing a delayed phase with which the test parallel data has been received correctly and for which the result of the comparison indicates a match is determined from among the plurality of delayed phases; and the phase of a receive clock to be used for reception of parallel data is determined from the determined phase range.. . ... Fujitsu Semiconductor Limited

03/12/15 / #20150070242

Phase shifter, predistorter, and phased array antenna

There are provided a transformer including inductors, and variable capacitors. Capacitance values of the variable capacitors are controlled by a control signal. ... Fujitsu Semiconductor Limited

03/12/15 / #20150070203

Mixed-signal circuitry

Mixed-signal circuitry, comprising: an array of adc units configured to operate in a time-interleaved manner, and each operable in each of a series of time windows to convert an analogue input value into a corresponding digital output value, each conversion comprising a sequence of sub-conversion operations, each successive sub-conversion operation of a sequence being triggered by completion of the preceding sub-conversion operation; and a controller, wherein: at least one of the adc units is operable to act as a reporting adc unit and indicate, for each of one or more monitored said conversions, whether or not a particular one of the sub-conversion operations completed during the time window concerned; and the controller is operable to consider at least one such indication and to control the circuitry in dependence upon the or each considered indication.. . ... Fujitsu Semiconductor Limited

03/12/15 / #20150070202

Circuitry and methods for use in mixed-signals circuitry

A switching circuit, comprising: a main switch having a control terminal; and a clock-path portion connected to the control terminal of the main switch to apply a driving clock signal thereto so as to drive the main switch, wherein the circuit is configured to controllably apply a biasing voltage to the clock-path portion so as to bias a voltage level of the driving clock signal as applied to the control terminal of the main switch.. . ... Fujitsu Semiconductor Limited

03/12/15 / #20150070201

Circuitry and methods for use in mixed-signal circuitry

Mixed-signal circuitry, comprising: a first switching-circuitry unit for use in an analogue-to-digital converter; and a second switching-circuitry unit for use in a digital-to-analogue converter, wherein: the first switching-circuitry unit is configured to sample an input analogue signal and output a plurality of samples based on a first plurality of clock signals; the second switching-circuitry unit is configured to generate an output analogue signal based on a plurality of data signals and a second plurality of clock signals; and the first and second pluralities of clock signals have the same specifications as one another.. . ... Fujitsu Semiconductor Limited

03/12/15 / #20150070199

Circuitry and methods for use in mixed-signal circuitry

A method of calibrating switching circuitry, the switching circuitry comprising a measurement node and a plurality of output switches connected to the measurement node, and the circuitry being configured, in each clock cycle of a series of clock cycles, to control whether or not one or more of said output switches carry a given current based upon input data, the method comprising: inputting a plurality of different data sequences to the circuitry, each sequence causing a given pattern of voltages to occur at the measurement node as a result of currents passing through the output switches; measuring the voltages occurring at the measurement node for each said sequence; and calibrating the switching circuitry in dependence upon a result of said measuring.. . ... Fujitsu Semiconductor Limited

03/12/15 / #20150070104

Components and circuits for output termination

A lossy electrical-signal transmission line having first and second ends, the transmission line being configured such that: its characteristic impedance at the first end has a first value; its characteristic impedance at the second end has a second value, lower than the first value; and its series resistance measured from its first end to its second end is within a given range of the difference between said first and second values.. . ... Fujitsu Semiconductor Limited

03/12/15 / #20150070077

Signal distribution circuitry

Signal distribution circuitry for use in an integrated circuit, the signal distribution circuitry comprising: first and second output nodes, for connection to respective output signal lines; first and second supply nodes for connection to respective high and low voltage sources; and switching circuitry connected to the first and second output nodes and the first and second supply nodes and operable based on an input signal to conductively connect the first and second output nodes either to the first and second supply nodes, respectively, in a first state when the input signal has a first value, or to each other, in a second state when the input signal has a second value different from the first value, so as to transmit output signals dependent on the input signal via such output signal lines.. . ... Fujitsu Semiconductor Limited

03/12/15 / #20150070074

Circuitry and methods for use in mixed-signal circuitry

Switching circuitry for use in a digital-to-analogue converter, the circuitry comprising: a common node; first and second output nodes; and a plurality of switches connected between the common node and the first and second output nodes and operable in each clock cycle of a series of clock cycles, based on input data, to conductively connect the common node to either the first or second output node along a given one of a plurality of paths, wherein the circuitry is arranged such that a data-controlled switch and a clock-controlled switch are provided in series along each said path from the common node to the first or second output node.. . ... Fujitsu Semiconductor Limited

03/12/15 / #20150070066

Circuitry useful for clock generation and distribution

An integrated circuit comprising an inductor arrangement, the arrangement comprising: four inductors adjacently located in a group and arranged to define two rows and two columns, wherein: the integrated circuit is configured to cause two of those inductors diagonally opposite from one another in the arrangement to produce an electromagnetic field having a first phase, and to cause the other two of those inductors to produce an electromagnetic field having a second phase, the first and second phases being substantially in antiphase.. . ... Fujitsu Semiconductor Limited

03/12/15 / #20150070065

Signal-alignment circuitry and methods

Signal-alignment circuitry, comprising: phase-rotation circuitry connected to receive one or more input clock signals and operable to generate therefrom one or more output clock signals; and control circuitry operable to control the amount of phase rotation applied by the phase-rotation circuitry to carry out a plurality of alignment operations, the alignment operations comprising: one or more first operations each comprising rotating one or more of said output clock signals relative to one or more of the other said output clock signals, to bring a phase relationship between said output clock signals, or clock signals derived therefrom, towards or into a given phase relationship; and one or more second operations each comprising rotating all of said output clock signals together, to bring a phase relationship between said output or derived clock signals and said input clock signals or an external-reference signal towards or into a given phase relationship.. . ... Fujitsu Semiconductor Limited

03/12/15 / #20150069586

Semiconductor device and method of manufacturing the same

A method of manufacturing a semiconductor device includes: forming a first electrode on a first semiconductor substrate; coating the semiconductor substrate with an insulating material having a first viscosity at a first temperature, having a second viscosity lower than the first viscosity at a second temperature higher than the first temperature, and having a third viscosity higher than the second viscosity at a third temperature higher than the second temperature; and forming a first insulating film by curing the insulating material. In this method, the forming the first insulating film includes: bringing the insulating material to the second viscosity by heating the insulating material under a first condition; and bringing the insulating material to the third viscosity by heating the insulating material under a second condition. ... Fujitsu Semiconductor Limited

03/05/15 / #20150062136

Image processing method and image processing apparatus

An image processing method includes acquiring a drawing instruction for a graphic to be drawn and area information indicating a partitioned area in which at least a part of the graphic is drawn; classifying each partitioned area indicated by the area information such that partitioned areas in which the graphic at least a part of which is drawn is the same, are classified into a same group; correlating and storing to a first storage unit and for each classified group, the area information that indicates the partitioned areas classified into the group and the drawing instruction acquired for the graphic at least partially drawn in the partitioned areas classified into the group; and generating for each indicated partitioned area, image data indicating pixels within the partitioned area, based on the drawing instruction correlated with the area information indicating the partitioned area and stored in the first storage unit.. . ... Fujitsu Semiconductor Limited

03/05/15 / #20150060969

Semiconductor device and method for manufacturing semiconductor device

A semiconductor device includes a transistor formed on a semiconductor substrate, a first insulation film formed above the semiconductor substrate, and first and second capacitors located on the first insulation film. The first capacitor includes a lower electrode, a ferroelectric, and an upper electrode. ... Fujitsu Semiconductor Limited

02/26/15 / #20150054129

Semiconductor device with pads of enhanced moisture blocking ability

A semiconductor device is provided having a pad with an improved moisture blocking ability. The semiconductor device has: a circuit portion including a plurality of semiconductor elements formed on a semiconductor substrate; lamination of insulator covering the circuit portion, including a passivation film as an uppermost layer having openings; ferro-electric capacitors formed in the lamination of insulator; wiring structure formed in the lamination of insulator and connected to the semiconductor elements and the ferro-electric capacitors; pad electrodes connected to the wiring structure, formed in the lamination of insulator and exposed in the openings of the passivation film; a conductive pad protection film, including a pd film, covering each pad electrode via the opening of the passivation film, and extending on the passivation film; and stud bump or bonding wire connected to the pad electrode via the conductive pad protection film.. ... Fujitsu Semiconductor Limited

02/05/15 / #20150039900

Program execution method and decryption apparatus

A method for program execution in a system including a decryption apparatus that prevents external referencing and an information processing apparatus communicating therewith and accessing first and third storage areas, includes: the decryption apparatus detecting a series of commands from a command group obtained by decrypting at least a portion of a program stored in the first storage area; obfuscating and storing the series of commands to a second storage area storing the decrypted portion and within the first storage area; assigning, when an execution request is received from the information processing apparatus, the third storage area having a capacity equivalent to any one series of commands; and storing to the third storage area, a series of certain commands stored in the second area and obtained by canceling obfuscation of the commands that correspond to the execution request; and the information processing unit executing the series of certain commands.. . ... Fujitsu Semiconductor Limited

02/05/15 / #20150036017

Imaging control unit, imaging apparatus, and method for controlling an imaging apparatus

An imaging control unit includes: a calculating unit that obtains block brightness-values of a plurality of blocks from each pixel of an image data of a frame, the image data of a frame being divided into the plurality of blocks; a limiting unit that limits to a first limit brightness-value a block brightness-value which is larger than the first limit brightness-value among the plurality of block brightness-values; and a controlling unit that controls an exposure amount of an imaging unit so that a representing brightness-value of the plurality of the block brightness-values correspond to a target brightness-value which is less than first limit brightness-value.. . ... Fujitsu Semiconductor Limited

02/05/15 / #20150035125

Semiconductor device, semiconductor wafer and manufacturing method of semiconductor device

A semiconductor device includes wiring layers formed over a semiconductor wafer, a via-layer between the wiring layers, conductive films in the wiring layers, and a via-plug in the via-layer connecting the conductive films of the wiring layers above and below, a scribe region at an outer periphery of a chip region along an edge of the semiconductor substrate and including a pad region in the vicinity of the edge, the pad region overlapping the conductive films of the plurality of wiring layers in the plan view, the plurality of wiring layers including first second wiring layers, the conductive film of the first wiring layer includes a first conductive pattern formed over an entire surface of said pad region in a plan view, and the conductive film of the second wiring layer includes a second conductive pattern formed in a part of the pad region in a plan view.. . ... Fujitsu Semiconductor Limited

01/29/15 / #20150028451

Semiconductor device and method of designing the same

A semiconductor device includes: a semiconductor substrate having a memory cell array region and a peripheral circuit region; a ferroelectric capacitor formed over the semiconductor substrate in the memory cell array region; and a dummy capacitor formed over the semiconductor substrate in the peripheral circuit region, with a layered structure same as that of the ferroelectric capacitor, with an area larger than that of the ferroelectric capacitor, and with a line width not larger than the width of the ferroelectric capacitor.. . ... Fujitsu Semiconductor Limited

01/22/15 / #20150021732

Semiconductor device

A semiconductor device includes: a first well provided in a semiconductor substrate; a second well provided in the semiconductor substrate, so as to be isolated from the first well; a schottky barrier diode formed in the first well; and a pn junction diode formed in the second well, with an impurity concentration of the pn junction thereof set higher than an impurity concentration of the schottky junction of the schottky barrier diode, and being connected antiparallel with the schottky barrier diode.. . ... Fujitsu Semiconductor Limited

01/15/15 / #20150014820

Semiconductor device manufacturing method and support substrate-attached wafer

A recessed portion is formed around an outer edge of a device wafer at a peripheral edge portion of a first face of the device wafer. A recessed portion is formed around an outer edge of a support substrate, at a bonding face of the support substrate. ... Fujitsu Semiconductor Limited

01/08/15 / #20150008526

Semiconductor device

A semiconductor device includes: a substrate; a first active region formed in the substrate and that includes a first region that has a first width and a second region including a second width larger than the first width and extended in a first direction; a second active region formed in the substrate and extended in parallel to the second region of the first active region; and an element isolation insulating film formed in the substrate and that partitions the first active region and the second active region, respectively, wherein the second region of the first active region or the second active region includes a depressed part depressed in a second direction that is perpendicular to the first direction in a plan view.. . ... Fujitsu Semiconductor Limited

01/01/15 / #20150001621

Semiconductor device

A semiconductor device including a gate insulating film; a gate electrode; a source region of a first conductivity; a drain region of the first conductivity type; a drift region of the first conductivity type formed between the channel region and the drain region; a first semiconductor region of a second conductivity type that encloses the source region, the drift region and the drain region, and includes the channel region; and a first shield wiring that encloses a portion of the source region in a plan view in conjunction with the gate electrode, the portion being not covered by the gate electrode, and is connected to the first semiconductor region, or that covers the portion and is connected to the first semiconductor region and the source region.. . ... Fujitsu Semiconductor Limited








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