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Fujitsu Semiconductor Limited patents (2016 archive)


Recent patent applications related to Fujitsu Semiconductor Limited. Fujitsu Semiconductor Limited is listed as an Agent/Assignee. Note: Fujitsu Semiconductor Limited may have other listings under different names/spellings. We're not affiliated with Fujitsu Semiconductor Limited, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "F" | Fujitsu Semiconductor Limited-related inventors


Electronic devices and systems, and methods for making and using the same

Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk cmos process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a deeply depleted channel (ddc) design, allowing cmos based devices to have a reduced σvt compared to conventional bulk cmos and can allow the threshold voltage vt of fets having dopants in the channel region to be set much more precisely. ... Fujitsu Semiconductor Limited

Semiconductor device, method of manufacturing the same, and method of evaluating semiconductor device

A semiconductor device has: a silicon (semiconductor) substrate; a gate insulating film and a gate electrode, which are formed on the silicon substrate in this order; and source/drain material layers formed in recesses (holes) in the silicon substrate, the recesses being located beside the gate electrode. Here, each of side surfaces of the recesses, which are closer to the gate electrode, is constituted of at least one crystal plane of the silicon substrate.. ... Fujitsu Semiconductor Limited

Transistor with threshold voltage set notch and method of fabrication thereof

A structure and method of fabrication thereof relate to a deeply depleted channel (ddc) design, allowing cmos based devices to have a reduced σvt compared to conventional bulk cmos and can allow the threshold voltage vt of fets having dopants in the channel region to be set much more precisely. A novel dopant profile indicative of a distinctive notch enables tuning of the vt setting within a precise range. ... Fujitsu Semiconductor Limited

Cmos structures and processes based on selective thinning

Methods for fabricating semiconductor devices and devices therefrom are provided. A method includes providing a substrate having a semiconducting surface with first and second layers, where the semiconducting surface has a plurality of active regions comprising first and second active regions. ... Fujitsu Semiconductor Limited

Rectification circuit, power source circuit, and rfid tag

A rectification circuit has a first terminal to which an alternating-current voltage is input from an antenna, a second terminal to which a direct-current voltage is input from the antenna, a first rectification element, a second rectification element, and a voltage rectification circuit. The first rectification element is connected between the first terminal and the second terminal, causes a current to flow in a first direction from the first terminal to the second terminal, and cuts off a current in a second direction from the second terminal to the first terminal. ... Fujitsu Semiconductor Limited

Semiconductor device

There is provided a semiconductor device including a memory region and a logic region. The memory region includes a transistor (memory transistor) that stores information by accumulating charge in a sidewall insulating film. ... Fujitsu Semiconductor Limited

Tipless transistors, short-tip transistors, and methods and circuits therefor

An integrated circuit can include a plurality of first transistors formed in a substrate and having gate lengths of less than one micron and at least one tipless transistor formed in the substrate and having a source-drain path coupled between a circuit node and a first power supply voltage. In addition or alternatively, an integrated circuit can include minimum feature size transistors; a signal driving circuit comprising a first transistor of a first conductivity type having a source-drain path coupled between a first power supply node and an output node, and a second transistor of a second conductivity type having a source-drain path coupled between a second power supply node and the output node, and a gate coupled to a gate of the first transistor, wherein the first or second transistor is a tipless transistor.. ... Fujitsu Semiconductor Limited

Semiconductor device

A semiconductor device includes first and second transistors connected to the same power supply. Each of the first and second transistors includes, under a channel region of a low concentration provided between a source region and a drain region of a first conductivity type, an impurity region of a second conductivity type having a higher concentration. ... Fujitsu Semiconductor Limited

Semiconductor device and method of manufacturing the same

An embodiment of a semiconductor device includes a plate line that is connected to ferroelectric capacitors selected from a plurality of ferroelectric capacitors and covers the selected ferroelectric capacitors and regions between the selected ferroelectric capacitors from above top electrodes.. . ... Fujitsu Semiconductor Limited

Reducing or eliminating pre-amorphization in transistor manufacture

A method for fabricating field effect transistors using carbon doped silicon layers to substantially reduce the diffusion of a doped screen layer formed below a substantially undoped channel layer includes forming an in-situ epitaxial carbon doped silicon substrate that is doped to form the screen layer in the carbon doped silicon substrate and forming the substantially undoped silicon layer above the carbon doped silicon substrate. The method may include implanting carbon below the screen layer and forming a thin layer of in-situ epitaxial carbon doped silicon above the screen layer. ... Fujitsu Semiconductor Limited

Semiconductor device and semiconductor device fabrication method

A multilayer wiring in a semiconductor device includes a first lower wiring formed in a first insulating layer, a via which is formed in a second insulating layer over the first insulating layer and which is connected to the first lower wiring, and an upper wiring connected to the via. The upper wiring has an outer edge at which a nick portion is formed beside a portion of the upper wiring to which the via is connected. ... Fujitsu Semiconductor Limited

Method of manufacturing semiconductor device

A protection film is formed on a semiconductor substrate. Impurity ions are implanted into the semiconductor substrate through the protection film. ... Fujitsu Semiconductor Limited

Semiconductor device manufacturing method and semiconductor device

A semiconductor device manufacturing method includes: forming an element isolation insulating film in a semiconductor substrate; forming a first film on a surface of the semiconductor substrate; forming a second film on the element isolation insulating film and on the first film; forming a first resist pattern that includes a first open above the element isolation insulating film in a first region; removing the second film on the element isolation insulating film in the first region to separate the second film in the first region into a plurality of parts by performing first etching; forming a third film on the second film in the first region; forming a first gate electrode on the third film in the first region; and forming a first insulating film that includes the first to third films under the first gate electrode by patterning the first to third films.. . ... Fujitsu Semiconductor Limited

Integrated circuit devices and methods

An integrated circuit can include multiple sram cells, each including at least two pull-up transistors, at least two pull-down transistors, and at least two pass-gate transistors, each of the transistors having a gate; at least one of the pull-up transistors, the pull-down transistors, or the pass-gate transistors having a screening region a distance below the gate and separated from the gate by a semiconductor layer, the screening region having a concentration of screening region dopants, the concentration of screening region dopants being higher than a concentration of dopants in the semiconductor layer, the screening region providing an enhanced body coefficient for the pull-down transistors and the pass-gate transistors to increase the read static noise margin for the sram cell when a bias voltage is applied to the screening region; and a bias voltage network operable to apply one or more bias voltages to the multiple sram cells.. . ... Fujitsu Semiconductor Limited

07/28/16 / #20160218103

Semiconductor integrated circuit device and method of manufacturing thereof

It is therefore an object of the present invention to provide a method in which, in a semiconductor integrated circuit device, a plurality of transistors having wide-rangingly different ioff levels are embedded together in a semiconductor device including transistors each using a non-doped channel. By controlling an effective channel length, a leakage current is controlled without changing an impurity concentration distribution in a transistor including a non-doped channel layer and a screen layer provided immediately under the non-doped channel layer.. ... Fujitsu Semiconductor Limited

07/28/16 / #20160218069

Semiconductor device, semiconductor wafer and manufacturing method of semiconductor device

A semiconductor device includes wiring layers formed over a semiconductor wafer, a via-layer between the wiring layers, conductive films in the wiring layers, and a via-plug in the via-layer connecting the conductive films of the wiring layers above and below, a scribe region at an outer periphery of a chip region along an edge of the semiconductor substrate and including a pad region in the vicinity of the edge, the pad region overlapping the conductive films of the plurality of wiring layers in the plan view, the plurality of wiring layers including first second wiring layers, the conductive film of the first wiring layer includes a first conductive pattern formed over an entire surface of said pad region in a plan view, and the conductive film of the second wiring layer includes a second conductive pattern formed in a part of the pad region in a plan view.. . ... Fujitsu Semiconductor Limited

07/21/16 / #20160211346

Epitaxial channel transistors and die with diffusion doped channels

Semiconductor structures can be fabricated by implanting a screen layer into a substrate, with the screen layer formed at least in part from a low diffusion dopant species. An epitaxial channel of silicon or silicon germanium is formed above the screen layer, and the same or different dopant species is diffused from the screen layer into the epitaxial channel layer to form a slightly depleted channel (sdc) transistor. ... Fujitsu Semiconductor Limited

07/21/16 / #20160211269

Semiconductor device and method of manufacturing the same

A method of manufacturing a semiconductor device includes: forming an insulating film above a semiconductor substrate; forming a conductive film on the insulating film; forming a dielectric film on the conductive film; forming a plurality of upper electrodes at intervals on the dielectric film; forming a first protective insulating film on the upper electrodes and the dielectric film by a sputtering method; forming a second protective insulating film on the first protective insulating film by an atomic layer deposition method, thereby filling gaps of a grain boundary of the dielectric film with the second protective insulating film; and patterning the conductive film after the second protective insulating film is formed to provide a lower electrode.. . ... Fujitsu Semiconductor Limited

06/16/16 / #20160172444

Method for fabricating a transistor device with a tuned dopant profile

A transistor device with a tuned dopant profile is fabricated by implanting one or more dopant migrating mitigating material such as carbon. The process conditions for the carbon implant are selected to achieve a desired peak location and height of the dopant profile for each dopant implant, such as boron. ... Fujitsu Semiconductor Limited

06/09/16 / #20160163823

Semiconductor structure with multiple transistors having various threshold voltages

A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. ... Fujitsu Semiconductor Limited

06/02/16 / #20160154920

Design method and design apparatus

A processor arranges a first dummy pattern in each of a plurality of circuit blocks of a first layer included in hierarchical design data of a semiconductor device; sets an arrangement candidate region as a candidate for arranging a second dummy pattern in a region, which is located between a circuit block boundary and the first dummy pattern and in which the first dummy pattern is not arranged, in each of the plurality of circuit blocks; arranges the plurality of circuit blocks in an upper-layer region of a second layer higher than the first layer; and arranges the second dummy pattern in a portion formed by joining a first arrangement candidate region of a first circuit block and a second arrangement candidate region of a second circuit block, which contact each other, among the arrangement candidate regions of the plurality of circuit blocks arranged in the upper-layer region.. . ... Fujitsu Semiconductor Limited

05/26/16 / #20160148932

Semiconductor device and method of manufacturing the same

A semiconductor device including an insulating film in a first region of a semiconductor substrate; a first impurity region and a second impurity region of a first conductivity type, each of the regions including a part located deeper than the insulating film in contact with each other, and the insulating film being sandwiched by the first and second impurity regions in planar view in the first region of the semiconductor substrate; a metal silicide film on the first impurity region and in schottky junction with the first impurity region; a first impurity of the first impurity region having a peak of a concentration profile deeper than a bottom of the insulating film; a second impurity of the second impurity region having a concentration higher than a concentration of the first impurity in a part of the first impurity region shallower than the bottom of the insulating film.. . ... Fujitsu Semiconductor Limited

05/19/16 / #20160141292

Cmos gate stack structures and processes

A semiconductor device includes a substrate having a semiconducting surface having formed therein a first active region and a second active region, where the first active region consists of a substantially undoped layer at the surface and a highly doped screening layer of a first conductivity type beneath the first substantially undoped layer, and the second active region consists of a second substantially undoped layer at the surface and a second highly doped screening layer of a second conductivity type beneath the second substantially undoped layer. The semiconductor device also includes a gate stack formed in each of the first active region and the second active region consists of at least one gate dielectric layer and a layer of a metal, where the metal has a workfunction that is substantially midgap with respect to the semiconducting surface.. ... Fujitsu Semiconductor Limited

05/12/16 / #20160133527

Semiconductor device and manufacturing method thereof

A first well in a first conductivity type which is formed at a first region and is electrically connected to a first power supply line, a second well in a second conductivity type being an opposite conductivity type of the first conductivity type which is formed at a second region and is electrically connected to a second power supply line, a third well in the second conductivity type which is integrally formed with the second well at a third region adjacent to the second region, a fourth well in the first conductivity type integrally formed with the first well at a fourth region adjacent to the first region, a fifth well in the first conductivity type which is formed at the third region to be shallower than the third well, and a sixth well in the second conductivity type which is formed at the fourth region to be shallower than the fourth well, are included.. . ... Fujitsu Semiconductor Limited

03/31/16 / #20160093627

Semiconductor device and method of manufacturing the same

A semiconductor device includes: a semiconductor substrate; a ferroelectric capacitor above the semiconductor substrate; a first guard ring around the ferroelectric capacitor above the semiconductor substrate. The ferroelectric capacitor includes a bottom electrode, a capacitor insulating film and a top electrode. ... Fujitsu Semiconductor Limited

03/17/16 / #20160079234

Semiconductor device

A semiconductor device includes: a first well provided in a semiconductor substrate; a second well provided in the semiconductor substrate, so as to be isolated from the first well; a schottky barrier diode formed in the first well; and a pn junction diode formed in the second well, with an impurity concentration of the pn junction thereof set higher than an impurity concentration of the schottky junction of the schottky barrier diode, and being connected antiparallel with the schottky barrier diode.. . ... Fujitsu Semiconductor Limited

02/25/16 / #20160056780

Operational amplifier input offset correction with transistor threshold voltage adjustment

A device can include an operational amplifier (op amp) circuit having a differential transistor pair, a first transistor of the differential transistor pair being formed in a first well of a substrate and a second transistor of the differential transistor pair being formed in a second well of the substrate; a body bias generator configured to generate at least a first body bias voltage for the first well, and not the second well, that varies in response to a first body bias control value; and a control circuit configured to selectively generate the first body bias control value in response to an input offset voltage of the op amp.. . ... Fujitsu Semiconductor Limited

02/25/16 / #20160055406

Semiconductor device

In a semiconductor device that generates a power supply voltage from an rf carrier signal received by an antenna through the use of a rectification circuit, rectification circuits, each including a plurality of capacitors and a plurality of diodes, are connected in multistage. The rectification circuits includes limiter circuits that are turned on at a voltage larger than an on-voltage of the diodes, clamp cathodes of the diodes at a first voltage. ... Fujitsu Semiconductor Limited

02/11/16 / #20160043165

Semiconductor device and method of manufacturing the same

A semiconductor device includes: a semiconductor substrate; a base above the semiconductor substrate; a first conductive plug in the base; a memory cell region in the base; and a logic circuit region connected to the memory cell region, the logic circuit including a first capacitor. The first capacitor includes: a first bottom electrode, a part of a lower surface of the first bottom electrode being in contact with the first conductive plug; a first insulating film on the first bottom electrode; and a first top electrode on the first insulating film. ... Fujitsu Semiconductor Limited

01/28/16 / #20160026207

Power up body bias circuits and methods

An integrated circuit device can include at least a first body bias circuit configured to generate a first body bias voltage different from power supply voltages of the ic device; at least a first bias control circuit configured to set a first body bias node to a first power supply voltage, and subsequently enabling the first body bias node to be set to the first body bias voltage; and a plurality of first transistors having bodies connected to the first body bias node.. . ... Fujitsu Semiconductor Limited

01/21/16 / #20160020768

Digital circuits having improved transistors, and methods therefor

Digital circuits are disclosed that may include multiple transistors having controllable current paths coupled between first and second logic nodes. One or more of the transistors may have a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region. ... Fujitsu Semiconductor Limited

01/21/16 / #20160020293

Semiconductor device

A method for manufacturing a semiconductor device includes, forming, on a substrate, an element isolation insulating film which includes a protruding portion protruding above a level of a surface of the substrate, forming a first film on the substrate and on the element isolation insulating film, polishing the first film to expose the protruding portion, forming a first resist pattern which straddles the first film and the protruding portion after polishing the first film, patterning the first film using the first resist pattern as a mask to form a first pattern, and forming a sidewall film at side surfaces of the first pattern.. . ... Fujitsu Semiconductor Limited








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