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Globalfoundries Inc patents


Recent patent applications related to Globalfoundries Inc. Globalfoundries Inc is listed as an Agent/Assignee. Note: Globalfoundries Inc may have other listings under different names/spellings. We're not affiliated with Globalfoundries Inc, we're just tracking patents.

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Peaking amplifier frequency tuning

A circuit including: input and output nodes and first and second feedback nodes; a first input amplifier having an input connected to the input node and an output connected to the first feedback node; a second input amplifier having an input connected to the input node and an output connected to the second feedback node; a capacitor connecting the first feedback node and the second feedback node; an amplifier having an input connected to the first feedback node and an output connected to the output node; a base feedback amplifier with an input connected to the output node and an output connected to the first feedback node; a tunable feedback amplifier with an input connected to the output node and an output connected to the second feedback node; and a tuning circuit for varying a transconductance of the tunable feedback circuit and operational frequency of the peaking amplifier circuit.. . ... Globalfoundries Inc

Source/drain parasitic capacitance reduction in finfet-based semiconductor structure having tucked fins

A method of reducing parasitic capacitance includes providing a starting semiconductor structure, the starting semiconductor structure including a semiconductor substrate with fin(s) thereon, the fin(s) having at least two dummy transistors integrated therewith and separated by a dielectric region, the dummy transistors including dummy gates with spacers and gate caps, the fin(s) having ends tucked by the dummy gates. The method further includes removing the dummy gates and gate caps, resulting in gate trenches, protecting area(s) of the structure during fabrication process(es) where source/drain parasitic capacitance may occur, and forming air-gaps at a bottom portion of unprotected gate trenches to reduce parasitic capacitance. ... Globalfoundries Inc

Field effect transistor (fet) with a gate having a recessed work function metal layer and method of forming the fet

A hash table method and structure comprises a processor that receives a plurality of access requests for access to a storage device. The processor performs a plurality of hash processes on the access requests to generate a first number of addresses for each access request. ... Globalfoundries Inc

Unmerged epitaxial process for finfet devices with aggressive fin pitch scaling

Methods for forming a semiconductor device include forming a first spacer on a plurality of fins. A second spacer is formed on the first spacer, the second spacer being formed from a different material from the first spacer. ... Globalfoundries Inc

Gate cuts after metal gate formation

Structures involving a field-effect transistor and methods for forming a structure that involves a field-effect transistor. A first metal gate electrode and a second metal gate electrode are formed that are embedded in a first dielectric layer. ... Globalfoundries Inc

Cost-free mtp memory structure with reduced terminal voltages

Device and methods for forming a single transistor non-volatile (nv) multi-time programmable (mtp) memory cell are disclosed. The disclosed memory cell is derived via the disclosed method that includes providing a substrate and forming at least a transistor well with a second polarity type dopant and first and second capacitor wells with a first polarity type dopant in the substrate. ... Globalfoundries Inc

Gate cut method

A method of manufacturing a finfet structure involves forming gate cuts within a sacrificial gate layer prior to patterning and etching the sacrificial gate layer to form longitudinal sacrificial gate structures. By forming transverse cuts in the sacrificial gate layer before defining the sacrificial gate structures longitudinally, dimensional precision of the gate cuts at lower critical dimensions can be improved.. ... Globalfoundries Inc

Methods of forming an air gap adjacent a gate of a transistor and a gate contact above the active region of the transistor

One method includes performing an etching process to define a gate cavity that exposes an upper surface and at least a portion of the sidewalls of a gate structure and forming a replacement spacer structure adjacent the exposed sidewalls of the gate structure, wherein the replacement spacer structure exposes a portion of the upper surface of the gate structure and includes at least one air space. In this example, the method also includes forming a conformal etch stop layer and a replacement gate cap structure in the gate cavity, selectively removing a portion of the replacement gate cap structure and a portion of the conformal etch stop layer so as to thereby expose the upper surface of the gate structure, and forming a conductive gate contact structure (cb) in the conductive gate contact opening, wherein the entire conductive gate contact structure (cb) is positioned vertically above the active region.. ... Globalfoundries Inc

Structure and method for capping cobalt contacts

A process for forming a conductive structure includes the formation of a self-aligned silicide cap over a cobalt-based contact. The silicide cap is formed in situ by the deposition of a thin silicon layer over exposed portions of a cobalt contact, followed by heat treatment to react the deposited silicon with the cobalt and form cobalt silicide, which is an effective barrier to cobalt migration and oxidation.. ... Globalfoundries Inc

Methods of forming conductive structures

One illustrative method disclosed herein includes, among other things, forming a first trench/via and a wider second trench/via in a layer of insulating material, forming a conductive adhesion layer in the first and second trench/vias and forming a conductive liner layer in the second trench/via such that the material of the conductive liner layer substantially fills the first trench/via. In this particular example, the method also includes removing portions of the conductive liner layer positioned within the second trench/via and above an upper surface of the conductive adhesion layer and removing portions of the conductive adhesion layer positioned above an upper surface of the layer of insulating material to define a conductive structure positioned in the first trench/via that comprises the material of the conductive adhesion layer and the material of the conductive liner layer.. ... Globalfoundries Inc

Vertical field-effect transistors with controlled dimensions

Device structures and fabrication methods for a vertical field-effect transistor. A semiconductor fin is formed that projects from a first source/drain region. ... Globalfoundries Inc

Low resistance ruthenium-containing contacts

A conductive source/drain contact is formed within a trench overlying a raised epitaxial source/drain junction. The conductive contact includes a conductive liner and a conductive fill material formed directly over the conductive liner. ... Globalfoundries Inc

Field-effect transistors with a t-shaped gate electrode

Device structures for a field-effect transistor and methods for forming a device structure for a field-effect transistor. A first dielectric layer is formed, and a second dielectric layer are formed on the first dielectric layer. ... Globalfoundries Inc

On-chip capacitors with floating islands

Structures for an on-chip capacitor and methods of forming an on-chip capacitor. A metal terminal is formed that has a side edge. ... Globalfoundries Inc

09/20/18 / #20180269273

Interconnect structures for a metal-insulator-metal capacitor

Methods for contacting a metal-insulator-metal (mim) capacitor, as well as structures including a mim capacitor. A dielectric layer is formed on an electrode of a metal-insulator-metal capacitor. ... Globalfoundries Inc

09/20/18 / #20180269209

Mtp memory for soi process

Embodiments of a multi-time programmable (mtp) structure for non-volatile memory cells are presented. The memory cell includes an ultra-thin silicon-on-insulator (soi) substrate. ... Globalfoundries Inc

09/20/18 / #20180269191

Micro-led display assembly

The present disclosure relates to semiconductor structures and, more particularly, to a micro-light emitting diode (led) display assembly and methods of manufacture. The structure includes an interposer and a plurality of micro-led arrays each of which include a plurality of through-vias connecting pixels of the plurality of micro-led arrays to the interposer.. ... Globalfoundries Inc

09/20/18 / #20180269150

Metal interconnects for super (skip) via integration

The present disclosure relates to semiconductor structures and, more particularly, to metal interconnect structures for super (skip) via integration and methods of manufacture. The structure includes: a first wiring layer with one or more wiring structures; a second wiring layer including an interconnect and wiring structure; and at least one upper wiring layer with one or more via interconnect and wiring structures located above the second wiring layer. ... Globalfoundries Inc

09/20/18 / #20180269105

Bonding of iii-v-and-si substrates with interconnect metal layers

A iii-v-and-si substrate device is described including integration of a backend unit and a frontend unit. The backend unit includes interlevel dielectric (ild) layers having metal lines and via contacts. ... Globalfoundries Inc

09/20/18 / #20180269103

Chamferless via structures

Chamferless via structures and methods of manufacture are provided. The method includes: forming at least one non-self-aligned via within at least dielectric material; plugging the at least one non-self-aligned via with material; forming a protective sacrificial mask over the material which plugs the at least one non-self-aligned via, after a recessing process; forming at least one trench within the dielectric material, with the protective sacrificial mask protecting the material during the trench formation; removing the protective sacrificial mask and the material within the at least one non-self-aligned via to form a wiring via; and filling the wiring via and the at least one trench with conductive material.. ... Globalfoundries Inc

09/20/18 / #20180269081

System and method for status-dependent controlling of a substrate ambient in microprocessing

The present disclosure provides systems and techniques in which an ambient may be controlled on the basis of a current status of a micro-processed substrate so as to maintain the status within predefined limits. In illustrative embodiments, the substrate may be stored in an ambient, for which temperature and/or contents of one or more gaseous species may be controlled so as to reduce the change of status. ... Globalfoundries Inc

09/20/18 / #20180266807

Method and device for measuring plating ring assembly dimensions

A method for obtaining distance measurements for a plating ring assembly and related device are provided. Embodiments include attaching a measurement device to a plating ring assembly, the plating ring assembly including: an outer ring, wherein the measurement device is attached to the outer ring and configured to rotate along the outer ring, a seal extending from a bottom surface of the outer ring along a circumference of the plating ring assembly, contact fingers located along the circumference of the plating ring assembly, between the outer ring and the seal, rotating the measurement device along the circumference of the outer ring by rotating the measurement device or the plating ring assembly; and obtaining critical dimensions of and between the seal and contact fingers with the measurement device.. ... Globalfoundries Inc

09/06/18 / #20180254630

Method to protect sensitive devices from electrostatic discharge damage

Esd protection circuitry that includes one, or more, of the following features, characteristics and/or advantages: (i) use of different “diode types” (for example, schottky type, pn type, p-type diode-connected field-effect transistor (fet) type, nfet type)) in a series-connected diode set (connected in series with respect to a device-under-protection) and a parallel-connected diode set (connected in parallel with respect to a device-under-protection and the series-connected diode set); (ii) a fet is connected in series with a target device such that the fet's gate can be turned on during normal operation and the fet's gate is resistively coupled to the fet's source; and/or (iii) two fets are connected in series with a target device such both fets gates can be turned on during normal operation, one fet's gate is resistively coupled to its source, and the other fet's gate is electrically coupled to its drain.. . ... Globalfoundries Inc

09/06/18 / #20180254343

Method of forming a semiconductor device

A method of forming a semiconductor device includes forming a first well and a second well in a substrate, wherein the first well is doped with dopants of a first conductivity type and the second well is doped with dopants of a second conductivity type. A third well is formed within the first well, and a gate structure is formed above the substrate, the gate structure partially overlying at least the first and second wells. ... Globalfoundries Inc

09/06/18 / #20180254340

Tunnel finfet with self-aligned gate

Structures and methods for a tunnel field-effect transistor (tfet). The tfet includes a gate electrode, a source region having a first conductivity type, a drain region having a second conductivity type opposite from the first conductivity type, and a dielectric layer separating the gate electrode from the source region and the drain region. ... Globalfoundries Inc

09/06/18 / #20180254331

Etch-resistant spacer formation on gate structure

The disclosure relates to methods of forming etch-resistant spacers in an integrated circuit (ic) structure. Methods according to the disclosure can include: forming a mask on an upper surface of a gate structure positioned over a substrate; forming a spacer material on the substrate, the mask, and exposed sidewalls of the gate structure; forming a separation layer over the substrate and laterally abutting the spacer material to a predetermined height, such that an exposed portion of the spacer material is positioned above an upper surface of the separation layer and at least partially in contact with the mask; and implanting a dopant into the exposed portion of the spacer material to yield a dopant-implanted region within the spacer material, wherein the dopant-implanted region of the spacer material has a greater etch resistivity than a remainder of the spacer material.. ... Globalfoundries Inc

09/06/18 / #20180254327

Buried contact structures for a vertical field-effect transistor

Structures including a vertical field-effect transistor and fabrication methods for a structure including a vertical field-effect transistor. A vertical field-effect transistor includes a source/drain region located in a section of a semiconductor layer, a first semiconductor fin projecting from the source/drain region, a second semiconductor fin projecting from the source/drain region, and a gate electrode on the section of the semiconductor layer and coupled with the first semiconductor fin and with the second semiconductor fin. ... Globalfoundries Inc

09/06/18 / #20180254315

Thin film resistor methods of making contacts

A method for forming a thin film resistor (tfr) without via penetration and the resulting device are provided. Embodiments include forming a first ild over a substrate; forming a second ild over the first ild; forming a first metal layer in the second ild; forming a first nitride layer over the second ild and the first metal layer; forming a third ild over the first nitride layer; forming vias through the third ild and the first nitride layer, coupled to the first metal layer; forming a tfr layer over two of the vias and the third ild between the two vias; forming a second nitride layer over the tfr layer and the third ild; forming a fourth ild over the second nitride layer; and forming a second metal layer in the fourth ild and the second nitride layer.. ... Globalfoundries Inc

09/06/18 / #20180254239

Forming metal cap layer over through-glass-vias (tgvs)

Methods for reliable interconnect structures between thin metal capture pads and tgv metallization and resulting devices are provided. Embodiments include forming a tgv in a glass substrate; filling with metal conductive paste; forming a metal layer on top and bottom surfaces of the substrate; patterning the metal layer, leaving at least a portion over the tgv top surface and an area surrounding the tgv; forming a dielectric layer on the metal layer and on the substrate top and bottom surfaces; patterning the dielectric layer, including exposing the metal layer over the tgv top surface and the area surrounding the tgv; forming a second metal layer on the dielectric layer and on the exposed portion of the first metal layer over the tgv top surface and the area surrounding the tgv; patterning the second metal layer exposing the dielectric layer; and forming a third metal layer on the second metal layer.. ... Globalfoundries Inc

08/23/18 / #20180240897

Heterojunction bipolar transistor with a thickened extrinsic base

Device structures and fabrication methods for a heterojunction bipolar transistor. A collector of the device structure has a top surface and a sidewall that is inclined relative to the top surface. ... Globalfoundries Inc

08/23/18 / #20180240889

Semiconductor devices having equal thickness gate spacers

A method is presented for forming equal thickness gate spacers for a cmos (complementary metal oxide semiconductor) device, the method includes forming a pfet (p-type field effect transistor) device and an nfet (n-type field effect transistor) device each including gate masks formed over dummy gates, forming pfet epi growth regions between the dummy gates of the pfet device, forming nfet epi growth regions between the dummy gates of the nfet device, depositing a nitride liner and an oxide over the pfet and nfet epi growth regions, the nitride liner and oxide extending up to the gate masks, and removing the dummy gates and the gate masks to form hkmgs (high-k metal gates) between the pfet and nfet epi growth regions.. . ... Globalfoundries Inc

08/23/18 / #20180240885

Simplified gate to source/drain region connections

Structures for a field-effect transistor and fabrication methods for forming a structure for a field-effect transistor. The structure may include a gate electrode, a source/drain region formed adjacent to a vertical sidewall of the gate electrode, and a conductive link that couples the vertical sidewall of the gate electrode with the source/drain region.. ... Globalfoundries Inc

08/23/18 / #20180240884

Spacer chamfering gate stack scheme

A method of forming a gate structure for a semiconductor device that includes forming first spacers on the sidewalls of replacement gate structures that are present on a fin structure, wherein an upper surface of the first spacers is offset from an upper surface of the replacement gate structure, and forming at least second spacers on the first spacers and the exposed surfaces of the replacement gate structure. The method may further include substituting the replacement gate structure with a functional gate structure having a first width portion in a first space between adjacent first spacers, and a second width portion having a second width in a second space between adjacent second spacers, wherein the second width is greater than the first width.. ... Globalfoundries Inc

08/23/18 / #20180240883

Air-gap gate sidewall spacer and method

Disclosed are integrated circuit (ic) structures and formation methods. In the methods, a gate with a sacrificial gate cap and a sacrificial gate sidewall spacer is formed on a channel region. ... Globalfoundries Inc

08/23/18 / #20180240875

Low resistance source drain contact formation

Techniques for forming ga-doped source drain contacts in ge-based transistors are provided. In one aspect, a method for forming ga-doped source and drain contacts includes the steps of: depositing a dielectric over a transistor; depositing a dielectric over the transistor; forming contact trenches in the dielectric over, and extending down to, source and drain regions of the transistor; depositing an epitaxial material into the contact trenches; implanting gallium ions into the epitaxial material to form an amorphous gallium-doped layer; and annealing the amorphous gallium-doped layer under conditions sufficient to form a crystalline gallium-doped layer having a homogenous gallium concentration of greater than about 5×1020 at./cm3. ... Globalfoundries Inc

08/23/18 / #20180240796

Semiconductor device including buried capacitive structures and a method of forming the same

A method includes forming a plurality of openings extending through a semiconductor layer, through a buried insulating layer, and into a substrate material in a second device region of a semiconductor device while covering a first device region of the semiconductor device. An insulating material is formed on sidewalls and on a bottom face of each of the plurality of openings, and a first capacitor electrode is formed in each of the plurality of openings in the presence of the insulating material, wherein each of the first capacitor electrodes includes a conductive material and partially fills a respective one of the plurality of openings.. ... Globalfoundries Inc

08/23/18 / #20180240715

Methods of forming vertical transistor devices with different effective gate lengths and the resulting devices

A device includes, among other things, a first vertical transistor device positioned above a semiconductor substrate. The first vertical transistor device includes a first gate structure, a first top spacer positioned above the first gate structure and having a first thickness in a vertical direction, and a first doped top source/drain structure positioned above the first top spacer. ... Globalfoundries Inc

08/23/18 / #20180240703

Middle of the line (mol) contact formation method and structure

Disclosed are a method of forming an integrated circuit (ic) structure with robust metal plugs and the resulting ic structure. In the method, openings are formed in an interlayer dielectric layer to expose semiconductor device surfaces. ... Globalfoundries Inc

08/23/18 / #20180238958

Ranking defects with yield impacts

Failure types that caused defective items to fail testing are identified, the defective items are grouped by the failure types to produce failure-type groups, and the defective items are analyzed to identify defect types that caused the failures. Failure-type limited yield within each of the failure-type groups, and failure-type group-specific defect ratio based on proportions of the defect types within each of the failure-type groups are determined. ... Globalfoundries Inc

08/16/18 / #20180233663

Integrated magnetic random access memory with logic device having low-k interconnects

Device and methods of forming a device are disclosed. The method includes providing a substrate and a first upper dielectric layer over first, second and third regions of the substrate. ... Globalfoundries Inc

08/16/18 / #20180233661

Device alignment mark using a planarization process

Device and methods of forming a device are disclosed. The method includes providing a substrate and forming a dielectric layer over the substrate. ... Globalfoundries Inc

08/16/18 / #20180233585

Merged gate and source/drain contacts in a semiconductor device

Provided are approaches for forming merged gate and source/drain (s/d) contacts in a semiconductor device. Specifically, one approach provides a dielectric layer over a set of gate structures formed over a substrate; a set of source/drain (s/d) openings patterned in the dielectric layer between the gate structures; a fill material formed over the gate structures, including within the s/d openings; and a set of gate openings patterned over the gate structures, wherein a portion of the dielectric layer directly adjacent the fill material formed within one of the s/d openings is removed. ... Globalfoundries Inc

08/16/18 / #20180233583

Transistors and methods of forming transistors using vertical nanowires

Devices and methods of fabricating vertical nanowires on semiconductor devices are provided. One method includes: obtaining an intermediate semiconductor device having a substrate, a first insulator disposed above the substrate, a material layer over the first insulator, a second insulator above the material layer, and a first hardmask; etching a plurality of vertical trenches through the hardmask, the first and second insulators, and the material layer; growing, epitaxially, a set of silicon nanowires from a bottom surface of the plurality of vertical trenches; etching a first set of vertical trenches to expose the material layer; etching a second set of vertical trenches to the substrate; depositing an insulating spacer material on a set of sidewalls of the first and second set of vertical trenches; and forming contacts in the first and second set of vertical trenches.. ... Globalfoundries Inc

08/16/18 / #20180233580

Semiconductor structure with gate height scaling

The present disclosure relates to semiconductor structures and, more particularly, to semiconductor gate structures with gate height scaling and methods of manufacture. The method includes: forming at least one dummy gate structure with hardmask material; forming a plurality of materials over source and drain regions on sides of the at least one dummy gate structure; removing upper materials of the hardmask material such that a first material of the hardmask material remains on the dummy gate structure and in combination with a blocking material of the plurality of materials maintains a uniform gate height; forming a replacement gate structure by removing remaining material of the dummy gate structure to form a trench and depositing replacement gate material in the trench; and forming contacts to the source and drain regions.. ... Globalfoundries Inc

08/16/18 / #20180233579

Gate cut integration and related device

A method for forming gate cuts during rmg processing and the resulting device are provided. Embodiments include forming si fins over a substrate; forming a sti layer over the substrate and recessed, exposing upper portions of the si fins; forming polysilicon dummy gate electrodes perpendicular to the si fins, separated by sti regions, on the upper portions of the si fins and on the sti layer between the si fins; forming a hardmask over the polysilicon dummy gate electrodes; etching through the hardmask and polysilicon dummy gate electrodes forming cavities between some of the si fins; oxidizing polysilicon exposed on sides of the cavities and any residual polysilicon remaining at a bottom of one or more of the cavities; filling the cavities with sin; removing the polysilicon dummy gate electrodes; and forming rmgs.. ... Globalfoundries Inc

08/16/18 / #20180233566

Field effect transistor structure with recessed interlayer dielectric and method

Disclosed are a field effect transistor (fet) and a fet formation method. In the fet, an interlayer dielectric (ild) layer is positioned laterally adjacent to a sidewall spacer of a replacement metal gate and a cap layer covers the ild layer, the sidewall spacer and the gate. ... Globalfoundries Inc

08/16/18 / #20180233509

Strap layout for non-volatile memory device

A device and methods for forming the device are disclosed. The method includes providing a substrate prepared with a memory cell region and forming memory cell pairs in the cell region. ... Globalfoundries Inc

08/16/18 / #20180233505

Self-aligned sacrificial epitaxial capping for trench silicide

A method for forming a self-aligned sacrificial epitaxial cap for trench silicide and the resulting device are provided. Embodiments include a si fin formed in a pfet region; a pair of si fins formed in a nfet region; epitaxial s/d regions formed on ends of the si fins; a replacement metal gate formed over the si fins in the pfet and nfet regions; metal silicide trenches formed over the epitaxial s/d regions in the pfet and neft regions; a metal layer formed over top surfaces of the s/d region in the pfet region and top and bottom surfaces of the s/d regions in the nfet region, wherein the epitaxial s/d regions in the pfet and nfet regions are diamond shaped in cross-sectional view.. ... Globalfoundries Inc

08/16/18 / #20180233488

Integrated circuit package with thermally conductive pillar

Embodiments of the present disclosure relate to an integrated circuit (ic) package, including a molding compound positioned on a first die and laterally adjacent to a stack of dies positioned on the first die. The stack of dies electrically couples the first die to an uppermost die, and a thermally conductive pillar extends through the molding compound from the first die to an upper surface of the molding compound. ... Globalfoundries Inc

08/16/18 / #20180233462

Seal ring for wafer level package

Devices and methods for forming a device are disclosed. At least one die is provided. ... Globalfoundries Inc

08/16/18 / #20180233417

Dual liner silicide

A method for fabricating a dual silicide device includes growing source and drain (s/d) regions for an n-type device, forming a protection layer over a gate structure and the s/d regions of the n-type device and growing s/d regions for a p-type device. A first dielectric layer is conformally deposited and portions removed to expose the s/d regions. ... Globalfoundries Inc

08/16/18 / #20180233415

Finfet device and method of manufacturing

A method for producing a finfet having a fin with thinned sidewalls on a lower portion above a shallow trench isolation (sti) regions is provided. Embodiments include forming a fin surrounded by sti regions on a substrate; recessing the sti regions, revealing an upper portion of the fin; forming a spacer over side and upper surfaces of the upper portion of the fin; recessing the sti regions, exposing a lower portion of the fin; and thinning sidewalls of the lower portion of the fin.. ... Globalfoundries Inc

08/16/18 / #20180233413

Graphene contacts on source/drain regions of finfet devices

A finfet device includes a fin formed in a semiconductor substrate, a gate structure positioned above a portion of the fin, and source and drain regions positioned on opposite sides of the gate structure, wherein the semiconductor substrate includes a first semiconductor material. A silicon-carbide (sic) semiconductor material is positioned above the fin in the source region and the drain region, wherein the silicon-carbide (sic) semiconductor material is different from the first semiconductor material. ... Globalfoundries Inc

08/16/18 / #20180233412

Forming ts cut for zero or negative ts extension and resulting device

A method of forming a logic or memory cell with less than or equal to 0 nm of ts extending past the active fins and the resulting device are provided. Embodiments include forming gates across pairs of fins on a substrate; forming pairs of rsd between the gates on the fins; forming a planar sac cap on each of the gates; forming a metal layer over the substrate coplanar with the sacs; forming a ts structure in the metal layer over the fins, the ts structure formed over the pairs of rsd, each upper portion having a width equal to or less than an overall width of a pair of fins; forming spacers on opposite sides of the upper portions; removing the metal layer between adjacent spacers; forming an ild over the substrate; and forming a ca on each upper portion and a cb on a gate through the ild.. ... Globalfoundries Inc

08/16/18 / #20180233404

Variable space mandrel cut for self aligned double patterning

The present disclosure relates to semiconductor structures and, more particularly, to variable space mandrel cut for self-aligned double patterning and methods of manufacture. The method includes: forming a plurality of mandrels on a substrate; forming spacers about the plurality of mandrels and exposed portions of the substrate; removing a portion of at least one of the plurality of mandrels to form an opening; and filling in the opening with material.. ... Globalfoundries Inc

08/16/18 / #20180233401

Local trap-rich isolation

A trap-rich polysilicon layer is interposed between the active (soi) layer and the underlying handle portion of a semiconductor substrate to prevent or minimize parasitic surface conduction effects within the active layer and promote device linearity. In various embodiments, the trap-rich layer extends vertically through a portion of an isolation layer and laterally therefrom between the isolation layer and the handle portion of the substrate to underlie a portion of the device active area.. ... Globalfoundries Inc

08/16/18 / #20180233388

Method and system for detecting a coolant leak in a dry process chamber wafer chuck

Device and method of configuring a device to process a wafer is disclosed. The device includes a wafer chuck configured to mount the wafer, a dry wafer processing chamber configured to enclose the wafer chuck, a humidity sensor configured to measure relative humidity (rh) at an outlet of the dry wafer processing chamber, a humidity controller coupled to the humidity sensor, the humidity controller being configured to detect a change in rh above a threshold, and a process chamber controller coupled to the humidity controller. ... Globalfoundries Inc

08/16/18 / #20180233361

Dummy pattern addition to improve cd uniformity

A multiple exposure patterning process includes the incorporation of a dummy feature into the integration flow. The dummy feature, which is placed to overlie an existing masking layer and thus does not alter the printed image, improves the critical dimension uniformity (cdu) of main critical (non-dummy) features at the same masking level.. ... Globalfoundries Inc

08/16/18 / #20180233216

Circuit and method for detecting time dependent dielectric breakdown (tddb) shorts and signal-margin testing

The present disclosure relates to a structure which includes a twin-cell memory which is configured to program a plurality of write operations, a current sense amplifier which is connected to the twin-cell memory and is configured to sense a current differential and latch a differential voltage based on the current differential, and at least one current source which is connected to the current sense amplifier and is configured to add an offset current to the current sense amplifier to create the differential voltage.. . ... Globalfoundries Inc

08/16/18 / #20180231957

Crystal oscillator and the use thereof in semiconductor fabrication

Systems and methods are provided for implementing a crystal oscillator to monitor and control semiconductor fabrication processes. More specifically, a method is provided for that includes performing at least one semiconductor fabrication process on a material of an integrated circuit (ic) disposed within a processing chamber. ... Globalfoundries Inc

08/09/18 / #20180226505

Vertical transport field effect transistors

The present disclosure relates to semiconductor structures and, more particularly, to vertical transport field effect transistor devices and methods of manufacture. A structure includes: a vertical fin structure having a lower dopant region, an upper dopant region and a channel region between the lower dopant region and the upper dopant region; and a doped semiconductor material provided on sides of the vertical fin structure at a lower portion. ... Globalfoundries Inc

08/09/18 / #20180226503

Vertical pillar-type field effect transistor and method

Disclosed is a method of forming a vertical pillar-type field effect transistor (fet). One or more semiconductor pillars are formed by epitaxial deposition in one or more openings, respectively, that extend through a first dielectric layer and that have high aspect ratios in two directions. ... Globalfoundries Inc

08/09/18 / #20180226402

Integration of vertical field-effect transistors and saddle fin-type field effect transistors

Structures for the integration of a vertical field-effect transistor and a saddle fin-type field-effect transistor into an integrated circuit, as well as methods of integrating a vertical field-effect transistor and a saddle fin-type field-effect transistor into an integrated circuit. A trench isolation is formed in a substrate that defines a first device region and a second device region. ... Globalfoundries Inc

08/09/18 / #20180226394

Finfet esd device with schottky diode

A fin field effect transistor (finfet) esd device is disclosed. The device may include: a substrate; a silicon-controlled rectifier (scr) over the substrate, the scr including: a p-well region over the substrate; an n-well region laterally abutting the p-well region over the substrate; a first p+ doped region over the p-well region; a first n+ doped region over the p-well region; and a second n+ doped region over the p-well region; and a schottky diode electrically coupled to the n-well region, wherein the schottky diode spans the n-well region and the p-well region, and wherein the schottky diode controls electrostatic discharge (esd) between the second n+ doped region and the n-well region.. ... Globalfoundries Inc

08/09/18 / #20180226347

Heterojunction bipolar transistors with stress material for improved mobility

According to a semiconductor device herein, the device includes a substrate. An active device is formed in the substrate. ... Globalfoundries Inc

08/09/18 / #20180226294

Devices with chamfer-less vias multi-patterning and methods for forming chamfer-less vias

Semiconductor devices and methods of fabricating the semiconductor devices with chamfer-less via multi-patterning are disclosed. One method includes, for instance: obtaining an intermediate semiconductor device; performing a trench etch into a portion of the intermediate semiconductor device to form a trench pattern; depositing an etching stack; performing at least one via patterning process; and forming at least one via opening into a portion of the intermediate semiconductor device. ... Globalfoundries Inc

08/09/18 / #20180226292

Trench isolation formation from the substrate back side using layer transfer

Structures with trench isolation and methods for making a structure with trench isolation. A transistor is formed by front-end-of-line processing on a first surface of a semiconductor substrate. ... Globalfoundries Inc

08/09/18 / #20180226166

Extreme ultraviolet mirrors and masks with improved reflectivity

Extreme ultraviolet mirrors and masks used in lithography and methods for manufacturing an extreme ultraviolet mirror or mask. Initial data is obtained that includes materials and optical properties for a first intermixed layer, a second intermixed layer, a first pure layer, and a second pure layer in each of a plurality of periods of a multi-layer stack for an optical element. ... Globalfoundries Inc

08/09/18 / #20180225406

Context aware processing to resolve strong spacing effects due to strain relaxation in standard cell library

Methods and systems assign an alignment context to each of the cells within an integrated circuit layout, from previously established alignment contexts, based on how the different cell widths cause each of the cells to align with adjoining cells. Also, such methods and systems retrieve standard signal delay times for each of the cells from a standard cell library. ... Globalfoundries Inc

08/02/18 / #20180219096

Semiconductor structure including low-k spacer material

A semiconductor structure includes a substrate, and a replacement metal gate (rmg) structure is attached to the substrate. The rmg structure includes a lower portion and an upper tapered portion. ... Globalfoundries Inc

08/02/18 / #20180219079

Spacers for tight gate pitches in field effect transistors

Structures for spacers of a field-effect transistor and methods for forming such spacers. A mask layer has a feature separated from a vertical sidewall of a first gate structure by a space of predetermined width that exposes a top surface of a semiconductor body. ... Globalfoundries Inc

08/02/18 / #20180219006

Diode-triggered schottky silicon-controlled rectifier for fin-fet electrostatic discharge control

Various embodiments include fin-type field effect transistor (finfet) structures. In some cases, a finfet structure includes: a substrate; a silicon-controlled rectifier (scr) over the substrate, the scr including: a p-well region and an adjacent n-well region over the substrate; and a negatively charged fin over the p-well region; and a schottky diode electrically coupled with the scr, the schottky diode spanning between the p-well region and the n-well region, the schottky diode for controlling electrostatic discharge (esd) across the negatively charged fin and the n-well region.. ... Globalfoundries Inc

08/02/18 / #20180218991

Methods of forming integrated circuit structure for joining wafers and resulting structure

The disclosure is directed to an integrated circuit structure for joining wafers and methods of forming same. The ic structure may include: a metallic pillar over a substrate, the metallic pillar including an upper surface; a wetting inhibitor layer about a periphery of the upper surface of the metallic pillar; and a solder material over the upper surface of the metallic pillar, the solder material being within and constrained by the wetting inhibitor layer. ... Globalfoundries Inc

08/02/18 / #20180218981

Circuit design having aligned power staples

A multi-layer integrated circuit structure includes (among other components) a first layer having gate conductors, a second layer having m0 conductors, a third layer having m1 conductors, and a fourth layer having m2 conductors. The m0 and m2 conductors are perpendicular to the gate conductors, and parallel to each other. ... Globalfoundries Inc

08/02/18 / #20180218947

Methods, apparatus and system for providing adjustable fin height for a finfet device

A method and system are disclosed herein for an adjustable effective fin height in a gate region of a finfet device. Fin structures, each having a first height, a fin, an oxide liner, and a nitride liner, are formed. ... Globalfoundries Inc

08/02/18 / #20180217584

Insitu tool health and recipe quality monitoring on a cdsem

Systems, methods, and computer program products for monitoring the tool health of on a critical dimension scanning electron microscope (cdsem) and recipe quality on a cdsem. Run-time data from a critical dimension scanning electron microscope is received at a computer. ... Globalfoundries Inc

08/02/18 / #20180217184

Gimbal assembly test system and method

Aspects of the present disclosure provide a gimbal assembly test system including: a protective cover affixed to a test surface of a wafer probe card mounted within a gimbal bearing, wherein the protective cover includes an exterior surface oriented outward from the test surface of the wafer probe card; and a recess extending into the exterior surface of the protective cover and shaped to matingly engage a load cell tip therein.. . ... Globalfoundries Inc

07/26/18 / #20180212058

Compact otp/mtp technology

Methods of forming a compact finfet otp/mtp cell and a compact fdsoi otp/mtp cell and resulting devices are provided. Embodiments include providing a substrate having a box layer; forming fins on the box layer with a gap in between; forming first and second gates, laterally separated, over and perpendicular to the fins; forming at least one third gate between the first and second gates and contacting the box layer through the gap, each third gate overlapping an end of a fin or both fins; forming a s/d region in each of the fins adjacent to the first and second gates, respectively, remote from the at least one third gate; utilizing each of the first and second gates as a wl; utilizing each third gate as a sl or connecting a sl to the s/d region; and connecting a bl to the s/d region or the at least one third gate.. ... Globalfoundries Inc

07/26/18 / #20180212024

Stacked nanowire device width adjustment by gas cluster ion beam (gcib)

A method of making a nanowire device includes disposing a first nanowire stack over a substrate, the first nanowire stack including alternating layers of a first and second semiconducting material, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface; disposing a second nanowire stack over the substrate, the second nanowire stack including alternating layers of the first and second semiconducting materials, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface; forming a first gate spacer along a sidewall of a first gate region on the first nanowire stack and a second gate spacer along a sidewall of a second gate region on the second nanowire stack; oxidizing a portion of the first nanowire stack within the first gate spacer; and removing the first semiconducting material from the first nanowire stack and the second nanowire stack.. . ... Globalfoundries Inc

07/26/18 / #20180211927

Reliable pad interconnects

A device and methods of forming the device are disclosed. A substrate with a circuits component and a dielectric layer with interconnects is provided. ... Globalfoundries Inc

07/26/18 / #20180211873

Recessing of liner and conductor for via formation

The disclosure relates to integrated circuit (ic) fabrication techniques. Methods according to the disclosure can include: forming a reaction layer on the upper surface of a conductor, the upper surface of a refractory metal liner, and the upper surface of an insulator layer; annealing the reaction layer such that a portion of the reaction layer reacts with the conductor to form a semiconductor-metal alloy region; removing a portion of the reaction layer to expose the refractory metal liner; removing a portion of the refractory metal liner to approximately a depth of the semiconductor-metal alloy region; and removing the semiconductor-metal alloy region to expose a portion of the conductor such that a remainder of the conductor and a remainder of the refractory metal liner are recessed relative to an upper surface of the insulator layer.. ... Globalfoundries Inc

07/26/18 / #20180211871

Self-aligned via forming to conductive line and related wiring structure

A method of forming a via and a wiring structure formed are disclosed. The method may include forming a conductive line in a first dielectric layer; forming a hard mask adjacent to the conductive line after the conductive line forming; forming a second dielectric layer over the hard mask; and forming a via opening to the conductive line in the second dielectric layer. ... Globalfoundries Inc

07/19/18 / #20180204944

Semiconductor device structure

. . The present disclosure provides a semiconductor device structure including an active region having a semiconductor-on-insulator (soi) configuration, a semiconductor device of lateral double-diffused mos (ldmos) type, a dual ground plane region formed by two well regions which are counter-doped to each other, the dual ground plane region extending below the semiconductor device, and a deep well region extending below the dual ground plane region. Herein, the semiconductor device of ldmos type comprises a gate structure formed on the active region, a source region and a drain region formed in the active region at opposing sides of the gate structure, and a channel region and a drift region, both of which being formed in the active region and defining a channel drift junction, wherein the channel drift junction is overlain by the gate structure.. ... Globalfoundries Inc

07/19/18 / #20180204929

Metal gate formation using an energy removal film

Structures for a field-effect transistor and methods for forming a field-effect transistor. An interlayer dielectric layer is formed on a substrate. ... Globalfoundries Inc

07/19/18 / #20180204927

Air-gap gate sidewall spacer and method

Disclosed are integrated circuit (ic) structures and formation methods. In the methods, a gate with a sacrificial gate cap and a sacrificial gate sidewall spacer is formed on a channel region. ... Globalfoundries Inc

07/19/18 / #20180204926

Transistor using selective undercut at gate conductor and gate insulator corner

Methods form transistor structures that include, among other components, a substrate having an active region bordered by an isolation region, a gate insulator on the substrate, and a gate conductor on the gate insulator. First and second sections of the gate conductor are within the active region of the substrate, while a third section is in the isolation region of the substrate. ... Globalfoundries Inc

07/19/18 / #20180204920

Field effect transistor structure with recessed interlayer dielectric and method

Disclosed are a field effect transistor (fet) and a fet formation method. In the fet, an interlayer dielectric (ild) layer is positioned laterally adjacent to a sidewall spacer of a replacement metal gate and a cap layer covers the ild layer, the sidewall spacer and the gate. ... Globalfoundries Inc

07/19/18 / #20180204840

Self-aligned junction structures

The present disclosure relates to semiconductor structures and, more particularly, to self-aligned junction structures and methods of manufacture. The structure includes: a plurality of epitaxial grown fin structures for first type devices; and a plurality epitaxial grown fin structures for second type devices having sidewall liners.. ... Globalfoundries Inc

07/19/18 / #20180204796

Embedded metal-insulator-metal (mim) decoupling capacitor in monolitic three-dimensional (3d) integrated circuit (ic) structure

Various embodiments include three-dimensional (3d) integrated circuit (ic) structures and methods of forming such structures. In some cases, a 3d ic structure includes: a substrate; a first set of transistors overlying the substrate; a first inter-level dielectric (ild) overlying the first set of transistors and the substrate; a dielectric overlying the first ild; a semiconductor layer overlying the dielectric; a second set of transistors overlying the semiconductor layer; a capacitor embedded within the dielectric; and a first contact extending through the semiconductor layer and the dielectric to contact one layer of the capacitor, and a second contact extending through the semiconductor layer and the dielectric to contact a second, distinct layer of the capacitor.. ... Globalfoundries Inc

07/19/18 / #20180204761

Lateral pin diodes and schottky diodes

Lateral pin diodes and schottky diodes with low parasitic capacitance and variable breakdown voltage structures and methods of manufacture are disclosed. The structure includes a diode with breakdown voltage determined by a dimension between p- and n-terminals formed in an i-region above a substrate.. ... Globalfoundries Inc

07/19/18 / #20180204665

Integrated circuits and coupled inductors with isotropic magnetic cores, and methods for fabricating the same

Integrated circuits and coupled inductors with isotropic magnetic cores, and methods for fabricating integrated circuits and coupled inductors with isotropic magnetic cores are provided. In an embodiment, a method for fabricating an integrated circuit is provided. ... Globalfoundries Inc

07/19/18 / #20180203359

Mobile dispense device for chemicals used in micro-processing

The present disclosure relates to techniques for supplying different chemical products to process tools of a manufacturing environment used for micro-processing substrates. To this end, the various types of chemical products may be supplied by providing mobile dispense devices having incorporated therein any required hardware components for dispensing a chemical product. ... Globalfoundries Inc

07/12/18 / #20180198061

Hall element for 3-d sensing and method for producing the same

A method of forming a 3d hall effect sensor and the resulting device are provided. Embodiments include forming a p-type well in a substrate; forming a first n-type well in a first region surrounded by the p-type well in top view; forming a second n-type well in a second region surrounding the p-type well; implanting n-type dopant in the first and second n-type wells; and implanting p-type dopant in the p-type well and the first n-type well.. ... Globalfoundries Inc

07/12/18 / #20180198000

Semiconductor structure including a varactor and method for the formation thereof

A method includes providing a semiconductor structure comprising a varactor region and a field effect transistor region. The varactor region includes a body region in a semiconductor material that is doped to have a first conductivity type. ... Globalfoundries Inc

07/12/18 / #20180197980

Finfet with merge-free fins

A semiconductor device comprises an insulation layer, an active semiconductor layer formed on an upper surface of the insulation layer, and a plurality of fins formed on the insulation layer. The fins are formed in the gate and spacer regions between a first source/drain region and second source/drain region, without extending into the first and second source/drain regions.. ... Globalfoundries Inc

07/12/18 / #20180197972

Method to improve reliability of replacement gate device

A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill.. . ... Globalfoundries Inc

07/12/18 / #20180197913

Leds with three color rgb pixels for displays

Devices and methods of forming the devices are disclosed. The device includes a substrate and a color led pixel disposed on the substrate. ... Globalfoundries Inc

07/12/18 / #20180197882

Fully depleted silicon-on-insulator (fdsoi) transistor device and self-aligned active area in fdsoi bulk exposed regions

Methods for eliminating the distance between a bulex and soi and the resulting devices are disclosed. Embodiments include providing a silicon layer on a box layer on a silicon substrate; forming two active areas in the silicon layer, separated by a space; forming first and second polysilicon gates over one active area, a third polysilicon gate over the space, and fourth and fifth polysilicon gates over the other active area, the second and fourth gates abutting edges of the space; forming spacers at opposite sides of each gate; removing the second, third, and fourth gates and the corresponding spacers; removing the silicon layer and box layer in the space, forming a trench and exposing the silicon substrate; forming second spacers on sidewalls of the trench; forming raised source/drain regions on each active area; and forming a p-well contact on the silicon substrate between the second spacers.. ... Globalfoundries Inc

07/12/18 / #20180197867

Semiconductor memory devices having an undercut source/drain region

A semiconductor memory device includes, for example, a substrate having a fin having a web portion extending from the substrate and a first overhanging fin portion extending outward from the web portion and spaced from the substrate, the fin comprising a source/drain region in the web portion of the fin, a first source/drain region in the first overhanging fin portion, an isolation material surrounding the web portion and disposed under the first overhanging fin portion of the fin, an upper surface of the isolation material being below an upper surface of the fin, a first gate disposed over the fin between the source/drain region in the web portion of the fin and the first source/drain region in the first overhanging fin portion of the fin, and a capacitor operably electrically connected to the first source/drain region in the first overhanging fin portion.. . ... Globalfoundries Inc

07/12/18 / #20180197734

Buffer layer to inhibit wormholes in semiconductor fabrication

Reducing wormhole formation during n-type transistor fabrication includes providing a starting structure, the starting structure including a semiconductor substrate, a n-type source region and a n-type drain region of a transistor. The method further includes removing a portion of each of the n-type source region and the n-type drain region, the removing creating a source trench and a drain trench, and forming a buffer layer of silicon-based material(s) over the n-type source region and n-type drain region that is sufficiently thick to inhibit interaction between metal contaminants that may be present below surfaces of the n-type source trench and/or the n-type drain trench, and halogens subsequently introduced prior to source and drain formation. ... Globalfoundries Inc

07/12/18 / #20180196340

Creating knowledge base for optical proximity correction to reduce sub-resolution assist feature printing

Embodiments of the present disclosure include methods, program products, and systems for creating a knowledge base for optical proximity correction (opc). Methods according to the disclosure can include: fabricating a circuit using a proposed ic layout; identifying a plurality of features in an image of the fabricated circuit; predicting, based on the identifying and a predictive algorithm, whether the fabricated circuit includes a printed sub-resolution assist feature (sraf) from the proposed ic layout; determining the predicting as being correct when the fabricated circuit includes the printed sraf, or as being incorrect when the fabricated circuit does not include the printed sraf; in response to the predicting being incorrect: adjusting the predictive algorithm, and flagging the fabricated circuit as incorrectly predicted; in response to the predicting being correct, flagging the fabricated circuit as correctly predicted; and storing the image of the fabricated circuit in a repository of training data.. ... Globalfoundries Inc

07/05/18 / #20180191802

Nanosecond accuracy under precision time protocol for ethernet by using high accuracy timestamp assist device

In methods, systems, and devices, master and slave node timestamp synchronization units identify a node start frame delimiter of a time protocol message on transmission medium by matching patterns in the time protocol message to known start frame delimiter patterns. Master and slave node processors of such timestamp synchronization units capture a corresponding node clock time at which the node start frame delimiter is identified by referring to a corresponding node clock signal while each is identifying the node start frame delimiter. ... Globalfoundries Inc

07/05/18 / #20180190817

Method and structure to provide integrated long channel vertical finfet device

A vertical fin field effect transistor includes a semiconductor fin disposed over a well region and a gate conductor layer disposed over a sidewall of the fin, and extending laterally over a top surface of the well region adjacent to the fin. The extension of the gate conductor over the bottom source/drain effectively increases the channel length of the vertical finfet device independent of the fin height. ... Globalfoundries Inc

07/05/18 / #20180190797

Transistor structure with varied gate cross-sectional area

Aspects of the present disclosure include finfet structures with varied cross-sectional areas and methods of forming the same. Methods according to the present disclosure can include, e.g., forming a structure including: a semiconductor fin positioned on a substrate, wherein the semiconductor fin includes: a gate area, and a terminal area laterally distal to the gate area, a sacrificial gate positioned on the gate area of the semiconductor fin, and an insulator positioned on the terminal area of the semiconductor fin; removing the sacrificial gate to expose the gate area of the semiconductor fin; increasing or reducing a cross-sectional area of the gate area of the semiconductor fin; and forming a transistor gate on the gate area of the semiconductor fin.. ... Globalfoundries Inc

07/05/18 / #20180190792

Method of forming semiconductor structure and resulting structure

The disclosure is directed to a semiconductor structure and method of forming same. The method including: implanting a species within a region of a substrate adjacent to a gate stack; forming a first spacer laterally adjacent to the gate stack over the substrate; and forming an opening within the implanted region of the substrate, the opening being substantially u-shaped and self-aligned with the first spacer. ... Globalfoundries Inc

07/05/18 / #20180190787

Method and structure for protecting gates during epitaxial growth

Embodiments of the present invention provide methods and structures for protecting gates during epitaxial growth. An inner spacer of a first material is deposited adjacent a transistor gate. ... Globalfoundries Inc

07/05/18 / #20180190770

High density memory cell structures

The present disclosure relates to semiconductor structures and, more particularly, to vertical memory cell structures and methods of manufacture. The vertical memory cell includes a vertical nanowire capacitor and vertical pass gate transistor. ... Globalfoundries Inc

07/05/18 / #20180190768

Strain retention semiconductor member for channel sige layer of pfet

A pfet includes a semiconductor-on-insulator (soi) substrate; and a trench isolation within the soi substrate, the trench isolation including a raised portion extending above an upper surface of the soi substrate. A compressive channel silicon germanium (csige) layer is over the soi substrate. ... Globalfoundries Inc

07/05/18 / #20180190644

Silicon-controlled rectifiers having a cathode coupled by a contact with a diode trigger

Silicon-controlled rectifiers, electrostatic discharge circuits, and methods of fabricating a silicon-controlled rectifier for use in an electrostatic discharge circuit. A device structure for the silicon controlled rectifier includes a first well of a first conductivity type in a semiconductor layer, a second well of a second conductivity type in the semiconductor layer, a cathode coupled with the first well, and an anode coupled with the second well. ... Globalfoundries Inc

07/05/18 / #20180190588

Contacts for local connections

The present disclosure relates to semiconductor structures and, more particularly, to contacts for local connections and methods of manufacture. The structure includes: at least one contact electrically shorted to a gate structure and a source/drain contact and located below a first wiring layer; and gate, source and drain contacts extending from selected gate structures and electrically connecting to the first wiring layer.. ... Globalfoundries Inc

07/05/18 / #20180190546

Method for forming replacement metal gate and related device

A method for eliminating line voids during rmg processing and the resulting device are provided. Embodiments include forming dummy gates over pfet and nfet regions of a substrate, each dummy gate having spacers at opposite sides, and an ild filling spaces between spacers; removing dummy gate material from the gates, forming a cavity between each pair of spacers; forming a high-k dielectric layer over the ild and spacers and in the cavities; forming a metal capping layer over the high-k dielectric layer; forming a first work function metal layer over the metal capping layer; removing the first work function metal layer from the pfet region; forming a second work function metal layer over the metal capping layer in the pfet region and over the first work function metal layer in the nfet region; and forming a metal layer over the second work function metal layer, filling the cavities.. ... Globalfoundries Inc

07/05/18 / #20180190537

Methods for removal of hard mask

Embodiments of a method of processing semiconductor devices are presented. The method includes providing a substrate prepared with isolation regions having a non-planar surface topology. ... Globalfoundries Inc

07/05/18 / #20180190483

Semiconductor structure having insulator pillars and semiconductor material on substrate

One aspect of the disclosure relates to a method of forming a semiconductor structure. The method may include: forming a set of openings within a substrate; forming an insulator layer within each opening in the set of openings; recessing the substrate between adjacent openings containing the insulator layer in the set of openings to form a set of insulator pillars on the substrate; forming sigma cavities within the recessed substrate between adjacent insulator pillars in the set of insulator pillars; and filling the sigma cavities with a semiconductor material over the recessed substrate between adjacent insulator pillars.. ... Globalfoundries Inc

06/28/18 / #20180182867

Fin field effect transistor complementary metal oxide semiconductor with dual strained channels with solid phase doping

A method of forming semiconductor devices that includes forming an oxide that is doped with a punch through dopant on a surface of a first semiconductor material having a first lattice dimension, and diffusing punch through dopant from the oxide into the semiconductor material to provide a punch through stop region. The oxide may then be removed. ... Globalfoundries Inc

06/28/18 / #20180182810

Integrated two-terminal device with logic device for embedded application

Devices and methods of forming a device are disclosed. The method includes providing a substrate and a first upper dielectric layer over first and second regions of the substrate. ... Globalfoundries Inc

06/28/18 / #20180182809

Integrated circuits including magnetic random access memory structures and methods for fabricating the same

Integrated circuits and methods for fabricating integrated circuits are provided herein. In an embodiment, the integrated circuit includes a plurality of magnetic random access memory (mram) structures. ... Globalfoundries Inc

06/28/18 / #20180182778

Structure and method for fully depleted silicon on insulator structure for threshold voltage modification

A method for fabricating a fully depleted silicon on insulator (fdsoi) device is described. A charge trapping layer in a buried oxide layer is provided on a semiconductor substrate. ... Globalfoundries Inc

06/28/18 / #20180182757

Tall single-fin fin-type field effect transistor structures and methods

Disclosed are methods of forming improved fin-type field effect transistor (finfet) structures and, particularly, relatively tall single-fin finfet structures that provide increased drive current over conventional single-fin finfet structures. The use of such a tall single-fin finfet provides significant area savings over a finfet that requires multiple semiconductor fins to achieve the same amount of drive current. ... Globalfoundries Inc

06/28/18 / #20180182711

Contact using multilayer liner

An opening is formed within a substrate made of a silicon material, and a cleaning process is performed; after which, the bottom and walls of the opening are contaminated with oxygen and fluorine particles. A lower blocking layer is formed within the opening, and the lower blocking layer contacts the bottom and walls of the opening. ... Globalfoundries Inc

06/28/18 / #20180182708

Corrosion and/or etch protection layer for contacts and interconnect metallization integration

The present disclosure relates to semiconductor structures and, more particularly, to a corrosion and/or etch protection layer for contacts and interconnect metallization integration structures and methods of manufacture. The structure includes a metallization structure formed within a trench of a substrate and a layer of cobalt phosphorous (cop) on the metallization structure. ... Globalfoundries Inc

06/28/18 / #20180182677

Test structure for testing via resistance and method

Aspects of the present disclosure include a semiconductor test device and method. The test device includes a first kelvin testable structure and a second kelvin testable structure. ... Globalfoundries Inc

06/28/18 / #20180182675

Integrated circuit structure including power rail and tapping wire with method of forming same

The disclosure relates to integrated circuit (ic) structures with substantially t-shaped wires, and methods of forming the same. An ic structure according to the present disclosure can include a first substantially t-shaped wire including a first portion extending in a first direction, and a second portion extending in a second direction substantially perpendicular to the first direction; an insulator laterally abutting the first substantially t-shaped wire at an end of the first portion, opposite the second portion; and a pair of gates each extending in the first direction and laterally abutting opposing sidewalls of the insulator and the first portion of the substantially t-shaped wire.. ... Globalfoundries Inc

06/28/18 / #20180182674

Method, apparatus, and system for using a cover mask for enabling metal line jumping over mol features in a standard cell

At least one method, apparatus and system disclosed involves providing an integrated circuit having metal feature flyover over an middle-of-line (mol) feature. A first location for a non-contact intersection region between a first middle of line (mol) interconnect feature and a metal feature in a functional cell is determined. ... Globalfoundries Inc

06/28/18 / #20180182671

Crack prevent and stop for thin glass substrates

A method of forming a 3d crack-stop structure in, through, and wrapped around the edges of a substrate to prevent through-substrate cracks from propagating and breaking the substrate and the resulting device are provided. Embodiments include providing a substrate including one or more dies; forming a continuous first trench near an outer edge of the substrate; forming a continuous second trench parallel to and on an opposite side of the first trench from the outer edge; forming a continuous row of vias parallel to and on an opposite side of the second trench from the first trench, forming a continuous third trench parallel to and near an outer edge of each of the dies; forming a protective layer wrapping around the outer edge of the substrate and over and filling the trenches and vias; and patterning active areas of the substrate between the vias and the third trench.. ... Globalfoundries Inc

06/28/18 / #20180182668

Middle of the line (mol) contacts with two-dimensional self-alignment

Disclosed are methods of forming an integrated circuit (ic) structure with self-aligned middle of the line (mol) contacts and the resulting ic structure. In the methods, different, selectively etchable, dielectric materials are used above the gate level for: a dielectric cap above a gate; a dielectric spacer above a gate sidewall spacer and laterally surrounding the dielectric cap; and a stack of dielectric layer(s) that covers the dielectric cap, the dielectric spacer, and metal plugs positioned laterally adjacent to the dielectric spacer and above source/drain regions. ... Globalfoundries Inc

06/21/18 / #20180175284

Integrated circuits and methods for fabricating integrated circuits with magnetic tunnel junction (mtj) structures

Integrated circuits and methods for fabricating integrated circuits with magnetic tunnel junction (mtj) structures are provided. An exemplary method for fabricating an integrated circuit includes forming an mtj structure including a top electrode layer. ... Globalfoundries Inc

06/21/18 / #20180175266

Wafer bond interconnect structures

The present disclosure relates to semiconductor structures and, more particularly, to wafer bond interconnect structures and methods of manufacture. The structure includes: a plurality of sub-pixels each comprising a contact plate; and redundant connections at opposite corners of each sub-pixel on a backside of the contact plate.. ... Globalfoundries Inc

06/21/18 / #20180175209

Semiconductor structure including one or more nonvolatile memory cells and method for the formation thereof

A semiconductor structure includes a support substrate including a semiconductor material, a buried insulation layer positioned above the support substrate, a semiconductor layer positioned above the buried insulation layer, the semiconductor layer having an upper surface and a lower surface, the lower surface being positioned on the buried insulation layer, and at least one nonvolatile memory cell. The nonvolatile memory cell includes a channel region, a front gate structure, a doped back gate region and a charge storage material. ... Globalfoundries Inc

06/21/18 / #20180175198

Device with diffusion blocking layer in source/drain region

One illustrative device disclosed herein includes, among other things, a fin defined on a substrate. A gate electrode structure is positioned above the fin in a channel region. ... Globalfoundries Inc

06/21/18 / #20180175197

Soi finfet fins with recessed fins and epitaxy in source drain region

Fabrication method for a semiconductor device and structure are provided, which includes: providing an isolation layer at least partially disposed adjacent to at least one sidewall of a fin structure extended above a substrate structure, the fin structure including a channel region; recessing an exposed portion of the fin structure to define a residual stress to be induced into the channel region of the fin structure, wherein upper surfaces of a recessed fin portion and the isolation layer are coplanar with each other; and epitaxially growing a semiconductor material from the recessed exposed portion of the fin structure to form at least one of a source region and a drain region of the semiconductor device.. . ... Globalfoundries Inc

06/21/18 / #20180175180

Bipolar junction transistors with a combined vertical-lateral architecture

Device structures and fabrication methods for a bipolar junction transistor. The device structure includes an intrinsic base, an emitter having a vertical arrangement relative to the intrinsic base, and a collector having a lateral arrangement relative to the intrinsic base. ... Globalfoundries Inc

06/21/18 / #20180175179

Symmetrical lateral bipolar junction transistor and use of same in characterizing and protecting transistors

A symmetrical lateral bipolar junction transistor (slbjt) is provided. The slbjt includes a p-type semiconductor substrate, a n-type well, an emitter of a slbjt situated in the n-type well, a base of the slbjt situated in the n-type well and spaced from the emitter by a distance on one side of the base, a collector of the slbjt situated in the n-type well and spaced from the base by the distance on an opposite side of the base, and an electrical connection to the substrate outside the n-type well. ... Globalfoundries Inc

06/21/18 / #20180175155

Gate structure with dual width electrode layer

A high-k dielectric metal gate (hkmg) transistor includes a substrate, an hkmg gate stack with a gate dielectric layer and a gate electrode layer positioned above the substrate. The gate electrode layer has an upper portion and a lower portion. ... Globalfoundries Inc

06/21/18 / #20180175107

Light emitting diodes (leds) with integrated cmos circuits

Disclosed is a device which includes first and second major substrate surfaces. The first substrate surface includes an led with first and second terminals while the second substrate surface includes cmos circuit components. ... Globalfoundries Inc

06/21/18 / #20180175064

Wafers and device structures with body contacts

Wafers for fabrication of devices that include a body contact, device structures with a body contact, methods for forming a wafer that supports the fabrication of devices that include a body contact, and methods for forming a device structure that includes a body contact. The wafer includes a buried oxide layer and a semiconductor layer on the buried oxide layer. ... Globalfoundries Inc

06/21/18 / #20180175037

Method, apparatus, and system having super steep retrograde well with silicon and silicon germanium fins

At least one method, apparatus and system disclosed involves forming a finfet device having silicon and silicon germanium fins. The method includes: forming an n-doped and a p-doped region in a semiconductor wafer; forming a layer of silicon above both the those regions; removing a portion of the silicon layer above the p-doped region to create a first recess; forming a layer of silicon germanium in the first recess; etching away at least a portion of the silicon layer and the underlying p-doped region; etching away at least a portion of the silicon germanium layer and the underlying n-doped region; forming fins from the unetched silicon and silicon germanium layers; and forming a shallow trench isolation dielectric in the etched away portion of the silicon layer and the underlying p-doped region and in the etched away portion of the silicon germanium layer and the underlying n-doped region.. ... Globalfoundries Inc

06/21/18 / #20180175025

Vertical transistors and methods of forming same

One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include a fin having a first source/drain region and a second source/drain, the first source/drain region being over a substrate and below a central region of the fin, and the second source/drain region being within a dielectric layer and over the central region of the fin; a gate structure within the dielectric layer substantially surrounding the central region of the fin between the first source/drain region and the second source drain region, wherein the fin includes at least one tapered region from the central region of the fin to at least one of the first source/drain region or the second source/drain region.. ... Globalfoundries Inc

06/21/18 / #20180174982

Integrated circuit structure with continuous metal crack stop

An integrated circuit (ic) structure is disclosed. The structure can include: an insulator positioned over a device layer; a capping layer positioned over the insulator; an inter-layer dielectric (ild) positioned over the capping layer; a first metal wire positioned over the ild, and outside an active area of the ic structure; a continuous metal crack stop in contact with, and interposed between, the first metal wire and the device layer, such that the continuous metal crack stop extends through at least the insulator, the capping layer, and the ild; a second metal wire positioned over the ild, and within the active area of the ic structure; and two vias vertically coupled to each other and interposed between the second metal wire and the device layer, such that the two vias extend through at least the insulator, the capping layer, and the ild.. ... Globalfoundries Inc

06/21/18 / #20180174965

Devices and methods of cobalt fill metallization

Devices and methods of fabricating integrated circuit devices via cobalt fill metallization are provided. A method includes, for instance, providing an intermediate semiconductor device having at least one trench, forming at least one layer of semiconductor material on the device, depositing a first cobalt (co) layer on the second layer, and performing an anneal reflow process on the device. ... Globalfoundries Inc

06/21/18 / #20180174948

Integrated circuit chip with molding compound handler substrate and method

Disclosed are integrated circuit (ic) chip structures (e.g., radio frequency (rf) ic chip structures) and methods of forming the structures with an electrically insulative molding compound handler substrate. Each structure includes at least: an electrically insulative molding compound handler substrate; an insulator layer on the handler substrate; and one or more semiconductor devices (e.g., rf semiconductor devices) on the insulator layer. ... Globalfoundries Inc

06/21/18 / #20180174896

Interconnection lines having variable widths and partially self-aligned continuity cuts

A semiconductor cell includes a dielectric layer. An array of parallel metal lines is disposed in a longitudinal direction within the dielectric layer. ... Globalfoundries Inc

06/21/18 / #20180174895

Interconnection cells having variable width metal lines and fully-self aligned variable length continuity cuts

A method includes providing a semiconductor structure having a mandrel layer and a hardmask layer disposed above a dielectric layer. A mandrel cell is patterned into the mandrel layer. ... Globalfoundries Inc

06/21/18 / #20180174894

Apparatus and method for forming interconnection lines having variable pitch and variable widths

A semiconductor cell includes a dielectric layer. An array of at least four parallel metal lines is disposed within the dielectric layer, the metal lines having line widths that are substantially equal to or greater than a predetermined minimum line width. ... Globalfoundries Inc

06/21/18 / #20180174855

Method for fin formation with a self-aligned directed self-assembly process and cut-last scheme

A method of making a semiconductor device includes disposing a first hard mask (hm), amorphous silicon, and second hm on a substrate; disposing oxide and neutral layers on the second hm; removing a portion of the oxide and neutral layers to expose a portion of the second hm; forming a guiding pattern by selectively backfilling with a polymer; forming a self-assembled block copolymer (bcp) on the guiding pattern; removing a portion of the bcp to form an etch template; transferring the pattern from said template into the substrate and forming uniform silicon fin arrays with two types of hm stacks with different materials and heights; gap-filling with oxide followed by planarization; selectively removing and replacing the taller hm stack with a third hm material; planarizing the surface and exposing both hm stacks; and selectively removing the shorter hm stack and the silicon fins underneath.. . ... Globalfoundries Inc

06/21/18 / #20180174646

Integrated circuits with sram devices having read assist circuits and methods for operating such circuits

Integrated circuits including semiconductor memory devices, read assist circuits for semiconductor memory devices, and methods for operating such circuits are provided. In an embodiment, a read assist circuit for use in a semiconductor memory device is provided. ... Globalfoundries Inc

06/21/18 / #20180172609

Method and system for non-destructive metrology of thin layers

A monitoring system and method are provided for determining at least one property of an integrated circuit (ic) comprising a multi-layer structure formed by at least a layer on top of an underlayer. The monitoring system receives measured data comprising data indicative of optical measurements performed on the ic, data indicative of x-ray photoelectron spectroscopy (xps) measurements performed on the ic and data indicative of x-ray fluorescence spectroscopy (xrf) measurements performed on the ic. ... Globalfoundries Inc

06/21/18 / #20180170748

Semiconductor devices with cavities and methods for fabricating semiconductor devices with cavities

Semiconductor devices with enclosed cavities and methods for fabricating semiconductor devices with enclosed cavities are provided. In an embodiment, a method for fabricating a semiconductor device with a cavity includes providing a substrate terminating at an uppermost surface and forming a sacrificial structure over the uppermost substrate of the substrate. ... Globalfoundries Inc

06/14/18 / #20180167038

Fully depleted silicon on insulator power amplifier

The present disclosure generally relates to semiconductor structures and, more particularly, to a fully depleted silicon on insulator power amplifier with unique biases and voltage standing wave ratio protection and methods of manufacture. The structure includes a pseudo-differential common source amplifier; first stage cascode devices connected to the pseudo-differential common source amplifier and protecting the pseudo-differential common source amplifier from an over stress; second stage cascode devices connected to the first stage cascode devices and providing differential outputs; and at least one loop receiving the differential outputs from the second stage cascode devices and feeding back the differential outputs to the second stage cascode devices.. ... Globalfoundries Inc

06/14/18 / #20180166566

Poly gate extension source to body contact

The present disclosure relates to semiconductor structures and, more particularly, to poly gate extension source to body contact structures and methods of manufacture. The structure includes: a substrate having a doped region; a gate structure over the doped region, the gate structure having a main body and a gate extension region; and a body contact region straddling over the gate extension region and remote from the main body of the gate structure.. ... Globalfoundries Inc

06/14/18 / #20180166536

Active and passive components with deep trench isolation structures

The present disclosure relates to semiconductor structures and, more particularly, to active and passive radio frequency (rf) components with deep trench isolation structures and methods of manufacture. The structure includes a bulk high resistivity wafer with a deep trench isolation structure having a depth deeper than a maximum depletion depth at worst case voltage bias difference between devices which are formed on the bulk high resistivity wafer.. ... Globalfoundries Inc








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