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Globalfoundries Inc patents


Recent patent applications related to Globalfoundries Inc. Globalfoundries Inc is listed as an Agent/Assignee. Note: Globalfoundries Inc may have other listings under different names/spellings. We're not affiliated with Globalfoundries Inc, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "G" | Globalfoundries Inc-related inventors


Hall element for 3-d sensing and method for producing the same

A method of forming a 3d hall effect sensor and the resulting device are provided. Embodiments include forming a p-type well in a substrate; forming a first n-type well in a first region surrounded by the p-type well in top view; forming a second n-type well in a second region surrounding the p-type well; implanting n-type dopant in the first and second n-type wells; and implanting p-type dopant in the p-type well and the first n-type well.. ... Globalfoundries Inc

Semiconductor structure including a varactor and method for the formation thereof

A method includes providing a semiconductor structure comprising a varactor region and a field effect transistor region. The varactor region includes a body region in a semiconductor material that is doped to have a first conductivity type. ... Globalfoundries Inc

Finfet with merge-free fins

A semiconductor device comprises an insulation layer, an active semiconductor layer formed on an upper surface of the insulation layer, and a plurality of fins formed on the insulation layer. The fins are formed in the gate and spacer regions between a first source/drain region and second source/drain region, without extending into the first and second source/drain regions.. ... Globalfoundries Inc

Method to improve reliability of replacement gate device

A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill.. . ... Globalfoundries Inc

Leds with three color rgb pixels for displays

Devices and methods of forming the devices are disclosed. The device includes a substrate and a color led pixel disposed on the substrate. ... Globalfoundries Inc

Fully depleted silicon-on-insulator (fdsoi) transistor device and self-aligned active area in fdsoi bulk exposed regions

Methods for eliminating the distance between a bulex and soi and the resulting devices are disclosed. Embodiments include providing a silicon layer on a box layer on a silicon substrate; forming two active areas in the silicon layer, separated by a space; forming first and second polysilicon gates over one active area, a third polysilicon gate over the space, and fourth and fifth polysilicon gates over the other active area, the second and fourth gates abutting edges of the space; forming spacers at opposite sides of each gate; removing the second, third, and fourth gates and the corresponding spacers; removing the silicon layer and box layer in the space, forming a trench and exposing the silicon substrate; forming second spacers on sidewalls of the trench; forming raised source/drain regions on each active area; and forming a p-well contact on the silicon substrate between the second spacers.. ... Globalfoundries Inc

Semiconductor memory devices having an undercut source/drain region

A semiconductor memory device includes, for example, a substrate having a fin having a web portion extending from the substrate and a first overhanging fin portion extending outward from the web portion and spaced from the substrate, the fin comprising a source/drain region in the web portion of the fin, a first source/drain region in the first overhanging fin portion, an isolation material surrounding the web portion and disposed under the first overhanging fin portion of the fin, an upper surface of the isolation material being below an upper surface of the fin, a first gate disposed over the fin between the source/drain region in the web portion of the fin and the first source/drain region in the first overhanging fin portion of the fin, and a capacitor operably electrically connected to the first source/drain region in the first overhanging fin portion.. . ... Globalfoundries Inc

Buffer layer to inhibit wormholes in semiconductor fabrication

Reducing wormhole formation during n-type transistor fabrication includes providing a starting structure, the starting structure including a semiconductor substrate, a n-type source region and a n-type drain region of a transistor. The method further includes removing a portion of each of the n-type source region and the n-type drain region, the removing creating a source trench and a drain trench, and forming a buffer layer of silicon-based material(s) over the n-type source region and n-type drain region that is sufficiently thick to inhibit interaction between metal contaminants that may be present below surfaces of the n-type source trench and/or the n-type drain trench, and halogens subsequently introduced prior to source and drain formation. ... Globalfoundries Inc

Creating knowledge base for optical proximity correction to reduce sub-resolution assist feature printing

Embodiments of the present disclosure include methods, program products, and systems for creating a knowledge base for optical proximity correction (opc). Methods according to the disclosure can include: fabricating a circuit using a proposed ic layout; identifying a plurality of features in an image of the fabricated circuit; predicting, based on the identifying and a predictive algorithm, whether the fabricated circuit includes a printed sub-resolution assist feature (sraf) from the proposed ic layout; determining the predicting as being correct when the fabricated circuit includes the printed sraf, or as being incorrect when the fabricated circuit does not include the printed sraf; in response to the predicting being incorrect: adjusting the predictive algorithm, and flagging the fabricated circuit as incorrectly predicted; in response to the predicting being correct, flagging the fabricated circuit as correctly predicted; and storing the image of the fabricated circuit in a repository of training data.. ... Globalfoundries Inc

Nanosecond accuracy under precision time protocol for ethernet by using high accuracy timestamp assist device

In methods, systems, and devices, master and slave node timestamp synchronization units identify a node start frame delimiter of a time protocol message on transmission medium by matching patterns in the time protocol message to known start frame delimiter patterns. Master and slave node processors of such timestamp synchronization units capture a corresponding node clock time at which the node start frame delimiter is identified by referring to a corresponding node clock signal while each is identifying the node start frame delimiter. ... Globalfoundries Inc

Method and structure to provide integrated long channel vertical finfet device

A vertical fin field effect transistor includes a semiconductor fin disposed over a well region and a gate conductor layer disposed over a sidewall of the fin, and extending laterally over a top surface of the well region adjacent to the fin. The extension of the gate conductor over the bottom source/drain effectively increases the channel length of the vertical finfet device independent of the fin height. ... Globalfoundries Inc

Transistor structure with varied gate cross-sectional area

Aspects of the present disclosure include finfet structures with varied cross-sectional areas and methods of forming the same. Methods according to the present disclosure can include, e.g., forming a structure including: a semiconductor fin positioned on a substrate, wherein the semiconductor fin includes: a gate area, and a terminal area laterally distal to the gate area, a sacrificial gate positioned on the gate area of the semiconductor fin, and an insulator positioned on the terminal area of the semiconductor fin; removing the sacrificial gate to expose the gate area of the semiconductor fin; increasing or reducing a cross-sectional area of the gate area of the semiconductor fin; and forming a transistor gate on the gate area of the semiconductor fin.. ... Globalfoundries Inc

Method of forming semiconductor structure and resulting structure

The disclosure is directed to a semiconductor structure and method of forming same. The method including: implanting a species within a region of a substrate adjacent to a gate stack; forming a first spacer laterally adjacent to the gate stack over the substrate; and forming an opening within the implanted region of the substrate, the opening being substantially u-shaped and self-aligned with the first spacer. ... Globalfoundries Inc

Method and structure for protecting gates during epitaxial growth

Embodiments of the present invention provide methods and structures for protecting gates during epitaxial growth. An inner spacer of a first material is deposited adjacent a transistor gate. ... Globalfoundries Inc

07/05/18 / #20180190770

High density memory cell structures

The present disclosure relates to semiconductor structures and, more particularly, to vertical memory cell structures and methods of manufacture. The vertical memory cell includes a vertical nanowire capacitor and vertical pass gate transistor. ... Globalfoundries Inc

07/05/18 / #20180190768

Strain retention semiconductor member for channel sige layer of pfet

A pfet includes a semiconductor-on-insulator (soi) substrate; and a trench isolation within the soi substrate, the trench isolation including a raised portion extending above an upper surface of the soi substrate. A compressive channel silicon germanium (csige) layer is over the soi substrate. ... Globalfoundries Inc

07/05/18 / #20180190644

Silicon-controlled rectifiers having a cathode coupled by a contact with a diode trigger

Silicon-controlled rectifiers, electrostatic discharge circuits, and methods of fabricating a silicon-controlled rectifier for use in an electrostatic discharge circuit. A device structure for the silicon controlled rectifier includes a first well of a first conductivity type in a semiconductor layer, a second well of a second conductivity type in the semiconductor layer, a cathode coupled with the first well, and an anode coupled with the second well. ... Globalfoundries Inc

07/05/18 / #20180190588

Contacts for local connections

The present disclosure relates to semiconductor structures and, more particularly, to contacts for local connections and methods of manufacture. The structure includes: at least one contact electrically shorted to a gate structure and a source/drain contact and located below a first wiring layer; and gate, source and drain contacts extending from selected gate structures and electrically connecting to the first wiring layer.. ... Globalfoundries Inc

07/05/18 / #20180190546

Method for forming replacement metal gate and related device

A method for eliminating line voids during rmg processing and the resulting device are provided. Embodiments include forming dummy gates over pfet and nfet regions of a substrate, each dummy gate having spacers at opposite sides, and an ild filling spaces between spacers; removing dummy gate material from the gates, forming a cavity between each pair of spacers; forming a high-k dielectric layer over the ild and spacers and in the cavities; forming a metal capping layer over the high-k dielectric layer; forming a first work function metal layer over the metal capping layer; removing the first work function metal layer from the pfet region; forming a second work function metal layer over the metal capping layer in the pfet region and over the first work function metal layer in the nfet region; and forming a metal layer over the second work function metal layer, filling the cavities.. ... Globalfoundries Inc

07/05/18 / #20180190537

Methods for removal of hard mask

Embodiments of a method of processing semiconductor devices are presented. The method includes providing a substrate prepared with isolation regions having a non-planar surface topology. ... Globalfoundries Inc

07/05/18 / #20180190483

Semiconductor structure having insulator pillars and semiconductor material on substrate

One aspect of the disclosure relates to a method of forming a semiconductor structure. The method may include: forming a set of openings within a substrate; forming an insulator layer within each opening in the set of openings; recessing the substrate between adjacent openings containing the insulator layer in the set of openings to form a set of insulator pillars on the substrate; forming sigma cavities within the recessed substrate between adjacent insulator pillars in the set of insulator pillars; and filling the sigma cavities with a semiconductor material over the recessed substrate between adjacent insulator pillars.. ... Globalfoundries Inc

06/28/18 / #20180182867

Fin field effect transistor complementary metal oxide semiconductor with dual strained channels with solid phase doping

A method of forming semiconductor devices that includes forming an oxide that is doped with a punch through dopant on a surface of a first semiconductor material having a first lattice dimension, and diffusing punch through dopant from the oxide into the semiconductor material to provide a punch through stop region. The oxide may then be removed. ... Globalfoundries Inc

06/28/18 / #20180182810

Integrated two-terminal device with logic device for embedded application

Devices and methods of forming a device are disclosed. The method includes providing a substrate and a first upper dielectric layer over first and second regions of the substrate. ... Globalfoundries Inc

06/28/18 / #20180182809

Integrated circuits including magnetic random access memory structures and methods for fabricating the same

Integrated circuits and methods for fabricating integrated circuits are provided herein. In an embodiment, the integrated circuit includes a plurality of magnetic random access memory (mram) structures. ... Globalfoundries Inc

06/28/18 / #20180182778

Structure and method for fully depleted silicon on insulator structure for threshold voltage modification

A method for fabricating a fully depleted silicon on insulator (fdsoi) device is described. A charge trapping layer in a buried oxide layer is provided on a semiconductor substrate. ... Globalfoundries Inc

06/28/18 / #20180182757

Tall single-fin fin-type field effect transistor structures and methods

Disclosed are methods of forming improved fin-type field effect transistor (finfet) structures and, particularly, relatively tall single-fin finfet structures that provide increased drive current over conventional single-fin finfet structures. The use of such a tall single-fin finfet provides significant area savings over a finfet that requires multiple semiconductor fins to achieve the same amount of drive current. ... Globalfoundries Inc

06/28/18 / #20180182711

Contact using multilayer liner

An opening is formed within a substrate made of a silicon material, and a cleaning process is performed; after which, the bottom and walls of the opening are contaminated with oxygen and fluorine particles. A lower blocking layer is formed within the opening, and the lower blocking layer contacts the bottom and walls of the opening. ... Globalfoundries Inc

06/28/18 / #20180182708

Corrosion and/or etch protection layer for contacts and interconnect metallization integration

The present disclosure relates to semiconductor structures and, more particularly, to a corrosion and/or etch protection layer for contacts and interconnect metallization integration structures and methods of manufacture. The structure includes a metallization structure formed within a trench of a substrate and a layer of cobalt phosphorous (cop) on the metallization structure. ... Globalfoundries Inc

06/28/18 / #20180182677

Test structure for testing via resistance and method

Aspects of the present disclosure include a semiconductor test device and method. The test device includes a first kelvin testable structure and a second kelvin testable structure. ... Globalfoundries Inc

06/28/18 / #20180182675

Integrated circuit structure including power rail and tapping wire with method of forming same

The disclosure relates to integrated circuit (ic) structures with substantially t-shaped wires, and methods of forming the same. An ic structure according to the present disclosure can include a first substantially t-shaped wire including a first portion extending in a first direction, and a second portion extending in a second direction substantially perpendicular to the first direction; an insulator laterally abutting the first substantially t-shaped wire at an end of the first portion, opposite the second portion; and a pair of gates each extending in the first direction and laterally abutting opposing sidewalls of the insulator and the first portion of the substantially t-shaped wire.. ... Globalfoundries Inc

06/28/18 / #20180182674

Method, apparatus, and system for using a cover mask for enabling metal line jumping over mol features in a standard cell

At least one method, apparatus and system disclosed involves providing an integrated circuit having metal feature flyover over an middle-of-line (mol) feature. A first location for a non-contact intersection region between a first middle of line (mol) interconnect feature and a metal feature in a functional cell is determined. ... Globalfoundries Inc

06/28/18 / #20180182671

Crack prevent and stop for thin glass substrates

A method of forming a 3d crack-stop structure in, through, and wrapped around the edges of a substrate to prevent through-substrate cracks from propagating and breaking the substrate and the resulting device are provided. Embodiments include providing a substrate including one or more dies; forming a continuous first trench near an outer edge of the substrate; forming a continuous second trench parallel to and on an opposite side of the first trench from the outer edge; forming a continuous row of vias parallel to and on an opposite side of the second trench from the first trench, forming a continuous third trench parallel to and near an outer edge of each of the dies; forming a protective layer wrapping around the outer edge of the substrate and over and filling the trenches and vias; and patterning active areas of the substrate between the vias and the third trench.. ... Globalfoundries Inc

06/28/18 / #20180182668

Middle of the line (mol) contacts with two-dimensional self-alignment

Disclosed are methods of forming an integrated circuit (ic) structure with self-aligned middle of the line (mol) contacts and the resulting ic structure. In the methods, different, selectively etchable, dielectric materials are used above the gate level for: a dielectric cap above a gate; a dielectric spacer above a gate sidewall spacer and laterally surrounding the dielectric cap; and a stack of dielectric layer(s) that covers the dielectric cap, the dielectric spacer, and metal plugs positioned laterally adjacent to the dielectric spacer and above source/drain regions. ... Globalfoundries Inc

06/21/18 / #20180175284

Integrated circuits and methods for fabricating integrated circuits with magnetic tunnel junction (mtj) structures

Integrated circuits and methods for fabricating integrated circuits with magnetic tunnel junction (mtj) structures are provided. An exemplary method for fabricating an integrated circuit includes forming an mtj structure including a top electrode layer. ... Globalfoundries Inc

06/21/18 / #20180175266

Wafer bond interconnect structures

The present disclosure relates to semiconductor structures and, more particularly, to wafer bond interconnect structures and methods of manufacture. The structure includes: a plurality of sub-pixels each comprising a contact plate; and redundant connections at opposite corners of each sub-pixel on a backside of the contact plate.. ... Globalfoundries Inc

06/21/18 / #20180175209

Semiconductor structure including one or more nonvolatile memory cells and method for the formation thereof

A semiconductor structure includes a support substrate including a semiconductor material, a buried insulation layer positioned above the support substrate, a semiconductor layer positioned above the buried insulation layer, the semiconductor layer having an upper surface and a lower surface, the lower surface being positioned on the buried insulation layer, and at least one nonvolatile memory cell. The nonvolatile memory cell includes a channel region, a front gate structure, a doped back gate region and a charge storage material. ... Globalfoundries Inc

06/21/18 / #20180175198

Device with diffusion blocking layer in source/drain region

One illustrative device disclosed herein includes, among other things, a fin defined on a substrate. A gate electrode structure is positioned above the fin in a channel region. ... Globalfoundries Inc

06/21/18 / #20180175197

Soi finfet fins with recessed fins and epitaxy in source drain region

Fabrication method for a semiconductor device and structure are provided, which includes: providing an isolation layer at least partially disposed adjacent to at least one sidewall of a fin structure extended above a substrate structure, the fin structure including a channel region; recessing an exposed portion of the fin structure to define a residual stress to be induced into the channel region of the fin structure, wherein upper surfaces of a recessed fin portion and the isolation layer are coplanar with each other; and epitaxially growing a semiconductor material from the recessed exposed portion of the fin structure to form at least one of a source region and a drain region of the semiconductor device.. . ... Globalfoundries Inc

06/21/18 / #20180175180

Bipolar junction transistors with a combined vertical-lateral architecture

Device structures and fabrication methods for a bipolar junction transistor. The device structure includes an intrinsic base, an emitter having a vertical arrangement relative to the intrinsic base, and a collector having a lateral arrangement relative to the intrinsic base. ... Globalfoundries Inc

06/21/18 / #20180175179

Symmetrical lateral bipolar junction transistor and use of same in characterizing and protecting transistors

A symmetrical lateral bipolar junction transistor (slbjt) is provided. The slbjt includes a p-type semiconductor substrate, a n-type well, an emitter of a slbjt situated in the n-type well, a base of the slbjt situated in the n-type well and spaced from the emitter by a distance on one side of the base, a collector of the slbjt situated in the n-type well and spaced from the base by the distance on an opposite side of the base, and an electrical connection to the substrate outside the n-type well. ... Globalfoundries Inc

06/21/18 / #20180175155

Gate structure with dual width electrode layer

A high-k dielectric metal gate (hkmg) transistor includes a substrate, an hkmg gate stack with a gate dielectric layer and a gate electrode layer positioned above the substrate. The gate electrode layer has an upper portion and a lower portion. ... Globalfoundries Inc

06/21/18 / #20180175107

Light emitting diodes (leds) with integrated cmos circuits

Disclosed is a device which includes first and second major substrate surfaces. The first substrate surface includes an led with first and second terminals while the second substrate surface includes cmos circuit components. ... Globalfoundries Inc

06/21/18 / #20180175064

Wafers and device structures with body contacts

Wafers for fabrication of devices that include a body contact, device structures with a body contact, methods for forming a wafer that supports the fabrication of devices that include a body contact, and methods for forming a device structure that includes a body contact. The wafer includes a buried oxide layer and a semiconductor layer on the buried oxide layer. ... Globalfoundries Inc

06/21/18 / #20180175037

Method, apparatus, and system having super steep retrograde well with silicon and silicon germanium fins

At least one method, apparatus and system disclosed involves forming a finfet device having silicon and silicon germanium fins. The method includes: forming an n-doped and a p-doped region in a semiconductor wafer; forming a layer of silicon above both the those regions; removing a portion of the silicon layer above the p-doped region to create a first recess; forming a layer of silicon germanium in the first recess; etching away at least a portion of the silicon layer and the underlying p-doped region; etching away at least a portion of the silicon germanium layer and the underlying n-doped region; forming fins from the unetched silicon and silicon germanium layers; and forming a shallow trench isolation dielectric in the etched away portion of the silicon layer and the underlying p-doped region and in the etched away portion of the silicon germanium layer and the underlying n-doped region.. ... Globalfoundries Inc

06/21/18 / #20180175025

Vertical transistors and methods of forming same

One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include a fin having a first source/drain region and a second source/drain, the first source/drain region being over a substrate and below a central region of the fin, and the second source/drain region being within a dielectric layer and over the central region of the fin; a gate structure within the dielectric layer substantially surrounding the central region of the fin between the first source/drain region and the second source drain region, wherein the fin includes at least one tapered region from the central region of the fin to at least one of the first source/drain region or the second source/drain region.. ... Globalfoundries Inc

06/21/18 / #20180174982

Integrated circuit structure with continuous metal crack stop

An integrated circuit (ic) structure is disclosed. The structure can include: an insulator positioned over a device layer; a capping layer positioned over the insulator; an inter-layer dielectric (ild) positioned over the capping layer; a first metal wire positioned over the ild, and outside an active area of the ic structure; a continuous metal crack stop in contact with, and interposed between, the first metal wire and the device layer, such that the continuous metal crack stop extends through at least the insulator, the capping layer, and the ild; a second metal wire positioned over the ild, and within the active area of the ic structure; and two vias vertically coupled to each other and interposed between the second metal wire and the device layer, such that the two vias extend through at least the insulator, the capping layer, and the ild.. ... Globalfoundries Inc

06/21/18 / #20180174965

Devices and methods of cobalt fill metallization

Devices and methods of fabricating integrated circuit devices via cobalt fill metallization are provided. A method includes, for instance, providing an intermediate semiconductor device having at least one trench, forming at least one layer of semiconductor material on the device, depositing a first cobalt (co) layer on the second layer, and performing an anneal reflow process on the device. ... Globalfoundries Inc

06/21/18 / #20180174948

Integrated circuit chip with molding compound handler substrate and method

Disclosed are integrated circuit (ic) chip structures (e.g., radio frequency (rf) ic chip structures) and methods of forming the structures with an electrically insulative molding compound handler substrate. Each structure includes at least: an electrically insulative molding compound handler substrate; an insulator layer on the handler substrate; and one or more semiconductor devices (e.g., rf semiconductor devices) on the insulator layer. ... Globalfoundries Inc

06/21/18 / #20180174896

Interconnection lines having variable widths and partially self-aligned continuity cuts

A semiconductor cell includes a dielectric layer. An array of parallel metal lines is disposed in a longitudinal direction within the dielectric layer. ... Globalfoundries Inc

06/21/18 / #20180174895

Interconnection cells having variable width metal lines and fully-self aligned variable length continuity cuts

A method includes providing a semiconductor structure having a mandrel layer and a hardmask layer disposed above a dielectric layer. A mandrel cell is patterned into the mandrel layer. ... Globalfoundries Inc

06/21/18 / #20180174894

Apparatus and method for forming interconnection lines having variable pitch and variable widths

A semiconductor cell includes a dielectric layer. An array of at least four parallel metal lines is disposed within the dielectric layer, the metal lines having line widths that are substantially equal to or greater than a predetermined minimum line width. ... Globalfoundries Inc

06/21/18 / #20180174855

Method for fin formation with a self-aligned directed self-assembly process and cut-last scheme

A method of making a semiconductor device includes disposing a first hard mask (hm), amorphous silicon, and second hm on a substrate; disposing oxide and neutral layers on the second hm; removing a portion of the oxide and neutral layers to expose a portion of the second hm; forming a guiding pattern by selectively backfilling with a polymer; forming a self-assembled block copolymer (bcp) on the guiding pattern; removing a portion of the bcp to form an etch template; transferring the pattern from said template into the substrate and forming uniform silicon fin arrays with two types of hm stacks with different materials and heights; gap-filling with oxide followed by planarization; selectively removing and replacing the taller hm stack with a third hm material; planarizing the surface and exposing both hm stacks; and selectively removing the shorter hm stack and the silicon fins underneath.. . ... Globalfoundries Inc

06/21/18 / #20180174646

Integrated circuits with sram devices having read assist circuits and methods for operating such circuits

Integrated circuits including semiconductor memory devices, read assist circuits for semiconductor memory devices, and methods for operating such circuits are provided. In an embodiment, a read assist circuit for use in a semiconductor memory device is provided. ... Globalfoundries Inc

06/21/18 / #20180172609

Method and system for non-destructive metrology of thin layers

A monitoring system and method are provided for determining at least one property of an integrated circuit (ic) comprising a multi-layer structure formed by at least a layer on top of an underlayer. The monitoring system receives measured data comprising data indicative of optical measurements performed on the ic, data indicative of x-ray photoelectron spectroscopy (xps) measurements performed on the ic and data indicative of x-ray fluorescence spectroscopy (xrf) measurements performed on the ic. ... Globalfoundries Inc

06/21/18 / #20180170748

Semiconductor devices with cavities and methods for fabricating semiconductor devices with cavities

Semiconductor devices with enclosed cavities and methods for fabricating semiconductor devices with enclosed cavities are provided. In an embodiment, a method for fabricating a semiconductor device with a cavity includes providing a substrate terminating at an uppermost surface and forming a sacrificial structure over the uppermost substrate of the substrate. ... Globalfoundries Inc

06/14/18 / #20180167038

Fully depleted silicon on insulator power amplifier

The present disclosure generally relates to semiconductor structures and, more particularly, to a fully depleted silicon on insulator power amplifier with unique biases and voltage standing wave ratio protection and methods of manufacture. The structure includes a pseudo-differential common source amplifier; first stage cascode devices connected to the pseudo-differential common source amplifier and protecting the pseudo-differential common source amplifier from an over stress; second stage cascode devices connected to the first stage cascode devices and providing differential outputs; and at least one loop receiving the differential outputs from the second stage cascode devices and feeding back the differential outputs to the second stage cascode devices.. ... Globalfoundries Inc

06/14/18 / #20180166566

Poly gate extension source to body contact

The present disclosure relates to semiconductor structures and, more particularly, to poly gate extension source to body contact structures and methods of manufacture. The structure includes: a substrate having a doped region; a gate structure over the doped region, the gate structure having a main body and a gate extension region; and a body contact region straddling over the gate extension region and remote from the main body of the gate structure.. ... Globalfoundries Inc

06/14/18 / #20180166536

Active and passive components with deep trench isolation structures

The present disclosure relates to semiconductor structures and, more particularly, to active and passive radio frequency (rf) components with deep trench isolation structures and methods of manufacture. The structure includes a bulk high resistivity wafer with a deep trench isolation structure having a depth deeper than a maximum depletion depth at worst case voltage bias difference between devices which are formed on the bulk high resistivity wafer.. ... Globalfoundries Inc

06/14/18 / #20180166438

Integrated circuits with high current capacity and methods for producing the same

Integrated circuits and methods of producing integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a source and a drain defined within a body isolation well. ... Globalfoundries Inc

06/14/18 / #20180166402

Integrated efuse

A semiconductor device includes a metal thin film such as an efuse or a precision resistor above and laterally displaced from an interconnect structure. A first dielectric layer is disposed over the interconnect structure and optionally under the metal thin film, and is adapted to prevent etching of the interconnect structure during patterning of the metal thin film. ... Globalfoundries Inc

06/14/18 / #20180166385

Interconnect structure and method of forming the same

Aspects of the present disclosure include a method for forming a contact on a semiconductor device, the semiconductor device including a conductive region disposed over a substrate, the method comprising: depositing a dielectric material on the substrate; forming an opening in the dielectric material to expose the conductive region; forming a barrier layer on a lower surface and sidewalls of the opening in the dielectric material, the barrier layer terminating below an upper surface of the dielectric material and surrounding a lower portion of the opening; depositing cobalt in the lower portion of the opening, the cobalt terminating at an upper surface of the barrier layer; depositing tungsten to fill the opening to at least the upper surface of the dielectric material; and planarizing the upper surface of the dielectric material with the tungsten in the opening.. . ... Globalfoundries Inc

06/14/18 / #20180166383

Airgaps to isolate metallization features

The present disclosure relates to semiconductor structures and, more particularly, to airgaps which isolate metal lines and methods of manufacture. The structure includes: a plurality of metal lines formed on an insulator layer; and a dielectric material completely filling a space having a first dimension between metal lines of the plurality of metal lines and providing a uniform airgap with a space having a second dimension between metal lines of the plurality of metal lines. ... Globalfoundries Inc

06/14/18 / #20180166381

Through-silicon via with improved substrate contact for reduced through-silicon via (tsv) capacitance variability

The present disclosure relates to semiconductor structures and, more particularly, to through-silicon via (tsv) structures with improved substrate contact and methods of manufacture. The structure includes: a substrate of a first species type; a layer of different species type on the substrate; a through substrate via formed through the substrate and comprising an insulator sidewall and conductive fill material; a second species type adjacent the through substrate via; a first contact in electrical contact with the layer of different species type; and a second contact in electrical contact with the conductive fill material of the through substrate via.. ... Globalfoundries Inc

06/14/18 / #20180166356

Fan-out circuit packaging with integrated lid

Various embodiments include integrated circuit (ic) package structures. In some cases, an ic package includes: a carrier having a recess; a plurality of ic chips coupled with the carrier inside the recess, the plurality of ic chips each including a plurality of connectors; a thermally conductive material between the plurality of ic chips and the carrier within the recess, the thermally conductive material coupling the plurality of ic chips with the carrier; a dielectric layer contacting the plurality of ic chips and the carrier; a redistribution layer (rdl) contacting the dielectric layer and the plurality of connectors, the rdl including a plurality of fan-out vias extending from the plurality of connectors and at least one connector coupling adjacent ic chips in the plurality of ic chips; and a set of solder balls contacting the rdl and connected with the plurality of fan-out vias.. ... Globalfoundries Inc

06/14/18 / #20180166335

Self-aligned middle of the line (mol) contacts

Disclosed are methods and integrated circuit (ic) structures. The methods enable formation of a gate contact on a gate above (or close thereto) an active region of a field effect transistor (fet) and provide protection against shorts between the gate contact and metal plugs on source/drain regions and between the gate and source/drain contacts to the metal plugs. ... Globalfoundries Inc

06/14/18 / #20180166319

Air-gap spacers for field-effect transistors

Structures for air-gap spacers in a field-effect transistor and methods for forming air-gap spacers in a field-effect transistor. A gate structure is formed on a top surface of a semiconductor body. ... Globalfoundries Inc

06/14/18 / #20180165402

Forming multi-sized through-silicon-via (tsv) structures

Various embodiments include approaches for designing through-silicon vias (tsvs) in integrated circuits (ics). In some cases, a method includes: identifying types of through-silicon vias (tsvs) for placement within an integrated circuit (ic) design based upon an electrical requirement for the tsvs, wherein the ic design includes distinct types of tsvs; calculating etch and fill rates for the ic design with the distinct types of tsvs with common etching and filling processes; and providing fabrication instructions to form the distinct types of tsvs according to the calculated etch and fill rates in the common processes.. ... Globalfoundries Inc

06/14/18 / #20180164674

Photomask blank including a thin chromium hardmask

Methods for manufacturing a photomask, photomask blanks, and photomasks used in chip fabrication. A phase-shift layer is formed on a mask blank, a hardmask layer is formed on the phase-shift layer, and a layer stack is formed on the hardmask layer to make a photomask blank. ... Globalfoundries Inc

06/14/18 / #20180164508

Photonics chip

The present disclosure relates to semiconductor structures and, more particularly, to photonics chips and methods of manufacture. A structure includes: a photonics chip having a grated optical coupler; an interposer attached to the photonics chip, the interposer having a grated optical coupler; an optical epoxy material provided between the grated optical coupler of the photonics chip and the grated optical coupler of the interposer; and epoxy underfill material provided at interstitial regions between the photonics chip and the interposer which lie outside of an area of the grated optical couplers of the photonics chip and the interposer.. ... Globalfoundries Inc

06/07/18 / #20180159471

Digitally controlled varactor structure for high resolution dco

A digitally controlled varactor device comprising: a set of bulk nmos field effect transistors bulk tied to a ground, the set bulk nmos field effect transistors having: a first transistor including: a source coupled to a dc voltage source; and a gate coupled to a digitally controlled oscillator; a second transistor including: a source coupled to the dc voltage source; and a gate coupled to the digitally controlled oscillator; and a third transistor including: a source coupled to a drain of the first transistor; and a drain coupled to a drain of the second transistor. The transistors in the digitally controlled varactor may be fdsoi nmos devices with backgate coupled to a dc voltage source.. ... Globalfoundries Inc

06/07/18 / #20180158967

Electrical and optical via connections on a same chip

The present disclosure relates to semiconductor structures and, more particularly, to electrical and optical via connections on a same chip and methods of manufacture. The structure includes an optical through substrate via (tsv) comprising an optical material filling the tsv. ... Globalfoundries Inc

06/07/18 / #20180158931

Self-aligned finfet formation

A method for fabricating a semiconductor device comprises forming a first hardmask, a planarizing layer, and a second hardmask on a substrate. Removing portions of the second hardmask and forming alternating blocks of a first material and a second material over the second hardmask. ... Globalfoundries Inc

06/07/18 / #20180158897

Capacitor structure

Devices and methods for forming a device are disclosed. A substrate is provided. ... Globalfoundries Inc

06/07/18 / #20180158835

Logic and flash field-effect transistors

Methods of forming a device structure for a field-effect transistor and device structures for a field-effect transistor. A first gate dielectric layer is formed on a semiconductor layer in a first area. ... Globalfoundries Inc

06/07/18 / #20180158833

Semiconductor structure including a plurality of pairs of nonvolatile memory cells and an edge cell

A semiconductor structure includes a plurality of pairs of nonvolatile memory cells arranged in a row, an edge cell positioned adjacent to the pairs of nonvolatile memory cells, and first, second, third, and fourth gates. Each pair of nonvolatile memory cells includes first and second nonvolatile memory cells. ... Globalfoundries Inc

06/07/18 / #20180158821

Gate structures with low resistance

The present disclosure relates to semiconductor structures and, more particularly, to gate structures with low resistance and methods of manufacture. The structure includes: an nfet device formed in a first cavity having a first volume which is filled with conductive material; and a pfet device forming in a second cavity having a second volume greater than the first volume. ... Globalfoundries Inc

06/07/18 / #20180158817

Tunneling field effect transistor

Devices and methods for forming a device are disclosed. A substrate is provided. ... Globalfoundries Inc

06/07/18 / #20180158745

Semiconductor device comprising a die seal including long via lines

The patterning technique used for forming sophisticated metallization systems of semiconductor devices may be monitored and evaluated more efficiently by incorporating at least one via line feature into the die seal. In this manner, high statistical significance may be obtained compared to conventional strategies, in which the respective test structures for evaluating patterning processes may be provided at specific sites in the frame region and/or die region. ... Globalfoundries Inc

06/07/18 / #20180158733

Integrated ciurcuit product having a through-substrate-via (tsv) and a metallization layer that are formed after formation of a semiconductor device

An integrated circuit product includes a substrate, an interlayer dielectric (ild) material positioned above the substrate and a through-substrate-via (tsv) extending continuously through the substrate and the ild material. The tsv includes a substrate portion of the tsv that is positioned in and extends continuously through the substrate and an ild portion of the tsv that is positioned in and extends continuously through the ild. ... Globalfoundries Inc

06/07/18 / #20180158723

Dual photoresist approach to lithographic patterning for pitch reduction

Methods of lithographic patterning a dielectric layer. A first resist layer is formed on a hardmask layer, and a second resist layer is formed on the first resist layer. ... Globalfoundries Inc

06/07/18 / #20180158532

Parallel programming of one time programmable memory array for reduced test time

The present disclosure relates to a method of a non-volatile one time programmable memory (otpm) including parallel programming of all banks of the otpm by programming two rows per bank at a time, verifying the programming by comparing a first row of the two rows per bank, and verifying the programming by comparing a second row of the two rows per bank.. . ... Globalfoundries Inc

05/31/18 / #20180151726

Extended drain metal-oxide-semiconductor transistor

Devices and methods for forming a device are disclosed. A substrate is provided. ... Globalfoundries Inc

05/31/18 / #20180151690

Multiple-layer spacers for field-effect transistors

Structures for spacers in a device structure for a field-effect transistor and methods for forming spacers in a device structure for a field-effect transistor. A first spacer is located adjacent to a vertical sidewall of a gate electrode, a second spacer located between the first spacer and the vertical sidewall of the gate electrode, and a third spacer located between the second spacer and the vertical sidewall of the gate electrode. ... Globalfoundries Inc

05/31/18 / #20180151689

Spacers for tight gate pitches in field effect transistors

Structures for spacers of a field-effect transistor and methods for forming such spacers. A mask layer has a feature separated from a vertical sidewall of a first gate structure by a space of predetermined width that exposes a top surface of a semiconductor body. ... Globalfoundries Inc

05/31/18 / #20180151504

Self aligned interconnect structures

The present disclosure relates to semiconductor structures and, more particularly, to self-aligned interconnect structures and methods of manufacture. The structure includes an interconnect structure which is self-aligned with an upper level via metallization, and both the interconnect structure and the upper level via metallization are composed of a pt group material.. ... Globalfoundries Inc

05/31/18 / #20180151461

Stiffener for fan-out wafer level packaging and method of manufacturing

Aspects of the present disclosure include a wafer level chip package and method of manufacture. The wafer level chip package includes one or more semiconductor dies. ... Globalfoundries Inc

05/31/18 / #20180151449

Semiconductor structure including two-dimensional and three-dimensional bonding materials

One aspect of the disclosure is directed to a method of forming a semiconductor structure. The method including: removing each fin in a set of fins from between insulator pillars to expose a portion of a substrate between each insulator pillar, the substrate having a first device region and a second device region; forming a first material over the exposed portions of the substrate between each insulator pillar, the first material including a two-dimensional material; forming a second material over the first material in the first device region, the second material including a first three-dimensional bonding material; and forming a third material over the exposed first material in the second device region, the third material including a second three-dimensional bonding material.. ... Globalfoundries Inc

05/31/18 / #20180151433

Gate tie-down enablement with inner spacer

A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ild) is deposited on the gate conductor and the trench contacts and over the gate structure. ... Globalfoundries Inc

05/31/18 / #20180151238

Novel otprom for post-process programming using selective breakdown

At least one method, apparatus and system disclosed involves hard-coding data into an integrated circuit device. An integrated circuit device provided. ... Globalfoundries Inc

05/24/18 / #20180145160

Heterojunction bipolar transistor device integration schemes on a same wafer

The present disclosure generally relates to semiconductor structures and, more particularly, to heterojunction bipolar transistor device integration schemes on a same wafer and methods of manufacture. The structure includes: a power amplifier (pa) device comprising a base, a collector and an emitter on a wafer; and a low-noise amplifier (lna) device comprising a base, a collector and an emitter on the wafer, with the emitter having a same crystalline structure as the base.. ... Globalfoundries Inc

05/24/18 / #20180145088

Field-effect transistors with a buried body contact

Device structures for a field-effect transistor with a body contact and methods of forming such device structures. An opening is formed that extends through a device layer of a silicon-on-insulator (soi) substrate and into a buried oxide layer of the silicon-on-insulator substrate. ... Globalfoundries Inc

05/24/18 / #20180145079

Method, apparatus, and system having super steep retrograde well with engineered dopant profiles

Generally, in one embodiment, the present disclosure is directed to a method for forming a transistor. The method includes: implanting a substrate to form at least one of an n and p doped region; depositing an epitaxial semiconductor layer over the substrate; forming trenches through the epitaxial layer and partially through at least one of an n and p doped region; forming dielectric isolation regions in the trenches; forming a fin in an upper portion of the epitaxial semiconductor layer by partially recessing the dielectric isolation regions; forming a gate dielectric adjacent at least two surfaces of the fin; and diffusing dopant from at least one of the n and p doped regions at least partially into the epitaxial semiconductor layer to form a diffusion doped transition region adjacent a bottom portion of the fin.. ... Globalfoundries Inc

05/24/18 / #20180145073

Metal layer routing level for vertical fet sram and logic cell scaling

Methods of forming a vfet sram or logic device having a sub-fin level metal routing layer connected to a gate of one transistor pair and to the bottom s/d of another transistor pair and resulting device are provided. Embodiments include pairs of fins formed on a substrate; a bottom s/d layer patterned on the substrate around the fins; conformal liner layers formed over the substrate; a ild formed over a liner layer; a metal routing layer formed between the pairs of fins on the liner layer between the first pair and on the bottom s/d layer between at least the second pair, an upper surface formed below the active fin portion; a gaa formed on the dielectric spacer around each fin of the first pair; and a bottom s/d contact xc or a dedicated xc formed on the metal routing layer adjacent to the gaa or through the gaa, respectively.. ... Globalfoundries Inc

05/24/18 / #20180144979

Self-aligned lithographic patterning

Methods of lithographic patterning. A metal hardmask layer is formed on a dielectric layer and a patterned layer is formed on the metal hardmask layer. ... Globalfoundries Inc

05/24/18 / #20180144976

Post spacer self-aligned cuts

The present disclosure relates to semiconductor structures and, more particularly, to post spacer self-aligned cut structures and methods of manufacture. The method includes: providing a non-mandrel cut; providing a mandrel cut; forming blocking material on underlying conductive material in the non-mandrel cut and the mandrel cut; forming trenches with the blocking material acting as a blocking mask at the mandrel cut and the non-mandrel cut; and filling the trenches with metallization features such that the metallization features have a tip to tip alignment.. ... Globalfoundries Inc

05/24/18 / #20180144857

Parallel stacked inductor for high-q and high current handling and method of making the same

A high performance, on-chip a parallel stacked inductor which achieves a higher q value. The inductor is formed on a layered substrate with a top metal layer having spiral winding conductive segments that terminate at an overpass junction, and a bottom metal layer traversing adjacent to, and parallel with, the top metal layer. ... Globalfoundries Inc

05/24/18 / #20180143248

Early development of a database of fail signatures for systematic defects in integrated circuit (ic) chips

Disclosed are embodiments of a method that provides for pre-production run development of a fail signature database, which stores fail signatures for systematic defects and corresponding root causes. The fail signatures in the database is subsequently accessed and used for a variety of purposes. ... Globalfoundries Inc

05/24/18 / #20180143077

Self-contained metrology wafer carrier systems

A self-contained metrology wafer carrier systems and methods of measuring one or more characteristics of semiconductor wafers are provided. A wafer carrier system includes, for instance, a housing configured for transport within the automated material handling system, the housing having a support configured to support a semiconductor wafer in the housing, and a metrology system disposed within the housing, the metrology system operable to measure at least one characteristic of the wafer, the metrology system comprising a sensing unit and a computing unit operably connected to the sensing unit. ... Globalfoundries Inc

05/17/18 / #20180138308

Method for fabricating a finfet metallization architecture using a self-aligned contact etch

A method of fabricating a finfet device includes a self-aligned contact etch where a source/drain contact module is performed prior to a replacement metal gate (rmg) module. In particular, the method involves forming a sacrificial gate over the channel region of a fin, and an interlayer dielectric over adjacent source/drain regions of the fin. ... Globalfoundries Inc

05/17/18 / #20180138307

Tunnel finfet with self-aligned gate

Structures and methods for a tunnel field-effect transistor (tfet). The tfet includes a gate electrode, a source region having a first conductivity type, a drain region having a second conductivity type opposite from the first conductivity type, and a and a dielectric layer separating the gate electrode from the source region and the drain region. ... Globalfoundries Inc

05/17/18 / #20180138285

Methods of forming integrated circuit structure with silicide reigon

Embodiments of the present disclosure relate to methods of forming an integrated circuit (ic) structure with a silicide region. Methods according to the present disclosure can include providing a structure including: a semiconductor region positioned on an electrostatic chuck, and a precursor metal positioned on and in contact with the semiconductor region; heating the semiconductor region of the structure to an annealing temperature by increasing a temperature of the electrostatic chuck; irradiating the structure with a radiant heat source, such that at least some of the precursor metal migrates into a portion of the semiconductor region to form a silicide region during the irradiating; and removing a remainder of the precursor metal from the structure to expose the silicide region, after the irradiating.. ... Globalfoundries Inc

05/17/18 / #20180138279

Transistor-based semiconductor device with air-gap spacers and gate contact over active area

A semiconductor structure includes a semiconductor substrate, a semiconductor fin on the semiconductor substrate, a transistor integrated with the semiconductor fin at a top portion thereof, the transistor including an active region including a source, a drain and a channel region therebetween. The semiconductor structure further includes a gate structure over the channel region, the gate structure including a gate electrode, an air-gap spacer pair on opposite sidewalls of the gate electrode, and a gate contact for the gate electrode. ... Globalfoundries Inc

05/17/18 / #20180138209

Semiconductor substrate with metallic doped buried oxide

An soi substrate includes a metallic doped isolation (i.e., buried oxide) layer. Doping of the isolation layer increases its thermal conductivity, which improves heat conduction and decreases the susceptibility of devices formed on the substrate to temperature-induced deterioration and/or failure over time. ... Globalfoundries Inc

05/17/18 / #20180138203

Self-aligned back-plane and well contacts for fully depleted silicon on insulator device

The present disclosure generally relates to semiconductor structures and, more particularly, to self-aligned back-plane and well contacts for a fully depleted silicon on insulator device and methods of manufacture. The structure includes a back-plane, a p-well and an n-well formed within a bulk substrate; a contact extending from each of the back-plane, the p-well and the n-well; a gate structure formed above the back-plane, the p-well and the n-well; and an insulating spacer isolating the contact of the back-plane from the gate structure.. ... Globalfoundries Inc

05/17/18 / #20180138187

Methods of forming semiconductor devices using semi-bidirectional patterning

Devices and methods of fabricating integrated circuit devices using semi-bidirectional patterning are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a dielectric layer, a first, a second, and a third hardmask layer, and a lithography stack; patterning a first set of lines; patterning a second set of lines between the first set of lines; etching to define a combination of the first and second set of lines; depositing a second lithography stack; patterning a third set of lines in a direction perpendicular to the first and second set of lines; etching to define the third set of lines, leaving an opl; depositing a spacer over the opl; etching the spacer, leaving a vertical set of spacers; and etching the second hardmask layer using the third hardmask layer and the set of vertical spacers as masks.. ... Globalfoundries Inc

05/17/18 / #20180138177

Formation of band-edge contacts

Formation of band-edge contacts include, for example, providing an intermediate semiconductor structure comprising a substrate and a gate thereon and source/drain regions adjacent the gate, depositing a non-epitaxial layer on the source/drain regions, deposing a metal layer on the non-epitaxial layer, and forming metal alloy contacts from the deposited non-epitaxial layer and metal layer on the source/drain regions by annealing the deposited non-epitaxial layer and metal layer.. . ... Globalfoundries Inc

05/17/18 / #20180138123

Interconnect structure and method of forming the same

Aspects of the present disclosure include a semiconductor device which includes a dielectric layer deposited over a conductive region and an interconnect electrically connecting the conductive region with a top surface of the dielectric layer. The interconnect includes a barrier layer extending from an interior of the dielectric layer to the conductive region and covering the conductive region. ... Globalfoundries Inc

05/17/18 / #20180138079

Electrically insulated fin structure(s) with alternative channel materials and fabrication methods

Semiconductor structures and fabrication methods are provided which includes, for instance, fabricating a semiconductor fin structure by: providing a fin structure extending above a substrate, the fin structure including a first fin portion, a second fin portion disposed over the first fin portion, and an interface between the first and the second fin portions, where the first fin portion and the second fin portion are lattice mismatched within the fin structure; and modifying, in part, the fin structure to obtain a modified fin structure, the modifying including selectively oxidizing the interface to form an isolation region within the modified fin structure, where the isolation region electrically insulates the first fin portion from the second fin portion, while maintaining structural stability of the modified fin structure.. . ... Globalfoundries Inc

05/17/18 / #20180138064

Wafer carrier purge apparatuses, automated mechanical handling systems including the same, and methods of handling a wafer carrier during integrated circuit fabrication

A wafer carrier purge apparatus, an automated mechanical handling system, and a method of handling a wafer carrier during integrated circuit fabrication are provided. The wafer carrier purge apparatus includes a purge plate adapted for insertion into a carrier storage position. ... Globalfoundries Inc

05/17/18 / #20180138046

Method and structure to control channel length in vertical fet device

A method of manufacturing a vertical field effect transistor includes an isotropic etch of a gate conductor to recess the gate and define the length of the transistor channel. A symmetric gate conductor geometry prior to the etch, in combination with the isotropic (i.e., lateral) etch, allows the effective vertical etch rate of the gate conductor to be independent of local pattern densities, resulting in a uniform channel length among plural transistors formed on a semiconductor substrate.. ... Globalfoundries Inc

05/17/18 / #20180136304

Apparatus and method for vector s-parameter measurements

The disclosure relates to an apparatus and a method for vector scattering parameter (s-parameter) measurements, and more particularly, to an apparatus and a method for providing a simple, low cost solution for tests requiring vector s-parameter measurements. The apparatus includes a source which provides an input signal, a divider which splits the input signal to a reference signal and a testing signal, a phase shifter which shifts the reference signal by a first phase and outputs a phase shifted signal, a device under test (dut) which shifts the testing signal by a second phase and outputs a dut shifted signal, a combiner which combines the phase shifted signal and the dut shifted signal into a combined signal, and a detector which detects a product of the phase shifted signal and the dut shifted signal.. ... Globalfoundries Inc

05/17/18 / #20180135967

Three-dimensional scatterometry for measuring dielectric thickness

Methodologies and an apparatus for enabling three-dimensional scatterometry to be used to measure a thickness of dielectric layers in semiconductor devices are provided. Embodiments include initiating optical critical dimension (ocd) scatterometry on a three-dimensional test structure formed on a wafer, the three-dimensional test structure comprising patterned copper (cu) trenches with an ultra-low k (ulk) dielectric film formed over the patterned cu trenches; and obtaining, by a processor, a thickness of the ulk dielectric film based on results of the ocd scatterometry.. ... Globalfoundries Inc

05/10/18 / #20180130943

Magnetic tunnel junction element with reduced temperature sensitivity

A magnetic tunneling junction (mtj) with a reference layer is less temperature sensitive and is reflow compatible at 260° c. The reference layer may be a composite reference layer having n magnetic layers separated by (n−1) non-magnetic spacer layers. ... Globalfoundries Inc

05/10/18 / #20180130899

Method to form air-gap spacers and air-gap spacer-containing structures

A device includes an air-gap (i.e., air-gap spacer) formed in situ during the selective, non-conformal deposition of a conductive material. The air-gap is disposed between source/drain contacts and a gate conductor of the device and beneath a portion of the conductive material, and is configured to decrease capacitive coupling between adjacent conductive elements. ... Globalfoundries Inc

05/10/18 / #20180130895

Methods of forming gate electrodes on a vertical transistor device

One illustrative method of forming a vertical transistor device disclosed herein includes, among other things, forming bottom source/drain (s/d) regions. A plurality of vertically oriented channel semiconductor structures is formed above the bottom source/drain (s/d) regions. ... Globalfoundries Inc

05/10/18 / #20180130891

Gate structures

The present disclosure generally relates to semiconductor structures and, more particularly, to gate structures with minimized gate thickness loss and methods of manufacture. The structure includes: a plurality of gate structures; a film layer provided over the gate structures and adjacent to the gate structures; and a planarized cap layer on the film and over the plurality of gate structures, the planarized cap layer having a different selectivity to slurry of a chemical mechanical polishing (cmp) process than the film.. ... Globalfoundries Inc

05/10/18 / #20180130889

Self-aligned contact protection using reinforced gate cap and spacer portions

A method includes providing a starting structure, the starting structure including a semiconductor substrate, sources and drains, a hard mask liner layer over the sources and drains, a bottom dielectric layer over the hard mask liner layer, metal gates between the sources and drains, the metal gates defined by spacers, gate cap openings between corresponding spacers and above the metal gates, and a top dielectric layer above the bottom dielectric layer and in the gate cap openings, resulting in gate caps. The method further includes removing portions of the top dielectric layer, the removing resulting in contact openings and divot(s) at a top portion of the spacers and/or gate caps, and filling the divot(s) with etch-stop material, the etch-stop material having an etch-stop ability better than a material of the spacers and gate cap. ... Globalfoundries Inc

05/10/18 / #20180130878

Nanostructure field-effect transistors with enhanced mobility source/drain regions

Structures and fabrication methods for vertical-transport field-effect transistors. A nanostructure, a gate structure coupled with the nanostructure, and a source/drain region coupled with an end of the nanostructure are formed. ... Globalfoundries Inc

05/10/18 / #20180130733

Separation of integrated circuit structure from adjacent chip

Embodiments of the present disclosure relate to separating an integrated circuit (ic) structure from an adjacent chip. An ic structure according to embodiments of the disclosure may include: a semiconductor region including an interconnect pad positioned thereon, the interconnect pad electrically connected to a solder bump; and an ohmic heating wire positioned within the semiconductor region and in thermal communication with the interconnect pad, wherein the ohmic heating wire is configured to be heated above a melting temperature of the solder bump.. ... Globalfoundries Inc

05/10/18 / #20180130712

Spacer defined fin growth and differential fin width

Methods for forming fins with a straight profile by preventing fin bending during sti fill and annealing are disclosed. Embodiments include providing sti regions separated by si regions, each topped with a hardmask; planarizing the sti regions; removing the hardmask over a portion of the si regions, forming recesses; forming a conformal spacer layer over the sti regions and in the recesses; removing horizontal portions of the spacer layer; epitaxially growing si in each recess, forming fins; and etching the sti regions and a remainder of the spacer layer down to the si regions to reveal the fins.. ... Globalfoundries Inc

05/10/18 / #20180130711

Semiconductor fin loop for use with diffusion break

A finfet includes a source or a drain including: a first semiconductor fin extending parallel to a second semiconductor fin, and a semiconductor connector fin creating a first semiconductor fin loop by connecting an end of the first semiconductor fin to an end of the second semiconductor fin. A diffusion break isolates the source or the drain, and is positioned about the first semiconductor connector fin and the ends of the first semiconductor fin and the second semiconductor fin. ... Globalfoundries Inc

05/10/18 / #20180130703

Structure and method for capping cobalt contacts

A process for forming a conductive structure includes the formation of a self-aligned silicide cap over a cobalt-based contact. The silicide cap is formed in situ by the deposition of a thin silicon layer over exposed portions of a cobalt contact, followed by heat treatment to react the deposited silicon with the cobalt and form cobalt silicide, which is an effective barrier to cobalt migration and oxidation.. ... Globalfoundries Inc

05/10/18 / #20180130702

Encapsulation of cobalt metallization

Structures that include cobalt metallization and methods of forming such structures. A feature is located inside an opening in a dielectric layer and a cap layer located on a top surface of the feature. ... Globalfoundries Inc

05/10/18 / #20180130699

Skip via structures

The present disclosure relates to semiconductor structures and, more particularly, to skip via structures and methods of manufacture. The structure includes: a first wiring layer with one or more wiring structures; a second wiring layer with one or more wiring structures, located above the first wiring layer; a skip via with metallization, which passes through upper wiring levels including the second wiring layer and which makes contact with the one or more wiring structures of the first wiring layer; and a via structure which comprises a protective material and contacts at least one of the one or more wiring structures at the upper wiring level.. ... Globalfoundries Inc

05/10/18 / #20180130656

Forming defect-free relaxed sige fins

A method of forming defect-free relaxed sige fins is provided. Embodiments include forming fully strained defect-free sige fins on a first portion of a si substrate; forming si fins on a second portion of the si substrate; forming sti regions between adjacent sige fins and si fins; forming a cladding layer over top and side surfaces of the sige fins and the si fins and over the sti regions in the second portion of the si substrate; recessing the sti regions on the first portion of the si substrate, revealing a bottom portion of the sige fins; implanting dopant into the si substrate below the sige fins; and annealing.. ... Globalfoundries Inc

05/10/18 / #20180130521

Bending circuit for static random access memory (sram) self-timer

The present disclosure relates to a circuit, including a first transistor with a drain connected to a capacitor, a gate connected to an input of an inverter and a source connected to ground, a second transistor with a drain connected to the capacitor and a gate connected to the input of the inverter, a third transistor with a source connected to an output of the inverter, a drain connected to a source of the second transistor, and a gate connected to the input of the inverter, and a fourth transistor with a source connected to the source of the third transistor, a drain connected to ground, and a gate connected to the capacitor.. . ... Globalfoundries Inc

05/10/18 / #20180128874

System for detection of a photon emission generated by a device and methods for detecting the same

A system for detection of a photon emission generate by a device of an integrated circuit, and methods for detecting the same are provided. The system includes a device space configured to include the device. ... Globalfoundries Inc

05/03/18 / #20180123733

Ethernet physical layer device having an integrated physical coding and forward error correction sub-layers

Disclosed are ethernet physical layer devices (e.g., a transceiver, a receiver and a transmitter) with integrated physical coding and forward error correction sub-layers. Each physical layer device includes a physical coding sub-layer (pcs), a forward error correction sub-layer (fec) and integration block(s). ... Globalfoundries Inc

05/03/18 / #20180123027

High energy barrier perpendicular magnetic tunnel junction element with reduced temperature sensitivity

A magnetic tunneling junction (mtj) with a free layer that is less temperature sensitive and is reflow compatible at 260° c. The magnetic free layer may include various configurations, such as a single as-deposited crystalline magnetic layer or a composite free layer with more than one magnetic layers or a combination of composite and single magnetic layers. ... Globalfoundries Inc

05/03/18 / #20180122956

Thick fdsoi source-drain improvement

A method of forming a semiconductor device is disclosed including providing a semiconductor-on-insulator substrate comprising a semiconductor bulk substrate, a buried insulating layer positioned on the semiconductor bulk substrate and a semiconductor layer positioned on the buried insulating layer, providing at least one metal-oxide semiconductor gate structure positioned above the semiconductor layer comprising a gate electrode and a spacer formed adjacent to the gate electrode, selectively removing an upper portion of the semiconductor layer so as to define recessed portions of the semiconductor layer and epitaxially forming raised source/drain regions on the recessed portions of the semiconductor layer.. . ... Globalfoundries Inc

05/03/18 / #20180122919

Methods of forming a gate contact for a transistor above the active region and an air gap adjacent the gate of the transistor

One illustrative method disclosed includes, among other things, removing a portion of an initial gate cap layer and a portion of an initial sidewall spacer so as to thereby define a gate contact cavity that exposes a portion of a gate structure, completely forming a conductive gate contact structure (cb) in a gate contact cavity, wherein the entire conductive gate contact structure (cb) is positioned vertically above the active region. The method also comprises removing the remaining portion of the initial gate cap layer and to recess a vertical height of exposed portions of the initial sidewall spacer to thereby define a recessed sidewall spacer and a gate cap cavity and forming a replacement gate cap layer in the gate cap cavity so as to define an air space between an upper surface of the recessed sidewall spacer and a lower surface of the replacement gate cap layer.. ... Globalfoundries Inc

05/03/18 / #20180122913

Integration of vertical-transport transistors and electrical fuses

Structures for a vertical-transport field-effect transistor and an electrical fuse integrated into an integrated circuit, and methods of fabricating a vertical-transport field-effect transistor and an electrical fuse integrated into an integrated circuit. A doped semiconductor layer that includes a first region with a first electrode of the vertical electrical fuse and a second region with a first source/drain region of the vertical-transport field effect transistor. ... Globalfoundries Inc

05/03/18 / #20180122891

Semiconductor device resistor structure

A resistor body is separated from a doped well in a substrate by a resistor dielectric material layer. The doped well is defined by at least one doped region and can include a dopant gradient in the doped well to reduce parasitic capacitance of the resistor structure while retaining heat dissipation properties of the substrate. ... Globalfoundries Inc

05/03/18 / #20180122804

Special construct for continuous non-uniform active region finfet standard cells

Methods for abutting two cells with different sized diffusion regions and the resulting devices are provided. Embodiments include abutting a first cell having first drain and source diffusion regions and a second cell having second drain and source diffusion regions, larger than the first diffusion regions, by: forming a dummy gate at a boundary between the two cells; forming a continuous drain diffusion region having an upper portion crossing the dummy gate and encompassing the entire first drain diffusion region and part of the second drain diffusion region and having a lower portion beginning over the dummy gate and encompassing a remainder of the second drain diffusion region; forming a continuous source diffusion region that is the mirror image of the continuous drain diffusion region; and forming a poly-cut mask over the dummy gate between, but separated from, the continuous drain and source diffusion regions.. ... Globalfoundries Inc

05/03/18 / #20180122795

Memory cell with asymmetrical transistor, asymmetrical transistor and method of forming

An asymmetric transistor may be used for controlling a memory cell. The asymmetric transistor may include at least one gate stack having bottom to top: a gate dielectric layer having a planar upper surface and a uniform thickness extending atop the entirety of the device channel, a dielectric threshold voltage adjusting element including: a sloped dielectric element located on the planar upper surface of the gate dielectric layer, and a sidewall dielectric layer extending from the sloped dielectric element along a first sidewall of the opening space, and a gate conductor located atop an upper surface of the sloped dielectric element and along a side of the sidewall dielectric layer. ... Globalfoundries Inc

05/03/18 / #20180122730

Producing wafer level packaging using leadframe strip and related device

A method for producing wafer level packaging using an embedded leadframe strip and the resulting device are provided. Embodiments include placing dies into a mold with an active side of each die facing a surface of the mold; placing a leadframe strip on the mold, wherein the leadframe strip includes etched and half etched portions positioned between each die; placing a mold cover over the mold and dies; and adding mold compound in spaces between the dies and mold cover.. ... Globalfoundries Inc

05/03/18 / #20180122711

Dual liner silicide

A method for fabricating a dual silicide device includes growing source and drain (s/d) regions for an n-type device, forming a protection layer over a gate structure and the s/d regions of the n-type device and growing s/d regions for a p-type device. A first dielectric layer is conformally deposited and portions removed to expose the s/d regions. ... Globalfoundries Inc

05/03/18 / #20180122702

Methods of forming transistor devices with different threshold voltages and the resulting devices

A device includes a first transistor device having a first threshold voltage and including a first gate electrode structure positioned in a first gate cavity. The first gate electrode structure includes a first gate insulation layer, a first barrier layer, a first work function material layer formed above the first barrier layer, a second barrier layer formed above the first work function material layer, and a first conductive material formed above the second barrier layer. ... Globalfoundries Inc

05/03/18 / #20180122689

Contact module for optimizing emitter and contact resistance

An advanced contact module for optimizing emitter and contact resistance and methods of manufacture are disclosed. The method includes forming a first contact via to a first portion of a first device. ... Globalfoundries Inc

05/03/18 / #20180122644

Hard mask layer to reduce loss of isolation material during dummy gate removal

A method includes providing a starting semiconductor structure, the starting semiconductor structure including a semiconductor substrate with active region(s) separated by isolation regions, the active region(s) including source/drain regions of epitaxial semiconductor material, dummy gate structures adjacent each source/drain region, the dummy gate structures including dummy gate electrodes with spacers adjacent opposite sidewalls thereof and gate caps thereover, and openings between the dummy gate structures. The method further includes filling the openings with a dielectric material, recessing the dielectric material, resulting in a filled and recessed structure, and forming a hard mask liner layer over the filled and recessed structure to protect against loss of the recessed dielectric material during subsequent removal of unwanted dummy gate electrodes. ... Globalfoundries Inc

04/19/18 / #20180108776

Vertical transistors stressed from various directions

A vertical transistor includes a semiconductor substrate, and fin(s) over the semiconductor substrate (n-type fin(s) and/or p-type fin(s)), the fin(s) acting as vertical transistor channels for vertical transistors. Each of the fin(s) is lattice mismatched at one or more interface(s), being stressed from below, from above, from fin sidewalls or combination(s) thereof. ... Globalfoundries Inc

04/19/18 / #20180108749

Trench silicide contacts with high selectivity process

A method for forming self-aligned contacts includes patterning a mask between fin regions of a semiconductor device, etching a cut region through a first dielectric layer between the fin regions down to a substrate and filling the cut region with a first material, which is selectively etchable relative to the first dielectric layer. The first dielectric layer is isotropically etched to reveal source and drain regions in the fin regions to form trenches in the first material where the source and drain regions are accessible. ... Globalfoundries Inc

04/19/18 / #20180108732

Notched fin structures and methods of manufacture

The present disclosure relates to semiconductor structures and, more particularly, to notched fin structures and methods of manufacture. The structure includes: a fin structure composed of a substrate material and a stack of multiple epitaxially grown materials on the substrate material; a notch formed in a first epitaxially grown material of the stack of multiple epitaxially grown materials of the fin structure; an insulator material within the notch of the fin structure; and an insulator layer surrounding the fin structure and above a surface of the notch.. ... Globalfoundries Inc

04/19/18 / #20180108706

Spin-selective electron relay

Structures including a spin torque transfer magnetic tunnel junction (mtj) stack and methods for fabricating same. A first contact is coupled with a first portion of a free layer of the mtj stack, and a second contact is coupled with a second portion of the free layer of the mtj stack. ... Globalfoundries Inc

04/19/18 / #20180108668

Flash memory device

An integrated circuit product includes a silicon-on-insulator (soi) substrate and a flash memory device positioned in a first area of the soi substrate. The soi substrate includes a semiconductor bulk substrate, a buried insulating layer positioned above the semiconductor bulk substrate, and a semiconductor layer positioned above the buried insulating layer, and the flash memory device includes a flash transistor device and a read transistor device. ... Globalfoundries Inc

04/19/18 / #20180108654

Finfet device with low resistance fins

A method of forming a finfet device includes ion implanting a diffusion-inhibiting species such as carbon into source and drain regions of a semiconductor fin prior to a dopant activating anneal. The implanted carbon, which can be incorporated into the fin in conjunction with a replacement metal gate process after defining a sacrificial gate but prior to forming sidewall spacers on the gate, forms a barrier that impedes dopant diffusion across the barrier, which enables abrupt junctions and higher overall dopant concentrations within the semiconductor fin.. ... Globalfoundries Inc

04/19/18 / #20180108651

Deep trench metal-insulator-metal capacitors

Device structures for a metal-insulator-metal (mim) capacitor, as well as methods of fabricating a device structure for a mim capacitor. An active device level is formed on a substrate, a local interconnect level is formed on the active device level, and a metal-insulator-metal capacitor is formed in a via opening with a sidewall extending through the local interconnect level and the active device level to a given depth in the substrate. ... Globalfoundries Inc

04/19/18 / #20180108642

Interposer heater for high bandwidth memory applications

A method for integrating heaters in high bandwidth memory (hbm) applications and the related devices are provided. Embodiments include forming a silicon (si) interposer over a substrate; forming hbm and an integrated circuit (ic) over the si interposer; forming a heater on the si interposer in a space between the hbm and si interposer; and utilizing one or more temperature sensors in the hbm to monitor a temperature of the hbm.. ... Globalfoundries Inc

04/19/18 / #20180108607

Ic structure including tsv having metal resistant to high temperatures and method of forming same

An integrated circuit (ic) structure including: a first layer including a first plurality of active devices in a first semiconductor layer over a substrate; a first wiring layer over the first layer; a second layer including a second plurality of active devices within a second semiconductor layer over the first wiring layer; and a second wiring layer over the second layer, wherein the first wiring layer and the second wiring layer each including a first metal resistant to high temperature.. . ... Globalfoundries Inc

04/19/18 / #20180108571

Method, apparatus, and system for using a cover mask for enabling metal line jumping over mol features in a standard cell

At least one method, apparatus and system disclosed involves providing an integrated circuit having metal feature flyover over an middle-of-line (mol) feature. A first location for a non-contact intersection region between a first middle of line (mol) interconnect feature and a metal feature in a functional cell is determined. ... Globalfoundries Inc








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