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Gsi Technology Inc patents


Recent patent applications related to Gsi Technology Inc. Gsi Technology Inc is listed as an Agent/Assignee. Note: Gsi Technology Inc may have other listings under different names/spellings. We're not affiliated with Gsi Technology Inc, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "G" | Gsi Technology Inc-related inventors


Systems and methods of pipelined output latching involving synchronous memory arrays

Systems and methods of synchronous memories and synchronous memory operation are disclosed. According to one illustrative implementation, a memory device is disclosed comprising memory circuitry having a memory output, the memory circuitry including a sense amplifier having a first output and a second output, a first data path coupled to the first output of the sense amplifier, the first data path including 2 latches/registers, and a second data path coupled to the second output of the sense amplifier, the second data path including a plurality latches/registers. ... Gsi Technology Inc

Sparse matrix multiplication in associative memory device

A method for multiplying a first sparse matrix by a second sparse matrix in an associative memory device includes storing multiplicand information related to each non-zero element of the second sparse matrix in a computation column of the associative memory device; the multiplicand information includes at least a multiplicand value. According to a first linear algebra rule, the method associates multiplier information related to a non-zero element of the first sparse matrix with each of its associated multiplicands, the multiplier information includes at least a multiplier value. ... Gsi Technology Inc

Computational memory cell and processing array device using the memory cells for xor and xnor computations

A memory cell and processing array that has a plurality of memory are capable of performing logic functions, including an exclusive or (xor) or an exclusive nor (xnor) logic function. The memory cell may have a read port in which the digital data stored in the storage cell of the memory cell is isolated from the read bit line.. ... Gsi Technology Inc

Computational memory cell and processing array device using the memory cells for xor and xnor computations

A memory cell and processing array that has a plurality of memory are capable of performing logic functions, including an exclusive or (xor) or an exclusive nor (xnor) logic function. The memory cell may have a read port in which the digital data stored in the storage cell of the memory cell is isolated from the read bit line.. ... Gsi Technology Inc

Computational memory cell and processing array device using memory cells

A memory cell that may be used for computation and processing array using the memory cell are capable to performing a logic operation including a boolean and, a boolean or, a boolean nand or a boolean nor. The memory cell may have a read port that has isolation circuits that isolate the data stored in the storage cell of the memory cell from the read bit line.. ... Gsi Technology Inc

Computational memory cell and processing array device using memory cells

A memory cell that may be used for computation and processing array using the memory cell are capable to performing a logic operation including a boolean and, a boolean or, a boolean nand or a boolean nor. The memory cell may have a read port that has isolation circuits that isolate the data stored in the storage cell of the memory cell from the read bit line.. ... Gsi Technology Inc

Four steps associative full adder

A method to add a first one bit variable with a second one bit variable and a carry-in bit, to generate a sum bit and a carry-out bit, the method includes initiating the sum bit to the value of the second one bit variable, initiating the carry-out bit to a value of the carry-in bit and modifying the sum bit and the carry-out bit if a comparison of a sequence of the first one bit variable, the second one bit variable and an inverse value of the carry-in bit matches one of a predefined set of a change trigger sequences.. . ... Gsi Technology Inc

Computational memory cell and processing array device using memory cells

A memory cell that may be used for computation and processing array using the memory cell are capable to performing a logic operation including a boolean and, a boolean or, a boolean nand or a boolean nor. The memory cell may have a read port that has isolation circuits that isolate the data stored in the storage cell of the memory cell from the read bit line.. ... Gsi Technology Inc

Systems and method involving fast-acquisition lock features associated with phase locked loop circuitry

Systems and methods are disclosed relating to fields of clock/data acquisition or handling, such as clock/data locking and the like. In one exemplary implementation, phase lock loop (pll) circuitry may comprise voltage controlled oscillator (vco) circuitry, phase frequency detector, converting circuitry, and frequency detector (fd) circuitry that outputs a frequency difference signal proportional to frequency difference between frequencies of a feedback clock signal and a reference clock signal.. ... Gsi Technology Inc

Associative row decoder

A multiple instruction, multiple data memory device includes a memory array with several sections, one or more multiplexers between the sections and a decoder. Each section has memory cells arranged in rows and columns. ... Gsi Technology Inc

Systems and methods involving lock-loop circuits, clock signal alignment, phase-averaging feedback clock circuitry

Systems and methods associated with reducing clock skew are disclosed. In some exemplary embodiments, there is provided circuitry associated with lock loop circuits such as a phase lock loop (pll). ... Gsi Technology Inc

Systems and methods involving control-i/o buffer enable circuits and/or features of saving power in standby mode

Systems and methods are disclosed involving control i/o buffer enable circuitry and/or features of saving power in standby mode. In illustrative implementations, aspects of the present innovations may be directed to providing low standby power consumption, such as providing low standby power consumption in high-speed synchronous sram and rldram devices.. ... Gsi Technology Inc

Finding k extreme values in constant processing time

A method includes determining a set of k extreme values of a dataset of elements in a constant time irrespective of the size of the dataset. A method creates a set of k indicators, each indicator associated with one multi-bit binary number in a large dataset of multi-bit binary numbers. ... Gsi Technology Inc

In memory matrix multiplication and its usage in neural networks

A method for an associative memory array includes storing each column of a matrix in an associated column of the associative memory array, where each bit in row j of the matrix is stored in row r-matrix-row-j of the array, storing a vector in each associated column, where a bit j from the vector is stored in an r-vector-bit-j row of the array. The method includes simultaneously activating a vector-matrix pair of rows r-vector-bit-j and r-matrix-row-j to concurrently receive a result of a boolean function on all associated columns, using the results to calculate a product between the vector-matrix pair of rows, and writing the product to an r-product-j row in the array.. ... Gsi Technology Inc

07/27/17 / #20170213594

In-memory computational device

A computing device includes a memory array built of several sections having memory cells arranged in rows and column, at least one cell in each column of the memory array being connected to a bit line; and at least one multiplexer to connect a bit line in a first column of a first section to a bit line in a second column in a second section different from the first section, where the second column is not continuous with the first column; and a decoder to activate at least two word lines of the first section and a word line connected to a cell in the second column in the second section to write a bit line voltage associated with a result of a logical operation performed on the first column into the cell in the second column.. . ... Gsi Technology Inc

06/08/17 / #20170163269

Systems and method involving fast-acquisition lock features associated with phase locked loop circuitry

Systems and methods are disclosed relating to fields of clock/data acquisition or handling, such as clock/data locking and the like. In one exemplary implementation, phase lock loop (pll) circuitry may comprise voltage controlled oscillator (vco) circuitry, phase frequency detector, converting circuitry, and frequency detector (fd) circuitry that outputs a frequency difference signal proportional to frequency difference between frequencies of a feedback clock signal and a reference clock signal.. ... Gsi Technology Inc

05/04/17 / #20170125074

Systems and methods of pipelined output latching involving synchronous memory arrays

Systems and methods of synchronous memories and synchronous memory operation are disclosed. According to one illustrative implementation, a memory device is disclosed comprising memory circuitry having a memory output, the memory circuitry including a sense amplifier having a first output and a second output, a first data path coupled to the first output of the sense amplifier, the first data path including 2 latches/registers, and a second data path coupled to the second output of the sense amplifier, the second data path including a plurality latches/registers. ... Gsi Technology Inc

03/02/17 / #20170063372

Systems and methods involving pseudo complementary output buffer circuitry/schemes, power noise reduction and/or other features

A system may include a first inverter configured to invert a first data signal and a second inverter configured to invert a second data signal. A pull-up element may be coupled to an output of the first inverter on a first terminal and a power source on a second terminal, wherein the power source is also coupled to a pull-up element of a main output buffer. ... Gsi Technology Inc








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