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Imagination Technologies Limited patents


Recent patent applications related to Imagination Technologies Limited. Imagination Technologies Limited is listed as an Agent/Assignee. Note: Imagination Technologies Limited may have other listings under different names/spellings. We're not affiliated with Imagination Technologies Limited, we're just tracking patents.

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Tessellating patches of surface data in tile based computer graphics rendering

A method and system for culling a patch of surface data from one or more tiles in a tile based computer graphics system. A rendering space is divided into a plurality of tiles and a patch of surface data read. ... Imagination Technologies Limited

Graphics processing units and methods for controlling rendering complexity using cost indications for sets of tiles of a rendering space

A graphics processing unit (gpu) processes graphics data using a rendering space which is sub-divided into a plurality of tiles. The gpu comprises cost indication logic configured to obtain a cost indication for each of a plurality of sets of one or more tiles of the rendering space. ... Imagination Technologies Limited

Graphics processing units and methods using cost indications for sets of tiles of a rendering space

A graphics processing unit is configured to process graphics data using a rendering space which is sub-divided into a plurality of tiles. The graphics processing unit comprises one or more processing cores configured to process graphics data. ... Imagination Technologies Limited

Computing systems and methods for processing graphics data using cost indications for sets of tiles of a rendering space

A computing system comprises graphics rendering logic and image processing logic. The graphics rendering logic processes graphics data to render an image using a rendering space which is sub-divided into a plurality of tiles. ... Imagination Technologies Limited

Graphics processing units and methods for subdividing a set of one or more tiles of a rendering space for rendering

A graphics processing unit is configured to process graphics data using a rendering space which is sub-divided into a plurality of tiles. The graphics processing unit comprises one or more processing cores configured to process graphics data. ... Imagination Technologies Limited

Efficient catmull-rom interpolation

Interpolation logic described herein provides a good approximation to a bicubic interpolation, which is generally smoother than bilinear interpolation, without performing all the calculations normally needed for a bicubic interpolation. This allows an approximation of smooth bicubic interpolation to be performed on devices (e.g. ... Imagination Technologies Limited

Efficient interpolation using not linear interpolation

Interpolation logic described herein provides a good approximation to a bicubic interpolation, which is generally smoother than bilinear interpolation, without performing all the calculations normally needed for a bicubic interpolation. This allows an approximation of smooth bicubic interpolation to be performed on devices (e.g. ... Imagination Technologies Limited

Median value determination in a data processing system

Median values for a stream of received data values in a data processing system (e.g. An image processing system) are determined. ... Imagination Technologies Limited

Rendering a computer generated image using a stencil buffer with primitive concatenation

A method and apparatus for rendering a computer-generated image using a stencil buffer is described. The method divides an arbitrary closed polygonal contour into first and higher level primitives, where first level primitives correspond to contiguous vertices in the arbitrary closed polygonal contour and higher level primitives correspond to the end vertices of consecutive primitives of the immediately preceding primitive level. ... Imagination Technologies Limited

Rendering a computer generated image using a stencil buffer

A method and apparatus for rendering a computer-generated image using a stencil buffer is described. The method divides an arbitrary closed polygonal contour into first and higher level primitives, where first level primitives correspond to contiguous vertices in the arbitrary closed polygonal contour and higher level primitives correspond to the end vertices of consecutive primitives of the immediately preceding primitive level. ... Imagination Technologies Limited

Tile-based graphics

A tile-based graphics system has a rendering space sub-divided into a plurality of tiles which are to be processed. Graphics data items, such as parameters or texels, are fetched into a cache for use in processing one of the tiles. ... Imagination Technologies Limited

Graphics renderer and method for rendering 3d scene in computer graphics using object pointers and depth values

An apparatus and a method for generating 3-dimensional computer graphic images. The image is first sub-divided into a plurality of rectangular areas. ... Imagination Technologies Limited

Performance profiling in computer graphics

A method of profiling the performance of a graphics unit when rendering a scene according to a graphics pipeline, includes executing stages of the graphics pipeline using one or more units of rendering circuitry to perform at least one rendering task that defines a portion of the work required to render the scene, the at least one rendering task associated with a set flag; propagating an indication of the flag through stages of the graphics pipeline as the scene is rendered so that work done as part of the at least one rendering task is associated with the set flag; changing the value of a counter associated with a unit of rendering circuitry in response to an occurrence of an event whilst that unit performs an item of work associated with the set flag; and reading the value of the counter to thereby measure the occurrences of the event caused by completing the at least one rendering task.. . ... Imagination Technologies Limited

Image noise reduction

A reduced noise image can be formed from a set of images. One of the images of the set can be selected to be a reference image and other images of the set are transformed such that they are better aligned with the reference image. ... Imagination Technologies Limited

05/24/18 / #20180143832

Encoding and decoding variable length instructions

Methods of encoding and decoding are described which use a variable number of instruction words to encode instructions from an instruction set, such that different instructions within the instruction set may be encoded using different numbers of instruction words. To encode an instruction, the bits within the instruction are re-ordered and formed into instruction words based upon their variance as determined using empirical or simulation data. ... Imagination Technologies Limited

05/24/18 / #20180143805

Performing a comparison computation in a computer system

A method and computer system are provided for performing a comparison computation, e.g. For use in a check procedure for a reciprocal square root operation. ... Imagination Technologies Limited

05/03/18 / #20180121166

Division synthesis

A binary logic circuit for determining the ratio x/d in accordance with a rounding scheme, where x is a variable integer input of bit length w and d is a fixed positive integer of the form 2n±1, the binary logic circuit being configured to form the ratio as a plurality of bit slices, the bit slices collectively representing the ratio, wherein the binary logic circuit is configured to generate each bit slice according to a first modulo operation for calculating mod(2n±1) of a respective bit selection of the input x and in dependence on a check for a carry bit, wherein the binary logic circuit is configured to, responsive to the check, selectively combine a carry bit with the result of the first modulo operation.. . ... Imagination Technologies Limited

04/19/18 / #20180108174

Hidden culling in tile-based computer generated images

A method and system is provided for culling hidden objects in a tile-based graphics system before they are indicated in a display list for a tile. A rendering space is divided into a plurality of regions which may for example be a plurality of tiles or a plurality of areas into which one or more tiles are divided. ... Imagination Technologies Limited

04/19/18 / #20180107890

Performing object detection in an image

A single-instruction, multiple data processor performs object detection in an image by testing for a plurality of object features in a plurality of image regions, the processor comprising: a set of computation units operable to execute a plurality of classifier sequences in parallel, each classifier sequence comprising a plurality of classifier routines, and each classifier routine comprising identical instructions to the other classifier routines in each of the plurality of classifier sequences; wherein each computation unit is configured to independently maintain data identifying an image region and a feature under test on that computation unit, and each classifier routine is arranged to access the data, test the identified feature against the identified image region and update the data such that the computation units are operable to concurrently test different features against different image regions.. . ... Imagination Technologies Limited

04/19/18 / #20180107825

Verifying firmware binary images using a hardware design and formal assertions

Described herein are hardware monitors arranged to detect illegal firmware instructions in a firmware binary image using a hardware design and one or more formal assertions. The hardware monitors include monitor and detection logic configured to detect when an instantiation of the hardware design has started and/or stopped execution of the firmware and to detect when the instantiation of the hardware design has decoded an illegal firmware instruction. ... Imagination Technologies Limited

04/19/18 / #20180107765

Detecting out-of-bounds violations in a hardware design using formal verification

A hardware monitor arranged to detect out-of-bounds violations in a hardware design for an electronic device. The hardware monitors include monitor and detection logic configured to monitor the current operating state of an instantiation of the hardware design and detect when the instantiation of the hardware design implements a fetch of an instruction from memory; and assertion evaluation logic configured to evaluate one or more assertions that assert a formal property that compares the memory address of the fetched instruction to an allowable memory address range associated with the current operating state of the instantiation of the hardware design to determine whether there has been an out-of-bounds violation. ... Imagination Technologies Limited

04/19/18 / #20180107537

Out-of-bounds recovery circuit

Out-of-bounds recovery circuits configured to detect an out-of-bounds violation in an electronic device, and cause the electronic device to transition to a predetermined safe state when an out-of-bounds violation is detected. The out-of-bounds recovery circuits include detection logic configured to detect that an out-of-bounds violation has occurred when a processing element of the electronic device has fetched an instruction from an unallowable memory address range for the current operating state of the electronic device; and transition logic configured to cause the electronic device to transition to a predetermined safe state when an out-of-bounds violation has been detected by the detection logic.. ... Imagination Technologies Limited

04/12/18 / #20180101763

Buffer addressing for a convolutional neural network

A method for providing input data for a layer of a convolutional neural network “cnn”, the method comprising: receiving input data comprising input data values to be processed in a layer of the cnn; determining addresses in banked memory of a buffer in which the received data values are to be stored based upon format data indicating a format parameter of the input data in the layer and indicating a format parameter of a filter which is to be used to process the input data in the layer; and storing the received input data values at the determined addresses in the buffer for retrieval for processing in the layer.. . ... Imagination Technologies Limited

03/29/18 / #20180088989

Task scheduling in a gpu

A method of scheduling tasks within a gpu or other highly parallel processing unit is described which is both age-aware and wakeup event driven. Tasks which are received are added to an age-based task queue. ... Imagination Technologies Limited

03/22/18 / #20180084277

Data compression using spatial decorrelation

Methods and modules for spatial decorrelation and recorrelation are described. A block of data values can be spatially decorrelated in two dimensions efficiently by processing rows of the data values in a particular order such that if the results of spatially decorrelating a first row will be used for column-wise spatial decorrelation of a second row then the data values of the first row are processed in an earlier iteration to that in which the data values of the second row are processed. ... Imagination Technologies Limited

03/15/18 / #20180074835

Build-time memory management for multi-core embedded system

Methods for generating executable files for two or more independent programs to be run on separate processor cores of an embedded system wherein the programs share data/code via shared memory by symbolically referring to data/code generated by another program. The methods implement a two-stage link process. ... Imagination Technologies Limited

03/08/18 / #20180067727

Trailing or leading zero counter having parallel and combinational logic

A trailing/leading zero counter is described which comprises a plurality of hardware logic blocks, each of which calculates one bit of the output value (i.e. The number of trailing/leading zeros depending on whether it is a trailing/leading zero counter). ... Imagination Technologies Limited

03/01/18 / #20180061112

Systems and methods for distributed scalable ray processing

Ray tracing systems have computation units (“racs”) adapted to perform ray tracing operations (e.g. Intersection testing). ... Imagination Technologies Limited

03/01/18 / #20180061027

Image filtering based on image gradients

Image processing methods and systems apply filtering operations to images, wherein the filtering operations use filter costs which are based on image gradients in the images. In this way, image data is filtered for image regions in dependence upon the image gradients for the image regions. ... Imagination Technologies Limited

02/22/18 / #20180052669

String logging in an embedded system

Methods for logging strings during execution of a program running on an embedded system without storing the strings in the memory of the embedded system include, during the build process, receiving source code for a program that comprises one or more log statements that identifies a string to be logged; generating object code based on the source code that comprises a special log section that includes the identified strings, and, for each log statement one or more instructions that cause a reference to the corresponding string to be stored in memory of the embedded system; generating execution code based on the object code wherein the special log section is marked as non-loadable and each reference is a location of the corresponding string in the special log section; and, loading the generated executable code into the memory of the embedded system such that the identified strings are not loaded into the memory of the embedded system.. . ... Imagination Technologies Limited

02/01/18 / #20180033196

Tessellation of patches of surfaces in a tile based rendering system

A method and apparatus are provided for tessellating patches of surfaces in a tile based three dimensional computer graphics rendering system. For each tile in an image a per tile list of primitive indices is derived for tessellated primitives which make up a patch. ... Imagination Technologies Limited

02/01/18 / #20180033187

Processing primitives which have unresolved fragments in a graphics processing system

A graphics processing system performs hidden surface removal and texturing/shading on fragments of primitives. The system includes a primary depth buffer (pdb) for storing depth values of resolved fragments, and a secondary depth buffer (sdb) for storing depth values of unresolved fragments. ... Imagination Technologies Limited

01/18/18 / #20180020223

Mip map compression

Methods and apparatus for compressing image data are described along with corresponding methods and apparatus for decompressing the compressed image data. An encoder unit, which generates the compressed image data, comprises an input arranged to receive a first image and a second image, wherein the second image is twice the width and height of the first image, a prediction generator arranged to generate a prediction texture from the first image using an adaptive interpolator, a difference texture generator arranged to generate a difference texture from the prediction texture and the second image and in encoder unit arranged to encode the difference texture.. ... Imagination Technologies Limited

01/04/18 / #20180007647

Reference synchronisation

A method at a first device for synchronising a first clock of the first device to a second clock of a second device, includes receiving a first message comprising an identifier from a third device; generating a first timestamp in dependence on the time at which the first message is received at the first device according to the first clock; receiving a second message from the second device comprising the identifier and a second timestamp, the second timestamp having been generated in dependence on the time at which the second device received the first message from the third device according to the second clock; and adjusting the first clock in dependence on a time difference between a time indicated by the first timestamp and a time indicated by the second timestamp.. . ... Imagination Technologies Limited

01/04/18 / #20180006802

Method and apparatus for time synchronisation in wireless networks

A wireless media distribution system is provided comprising an access point (6) for broadcasting media and a plurality of stations (2) for reception and playback of media. Each station is configured for receiving and decoding a timestamp in a beacon frame transmitted repeatedly from the access point. ... Imagination Technologies Limited

01/04/18 / #20180006798

Master synchronisation

A method at a first device for synchronising a first clock of the first device to a second clock of a second device, includes receiving a first message comprising an identifier from the second device; generating a first timestamp in dependence on the time at which the first message is received at the first device according to the first clock; receiving a second message from the second device comprising the identifier and a second timestamp, the second timestamp having been generated in dependence on the time at which the second device transmitted the first message to the first device; and adjusting the first clock in dependence on a time difference between a time indicated by the first timestamp and a time indicated by the second timestamp.. . ... Imagination Technologies Limited

01/04/18 / #20180004529

Indirect branch prediction

Methods and indirect branch predictor logic units to predict the target addresses of indirect branch instructions. The method comprises storing in a table predicted target addresses for indirect branch instructions indexed by a combination of the indirect path history for previous indirect branch instructions and the taken/not-taken history for previous conditional branch instructions. ... Imagination Technologies Limited

01/04/18 / #20180004244

Clock synchronisation

A first device for playing media synchronously with a second device, includes a hardware clock having an adjustable clock frequency; a software clock configured to derive time in dependence on the hardware clock; a controller configured to: determine a synchronisation error between the software clock and a clock of the second device; and adjust the clock frequency of the hardware clock in dependence on the synchronisation error; and a media playout device for playing media and configured to be clocked by the hardware clock.. . ... Imagination Technologies Limited

12/28/17 / #20170372698

Low power detection of a voice control activation phrase

. . Methods of low power detection of an activation phrase are described. A microphone system comprises dedicated hardware logic for detecting a pre-defined activation phrase in an audio stream received via a microphone. ... Imagination Technologies Limited

12/28/17 / #20170371622

Error bounded multiplication by invariant rationals

A hardware logic representation of a circuit to implement an operation to perform multiplication by an invariant rational is generated by truncating an infinite single summation array (which is represented in a finite way). The truncation is performed by identifying a repeating section and then discarding all but a finite number of the repeating sections whilst still satisfying a defined error bound. ... Imagination Technologies Limited

12/28/17 / #20170371621

Low-area fixed-point polynomials

Methods of implementing fixed-point polynomials in hardware logic include distributing a defined error bound for the whole polynomial between operators in a data-flow graph for the polynomial by solving an optimization problem that outputs an accuracy parameter and a precision parameter for each node. Each operator is then itself optimized to satisfy the part of the error bound allocated to that operator and as defined by the accuracy and precision parameters.. ... Imagination Technologies Limited

12/21/17 / #20170366820

Method and apparatus for compressing and decompressing data

Methods and apparatus are provided for compressing and decompressing image data by producing two sets of reduced size image data, generating a modulation value for each elementary of the area from the image data, the modulation value encoding information about how to combine the sets of reduced size image data to generate an approximation to the image. In one arrangement, a set of index values is generated corresponding to a set of modulation values for each of the respective elementary areas of a group of elementary areas and these are assigned to each respective group and a second set of index values corresponding to one of the set of first index values for each elementary areas is assigned to each first group of elementary areas. ... Imagination Technologies Limited

12/21/17 / #20170365100

Augmented reality occlusion

A method for generating an augmented reality image from first and second images, wherein at least a portion of at least one of the first and the second image is captured from a real scene, the method comprising: identifying a confidence region in which a confident determination as to which of the first and second image to render in that region of the augmented reality image can be made; identifying an uncertainty region in which it is uncertain as to which of the first and second image to render in that region of the augmented reality image; determining at least one blending factor value in the uncertainty region based upon a similarity between a first colour value in the uncertainty region and a second colour value in the confidence region; and generating an augmented reality image by combining, in the uncertainty region, the first and second images using the at least one blending factor value.. . ... Imagination Technologies Limited

12/21/17 / #20170364609

Livelock detection in a hardware design using formal evaluation logic

A hardware monitor arranged to detect livelock in a hardware design for an integrated circuit. The hardware monitor includes monitor and detection logic configured to detect when a particular state has occurred in an instantiation of the hardware design; and assertion evaluation logic configured to periodically evaluate one or more assertions that assert a formal property related to reoccurrence of the particular state in the instantiation of the hardware design to detect whether the instantiation of the hardware design is in a livelock comprising the predetermined state. ... Imagination Technologies Limited

12/21/17 / #20170364363

Livelock recovery circuit

Livelock recovery circuits configured to detect livelock in a processor, and cause the processor to transition to a known safe state when livelock is detected. The livelock recovery circuits include detection logic configured to detect that the processor is in livelock when the processor has illegally repeated an instruction; and transition logic configured to cause the processor to transition to a safe state when livelock has been detected by the detection logic.. ... Imagination Technologies Limited

12/21/17 / #20170364357

Fetching instructions in an instruction fetch unit

A method in an instruction fetch unit configured to initiate a fetch of an instruction bundle from a first memory and to initiate a fetch of an instruction bundle from a second memory, wherein a fetch from the second memory takes a predetermined fixed plurality of processor cycles, the method comprising: identifying that an instruction bundle is to be selected for fetching from the second memory in a predetermined future processor cycle; and initiating a fetch of the identified instruction bundle from the second memory a number of processor cycles prior to the predetermined future processor cycle based upon the predetermined fixed plurality of processor cycles taken to fetch from the second memory. . ... Imagination Technologies Limited

12/21/17 / #20170364329

Approximating functions

A binary logic circuit for approximating a mathematical function over a predefined range as a series of linear segments, each linear segment having one of a predetermined set of fixed gradients and a corresponding base value, the binary logic circuit comprising: an input for receiving an input variable in the predefined range; a plurality of logic chains each comprising: a binary multiplier adapted to perform multiplication by a respective one of the set of fixed gradients using h-1 binary adders, where h is the extended hamming weight; and a binary adder adapted to add a base value to the input or output of the binary multiplier; and selection logic configured to select one of the logic chains in dependence on the input variable so as to provide, for the received input variable, an approximate value of the mathematical function.. . ... Imagination Technologies Limited

12/14/17 / #20170357742

Deadlock detection in hardware design using assertion based verification

Methods and systems for detecting deadlock in a hardware design. The method comprises identifying one or more control signals in the hardware design; generating a state machine for each of the one or more control signals to track the state of the control signal; generating one or more assertions for each control signal to detect that the control signal is in a deadlock state from the state machine; and detecting whether any of the one or more control signal are in a deadlock state using the assertions. ... Imagination Technologies Limited

12/14/17 / #20170357512

Executing memory requests out of order

An on-chip cache is described which receives memory requests and in the event of a cache miss, the cache generates memory requests to a lower level in the memory hierarchy (e.g. To a lower level cache or an external memory). ... Imagination Technologies Limited

11/30/17 / #20170344668

Assessing performance of a hardware design using formal evaluation logic

A hardware monitor arranged to assess performance of a hardware design for an integrated circuit to complete a task. The hardware monitor includes monitoring and counting logic configured to count a number of cycles between start and completion of the symbolic task in an instantiation of the hardware design; and property evaluation logic configured to evaluate one or more formal properties related to the counted number of cycles to assess the performance of the instantiation of the hardware design in completing the symbolic task. ... Imagination Technologies Limited

11/30/17 / #20170344503

Hardware data structure for tracking partially ordered and reordered transactions

Methods and hardware data structures are provided for tracking ordered transactions in a multi-transactional hardware design comprising one or more slaves configured to receive transaction requests from a plurality of masters. The data structure includes one or more counters for keeping track of the number of in-flight transactions; a table that keeps track of the age of each of the in-flight transactions for each master using the one or more counters; and control logic that verifies that a transaction response for an in-flight transaction for a particular master has been issued by the slave in a predetermined order based on the tracked age for the in-flight transaction in the table.. ... Imagination Technologies Limited

11/23/17 / #20170337729

Primitive processing in a graphics processing system

A graphics processing system has a rendering space which is divided into tiles. Primitives within the tiles are processed to perform hidden surface removal and to apply texturing to the primitives. ... Imagination Technologies Limited

11/09/17 / #20170324983

Compressing and decompressing image data using compacted region transforms

There is a method of compressing image data comprising a set of image values each representing a position in image-value space so as to define an occupied region thereof. The method comprises selectively applying a series of compression transforms to subsets of the image data items to generate a transformed set of image data items occupying a compacted region of value space. ... Imagination Technologies Limited

11/09/17 / #20170323421

Primitive processing in a graphics processing system with tag buffer storage of primitive identifiers

A graphics processing system has a rendering space which comprises one or more tiles. The system comprises a processing module configured to perform hidden surface removal for primitives of a tile to determine primitive identifiers identifying the primitives which are visible at each of a plurality of sample positions in the tile. ... Imagination Technologies Limited

11/09/17 / #20170323197

Convolutional neural network hardware configuration

A method of configuring a hardware implementation of a convolutional neural network (cnn), the method comprising: determining, for each of a plurality of layers of the cnn, a first number format for representing weight values in the layer based upon a distribution of weight values for the layer, the first number format comprising a first integer of a first predetermined bit-length and a first exponent value that is fixed for the layer; determining, for each of a plurality of layers of the cnn, a second number format for representing data values in the layer based upon a distribution of expected data values for the layer, the second number format comprising a second integer of a second predetermined bit-length and a second exponent value that is fixed for the layer; and storing the determined number formats for use in configuring the hardware implementation of a cnn.. . ... Imagination Technologies Limited

11/09/17 / #20170323196

Hardware implementation of a convolutional neural network

A method in a hardware implementation of a convolutional neural network (cnn), includes receiving a first subset of data having at least a portion of weight data and at least a portion of input data for a cnn layer and performing, using at least one convolution engine, a convolution of the first subset of data to generate a first partial result; receiving a second subset of data comprising at least a portion of weight data and at least a portion of input data for the cnn layer and performing, using the at least one convolution engine, a convolution of the second subset of data to generate a second partial result; and combining the first partial result and the second partial result to generate at least a portion of convolved data for a layer of the cnn.. . ... Imagination Technologies Limited

10/26/17 / #20170309282

Comfort noise generation

A system for generating comfort noise for a stream of frames carrying an audio signal includes frame characterizing logic configured to generate a set of filter parameters characterising the frequency content of a frame; an analysis filter adapted using the filter parameters and configured to filter the frame so as to generate residual samples; an analysis controller configured to cause the residual samples to be stored in a store responsive to receiving an indication that the frame does not comprise speech; and a synthesis controller operable to select stored residual samples from the store and cause a synthesis filter, inverse to the analysis filter and adapted using filter parameters generated by the frame characterizing logic for one or more frames not comprising speech, to filter the selected residual samples so as to generate a frame of comfort noise.. . ... Imagination Technologies Limited

10/26/17 / #20170309059

Dedicated ray memory for ray tracing in graphics systems

A ray tracing unit is implemented in a graphics rendering system. The ray tracing unit comprises: processing logic configured to perform ray tracing operations on rays, a dedicated ray memory coupled to the processing logic and configured to store ray data for rays to be processed by the processing logic, an interface to a memory system, and control logic configured to manage allocation of ray data to either the dedicated ray memory or the memory system. ... Imagination Technologies Limited

10/26/17 / #20170308502

Circuit architecture mapping signals to functions for state machine execution

An integrated circuit includes a memory configured to store a plurality of functions; a mapping interface configured to perform a mapping from a received first signal to a first function of the plurality of functions; and a state machine configured to, in response to said mapping, execute the first function; wherein the integrated circuit is arranged to, in dependence on the execution of the first function at the state machine, modify said mapping between the first signal and the first function so as to re-map the first signal to a second function of the plurality of functions such that, on receiving a subsequent first signal, the state machine is configured to execute the second function.. . ... Imagination Technologies Limited

10/26/17 / #20170308488

Communication interface between host system and state machine

A communications interface for interfacing between a host system and a state machine, the communications interface comprising: an event slot, the event slot comprising a plurality of registers including: a write register for writing by the host system, and a read register for reading by the host system, wherein the event slot is addressed from the host system by a single address location permitting the host system to write data to the write register and/or read data from the read register; and wherein the write register and the read register are individually addressable by the state machine.. . ... Imagination Technologies Limited

10/26/17 / #20170308355

Evaluating polynomials in hardware logic

An accurate implementation of a polynomial using floating-point or other rounded arithmetic can be generated using a plurality of hardware logic components which each implement an input polynomial such that the zeros in the input polynomial can be determined correctly. The number of different hardware logic components that are used can be reduced by analysing the set of input polynomials and from it generating a set of polynomial components, where each polynomial in the set of input polynomials which is not also in the set of polynomial components, can be generated from a single one of the polynomial components.. ... Imagination Technologies Limited

10/26/17 / #20170308354

Sorting numbers in hardware

An efficient hardware apparatus for calculating the maximum and/or minimum of two n-bit binary input values generates a number of separate select signals, each of which is then used to control the selection of a single bit from one of the two binary inputs. A select signal for an ith bit of the output depends upon bits [n−1, i] in each of the two binary inputs and based on the select signal the ith bit is selected from one of the two inputs.. ... Imagination Technologies Limited

10/12/17 / #20170295283

Auto-tuning of an acoustic echo canceller

A gain control system for dynamically tuning an echo canceller, the echo canceller being configured to estimate an echo of a far-end signal and subtract that estimate from a microphone signal to output an echo cancelled signal, the system comprising an echo measurement unit configured to calculate a ratio of the microphone signal to the far-end signal, an attenuation unit configured to attenuate at least one of the microphone signal and the far-end signal to output a second microphone signal and a second far-end signal to the echo canceller, the ratio of the second microphone signal to the second far-end signal being different from the calculated ratio, and an attenuation controller configured to control the attenuation unit, in dependence on the calculated ratio, so as to alter the ratio of the second microphone signal to the second far-end signal and control the echo-cancelled signal.. . ... Imagination Technologies Limited

10/12/17 / #20170293646

Apparatus and methods for out of order item selection and status updating

An apparatus, system, and method provide a way for tracking the age of items stored within a queue. An apparatus includes an item storage array and an array of age-tracking bits. ... Imagination Technologies Limited

10/12/17 / #20170293556

Read discards in a processor system with write-back caches

A system and method provide for a better way of managing a shared memory system. A multiprocessor system includes a first and second cpu, with each cpu having a private l1 cache. ... Imagination Technologies Limited

10/12/17 / #20170293486

Processors supporting atomic writes to multiword memory locations & methods

A system and method process atomic instructions. A processor system includes a load store unit (lsu), first and second registers, a memory interface, and a main memory. ... Imagination Technologies Limited

10/05/17 / #20170287122

Noise enhanced histograms

Apparatus for binning an input value into one of a plurality of bins which collectively represent a histogram of input values, each of the plurality of bins representing a corresponding range of input values, the apparatus comprising: an input for receiving an input value; a noise source configured to generate an error value according to a predetermined noise distribution; and a binning controller configured to mix the received input value with the error value so as to generate a modified input value and to allocate the modified input value to the bin corresponding to that modified input value.. . ... Imagination Technologies Limited

10/05/17 / #20170286151

Handling memory requests

A converter module is described which handles memory requests issued by a cache (e.g. An on-chip cache), where these memory requests include memory addresses defined within a virtual memory space. ... Imagination Technologies Limited

09/28/17 / #20170280069

Generating sparse sample histograms in image processing

Apparatus for binning an input value into an array of bins, each bin representing a range of input values and the bins collectively representing a histogram of input values, the apparatus comprising: an input for receiving the input value; a memory for storing the array; and a binning controller configured to: derive a plurality of bin values from the input value according to a binning distribution located about the input value, the binning distribution spanning a range of input values and each bin value having a respective input value dependent on the position of the bin value in the binning distribution; and allocate the plurality of bin values to a plurality of bins in the array, each bin value being allocated to a bin selected according to the respective input value of the bin value.. . ... Imagination Technologies Limited

09/28/17 / #20170278297

Query resolver for global illumination of 3-d rendering

Rendering system combines point sampling and volume sampling operations to produce rendering outputs. For example, to determine color information for a surface location in a 3-d scene, one or more point sampling operations are conducted in a volume around the surface location, and one or more sampling operations of volumetric light transport data are performed farther from the surface location. ... Imagination Technologies Limited

09/28/17 / #20170277941

Learned feature motion detection

A data processing device for detecting motion in a sequence of frames each comprising one or more blocks of pixels, includes a sampling unit configured to determine image characteristics at a set of sample points of a block, a feature generation unit configured to form a current feature for the block, the current feature having a plurality of values derived from the sample points, and motion detection logic configured to generate a motion output for a block by comparing the current feature for the block to a learned feature representing historical feature values for the block.. . ... Imagination Technologies Limited

09/28/17 / #20170277539

Exception handling in processor using branch delay slot instruction set architecture

A processor employs hardware to save the program counter value of the next instruction to be executed in a branch instruction when an exception occurs. This is the branch target address in the case where the exception occurs in the delay slot of a taken branch. ... Imagination Technologies Limited

09/28/17 / #20170277514

Unified multiply unit

Embodiments disclosed pertain to apparatuses, systems, and methods for performing multi-precision single instruction multiple data (simd) operations on integer, fixed point and floating point operands. Disclosed embodiments pertain to a circuit that is capable of performing concurrent multiply, fused multiply-add, rounding, saturation, and dot products on the above operand types. ... Imagination Technologies Limited

09/21/17 / #20170272769

Decoding frames

A system for decoding a data stream, comprising: a first decoder configured to decode the data stream at a first rate so as to generate a first stream of frames for playback and arranged to continue generating the first stream despite encountering an error in a particular frame; a second decoder operable to decode the data stream at a second rate so as to generate a second stream of frames; and a controller configured to: detect the error and cause the second decoder to decode the data stream from the particular frame in dependence on error correction data, the second rate being faster than the first rate such that the second stream catches up with the first stream; determine when the second decoder catches up with the first decoder; and cause the second decoder to operate at the first rate so as to generate the second stream for playback.. . ... Imagination Technologies Limited

09/21/17 / #20170272579

Auto-tuning of acoustic echo canceller

A gain control system for dynamically tuning an echo canceller, the echo canceller being configured to estimate an echo of a far-end signal and subtract that echo estimate from a microphone signal to output an echo cancelled signal, the gain control system comprising a monitoring unit configured to estimate an energy associated with an impulse response of an adaptive filter configured to generate the echo estimate from the far-end signal and a gain tuner configured to adjust an attenuation of at least one of the microphone signal and the far-end signal in dependence on the estimated energy.. . ... Imagination Technologies Limited

09/21/17 / #20170270146

Hierarchy merging

A hierarchy is a multi-level linked structure of nodes, wherein the hierarchy represents data relating to a set of one or more items to be processed. Where there are multiple input hierarchies, it may improve the efficiency of the processing of the items to merge the input hierarchies to form a merged hierarchy. ... Imagination Technologies Limited

09/21/17 / #20170270046

Non-linear cache logic

Cache logic for generating a cache address from a binary memory address comprising a first binary sequence of a first predefined length and a second binary sequence of a second predefined length, the cache logic comprising: a plurality of substitution units each configured to receive a respective allocation of bits of the first binary sequence and to replace its allocated bits with a corresponding substitute bit string selected in dependence on the received allocation of bits; a mapping unit configured to combine the substitute bit strings output by the substitution units so as to form one or more binary strings of the second predefined length; and combination logic arranged to combine the one or more binary strings with the second binary sequence by a reversible operation so as to form a binary output string for use as at least part of a cache address in a cache memory.. . ... Imagination Technologies Limited

09/21/17 / #20170269902

Check procedure for floating point operations

Method and computer system for implementing an operation on ≧1 floating point input, in accordance with a rounding mode, e.g. Using a newton-raphson technique. ... Imagination Technologies Limited

09/14/17 / #20170263044

Methods and graphics processing units for determining differential data for rays of a ray bundle

. . Graphics processing system configured to perform ray tracing. Rays are bundled together and processed together. ... Imagination Technologies Limited

09/14/17 / #20170263043

Importance sampling for determining a light map

A bounce light map for a scene is determined for use in rendering the scene in a graphics processing system. Initial lighting indications representing lighting within the scene are determined. ... Imagination Technologies Limited

09/07/17 / #20170256020

Task assembly for simd processing

A cache system in a graphics processing system stores graphics data items for use in rendering primitives. It is determined whether graphics data items relating to primitives to be rendered are present in the cache, and if not then computation instances for generating the graphics data items are created. ... Imagination Technologies Limited

08/24/17 / #20170243598

Controlling analogue gain using digital gain estimation

A gain control system for controlling gain applied to an audio signal includes a power estimator configured to estimate the power of a digital signal derived from the audio signal, a digital gain estimator configured to determine, in dependence on the estimated power, a digital gain which would modify the power of the digital signal so as to reach a target power level, and a gain controller configured to adjust an analogue gain applied to the audio signal in dependence on the determined digital gain.. . ... Imagination Technologies Limited

08/10/17 / #20170228920

Compacting results vectors between stages of graphics processing

Ray tracing, and more generally, graphics operations taking place in a 3-d scene, involve a plurality of constituent graphics operations. Responsibility for executing these operations can be distributed among different sets of computation units. ... Imagination Technologies Limited

08/03/17 / #20170221261

Frustum rendering in computer graphics

A graphics processing system comprising: a tiling unit configured to tile a first view of a scene into a plurality of tiles; a processing unit configured to identify a first subset of the tiles that are associated with regions of the scene that are viewable in a second view; and a rendering unit configured to render to a render target each of the identified tiles.. . ... Imagination Technologies Limited

08/03/17 / #20170221177

Sparse rendering in computer graphics

A graphics processing system comprising: a tiling unit configured to tile a first view of a scene into a plurality of tiles and generate a list of primitives associated with each tile; a processing unit configured to identify a first subset of the tiles that are each associated with at least a predetermined number of primitives in dependence on the list; and a rendering unit configured to render to a render target each of the identified tiles.. . ... Imagination Technologies Limited

08/03/17 / #20170220707

Identifying bugs in a counter using formal

A method of detecting a bug in a counter of a hardware design that includes formally verifying, using a formal verification tool, an inductive assertion from a non-reset state of an instantiation of the hardware design. The inductive assertion establishes a relationship between the counter and a test bench counter at two or more points in time. ... Imagination Technologies Limited

08/03/17 / #20170220471

Control of pre-fetch traffic

Methods and systems for improved control of traffic generated by a processor are described. In an embodiment, when a device generates a pre-fetch request for a piece of data or an instruction from a memory hierarchy, the device includes a pre-fetch identifier in the request. ... Imagination Technologies Limited

08/03/17 / #20170220353

Stack pointer value prediction

Methods and apparatus for predicting the value of a stack pointer which store data when an instruction is seen which grows the stack. The information which is stored includes a size parameter which indicates by how much the stack is grown and one or both of: the register id currently holding the stack pointer value or the current stack pointer value. ... Imagination Technologies Limited

07/20/17 / #20170208170

Echo path change detector

An echo path monitoring system for controlling an adaptive filter configured to estimate an echo of a far-end signal comprised in a microphone signal, the system comprising a comparison generator configured to compare the microphone signal with the estimated echo to obtain a first comparison and compare an error signal, which represents a difference between the microphone signal and the estimated echo, with the estimated echo to obtain a second comparison, and a controller configured to combine the first and second comparisons to form a parameter indicative of a state of the microphone signal and, in dependence on said parameter, control an operating mode of the adaptive filter.. . ... Imagination Technologies Limited

07/20/17 / #20170206706

Rendering in computer graphics systems

A graphics system has a rendering space divided into a plurality of rectangular areas, each being sub-divided into a plurality of smaller rectangular areas of a plurality of pixels. Data is received representing a tiled set of polygons to be rendered in a selected one of the rectangular areas. ... Imagination Technologies Limited

07/20/17 / #20170206086

Execution of load instructions in a processor

Techniques for executing a load instruction in a processor are described. In one example, load instructions which are detected to have an offset (or displacement) of zero are sent directly to a data cache, bypassing the address generation stage thereby reducing pipeline length. ... Imagination Technologies Limited

07/20/17 / #20170205864

Dynamic power measurement using formal

Methods, systems and hardware monitors for verifying that an integrated circuit defined by a hardware design meets a power requirement including detecting whether a power consuming transition has occurred for one or more flip-flops of an instantiation of the hardware design; in response to detecting that a power consuming transition has occurred, updating a count of power consuming transitions for the instantiation of the hardware design; and determining, whether the power requirement is met at a particular point in time by evaluating one or more properties that are based on the count of power consuming transitions.. . ... Imagination Technologies Limited

07/13/17 / #20170201675

Controlling the focus of a camera using focus statistics

Apparatus for controlling the focus of a camera arranged to capture a sequence of frames, includes an image processor configured to: form an image characteristic for a plurality of blocks of a first frame, each block comprising one or more pixels of the first frame; and calculate an image parameter for each block by combining the image characteristics of blocks lying within a predefined zone relative to that block; and a focus controller configured to derive a measure of focus for a selected frame area of the first frame by identifying a set of blocks whose respective predefined zones, when combined, substantially represent the selected frame area, and forming a measure of focus for the selected frame area by so combining the image parameters of the set of blocks; wherein the focus controller is configured to generate a signal for controlling camera focus in dependence on the measure of focus formed for the selected frame area of the first frame.. . ... Imagination Technologies Limited

07/06/17 / #20170193631

Memory management for systems for generating 3-dimensional computer images

A memory management system for generating 3-dimensional computer images is provided. The memory management system includes a device for subdividing an image into a plurality of rectangular areas, a memory for storing object data pertaining to objects in the image which fall in each rectangular area, a device for storing the object data in the memory, a device for deriving image data and shading data for each rectangular area from the object data, a device for supplying object data for each rectangular area from the respective portion of the memory and, if the rectangular area contains objects also falling in at least one other rectangular area, also from the global list, to the deriving device, and a device for storing the image data and shading data derived by the deriving device for display. ... Imagination Technologies Limited

07/06/17 / #20170193281

Face detection in an image data stream using skin colour patch constructs

A data processing system for performing face detection on a stream of frames of image data, the data processing system comprising: a skin patch identifier configured to identify one or more patches of skin colour in a first frame and characterise each patch in the first frame using a respective patch construct of a predefined shape; a first search tile generator configured to generate one or more first search tiles from the one or more patch constructs; and a face detector configured to detect faces in the stream by performing face detection in one or more frames of the stream within the first search tiles.. . ... Imagination Technologies Limited

07/06/17 / #20170192779

Scheduling execution of instructions on a processor having multiple hardware threads with different execution resources

A method and apparatus are provided for executing instructions of a multi-threaded processor having multiple hardware threads with differing hardware resources comprising the steps of receiving a plurality of streams of instructions and determining which hardware threads are able to receive instructions for execution, determining whether a thread determined to be available for executing an instructions has the hardware resources available required by that instructions and executing the instruction in dependence on the result of the determination.. . ... Imagination Technologies Limited

06/22/17 / #20170180651

Capturing an image

An imaging device for capturing an image of a scene, comprising: an image sensor; an optical arrangement operable to focus light from a portion of the scene onto the image sensor whilst preventing light from other portions of the scene from being focused onto the sensor; a controller configured to cause the optical arrangement to focus light from a sequence of portions of the scene onto the sensor so that the sensor captures the said sequence of portions of the scene; and a processor configured to use the captured portions of the scene to construct an image of the scene.. . ... Imagination Technologies Limited

06/22/17 / #20170178386

Allocation of tiles to processing engines in a graphics processing system

A graphics processing system processes primitive fragments using a rendering space which is sub-divided into tiles. The graphics processing system comprises processing engines configured to apply texturing and/or shading to primitive fragments. ... Imagination Technologies Limited

06/22/17 / #20170178295

Artefact detection and correction

An artefact detector detects artefacts in a video sequence comprising interpolated frames generated by performing motion estimation. The detector comprises a pixel processor which processes pixel values in first and second input frames of the video sequence to identify respective blocks of pixels representing an image feature. ... Imagination Technologies Limited

06/22/17 / #20170178282

Multistage collector for outputs in multiprocessor systems

Aspects include a multistage collector to receive outputs from plural processing elements. Processing elements may comprise (each or collectively) a plurality of clusters, with one or more alus that may perform simd operations on a data vector and produce outputs according to the instruction stream being used to configure the alu(s). ... Imagination Technologies Limited

06/22/17 / #20170178280

Tile based computer graphics

A method and system for generating and shading a computer graphics image in a tile based computer graphics system is provided. Geometry data is supplied and a plurality of primitives are derived from the geometry data. ... Imagination Technologies Limited

06/22/17 / #20170177521

Arbiter verification

Operation of an arbiter in a hardware design is verified. The arbiter receives a plurality of requests over a plurality of clock cycles, including a monitored request and outputs the requests in priority order. ... Imagination Technologies Limited

06/22/17 / #20170177227

Lossy data compression

A lossy method of compressing data, such as image data, which uses wrap-around wavelet compression is described. Each data value is divided into two parts and the first parts, which comprise the most significant bits from the data values, are compressed using wrap-around wavelet compression. ... Imagination Technologies Limited

06/15/17 / #20170169602

Foveated rendering

Foveated rendering for rendering an image uses a ray tracing technique to process graphics data for a region of interest of the image, and a rasterisation technique is used to process graphics data for other regions of the image. A rendered image can be formed using the processed graphics data for the region of interest of the image and the processed graphics data for the other regions of the image. ... Imagination Technologies Limited

06/15/17 / #20170168989

Configurable fft architecture

A device for performing a fast fourier transform (fft) on an input dataset includes an fft pipeline having a first stage configured to receive the input dataset, a plurality of intermediate stages and a final stage, each stage having a stage input; a computational element; and a stage output; a controller configured to select a size for the fft; and a multiplexer configured to: receive data output from one of the intermediate stages and data output from the final stage; select one of the received outputs in dependence on the selected fft size; and output said selection as a result of the fft on the input dataset.. . ... Imagination Technologies Limited

06/15/17 / #20170168949

Migration of data to register file cache

Methods and migration units for use in out-of-order processors for migrating data to register file caches associated with functional units of the processor to satisfy register read operations. The migration unit receives register read operations to be executed for a particular functional unit. ... Imagination Technologies Limited

06/08/17 / #20170164285

Intelligent power saving

A device comprising: a transceiver operable in a first or second mode and configured to receive packets from a remote device, each packet comprising an indication of whether or not the remote device has a further packet to transmit, wherein: in the first mode the transceiver: (i) sends a polling message in response to receiving the indication of a further packet for transmission; and (ii) listens for that further packet; and in the second mode the transceiver: (i) does not send a polling message in response to receiving the indication of a further packet for transmission; and (ii) listens for packets regardless of whether a received packet indicates that there is a further packet to transmit or not; and a controller configured to monitor an activity level for the transceiver and cause the transceiver to operate in the first or second mode in dependence on the activity level.. . ... Imagination Technologies Limited

06/08/17 / #20170161938

Relightable texture for use in rendering an image

Relightable free-viewpoint rendering allows a novel view of a scene to be rendered and relit based on multiple views of the scene from multiple camera viewpoints. An initial texture can be segmented into materials and an initial coarse colour estimate is determined for each material. ... Imagination Technologies Limited

06/08/17 / #20170161204

Gpu virtualisation

A method of gpu virtualization comprises allocating each virtual machine (or operating system running on a vm) an identifier by the hypervisor and then this identifier is used to tag every transaction deriving from a gpu workload operating within a given vm context (i.e. Every gpu transaction on the system bus which interconnects the cpu, gpu and other peripherals). ... Imagination Technologies Limited

06/08/17 / #20170160947

Digital signal processing data transfer

A technique for transferring data in a digital signal processing system is described. In one example, the digital signal processing system comprises a number of fixed function accelerators, each connected to a memory access controller and each configured to read data from a memory device, perform one or more operations on the data, and write data to the memory device. ... Imagination Technologies Limited

06/01/17 / #20170153871

Modulo hardware generator

A method of generating a hardware design to calculate a modulo value for any input value in a target input range with respect to a constant value d using one or more range reduction stages. The hardware design is generated through an iterative process that selects the optimum component for mapping successively increasing input ranges to the target output range until a component is selected that maps the target input range to the target output range. ... Imagination Technologies Limited

05/11/17 / #20170133104

Hardware monitor to verify memory units

Hardware monitors which can be used by a formal verification tool to exhaustively verify a hardware design for a memory unit. The hardware monitors include detection logic to monitor one or more control signals and/or data signals of an instantiation of the memory unit to detect symbolic writes and symbolic reads. ... Imagination Technologies Limited

05/11/17 / #20170132750

Multi-line image processing with parallel processing units

An image processing system is described herein in which a multi-line processing block has multiple inputs and multiple outputs. In order to provide the multiple outputs the multi-line processing block has multiple processing units operating in parallel on the multiple inputs. ... Imagination Technologies Limited

05/11/17 / #20170132009

Fetch ahead branch target buffer

A fetch ahead branch target buffer is used by a branch predictor to determine a target address for a branch instruction based on a fetch pointer for a previous fetch bundle, i.e. A fetch bundle which is fetched prior to a fetch bundle which includes the branch instruction. ... Imagination Technologies Limited

05/04/17 / #20170124237

Clock verification

Methods and systems for verifying a derived clock using assertion-based verification. The method comprises counting the number of full or half cycles of a fast clock that occur between the rising edge and the falling edge of a slow clock (i.e. ... Imagination Technologies Limited

05/04/17 / #20170123792

Processors supporting endian agnostic simd instructions and methods

A processor includes a register and a load store unit (lsu). The lsu loads data into the register from a memory. ... Imagination Technologies Limited

04/27/17 / #20170118326

Acoustic echo suppression

A controller for an echo suppressor configured to suppress a residual echo of a far-end signal included in a primary error signal, the controller adapted for operation with a primary adaptive filter configured to form a primary echo estimate of the far-end signal included in a microphone signal and an echo canceller configured to cancel that primary echo estimate from the microphone signal so as to form the primary error signal, the controller comprising: a secondary adaptive filter configured to form a secondary echo estimate of the far-end signal comprised in the microphone signal; and control logic operable in at least two modes selected in dependence on a convergence state of the primary adaptive filter, the control logic being configured to control activation of the echo suppressor in dependence one or more transient or steady state decision parameters.. . ... Imagination Technologies Limited

04/27/17 / #20170116756

Systems and methods for processing images of objects using lighting keyframes

An image processing system and method for determining an intrinsic colour component of one or more objects present in a sequence of frames, for use in rendering the object(s), is described. At least some of the frames of the sequence are to be used as lighting keyframes. ... Imagination Technologies Limited

04/27/17 / #20170116755

Systems and methods for processing images of objects using global lighting estimates

An image processing system and method for determining an intrinsic colour component of one or more objects for use in rendering the object(s) is described. One or more input images are received, each representing a view of the object(s), wherein values of the input image(s) are separable into intrinsic colour estimates and corresponding shading estimates. ... Imagination Technologies Limited

04/27/17 / #20170116754

Systems and methods for processing images of objects using coarse intrinsic colour estimates

An image processing system and method for determining an intrinsic colour component of one or more objects for use in rendering the object(s) is described herein. One or more input images are received, each representing a view of the object(s), wherein values of each of the input image(s) are separable into intrinsic colour estimates and corresponding shading estimates. ... Imagination Technologies Limited

04/27/17 / #20170116737

Systems and methods for processing images of objects using coarse surface normal estimates

An image processing system and method for determining a set of surface normals of one or more objects for use in rendering the object(s) is described. One or more input images are received, each representing a view of the object(s). ... Imagination Technologies Limited

04/27/17 / #20170116708

Systems and methods for processing images of objects using interpolation between keyframes

An image processing system and method for determining an intrinsic colour component of one or more objects present in a sequence of frames, for use in rendering the object(s), are described. Some of the frames of the sequence are to be used as lighting keyframes. ... Imagination Technologies Limited

04/20/17 / #20170109134

System and method for rounding reciprocal square root results of input floating point numbers

Methods and systems for determining whether an infinitely precise result of a reciprocal square root operation performed on an input floating point number is greater than a particular number in a first floating point precision. The method includes calculating the square of the particular number in a second lower floating point precision; calculating an error in the calculated square due to the second floating point precision; calculating a first delta value in the first floating point precision by calculating the square multiplied by the input floating point number less one; calculating a second delta value by calculating the error multiplied by the input floating point number plus the first delta value; and outputting an indication of whether the infinitely precise result of the reciprocal square root operation is greater than the particular number based on the second delta term.. ... Imagination Technologies Limited

04/13/17 / #20170103567

Asynchronous and concurrent ray tracing and rasterization rendering processes

. . Rendering systems that can use combinations of rasterization rendering processes and ray tracing rendering processes are disclosed. In some implementations, these systems perform a rasterization pass to identify visible surfaces of pixels in an image. ... Imagination Technologies Limited

04/13/17 / #20170102942

Variable length execution pipeline

In an aspect, a pipelined execution resource can produce an intermediate result for use in an iterative approximation algorithm in an odd number of clock cycles. The pipelined execution resource executes simd requests by staggering commencement of execution of the requests from a simd instruction. ... Imagination Technologies Limited

03/30/17 / #20170091987

Graphics renderer and method for rendering 3d scene in computer graphics using object pointers and depth values

An apparatus and a method for generating 3-dimensional computer graphic images. The image is first sub-divided into a plurality of rectangular areas. ... Imagination Technologies Limited

03/30/17 / #20170091986

Tessellating patches of surface data in tile based computer graphics rendering

A method and system for culling a patch of surface data from one or more tiles in a tile based computer graphics system. A rendering space is divided into a plurality of tiles and a patch of surface data read. ... Imagination Technologies Limited

03/30/17 / #20170090933

Fetch unit for predicting target for subroutine return instructions

A fetch unit configured to, in response to detecting a subroutine call and link instruction, calculate and store a predicted target address for the corresponding subroutine return instruction in a prediction stack, and if certain conditions are met, also cause to be stored in the prediction stack a predicted target instruction bundle. The fetch unit is also configured to, in response to detecting a subroutine return instruction, use the predicted target address in the prediction stack to determine the address of the next instruction bundle to be fetched, and if certain conditions are met, cause any valid predicted target instruction bundle in the prediction stack to be the next bundle to be decoded.. ... Imagination Technologies Limited

03/23/17 / #20170085916

Data compression using spatial decorrelation

Methods and modules for spatial decorrelation and recorrelation are described. A block of data values can be spatially decorrelated in two dimensions efficiently by processing rows of the data values in a particular order such that if the results of spatially decorrelating a first row will be used for column-wise spatial decorrelation of a second row then the data values of the first row are processed in an earlier iteration to that in which the data values of the second row are processed. ... Imagination Technologies Limited

03/16/17 / #20170078684

Method and apparatus for compressing and decompressing data

Methods and apparatus are provided for compressing and decompressing image data by producing two sets of reduced size image data, generating a modulation value for each elementary of the area from the image data, the modulation value encoding information about how to combine the sets of reduced size image data to generate an approximation to the image. In one arrangement, a set of index values is generated corresponding to a set of modulation values for each of the respective elementary areas of a group of elementary areas and these are assigned to each respective group and a second set of index values corresponding to one of the set of first index values for each elementary areas is assigned to each first group of elementary areas. ... Imagination Technologies Limited

03/16/17 / #20170078290

Encryption key updates in wireless communication systems

In an aspect, a wireless communication between a transmitter and a receiver involves determining updated keys according to a key management process for mac layer encryption. Such key is propagated to a transmitter mac and though a receiver key management process to a receiver mac. ... Imagination Technologies Limited

03/16/17 / #20170076420

Task execution in a simd processing unit with parallel groups of processing lanes

A simd processing unit processes a plurality of tasks which each include up to a predetermined maximum number of work items. The work items of a task are arranged for executing a common sequence of instructions on respective data items. ... Imagination Technologies Limited

03/16/17 / #20170075658

Trailing or leading digit anticipator

Methods and leading zero anticipators for estimating the number of leading zeros in a result of a fixed point arithmetic operation which is accurate to within one bit for any signed fixed point numbers. The leading zero anticipator includes an input encoding circuit which generates an encoded input string from the fixed point numbers; a window-based surrogate string generation circuit which generates a surrogate string whose leading one is an estimate of the leading one in the result of the arithmetic operation by examining consecutive windows of the encoded input string and setting corresponding bits of the surrogate string based on the examinations; and a counter circuit configured to estimate the number of leading zeros in the result of the arithmetic operation based on the leading one in the surrogate string.. ... Imagination Technologies Limited

03/09/17 / #20170070338

Synchronising devices using clock signal delay comparison

A circuit for estimating a time difference between a first signal and a second signal, the circuit comprising: a first signal line for receiving the first signal; a delay unit configured to receive the second signal and delay the second signal so as to provide a plurality of delayed versions of the second signal, each delayed version being delayed by a different amount of delay to the other delayed versions; a comparison unit configured to compare each of the delayed versions of the second signal with the first signal so as to identify which of the delayed versions of the second signal is the closest temporally matching signal to the first signal; and a difference estimator configured to estimate the time difference between the first and second signals in dependence on the identified delayed version.. . ... Imagination Technologies Limited

03/09/17 / #20170070337

Synchronising devices using clock signal time difference estimation

A controller for modifying a clock signal from a first clock, the controller comprising: a time comparison unit configured to estimate a time difference between a first signal associated with the first clock and a reference signal received at the controller, wherein the time comparison unit is configured to determine if the time difference is greater than or less than one clock period of the first clock; a first signal modifier configured to modify the clock signal by an integer number of clock periods; and a second signal modifier configured to modify the clock signal by a fraction of the clock period, wherein the controller is configured to select, for modifying the clock signal, the first signal modifier if the time difference is greater than one clock period or the second signal modifier if the time difference is less than one clock period.. . ... Imagination Technologies Limited

03/09/17 / #20170069132

Graphics processing method and system for processing sub-primitives using sub-primitive indications in a control stream

When untransformed display lists are used in a tile-based graphics processing system, the processing involved in deriving sub-primitives may need to be performed in both the geometry processing phase and the rasterisation phase. To reduce the duplication of this processing, the control stream data for a tile includes sub-primitive indications to indicate which sub-primitives are to be used for rendering a tile. ... Imagination Technologies Limited

03/09/17 / #20170069126

Graphics processing method and system for processing sub-primitives using cached graphics data hierarchy

When untransformed display lists are used in a tile-based graphics processing system, the processing involved in deriving sub-primitives may need to be performed in both the geometry processing phase and the rasterisation phase. To reduce the duplication of this processing, the control stream data for a tile includes sub-primitive indications to indicate which sub-primitives are to be used for rendering a tile. ... Imagination Technologies Limited

03/09/17 / #20170068616

Memory address generation for digital signal processing

Memory address generation for digital signal processing is described. In one example, a digital signal processing system-on-chip utilises an on-chip memory space that is shared between functional blocks of the system. ... Imagination Technologies Limited

03/09/17 / #20170068268

Synchronising devices using clock signal delay estimation

A circuit for modifying a clock signal, the circuit comprising: a delay unit configured to receive the clock signal and delay the clock signal so as to output a plurality of delayed versions of the clock signal, each delayed version being delayed by a different amount of delay to the other delayed versions; a delay estimator configured to determine an amount of delay for modifying the clock signal; and a multiplexer configured to: receive each of the delayed versions of the clock signal; select a delayed version of the clock signal in dependence on the determined amount of delay; and output the selected version of the clock signal.. . ... Imagination Technologies Limited

03/02/17 / #20170064087

Nearend speech detector

A nearend speech detector for classifying speech at a communication system receiving a microphone signal from a nearend microphone and a farend signal from a farend communication system, the nearend speech detector comprising: a signal processor configured to transform the microphone and farend signals into the frequency domain; a calculation unit configured to form: an estimate of a nearend signal representing nearend speech present in the microphone signal; and a measure of gain between the microphone signal and the nearend signal; and a signal classifier configured to classify speech at the communication system in dependence on a measure of variance of the gain and a measure of variance of the nearend signal.. . ... Imagination Technologies Limited

03/02/17 / #20170063703

Bandwidth management

A method of estimating available bandwidth for a network comprising a transmitting device and a receiving device, the method comprising: transmitting a media packet stream over the network to the receiving device, the media packets comprising media data for streaming media at the receiving device; transmitting one or more probe packets over the network so as to test the available bandwidth of the network, wherein the probe packets comprise duplicate data of the media packet stream; and determining, during transmission of the probe packets, a measure of network bandwidth availability in dependence on one or more metrics associated with receiving the media packet stream at the receiving device.. . ... Imagination Technologies Limited

03/02/17 / #20170063702

Bandwidth management

A method of transmitting a video packet stream from a transmitting device to a receiving device over a network, the method comprising: transmitting an audio packet stream to the receiving device; determining a measure of network bandwidth in dependence on one or more metrics associated with receiving the audio packet stream at the receiving device; and enabling a video packet stream in dependence on the determined measure.. . ... Imagination Technologies Limited

03/02/17 / #20170061571

Processing of primitive blocks in parallel tiling engine pipes

A tiling unit is arranged to process a sequence of primitive blocks using multiple parallel tiling engine pipes. Each tiling engine pipe processes a respective primitive block, and determines priorities for regions of the respective primitive block based on whether the primitive block overlaps with any of the other primitive blocks currently being processed in the parallel tiling engine pipes. ... Imagination Technologies Limited

02/09/17 / #20170039087

Hardware data structure for tracking ordered transactions

Methods and hardware data structures are provided for tracking ordered transactions in a multi-transactional hardware design using a counter and an indexed table. The data structure includes a counter that keeps track of the number of in-flight transactions; a table that keeps track of the age of each of the in-flight transactions using the counter; and control logic that verifies a transaction response has been received in the correct order (e.g. ... Imagination Technologies Limited

02/02/17 / #20170034059

Identifying a network condition using estimated processor load

A method of identifying a network condition between a pair of network devices, wherein one of the devices comprises a processor capable of executing instructions for forming a media stream for transmission over the network, the method comprising: monitoring a measure of delay in receiving media over the network; monitoring a measure of load on the processor; and identifying a network condition in dependence on a change in the measure of delay and the measure of load on the processor.. . ... Imagination Technologies Limited

02/02/17 / #20170034028

Estimating processor load using frame encoding times

A method of estimating processor load at a device for transmitting a media stream, the device comprising an encoder and a processor capable of executing instructions for the encoder, the method comprising: encoding a first media frame and a second media frame at the encoder; determining a first time period between a first timestamp associated with the first media frame and a second timestamp associated with the second media frame; determining a second time period between a first completion time representing completion of the encoding of the first media frame and a second completion time representing completion of the encoding of the second media frame; and forming a measure of processor load in dependence on a difference between the first and second time periods.. . ... Imagination Technologies Limited

02/02/17 / #20170032500

Denoising filter

A pixel filter includes an input arranged to receive a sequence of pixels, each pixel having an associated pixel value; a filter module arranged to perform a first recursive filter operation in a first direction through the sequence of pixels so as to form a first filtered pixel value for each pixel, and perform a second recursive filter operation in a second direction through the sequence of pixels so as to form a second filtered pixel value for each pixel, wherein the first and second recursive filter operations form a respective filtered pixel value for a given pixel in dependence on the pixel value at that pixel and the filtered pixel value preceding that pixel in their respective direction of operation, the filtered pixel value of the preceding pixel being scaled by a measure of similarity between data associated with that pixel and its preceding pixel; and filter logic configured to, for each pixel of the sequence, combine the first and second filtered pixel values formed in respect of the pixel by the first and second recursive filter operations so as to generate a filter output for the pixel.. . ... Imagination Technologies Limited

02/02/17 / #20170031655

Rounding floating point numbers

Embodiments disclosed pertain to apparatuses, systems, and methods for floating point operations. Disclosed embodiments pertain to a circuit that is capable of processing both a normal and denormal inputs and outputting normal and denormal results, and where a rounding module is used advantageously to reduce operational latency of the circuit.. ... Imagination Technologies Limited

01/12/17 / #20170011544

Atomic memory update unit & methods

In an aspect, an update unit can evaluate condition(s) in an update request and update one or more memory locations based on the condition evaluation. The update unit can operate atomically to determine whether to effect the update and to make the update. ... Imagination Technologies Limited

01/12/17 / #20170010820

Check pointing a shift register using a circular buffer

Hardware structures for check pointing a main shift register one or more times which include a circular buffer used to store the data elements most recently shifted onto the main shift register which has an extra data position for each check point and an extra data position for each restorable point in time; an update history shift register which has a data position for each check point which is used to store information indicating whether the circular buffer was updated in a particular clock cycle; a pointer that identifies a subset of the data positions of the circular buffer as active data positions; and check point generation logic that derives each check point by selecting a subset of the active data positions based on the information stored in the update history shift register.. . ... Imagination Technologies Limited








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