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Invensas Corporation patents


Recent patent applications related to Invensas Corporation. Invensas Corporation is listed as an Agent/Assignee. Note: Invensas Corporation may have other listings under different names/spellings. We're not affiliated with Invensas Corporation, we're just tracking patents.

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Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces

In a vertically integrated microelectronic package, a first microelectronic device is coupled to an upper surface of a circuit platform in a wire bond-only surface area thereof. Wire bond wires are coupled to and extends away from an upper surface of the first microelectronic device. ... Invensas Corporation

Substrate-less stackable package with wire-bond interconnect

A method for making a microelectronic unit includes forming a plurality of wire bonds on a first surface in the form of a conductive bonding surface of a structure comprising a patternable metallic element. The wire bonds are formed having bases joined to the first surface and end surfaces remote from the first surface. ... Invensas Corporation

Microelectronic components with features wrapping around protrusions of conductive vias protruding from through-holes passing through substrates

In a microelectronic component having conductive vias (114) passing through a substrate (104) and protruding above the substrate, conductive features (120e.a, 120e.b) are provided above the substrate that wrap around the conductive vias' protrusions (114′) to form capacitors, electromagnetic shields, and possibly other elements. Other features and embodiments are also provided.. ... Invensas Corporation

Preferred state encoding in non-volatile memories

The invention pertains to non-volatile memory devices, and more particularly to advantageously encoding data in non-volatile devices in a flexible manner by both nvm manufacturers and nvm users. Multiple methods of preferred state encoding (pse) and/or error correction code (ecc) encoding may be used in different pages or blocks in the same nvm device for different purposes which may be dependent on the nature of the data to be stored.. ... Invensas Corporation

Bonded structures

A bonded structure can include a first element having a first interface feature and a second element having a second interface feature. The first interface feature can be bonded to the second interface feature to define an interface structure. ... Invensas Corporation

Conductive barrier direct hybrid bonding

A method for forming a direct hybrid bond and a device resulting from a direct hybrid bond including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, capped by a conductive barrier, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads capped by a second conductive barrier, aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads capped by conductive barriers formed by contact bonding of the first non-metallic region to the second non-metallic region.. . ... Invensas Corporation

Embedded graphite heat spreader for 3dic

A device with thermal control is presented. In some embodiments, the device includes a plurality of die positioned in a stack, each die including a chip, interconnects through a thickness of the chip, metal features of electrically conductive composition connected to the interconnects on a bottom side of the chip, and adhesive or underfill layer on the bottom side of the chip. ... Invensas Corporation

Structures and methods for low temperature bonding using nanoparticles

A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. ... Invensas Corporation

Increased contact alignment tolerance for direct bonding

A bonded device structure including a first substrate having a first set of conductive contact structures, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the contact structures on the first substrate, a second substrate having a second set of conductive contact structures, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the contact structures on the second substrate, and a contact-bonded interface between the first and second set of contact structures formed by contact bonding of the first non-metallic region to the second non-metallic region. The contact structures include elongated contact features, such as individual lines or lines connected in a grid, that are non-parallel on the two substrates, making contact at intersections. ... Invensas Corporation

Wire bonding method and apparatus for electromagnetic interference shielding

Apparatuses relating generally to a microelectronic package having protection from electromagnetic interference are disclosed. In an apparatus thereof, a platform has an upper surface and a lower surface opposite the upper surface and has a ground plane. ... Invensas Corporation

Structure with integrated metallic waveguide

A structure can include a first element and a carrier bonded to the first element along an interface. A waveguide can be defined at least in part along the interface between the first element and the carrier. ... Invensas Corporation

Bonded structures with integrated passive component

In various embodiments, a bonded structure is disclosed. The bonded structure can include an element and a passive electronic component directly bonded to the element without an intervening adhesive. ... Invensas Corporation

Bonded structures with integrated passive component

In various embodiments, a bonded structure is disclosed. The bonded structure can include an element and a passive electronic component having a first surface bonded to the element and a second surface opposite the first surface. ... Invensas Corporation

Microelectronic assembly from processed substrate

Representative implementations of techniques, methods, and formulary provide repairs to processed semiconductor substrates, and associated devices, due to erosion or “dishing” of a surface of the substrates. The substrate surface is etched until a preselected portion of one or more embedded interconnect devices protrudes above the surface of the substrate. ... Invensas Corporation

06/28/18 / #20180182665

Processed substrate

Representative implementations of techniques, methods, and formulary provide repairs to processed semiconductor substrates, and associated devices, due to erosion or “dishing” of a surface of the substrates. The substrate surface is etched until a preselected portion of one or more embedded interconnect devices protrudes above the surface of the substrate. ... Invensas Corporation

06/28/18 / #20180182654

Die tray with channels

Representative implementations of devices and techniques provide a device and a technique for processing integrated circuit (ic) dies. The device comprises a die tray (such as a pick and place tray, for example) for holding the dies during processing. ... Invensas Corporation

06/28/18 / #20180182639

Processing stacked substrates

Representative implementations provide techniques for processing integrated circuit (ic) dies and related devices, in preparation for stacking and bonding the devices. The disclosed techniques provide removal of processing residue from the device surfaces while protecting the underlying layers. ... Invensas Corporation

06/28/18 / #20180180665

Wafer testing without direct probing

The invention pertains to in-wafer testing of integrated circuits. In particular, it pertains to apparatuses and methods for testing small integrated circuits that have pad sizes and pitches that are too small for using conventional wafer probing technology.. ... Invensas Corporation

06/21/18 / #20180177041

Surface integrated waveguides and circuit structures therefor

Apparatus, and corresponding method, relates generally to a microelectronic device. In such an apparatus, a first conductive layer is for providing a lower interior surface of a circuit structure. ... Invensas Corporation

06/21/18 / #20180174995

Bonded structures

A bonded structure can include a first element having a first conductive interface feature and a second element having a second conductive interface feature. An integrated device can be coupled to or formed with the first element or the second element. ... Invensas Corporation

06/21/18 / #20180173600

Self healing compute array

This disclosure pertains to hardware compute arrays (sometimes called systolic arrays) for applications such as artificial intelligence (ai), machine learning (ml), digital signal processing (dsp), graphics processing units (gpus), and other computationally intensive applications. More particularly, it pertains to novel and advantageous architecture innovations for efficiently and inexpensively implementing such arrays using multiple integrated circuits. ... Invensas Corporation

05/24/18 / #20180146557

Pressing of wire bond wire tips to provide bent-over tips

In a method for forming a microelectronic device, a substrate is loaded into a mold press. The substrate has a first surface and a second surface. ... Invensas Corporation

05/24/18 / #20180145105

Image sensor device

An image sensor device, as well as methods therefor, is disclosed. This image sensor device includes a substrate having bond pads. ... Invensas Corporation

05/10/18 / #20180130766

Adhesive with self-connecting interconnects

An adhesive with self-connecting interconnects is provided. The adhesive layer provides automatic 3d joining of microelectronic components with a conductively self-adjusting anisotropic matrix. ... Invensas Corporation

05/10/18 / #20180130757

Folding thin systems

A foldable microelectronic assembly and a method for forming the same are provided. One or more packages comprising encapsulated microelectronic elements are formed, along with a compliant layer. ... Invensas Corporation

05/10/18 / #20180130717

Integrated circuits protected by substrates with cavities, and methods of manufacture

Dies (110) with integrated circuits are attached to a wiring substrate (120), possibly an interposer, and are protected by a protective substrate (410) attached to a wiring substrate. The dies are located in cavities in the protective substrate (the dies may protrude out of the cavities). ... Invensas Corporation

05/10/18 / #20180130691

Method and apparatus for stacking devices in an integrated circuit assembly

Methods and apparatuses for stacking devices in an integrated circuit assembly are provided. A tray for supporting multiple dies of a semiconductor material enables both topside processing and bottom side processing of the dies. ... Invensas Corporation

05/03/18 / #20180124927

Contact structures with porous networks for solder connections, and methods of fabricating same

A contact pad includes a solder-wettable porous network (310) which wicks the molten solder (130) and thus restricts the lateral spread of the solder, thus preventing solder bridging between adjacent contact pads.. . ... Invensas Corporation

05/03/18 / #20180121283

Enhanced memory reliability in stacked memory devices

The invention pertains to semiconductor memories, and more particularly to enhancing the reliability of stacked memory devices. Apparatuses and methods are described for implementing raid-style error correction to increase the reliability of the stacked memory devices.. ... Invensas Corporation

04/19/18 / #20180108612

Embedded vialess bridges

Embedded vialess bridges are provided. In an implementation, discrete pieces containing numerous conduction lines or wires in a 3-dimensional bridge piece are embedded where needed in a main substrate to provide dense arrays of signal, power, and electrical ground wires below the surface of the main substrate. ... Invensas Corporation

04/12/18 / #20180102578

Flipped rf filters and components

Flipped radio frequency (rf) and microwave filters and components for compact package assemblies are provided. An example rf filter is constructed by depositing a conductive trace, such as a redistribution layer, onto a flat surface of a substrate, to form an rf filter element. ... Invensas Corporation

04/12/18 / #20180102331

Interconnections for a substrate associated with a backside reveal

An apparatus relating generally to a substrate is disclosed. In this apparatus, a post extends from the substrate. ... Invensas Corporation

04/12/18 / #20180102251

Direct-bonded native interconnects and active base die

Direct-bonded native interconnects and active base dies are provided. In a microelectronic architecture, active dies or chiplets connect to an active base die via their core-level conductors. ... Invensas Corporation

04/05/18 / #20180096973

System and method for providing 3d wafer assembly with known-good-dies

Systems and methods for providing 3d wafer assembly with known-good-dies are provided. An example method compiles an index of dies on a semiconductor wafer and removes the defective dies to provide a wafer with dies that are all operational. ... Invensas Corporation

04/05/18 / #20180096960

Tall and fine pitch interconnects

Representative implementations of devices and techniques provide interconnect structures and components for coupling various carriers, printed circuit board (pcb) components, integrated circuit (ic) dice, and the like, using tall and/or fine pitch physical connections. Multiple layers of conductive structures or materials are arranged to form the interconnect structures and components. ... Invensas Corporation

04/05/18 / #20180096931

Interface structures and methods for forming same

A stacked and electrically interconnected structure is disclosed. The stacked structure can include a first element comprising a first contact pad and a second element comprising a second contact pad. ... Invensas Corporation

03/22/18 / #20180082935

Low cte interposer

An interconnection component includes a first support portion, a second support portion, a redistribution layer and a passive device, wherein at least one of the first and second support portions is comprised of a semiconductor material. The first support portion includes first and second opposed major surfaces and a plurality of first conductive vias extending through the first support portion substantially perpendicular to major surfaces. ... Invensas Corporation

03/22/18 / #20180082916

Fine pitch bva using reconstituted wafer with area array accessible for testing

A method for simultaneously making a plurality of microelectronic packages by forming an electrically conductive redistribution structure along with a plurality of microelectronic element attachment regions on a carrier. The attachment regions being spaced apart from one another and overlying the carrier. ... Invensas Corporation

03/15/18 / #20180076278

Making electrical components in handle wafers of integrated circuit packages

A method for making an integrated circuit package includes providing a handle wafer having a first region defining a cavity. A capacitor is formed in the first region. ... Invensas Corporation

03/08/18 / #20180068930

Ssi pop

An assembly can include a first microelectronic package and a circuit structure comprising a plurality of dielectric layers and electrically conductive features thereon. The first package can include a substrate having a plurality of first contacts at a first or second surface thereof and a plurality of second contacts at the first surface thereof, and a first microelectronic element having a plurality of element contacts at a front surface thereof. ... Invensas Corporation

03/01/18 / #20180061774

Wire bond wires for interference shielding

Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. ... Invensas Corporation

02/15/18 / #20180047704

Multi-chip package with interconnects extending through logic chip

A microelectronic package includes a first microelectronic element comprising logic circuitry which is flip-chip mounted to a substrate, the substrate having terminals for connection with a circuit panel or other external component. A second microelectronic element overlies a rear surface of the first microelectronic element and has contacts electrically coupled with the substrate through electrically conductive interconnects extending through a region of the first microelectronic element. ... Invensas Corporation

02/08/18 / #20180040589

Microelectronic packages and assemblies with repeaters

A microelectronic assembly includes a circuit panel having a plurality of first contacts at a major surface thereof. One or more microelectronic packages comprise a plurality of microelectronic elements, the one or more packages having terminals electrically coupled with the first contacts, wherein each package includes at least one microelectronic element having a face, and element contacts at the face which are electrically coupled with the plurality of terminals. ... Invensas Corporation

02/08/18 / #20180040587

Vertical memory module enabled by fan-out redistribution layer

Vertical memory modules enabled by fan-out redistribution layer(s) (rdls) are provided. Memory dies may be stacked with each die having a signal pad directed to a sidewall of the die. ... Invensas Corporation

02/08/18 / #20180040572

Warpage balancing in thin packages

Representative implementations of devices and techniques provide reinforcement for a carrier or a package. A reinforcement layer is added to a surface of the carrier, often a bottom surface of the carrier that is generally under-utilized except for placement of terminal connections. ... Invensas Corporation

02/08/18 / #20180040544

Multi-surface edge pads for vertical mount packages and methods of making package stacks

Multi-surface edge pads for vertical mount packages and methods of making package stacks are provided. Example substrates for vertical surface mount to a motherboard have multi-surface edge pads. ... Invensas Corporation

02/01/18 / #20180033764

Wire bonding method and apparatus for electromagnetic interference shielding

Apparatuses relating generally to a microelectronic package having protection from electromagnetic interference are disclosed. In an apparatus thereof, a platform has an upper surface and a lower surface opposite the upper surface and has a ground plane. ... Invensas Corporation

01/25/18 / #20180026019

Package-on-package devices with wlp components with dual rdls for surface mount dies and methods therefor

Package-on-package (“pop”) devices with wlp (“wlp”) components with dual rdls (“rdls”) for surface mount dies and methods therefor. In a pop, a first ic die surface mount coupled to an upper surface of a package substrate. ... Invensas Corporation

01/25/18 / #20180026018

Package-on-package devices with multiple levels and methods therefor

Package-on-package (“pop”) devices with multiple levels and methods therefor are disclosed. In a pop device, a first integrated circuit die is surface mount coupled to an upper surface of a package substrate. ... Invensas Corporation

01/25/18 / #20180026017

Dies-on-package devices and methods therefor

Dies-on-package devices and methods therefor are disclosed. In a dies-on-package device, a first ic die is surface mount coupled to an upper surface of a package substrate. ... Invensas Corporation

01/25/18 / #20180026016

Package-on-package devices with upper rdl of wlps and methods therefor

Package-on-package (“pop”) devices with upper rdls of wlp (“wlp”) components and methods therefor are disclosed. In a pop device, a first ic die is surface mount coupled to an upper surface of the package substrate. ... Invensas Corporation

01/25/18 / #20180026011

Package-on-package devices with same level wlp components and methods therefor

Package-on-package (“pop”) devices with same level wafer-level packaged (“wlp”) components and methods therefor are disclosed. In a pop device, a first integrated circuit die is surface mount coupled to an upper surface of a package substrate. ... Invensas Corporation

01/25/18 / #20180026007

Package-on-package assembly with wire bond vias

A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. ... Invensas Corporation

01/25/18 / #20180025987

Wafer-level packaged components and methods therefor

Wafer-level packaged components are disclosed. In a wafer-level-packaged, an integrated circuit die has first contacts in an inner third region of a surface of the integrated circuit die. ... Invensas Corporation

01/18/18 / #20180019191

Conductive connections, structures with such connections, and methods of manufacture

A solder connection may be surrounded by a solder locking layer (1210, 2210) and may be recessed in a hole (1230) in that layer. The recess may be obtained by evaporating a vaporizable portion (1250) of the solder connection. ... Invensas Corporation

12/28/17 / #20170374738

Interposers and fabrication methods that use nanoparticle inks and magnetic fields

Interposer circuitry (130) is formed on a possibly sacrificial substrate (210) from a porous core (130′) covered by a conductive coating (130″) which increases electrical conductance. The core is printed from nanoparticle ink. ... Invensas Corporation

12/28/17 / #20170374734

Stacked transmission line

A stacked, multi-layer transmission line is provided. The stacked transmission line includes at least a pair of conductive traces, each conductive trace having a plurality of conductive stubs electrically coupled thereto. ... Invensas Corporation

12/28/17 / #20170373033

Deformable conductive contacts

Deformable conductive contacts are provided. A plurality of deformable contacts on a first substrate may be joined to a plurality of conductive pads on a second substrate during die level or wafer level assembly of microelectronics. ... Invensas Corporation

12/28/17 / #20170372994

Porous alumina templates for electronic packages

Interposers and methods of making the same are disclosed herein. In one embodiment, an interposer includes a region having first and second oppositely facing surfaces and a plurality of pores, each pore extending in a first direction from the first surface towards the second surface, wherein alumina extends along a wall of each pore; a plurality of electrically conductive connection elements extending in the first direction, consisting essentially of aluminum and being electrically isolated from one another by at least the alumina; a first conductive path provided at the first surface for connection with a first component external to the interposer; and a second conductive path provided at the second surface for connection with a second component external to the interposer, wherein the first and second conductive paths are electrically connected through at least some of the connection elements.. ... Invensas Corporation

12/21/17 / #20170365546

Method and structures for heat dissipating interposers

An interconnect element includes a semiconductor or insulating material layer that has a first thickness and defines a first surface; a thermally conductive layer; a plurality of conductive elements; and a dielectric coating. The thermally conductive layer includes a second thickness of at least 10 microns and defines a second surface of the interconnect element. ... Invensas Corporation

11/09/17 / #20170323867

Nanoscale interconnect array for stacked dies

A microelectronic assembly including an insulating layer having a plurality of nanoscale conductors disposed in a nanoscale pitch array therein and a pair of microelectronic elements is provided. The nanoscale conductors can form electrical interconnections between contacts of the microelectronic elements while the insulating layer can mechanically couple the microelectronic elements together.. ... Invensas Corporation

11/09/17 / #20170323667

Tfd i/o partition for high-speed, high-density applications

A microelectronic package can include a substrate having first and second surfaces, first, second, and third microelectronic elements each having a surface facing the first surface, terminals exposed at the second surface, and leads electrically connected between contacts of each microelectronic element and the terminals. The substrate can have first, second, and third spaced-apart apertures having first, second, and third parallel axes extending in directions of the lengths of the apertures. ... Invensas Corporation

10/26/17 / #20170310322

On-chip impedance network with digital coarse and analog fine tuning

System and method for providing precision a self calibrating resistance circuit is described that provides for matching a reference resistor using dynamically configurable resistance networks. The resistor network is coupled to the connection, wherein the resistor network provides a configurable resistance across the connection. ... Invensas Corporation

10/26/17 / #20170309518

Structures and methods for reliable packages

A device and method of forming the device that includes cavities formed in a substrate of a substrate device, the substrate device also including conductive vias formed in the substrate. Chip devices, wafers, and other substrate devices can be mounted to the substrate device. ... Invensas Corporation

10/12/17 / #20170294410

Microelectronic packages having stacked die and wire bond interconnects

A microelectronic package includes at least one microelectronic element having a front surface defining a plane, the plane of each microelectronic element parallel to the plane of any other microelectronic element. An encapsulation region overlying edge surfaces of each microelectronic element has first and second major surfaces substantially parallel to the plane of each microelectronic element and peripheral surfaces between the major surfaces. ... Invensas Corporation

10/12/17 / #20170294321

Carrier-less silicon interposer using photo patterned polymer as substrate

A component, e.g., interposer has first and second opposite sides, conductive elements at the first side and terminals at the second side. The terminals can connect with another component, for example. ... Invensas Corporation

09/28/17 / #20170278787

Microelectronic components with features wrapping around protrusions of conductive vias protruding from through-holes passing through substrates

In a microelectronic component having conductive vias (114) passing through a substrate (104) and protruding above the substrate, conductive features (120e.a, 120e.b) are provided above the substrate that wrap around the conductive vias' protrusions (114′) to form capacitors, electromagnetic shields, and possibly other elements. Other features and embodiments are also provided.. ... Invensas Corporation

09/07/17 / #20170256519

Stub minimization for wirebond assemblies without windows

A microelectronic assembly (300) or system (1500) includes at least one microelectronic package (100) having a microelectronic element (130) mounted face up above a first surface (108) of a substrate (102), one or more columns (138, 140) of contacts (132) extending in a first direction (142) along the microelectronic element front face. Columns (104a, 105b, 107a, 107b) of terminals (105 107) exposed at a second surface (110) of the substrate extend in the first direction. ... Invensas Corporation

09/07/17 / #20170256492

Ultra high performance interposer

An interconnection component includes a semiconductor material layer having a first surface and a second surface opposite the first surface and spaced apart in a first direction. At least two metalized vias extend through the semiconductor material layer. ... Invensas Corporation

08/31/17 / #20170250161

Correction die for wafer/die stack

Representative implementations of devices and techniques provide correction for a defective die in a wafer-to-wafer stack or a die stack. A correction die is coupled to a die of the stack with the defective die. ... Invensas Corporation

08/31/17 / #20170250140

High performance compliant substrate

A substrate structure is presented that can include a porous polyimide material and electrodes formed in the porous polyimide material. In some examples, a method of forming a substrate can include depositing a barrier layer on a substrate; depositing a resist over the barrier layer; patterning and etching the resist; forming electrodes; removing the resist; depositing a porous polyimide aerogel; depositing a dielectric layer over the aerogel material; polishing a top side of the interposer to expose the electrodes; and removing the substrate from the bottom side of the interposer.. ... Invensas Corporation

08/24/17 / #20170243761

Low cte component with wire bond interconnects

A component such as an interposer or microelectronic element can be fabricated with a set of vertically extending interconnects of wire bond structure. Such method may include forming a structure having wire bonds extending in an axial direction within one of more openings in an element and each wire bond spaced at least partially apart from a wall of the opening within which it extends, the element consisting essentially of a material having a coefficient of thermal expansion (“cte”) of less than 10 parts per million per degree celsius (“ppm/° c.”). ... Invensas Corporation

08/17/17 / #20170236794

Multichip modules and methods of fabrication

In a multi-chip module (mcm), a “super” chip (110n) is attached to multiple “plain” chips (110f′ “super” and “plain” chips can be any chips). The super chip is positioned above the wiring board (wb) but below at least some of plain chips (110f). ... Invensas Corporation

07/27/17 / #20170212848

Method for reduced load memory module

A method for reducing load in a memory module. In such a method, a plurality of memory chips are coupled to a circuit platform. ... Invensas Corporation

07/20/17 / #20170207159

Porous alumina templates for electronic packages

Interposers and methods of making the same are disclosed herein. In one embodiment, an interposer includes a region having first and second oppositely facing surfaces and a plurality of pores, each pore extending in a first direction from the first surface towards the second surface, wherein alumina extends along a wall of each pore; a plurality of electrically conductive connection elements extending in the first direction, consisting essentially of aluminum and being electrically isolated from one another by at least the alumina; a first conductive path provided at the first surface for connection with a first component external to the interposer; and a second conductive path provided at the second surface for connection with a second component external to the interposer, wherein the first and second conductive paths are electrically connected through at least some of the connection elements.. ... Invensas Corporation

07/13/17 / #20170200877

Light emitting diode device with reconstituted led components on substrate

Disclosed herein are technologies for forming a plurality of known good die (kgd)-light emitting diode (led) components into a larger size optically coherent led chips or devices. This abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. ... Invensas Corporation

07/13/17 / #20170200696

Multi-chip package with interconnects extending through logic chip

A microelectronic package includes a first microelectronic element comprising logic circuitry which is flip-chip mounted to a substrate, the substrate having terminals for connection with a circuit panel or other external component. A second microelectronic element overlies a rear surface of the first microelectronic element and has contacts electrically coupled with the substrate through electrically conductive interconnects extending through a region of the first microelectronic element. ... Invensas Corporation

07/06/17 / #20170194373

Method of fabricating low cte interposer without tsv structure

A microelectronic assembly including a dielectric region, a plurality of electrically conductive elements, an encapsulant, and a microelectronic element are provided. The encapsulant may have a coefficient of thermal expansion (cte) no greater than twice a cte associated with at least one of the dielectric region or the microelectronic element.. ... Invensas Corporation

07/06/17 / #20170194281

Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces

In a vertically integrated microelectronic package, a first microelectronic device is coupled to an upper surface of a circuit platform in a wire bond-only surface area thereof. Wire bond wires are coupled to and extends away from an upper surface of the first microelectronic device. ... Invensas Corporation

07/06/17 / #20170194279

Structures and methods for low temperature bonding using nanoparticles

A method of making an assembly can include forming a first conductive element at a first surface of a substrate of a first component, forming conductive nanoparticles at a surface of the conductive element by exposure to an electroless plating bath, juxtaposing the surface of the first conductive element with a corresponding surface of a second conductive element at a major surface of a substrate of a second component, and elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles cause metallurgical joints to form between the juxtaposed first and second conductive elements. The conductive nanoparticles can be disposed between the surfaces of the first and second conductive elements. ... Invensas Corporation

06/29/17 / #20170186801

Microelectronic package with horizontal and vertical interconnections

In a microelectronic package, a first wire bond wire is coupled to an upper surface of a substrate. A first bond mass is coupled to another end of the first wire bond wire. ... Invensas Corporation

06/29/17 / #20170186730

System and method for providing 3d wafer assembly with known-good-dies

Systems and methods for providing 3d wafer assembly with known-good-dies are provided. An example method compiles an index of dies on a semiconductor wafer and removes the defective dies to provide a wafer with dies that are all operational. ... Invensas Corporation

06/29/17 / #20170186474

Dual-channel dimm

A dual inline memory module can include a module card having first and second opposed surfaces and a plurality of microelectronic elements each having a surface facing a surface of the module card. The module card can have a plurality of parallel edge contacts, the edge contacts including first and second contacts, the first and second contacts configured to carry command and address information and data signals corresponding to first and second memory channels, respectively, the first memory channel being independent from the second memory channel. ... Invensas Corporation

06/22/17 / #20170179081

Flipped die stacks with multiple rows of leadframe interconnects

Stacked microelectronic packages comprise microelectronic elements each having a contact-bearing front surface and edge surfaces extending away therefrom, and a dielectric encapsulation region contacting an edge surface. The encapsulation defines first and second major surfaces of the package and a remote surface between the major surfaces. ... Invensas Corporation

06/22/17 / #20170179046

High yield substrate assembly

In accordance with a first method embodiment, a plurality of piggyback substrates are attached to a carrier substrate. The edges of the plurality of the piggyback substrates are bonded to one another. ... Invensas Corporation

06/22/17 / #20170178958

Method and structures for via substrate repair and assembly

A component can include a substrate having an opening extending between first and second surfaces thereof, and an electrically conductive via having first and second portions. The first portion can include a first layer structure extending within the opening and at least partially along an inner wall of the opening, and a first principal conductor extending within the opening and at least partially overlying the first layer structure. ... Invensas Corporation

06/15/17 / #20170171986

Multilayer wiring board for an electronic device

An electronic assembly is disclosed that includes a flexible insulating film, a semiconductor component that has a thickness of less than 50 micrometers, a conductive interconnect extending through the flexible insulating film, a second patterned metal wiring film adjacent, and a third patterned metal wiring film. The second patterned metal wiring film is electrically coupled with the third patterned metal wiring film through the conductive interconnect. ... Invensas Corporation

06/15/17 / #20170171003

Via structure for signal equalization

An apparatus relating generally to a substrate is disclosed. In such an apparatus, the substrate has a first surface and a second surface opposite the first surface. ... Invensas Corporation

06/15/17 / #20170170341

Integrated circuit device

An integrally packaged optronic integrated circuit device including an integrated circuit die containing at least one of a radiation emitter and radiation receiver and having a transparent packaging layer overlying a surface of the die, the transparent packaging layer having an opaque coating adjacent to edges of the layer.. . ... Invensas Corporation

06/15/17 / #20170170121

Embedded vialess bridges

Embedded vialess bridges are provided. In an implementation, discrete pieces containing numerous conduction lines or wires in a 3-dimensional bridge piece are embedded where needed in a main substrate to provide dense arrays of signal, power, and electrical ground wires below the surface of the main substrate. ... Invensas Corporation

06/15/17 / #20170170031

Fan-out wafer-level packaging using metal foil lamination

Fan-out wafer-level packaging (wlp) using metal foil lamination is provided. An example wafer-level package incorporates a metal foil, such as copper (cu), to relocate bonding pads in lieu of a conventional deposited or plated rdl. ... Invensas Corporation

06/01/17 / #20170154875

Multiple bond via arrays of different wire heights on a same substrate

Apparatuses relating generally to a substrate are disclosed. In such an apparatus, first wire bond wires (“first wires”) extend from a surface of the substrate. ... Invensas Corporation

05/18/17 / #20170141094

Microelectronic package with stacked microelectronic units and method for manufacture thereof

A microelectronic package may include a first microelectronic unit including a semiconductor chip having first chip contacts, an encapsulant contacting an edge of the semiconductor chip, and first unit contacts exposed at a surface of the encapsulant and electrically connected with the first chip contacts. The package may include a second microelectronic unit including a semiconductor chip having second chip contacts at a surface thereof, and an encapsulant contacting an edge of the chip of the second unit and having a surface extending away from the edge. ... Invensas Corporation

05/18/17 / #20170141083

Packaged microelectronic device for a package-on-package device

Methods and apparatuses relate generally to a packaged microelectronic device for a package-on-package device (“pop”) with enhanced tolerance for warping. In one such packaged microelectronic device, interconnect structures are in an outer region of the packaged microelectronic device. ... Invensas Corporation

05/18/17 / #20170141042

'rdl-first' packaged microelectronic device for a package-on-package device

Methods and apparatuses relate generally to a packaged microelectronic device for a package-on-package device (“pop”) with enhanced tolerance for warping. In one such packaged microelectronic device, at least one redistribution layer includes first interconnect pads on a lower surface and second interconnect pads on an upper surface of the at least one redistribution layer. ... Invensas Corporation

05/18/17 / #20170141020

Stiffened wires for offset bva

A component can include a generally planar element, a reinforcing dielectric layer overlying the generally planar element, an encapsulation overlying the reinforcing dielectric layer, and a plurality of wire bonds. Each wire bond can have a tip at a major surface of the encapsulation. ... Invensas Corporation

05/11/17 / #20170133081

High-bandwidth memory application with controlled impedance loading

A microelectronic assembly can include an address bus comprising a plurality of signal conductors each passing sequentially through first, second, third, and fourth connection regions, and first and second microelectronic packages. The first microelectronic package can include first and second microelectronic elements, and the second microelectronic package can include third and fourth microelectronic elements. ... Invensas Corporation

05/04/17 / #20170125331

Interconnection substrates for interconnection between circuit modules, and methods of manufacture

An interposer (110) has contact pads at the top and/or bottom surfaces for connection to circuit modules (e.g. Ics 112). ... Invensas Corporation

04/27/17 / #20170117260

Microelectronic package for wafer-level chip scale packaging with fan-out

Apparatuses and methods relating generally to a microelectronic package for wafer-level chip scale packaging with fan-out are disclosed. In an apparatus, there is a substrate having an upper surface and a lower surface opposite the upper surface. ... Invensas Corporation

04/27/17 / #20170117243

Anchoring structure of fine pitch bva

A microelectronic package can include a substrate having a first surface and a second surface opposite therefrom, the substrate having a first conductive element at the first surface, and a plurality of wire bonds, each of the wire bonds having a base electrically connected to a corresponding one of the first conductive elements and having a tip remote from the base, each wire bond having edge surfaces extending from the tip toward the base. The microelectronic package can also include an encapsulation having a major surface facing away from the first surface of the substrate, the encapsulation having a recess extending from the major surface in a direction toward the first surface of the substrate, the tip of a first one of the wire bonds being disposed within the recess, and an electrically conductive layer overlying an inner surface of the encapsulation exposed within the recess, the electrically conductive layer overlying and electrically connected with the tip of the first one of the wire bonds.. ... Invensas Corporation

04/27/17 / #20170117231

Wire bond wires for interference shielding

Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. ... Invensas Corporation

04/27/17 / #20170117030

Dram adjacent row disturb mitigation

The invention pertains to mitigation of row hammer attacks in dram integrated circuits. Apparatus and methods are disclosed for an embedded target row refresh (trr) solution with modest overhead. ... Invensas Corporation

04/13/17 / #20170103968

Embedded wire bond wires

Apparatuses relating generally to a vertically integrated microelectronic package are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface. ... Invensas Corporation

04/13/17 / #20170103957

Fan-out wafer-level packaging using metal foil lamination

Fan-out wafer-level packaging (wlp) using metal foil lamination is provided. An example wafer-level package incorporates a metal foil, such as copper (cu), to relocate bonding pads in lieu of a conventional deposited or plated rdl. ... Invensas Corporation

04/06/17 / #20170099733

Interposers and fabrication methods that use nanoparticle inks and magnetic fields

Interposer circuitry (130) is formed on a possibly sacrificial substrate (210) from a porous core (130′) covered by a conductive coating (130″) which increases electrical conductance. The core is printed from nanoparticle ink. ... Invensas Corporation

04/06/17 / #20170099474

Hd color imaging using monochromatic cmos image sensors integrated in 3d package

Hd color video using monochromatic cmos image sensors integrated in a 3d package is provided. An example 3dic package for color video includes a beam splitter to partition received light of an image stream into multiple light outputs. ... Invensas Corporation

04/06/17 / #20170096329

Microelectronic interconnect element with decreased conductor spacing

A microelectronic interconnect element can include a plurality of first metal lines and a plurality of second metal lines interleaved with the first metal lines. Each of the first and second metal lines has a surface extending within the same reference plane. ... Invensas Corporation

03/30/17 / #20170092620

Capacitive coupling of integrated circuit die components

Capacitive coupling of integrated circuit die components and other conductive areas is provided. Each component to be coupled has a surface that includes at least one conductive area, such as a metal pad or plate. ... Invensas Corporation

03/23/17 / #20170084584

Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate

A microelectronic assembly can include a circuit panel having first and second panel contacts at respective first and second surfaces thereof, and first and second microelectronic packages each having terminals mounted to the respective panel contacts. Each package can include a microelectronic element having a face and contacts thereon, a substrate having first and second surfaces, and terminals on the second surface configured for connecting the package with an external component. ... Invensas Corporation

03/23/17 / #20170084582

Compact semiconductor package and related methods

A method of forming a semiconductor package includes providing a substrate having one or more conductive elements disposed therein. Each conductive element extends from a first surface of the substrate toward a second surface of the substrate extending beyond the second surface. ... Invensas Corporation

03/23/17 / #20170084539

Integrated circuit assemblies with rigid layers used for protection against mechanical thinning and for other purposes, and methods of fabricating such assemblies

Die (110) and/or undiced wafers and/or multichip modules (mcms) are attached on top of an interposer (120) or some other structure (e.g. Another integrated circuit) and are covered by an encapsulant (160). ... Invensas Corporation

03/16/17 / #20170077076

Making electrical components in handle wafers of integrated circuit packages

A method for making an integrated circuit package includes providing a handle wafer having a first region defining a cavity. A capacitor is formed in the first region. ... Invensas Corporation

03/16/17 / #20170077016

Wafer-level flipped die stacks with leadframes or metal foil interconnects

An assembly includes a plurality of stacked encapsulated microelectronic packages, each package including a microelectronic element having a front surface with a plurality of chip contacts at the front surface and edge surfaces extending away from the front surface. An encapsulation region of each package contacts at least one edge surface and extends away therefrom to a remote surface of the package. ... Invensas Corporation

03/09/17 / #20170069599

Microelectronic package with horizontal and vertical interconnections

In a microelectronic package, a first wire bond wire is coupled to an upper surface of a substrate. A first bond mass is coupled to another end of the first wire bond wire. ... Invensas Corporation

03/09/17 / #20170069595

3d-joining of microelectronic components with conductively self-adjusting anisotropic matrix

3d joining of microelectronic components and a conductively self-adjusting anisotropic matrix are provided. In an implementation, an adhesive matrix automatically makes electrical connections between two surfaces that have electrical contacts, and bonds the two surfaces together. ... Invensas Corporation

03/09/17 / #20170069591

Wafer-level packaging using wire bond wires in place of a redistribution layer

An apparatus relates generally to a microelectronic package. In such an apparatus, a microelectronic die has a first surface, a second surface opposite the first surface, and a sidewall surface between the first and second surfaces. ... Invensas Corporation

03/09/17 / #20170069575

Microelectronic assembly with redistribution structure formed on carrier

A microelectronic assembly can be made by forming a redistribution structure supported on a carrier, the structure including two or more layers of deposited dielectric material and two or more electrically conductive layers and including conductive features such as pads and traces electrically interconnected by vias. Electrical connectors may project above a second surface of the structure opposite an interconnection surface of the redistribution structure adjacent to the carrier. ... Invensas Corporation

03/02/17 / #20170062389

Stub minimization using duplicate sets of terminals for wirebond assemblies without windows

A microelectronic assembly can include a microelectronic package connected with a circuit panel. The package has a microelectronic element having a front face facing away from a substrate of the package, and electrically connected with the substrate through conductive structure extending above the front face. ... Invensas Corporation

02/23/17 / #20170053886

Tall and fine pitch interconnects

Representative implementations of devices and techniques provide interconnect structures and components for coupling various carriers, printed circuit board (pcb) components, integrated circuit (ic) dice, and the like, using tall and/or fine pitch physical connections. Multiple layers of conductive structures or materials are arranged to form the interconnect structures and components. ... Invensas Corporation

02/23/17 / #20170053857

Low cte interposer

An interconnection component includes a first support portion has a plurality of first conductive vias extending therethrough substantially perpendicular to surfaces thereof such that each via has a first end adjacent a first surface and a second end adjacent a second surface. A second support portion has a plurality of second conductive vias extending therethrough substantially perpendicular to surfaces thereof such that each via has a first end adjacent the first surface and a second end adjacent the second surface. ... Invensas Corporation

02/16/17 / #20170047307

Structures and methods for low temperature bonding

A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. ... Invensas Corporation

02/09/17 / #20170040270

Methods and structures to repair device warpage

A method of processing an interconnection element can include providing a substrate element having front and rear opposite surfaces and electrically conductive structure, a first dielectric layer overlying the front surface and a plurality of conductive contacts at a first surface of the first dielectric layer, and a second dielectric layer overlying the rear surface and having a conductive element at a second surface of the second dielectric layer. The method can also include removing a portion of the second dielectric layer so as to reduce the thickness of the portion, and to provide a raised portion of the second dielectric layer having a first thickness and a lowered portion having a second thickness. ... Invensas Corporation

02/09/17 / #20170040268

Interconnections for a substrate associated with a backside reveal

An apparatus relating generally to a substrate is disclosed. In this apparatus, a post extends from the substrate. ... Invensas Corporation

02/09/17 / #20170040237

Integrated circuits protected by substrates with cavities, and methods of manufacture

Dies (110) with integrated circuits are attached to a wiring substrate (120), possibly an interposer, and are protected by a protective substrate (410) attached to a wiring substrate. The dies are located in cavities in the protective substrate (the dies may protrude out of the cavities). ... Invensas Corporation

02/02/17 / #20170033088

Stacked die integrated circuit

An apparatus relates generally to an integrated circuit package. In such an apparatus, a package substrate has a first plurality of via structures extending from a lower surface of the package substrate to an upper surface of the package substrate. ... Invensas Corporation

01/26/17 / #20170025390

Microelectronic element with bond elements to encapsulation surface

A microelectronic structure includes a semiconductor having conductive elements at a first surface. Wire bonds have bases joined to the conductive elements and free ends remote from the bases, the free ends being remote from the substrate and the bases and including end surfaces. ... Invensas Corporation

01/19/17 / #20170018529

Flipped die stack

A microelectronic assembly includes a stack of semiconductor chips each having a front surface defining a respective plane of a plurality of planes. A chip terminal may extend from a contact at a front surface of each chip in a direction towards the edge surface of the respective chip. ... Invensas Corporation

01/19/17 / #20170018517

Microelectronic assemblies formed using metal silicide, and methods of fabrication

Two microelectronic components (110, 120), e.g. A die and an interposer, are bonded to each other. ... Invensas Corporation

01/19/17 / #20170018510

Microelectronic assemblies with cavities, and methods of fabrication

Die (110) are attached to an interposer (420), and the interposer/die assembly is placed into a lid cavity (510). The lid (210) is attached to the top of the assembly, possibly to the encapsulant (474) at the top. ... Invensas Corporation

01/19/17 / #20170018485

Flipped die stack assemblies with leadframe interconnects

A microelectronic assembly includes a stack of microelectronic elements, e.g., semiconductor chips, each having a front surface defining a respective plane of a plurality of planes. A leadframe interconnect joined to a contact at a front surface of each chip may extend to a position beyond the edge surface of the respective microelectronic element. ... Invensas Corporation

01/12/17 / #20170012021

Structures and methods for low temperature bonding

A method of making an assembly can include forming a first conductive element at a first surface of a substrate of a first component, forming conductive nanoparticles at a surface of the conductive element by exposure to an electroless plating bath, juxtaposing the surface of the first conductive element with a corresponding surface of a second conductive element at a major surface of a substrate of a second component, and elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles cause metallurgical joints to form between the juxtaposed first and second conductive elements. The conductive nanoparticles can be disposed between the surfaces of the first and second conductive elements. ... Invensas Corporation








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