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Kabushiki Kaisha Toshiba patents


Recent patent applications related to Kabushiki Kaisha Toshiba. Kabushiki Kaisha Toshiba is listed as an Agent/Assignee. Note: Kabushiki Kaisha Toshiba may have other listings under different names/spellings. We're not affiliated with Kabushiki Kaisha Toshiba, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "K" | Kabushiki Kaisha Toshiba-related inventors


Electronic device

. . . . According to one embodiment, an electronic device includes a housing including a wall portion, a printed circuit board including a plurality of lines and provided in the housing, and a connector formed of a part of the housing and a part of the printed circuit board. The connector includes an engagement hole formed in the wall portion and into which a connector plug is inserted. ... Kabushiki Kaisha Toshiba

Wireless communication device, wireless communication method, computer device, and information processing method

According to one embodiment, a wireless communication device includes a wireless-communication interface and a wireless-network-information controller. The wireless-communication interface is configured to communicate with one or more terminal using a wireless network. ... Kabushiki Kaisha Toshiba

Wireless communication device and wireless communication method

According to one embodiment, a wireless communication device includes: a receiver configured to receive a first frame which contains data; and a transmitter configured to transmit a second frame and a third frame by frequency multiplexing, the third frame containing the data and being addressed to a first relay station different from a sender device of the first frame. The second frame is a frame to instruct the sender device of the first frame to perform a frame transmission.. ... Kabushiki Kaisha Toshiba

Confirming work supporting device, confirming work supporting system, and computer program product

According to an embodiment, a confirming work supporting device includes a storage and processing circuitry. The storage is configured to store therein rssi (received signal strength indicator) information that indicates reception strength of a wireless signal as measured by each of a plurality of installed wireless devices, from another wireless device. ... Kabushiki Kaisha Toshiba

Positioning device and program

A positioning server determines a location of a mobile device within an area including a plurality of base stations. The positioning server includes a communication circuit through which positioning data is received, a display device, an input unit, and a controller. ... Kabushiki Kaisha Toshiba

Information processing apparatus, information processing method, and computer program product

According to an embodiment, an information processing apparatus includes one or more processors. The one or more processors are configured to acquire target sentence data including a plurality of morphemes obtained by speech recognition and speech generation time of each morpheme from the plurality of morphemes; and assign display time according to a difference between a confirmed sentence of which a user's correction for the target sentence data is confirmed and a second confirmed sentence of a previous speech generation time.. ... Kabushiki Kaisha Toshiba

System and method of generating barcodes on scanned documents

A system and method for adding a barcode to an electronic document includes a multifunction peripheral having a user interface for accepting commands and data from a user, a scan engine that scans a tangible document into an electronic document, and a processor that generates a barcode from barcode identifying data. The user can enter a document identifier via a user interface as the barcode identifying data. ... Kabushiki Kaisha Toshiba

System and method for multifunction peripheral document notarization

A system and method for automated mfp notarization includes a display and a user input for receiving a notary request for document notarization. A device controller with processor and associated memory commences electronic notarization upon receipt of a notary request. ... Kabushiki Kaisha Toshiba

System and method for storing scanned documents

A system and method for simplified scanning of tangible documents commences with scanning them into electronic documents on an mfp. The mfp controller generates a scan command indicia and commences a scan when it is selected by a user. ... Kabushiki Kaisha Toshiba

Case and apparatus for image formation

A case of an exemplary embodiment accommodates an apparatus including a movable part and includes a case base, a first member, and a second member. The first member includes a first surface and a second surface opposing each other, and is provided with a hole formed by opening at least a side of the second surface, among a side of the first surface and the side of the second surface. ... Kabushiki Kaisha Toshiba

Communication control device, communication control method, and non-transitory computer readable medium

According to one embodiment, a communication control device includes processing circuitry. The processing circuitry acquires at least either; wired communication characteristic information or wireless communication characteristic information from relaying devices or, storage characteristic information indicating usage of a plurality of storage devices storing data units that are transferred via the relaying devices and sent or received by a terminal in the wireless network or, data characteristic information indicating states of a plurality of data units stored in each of the storage devices. ... Kabushiki Kaisha Toshiba

Semiconductor device

A semiconductor device of an embodiment includes first and second couplers, an encoding circuit, and a demodulating circuit. The encoding circuit executes differential manchester encoding on digital data based on a clock inputted thereto via the first coupler and outputs an encoded data. ... Kabushiki Kaisha Toshiba

Wireless communication apparatus, sensing apparatus and signal processing system

A wireless communication apparatus has a transmitter, a signal processor, and adpll circuitry. The transmitter to modulate transmission data using a local oscillation signal to generate a wireless signal to be transmitted from an antenna. ... Kabushiki Kaisha Toshiba

Wireless communication device and wireless communication system

According to an embodiment, a wireless communication device performs time-division communication and includes a storage and one or more processors. The storage is configured to store transmission data to be sent in a first period of time. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180278351

Content evaluating device, method, and storage medium

According to one embodiment, a content evaluating device includes a first storage, a second storage and a processor. The first storage is configured to store a first viewing log indicating a device with which the first content has been viewed in the first region and a second viewing log indicating a device with which second content has been viewed in the first region. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180278273

Decoding device and decoding method

According to one embodiment, a decoding device that decodes a multi-dimensional error correction code having two or more component codes includes a storage unit that stores therein the multi-dimensional error correction code, an additional-information storage unit that manages each syndrome of the at least two component codes or a reliability flag indicating whether the syndrome has a value of 0 or other than 0, a decoder that performs a first decoding process in a unit of component code with respect to the multi-dimensional error correction code stored in the storage unit to detect an error vector of each component code, and a detection unit that determines whether detection of the error vector by the decoder is false detection, based on the syndrome or the reliability flag stored in the additional-information storage unit.. . ... Kabushiki Kaisha Toshiba

09/27/18 / #20180278255

Frequency divider circuit

According to one embodiment, a frequency divider circuit includes a 1st flip-flop including a 1st terminal to which a clock signal is input, and including a 2nd terminal to which a 1st signal is input; a 2nd flip-flop including a 1st terminal to which the clock signal is input, and including a 2nd terminal to which a 2nd signal is input, the 2nd signal being output from the 1st flip-flop; a 3rd flip-flop including a 1st terminal to which the clock signal is input, and including a 2nd terminal to which a 3rd signal is input, the 3rd signal being output from the 2nd flip-flop; and an exclusive or gate including a 1st terminal to which the 4th signal is input, and including a 2nd terminal to which a 5th signal is input, the 5th signal being output from the 2nd flip-flop.. . ... Kabushiki Kaisha Toshiba

09/27/18 / #20180278239

Semiconductor device

A semiconductor device according to an embodiment includes; an n-channel type first mos transistor having a first drain connected to an input terminal, a first source connected to an output terminal, a first gate insulation film, and a first gate; a p-channel type second mos transistor having a second drain connected to the input terminal in parallel with the first drain, a second source connected to the output terminal in parallel with the first source, a second gate insulation film whose area is larger than an area of the first gate insulation film, and a second gate; an inverter connected to a control terminal in parallel with the first gate; and a delay circuit disposed between the inverter and second gate.. . ... Kabushiki Kaisha Toshiba

09/27/18 / #20180278220

Amplifier

An amplifier of an embodiment includes: a plurality of input transistors of a plurality of differential pairs; a plurality of first resistance circuits mutually connecting respective sources of the input transistors corresponding to the differential pairs and mutually connecting the respective sources and reference potential points; a plurality of second resistance circuits being connected between the respective sources of the plurality of input transistors and the reference potential points, respectively; and a control circuit configured to generate a control signal controlling whether or not to electrically connect the plurality of first resistance circuits and the plurality of second resistance circuits to the respective sources of the input transistors.. . ... Kabushiki Kaisha Toshiba

09/27/18 / #20180278183

Control system, controller, and control method for wound induction machine

According to one embodiment, a control system includes a chopper, a short-circuit unit, a voltage detector circuit, and a controller. The chopper reduces a direct current voltage between a converter connected to a stator in a wound induction machine and an inverter connected to a rotor in the wound induction machine. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180278180

Power conversion system

A power conversion system includes: an output terminal connected to a load; a switch configured to be turned on in a first case that an ac voltage from the ac power supply is normal, and to be turned off in a second case that the ac voltage from the ac power supply is abnormal; a power converter configured to convert the ac power from the ac power supply into dc power and store the dc power in a storage battery in the first case, and to convert the dc power in the storage battery into ac power and output the ac power to the output terminal in the second case; and a line-commutated inverter configured to operate in synchronization with an ac voltage appearing at the output terminal, and convert the dc power supplied from a fuel cell into ac power and output the ac power to the output terminal.. . ... Kabushiki Kaisha Toshiba

09/27/18 / #20180278176

Power conversion device

A power conversion device which converts electric power by having a power semiconductor element perform a switching operation includes voltage detection means for detecting a common mode voltage generated in the switching operation of the power semiconductor element, a voltage control power supply which generates a voltage which is opposite in polarity to and as high as the common mode voltage with a circuit which amplifies power of the common mode voltage detected by the voltage detection means, and voltage superimposition means for canceling the common mode voltage not lower than a switching frequency generated in the switching operation of the power semiconductor element, by superimposing the voltage generated by the voltage control power supply on an output from the power conversion device.. . ... Kabushiki Kaisha Toshiba

09/27/18 / #20180278171

Modular configurable adjustable-speed drive

Presently disclosed embodiments are directed to an adjustable-speed drive comprising a transformer module and an inverter module configured for installation in either of a side-by-side or stacked configurations. The disclosed embodiments utilize a modular design for the transformer and inverter modules. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180278170

Power generation system

A power generation system in an embodiment includes a power generator, a rectifying and smoothing circuit, a converter, a voltage measurement unit, and a switch. The power generator outputs ac power. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180278159

Semiconductor device

According to embodiments, a semiconductor device includes a first switching element in which a first reference voltage is input to a gate; a second switching element in which a first voltage is input to a gate; a third switching element to which the first switching element is in darlington connection; a fourth switching element to which the second switching element is in darlington connection; a first current mirror circuit to regulate currents flowing in the third and fourth switching elements; a fifth switching element switched between on and off states based on a difference between the first reference and the first voltages; a constant current circuit; a second current mirror circuit; and a voltage setting resistance element between a source of the first switching element and a gate of the third switching element or between a source of the second switching element and a gate of the fourth switching element.. . ... Kabushiki Kaisha Toshiba

09/27/18 / #20180278156

Dc-dc converter

According to one embodiment, a dc-dc converter includes a signal generator configured to output a first pwm signal having arbitrary amplitude and a duty cycle established based on an input voltage and an output voltage, a driver configured to output a second pwm signal being in phase with the first pwm signal and having amplitude of the input voltage based on the first pwm signal, a filter configured to extract a dc component from the second pwm signal, and a switch configured to supply an output of the filter to the signal generator in response to a first control signal.. . ... Kabushiki Kaisha Toshiba

09/27/18 / #20180278141

Power conversion device and power conversion system

A power conversion device includes: a first power conversion circuit that converts power inputted from outside and outputs the converted power to a second power conversion circuit connected to the first power conversion circuit via a dc link, which outputs the converted power to a load; smoothing capacitors provided in an output part of the first power conversion circuit and an input part of the second power conversion circuit; a first and second common mode current extraction circuits provided in an input part of the first power conversion and second power conversion circuits; and a virtual neutral potential line that connects the first and second common mode current extraction circuits; a dc link filter circuit that includes a y-shaped capacitor connected between the dc link part and the virtual neutral potential line.. . ... Kabushiki Kaisha Toshiba

09/27/18 / #20180278098

Noncontact power transmission apparatus and power transmission device

A noncontact power transmission apparatus includes an instrument including a first case, a power reception coil arranged to generate an induced current due to magnetic flux in a first direction intersecting a gravitational direction, and a holder configured to hold the power reception coil at a predetermined distance from an outer surface of the first case in the first case. A power transmission device includes a conductive second case that has an opening into which the instrument is inserted in which the instrument is stored, a power transmission coil provided in the second case so as to generate magnetic flux in the first direction, and disposed to generate an induced current in the power reception coil, and an elastic body that is provided in the second case, maintains a distance between the power transmission coil and the power reception coil to be constant, and supports the power transmission coil.. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180278092

Non-contact power transmission apparatus and power supply device

A non-contact power transmission apparatus includes a device including a power reception coil arranged to generate an induced current by magnetic flux in a first direction crossing a gravity direction. An outer shape of a first coil pattern has a first width in a second direction crossing the first direction and the gravity direction. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180278088

Uninterruptible power supply

An uninterruptible power supply is configured to receive, together with a first load, ac power supplied from an ac power source. The uninterruptible power supply includes: a converter configured to convert ac power from the ac power source into dc power; an inverter configured to convert dc power generated by the converter or dc power in a battery into ac power to supply the converted power to a second load; a controller configured to control reactive power generated at the converter to compensate at least a part of reactive power generated at the first load; and a limiter configured to limit reactive power generated at the converter to upper limit power or lower. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180278064

Storage battery management device, method, and computer program product

A storage battery management device manages storage battery systems in a power system, each storage battery systems having a storage battery device. The management device includes a soc estimation table in which a relationship between an open circuit voltage of the storage battery device and the soc is stored in advance; a measurement control unit that sets a predetermined soc area where the open circuit voltage and the soc can be considered as a monotonic function by discharging or charging a storage battery device of soc measurement target between storage battery systems, and measures the open circuit voltage of the storage battery device of soc measurement target by electrically disconnecting the storage battery device from a power supply/demand channel; and an estimation unit that estimates the soc of the storage battery device by referring to the soc estimation table based on the open circuit voltage measured in the soc area.. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277950

Phase shifter and array antenna device

An increase in size of a phase shifter is suppressed and a change amount of a passing phase is further increased. A phase shifter of an embodiment includes a signal input unit, first to fourth lines, a signal output unit, first and second phase variable elements, and a phase setter phase setter. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277917

Transmission line and signal processing device

A transmission line according to an embodiment, includes a first conductor layer, a second conductor layer spaced apart from the first conductor layer, a first conductor line including a first region facing the first conductor layer and a second region facing the second conductor layer, the first conductor line being spaced apart from the first conductor layer and the second conductor layer, the first conductor line extending in a first direction, and a second conductor line spaced apart from the first conductor layer, the second conductor layer, and the first conductor line, the second conductor line extending in the first direction, the second conductor line being shorter than the first conductor line in the first direction in length.. . ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277909

Composite electrolyte, secondary battery, battery pack and vehicle

According to an embodiment, a composite electrolyte is provided. The composite electrolyte includes an inorganic solid particle mixture and a nonaqueous electrolyte which includes li. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277908

Secondary battery, battery pack, and vehicle

According to one embodiment, there is provided a secondary battery including a negative electrode active material-containing layer, a positive electrode active material-containing layer, and an electrical insulation layer. The electrical insulation layer is provided between the negative electrode active material-containing layer and the positive electrode active material-containing layer and contains electrically insulating particles. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277907

Electrode group, secondary battery, battery pack and vehicle

According to one embodiment, an electrode group is provided. The electrode group includes a positive electrode, a negative electrode, and a solid electrolyte layer provided between the positive electrode and the negative electrode and including a first portion including first solid electrolyte particles in contact with the positive electrode, a second portion including second solid electrolyte particles in contact with the negative electrode, and a third portion provided between the first and second portions and including third solid electrolyte particles. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277906

Secondary battery, battery pack, and vehicle

In one embodiment, a secondary battery includes two or more electrode groups. The negative electrode tabs of one of the electrode groups and the positive electrode tabs of the other electrode group are arranged in rows. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277905

Electrode construct, electrode, secondary battery, battery module, battery pack, and vehicle

According to one embodiment, there is provided an electrode construct including an active material-containing layer and a sodium ion-blocking layer. The active material-containing layer contains a sodium-containing titanium composite oxide having a crystal structure belonging to a space group cmca or a space group fmmm. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277904

Secondary battery, battery pack, and vehicle

In one embodiment, a secondary battery includes, electrode groups, an insulating sheet, and a container member. The insulating sheet is disposed between the electrode groups. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277899

Secondary battery, battery pack, and vehicle

According to one embodiment, a secondary battery including a positive electrode, a negative electrode, a separator, a first electrolyte, and a second electrolyte is provided. The separator is provided at least between the positive electrode and the negative electrode. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277896

Composite electrolyte, secondary battery, battery pack, and vehicle

According to one embodiment, a composite electrolyte is provided. The composite electrolyte includes inorganic compound particles having lithium ion conductivity at 25° c. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277885

Secondary battery, battery pack, and vehicle

According to one embodiment, a secondary battery includes a positive electrode, a negative electrode, a separator, a first electrolyte and a second electrolyte. The separator is arranged at least between the positive electrode and the negative electrode. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277882

Electrode structure, secondary battery, battery pack, and vehicle

According to one embodiment, an electrode structure is provided. The electrode structure includes a current collector, an active material layer provided on at least one surface of the current collector, and a separator layer provided on the active material layer. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277871

Membrane electrode assembly, electrochemical cell, stack, fuel cell, and vehicle

A membrane electrode assembly of an embodiment includes: a first electrode having a first base, and a first catalyst layer provided on the first base, the first catalyst layer including a plurality of first catalyst units with a laminated structure, and the laminated structure including void layers; and an electrolyte membrane being in direct contact with both first surfaces of the first catalyst units facing each other among the first catalyst units , and second surfaces of the first catalyst units on the opposite side from the first base side. A portion is included where the electrolyte membrane exists over a region being at least 80% of a thickness of the first catalyst layer from the second surfaces of the first catalyst units toward the first base.. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277843

Electrode composite, secondary battery, battery pack and vehicle

According to one embodiment, an electrode composite is provided. The electrode composite includes a negative electrode active material-containing layer and an insulating particle layer. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277842

Active material, electrode, secondary battery, battery pack, and vehicle

According to one embodiment, there is provided an active material including particles of a composite oxide having an orthorhombic crystal structure and represented by the general formula li2+wna2−xm1yti6−zm2zo14−δ. The particles of the composite oxide have an average crystallite size of 50 nm to 90 nm and an average primary particle size of 0.1 μm to 0.6 μm. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277835

Electrode, secondary battery, battery pack, and vehicle

According to one embodiment, an electrode including active material particles is provided. The active material particles contain monoclinic niobium-titanium composite oxide particles and an amorphous carbon body. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277834

Active material, electrode, secondary battery, battery module, battery pack, and vehicle

According to one embodiment, an active material including a titanium-containing composite oxide phase and a carboxyl group-containing carbon coating layer is provided. The titanium-containing composite oxide phase includes a crystal structure belonging to a space group cmca and/or a space group fmmm. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277828

Electrode, nonaqueous electrolyte battery, battery pack and vehicle

According to one embodiment, an electrode is provided. The electrode includes an active material-containing layer. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277813

Separator, secondary battery, battery pack, and vehicle

According to one embodiment, a separator is provided. The separator is selectively permeable to monovalent cations and includes a first surface and a second surface which is a reverse surface to the first surface. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277779

Radiation detector

According to one embodiment, a radiation detector includes a first conductive layer, a second conductive layer, and an intermediate layer. The intermediate layer is provided between the first conductive layer and the second conductive layer. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277759

Memory device

A memory device according to an embodiment includes a first conductive layer; a second conductive layer; a first metal oxide layer that is provided between the first conductive layer and the second conductive layer and includes at least one first metal element selected from the group consisting of aluminum (al), gallium (ga), zirconium (zr), and hafnium (hf); and a second metal oxide layer that is provided between the first metal oxide layer and the second conductive layer and includes at least one second metal element selected from the group consisting of zinc (zn), titanium (ti), tin (sn), vanadium (v), niobium (nb), tantalum (ta), and tungsten (w). The first metal oxide layer includes a third metal element. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277757

Semiconductor memory device and manufacturing method for same

A semiconductor memory device includes a plurality of first interconnections extending in a first direction, and a second interconnection extending in a second direction different from the first direction. The device further includes a resistance change film provided between the plurality of first interconnections and the second interconnection, the resistance change film including(a) silicon and a semiconductor layer including one or more elements selected from among oxygen, carbon, nitrogen, phosphorus, boron, and germanium, or (b) a first layer containing the germanium and a second layer containing the silicon.. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277753

Memory device

A memory device includes a first conductive layer, a second conductive layer, and a variable resistance layer provided between the first and second conductive layers. The variable resistance layer includes a first layer having a semiconductor or a first metal oxide containing a first metal, and a second layer provided between the first layer and the second conductive layer, having a second metal oxide containing a second metal, and having crystal grains that are not in contact with at least one of an end face of the second layer on a side of the first conductive layer or an end face of the second layer on a side of the second conductive layer.. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277746

Magnetic memory

A magnetic memory includes: first to fourth wirings; first and second terminals; a first conductive layer including first to third regions, the second region being between the first region and the third region, the first region being electrically connected to the first terminal, and the third region being electrically connected to the second terminal; a first magnetoresistive element including a first and a second magnetic layer, and a first nonmagnetic layer disposed between the first and the magnetic layer; a first transistor including a third terminal electrically connected to the first magnetic layer, a fourth terminal electrically connected to the third wiring, and a first control terminal electrically connected to the first wiring; and a second transistor including a fifth terminal electrically connected to the first terminal, a sixth terminal electrically connected to the second wiring, and a second control terminal electrically connected to the first wiring.. . ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277744

Magnetic memory device and method of manufacturing the same

According to one embodiment, a magnetic memory device includes a first magnetic layer having a variable magnetization direction, a first non-magnetic layer provided on the first magnetic layer, and a second magnetic layer provided on the first magnetic layer and having a fixed magnetization direction and provided on the first magnetic layer. The second magnetic layer includes a non-magnetic metal including at least one of mo (molybdenum), ta (tantalum), w (tungsten), hf (hafnium), nb (niobium) and ti (titanium).. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277743

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes the following configuration. A resistance change element has first, second and third magnetic layers and a non-magnetic layer disposed between the first and second magnetic layers, and a metal layer disposed between the second and third magnetic layers. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277692

Solar cell, multi-junction solar cell, solar cell module, and solar power generation system

A solar cell of an embodiment includes a high-resistance oxide layer; a first electrode comprising line-patterned conductive members or mesh-patterned conductive members; a second electrode; and a light absorbing layer between the high-resistance oxide layer and the second electrode. The first electrode is disposed between the high-resistance oxide layer and the light absorbing layer.. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277667

Semiconductor device

A semiconductor device includes first and second electrodes, first semiconductor region of first conductivity type between the first and second electrodes, a second semiconductor region of second conductivity type between the first semiconductor region and the first electrode, a third semiconductor region of the second conductivity type between the first semiconductor region and the second electrode, a fourth semiconductor region of the first conductivity type between the third semiconductor region and the second electrode, a plurality of third electrodes between the second electrode and the first semiconductor region, wherein a gate insulating film is between each third electrode and the third semiconductor region, a fourth electrode extending between the third semiconductor region and the second electrode and electrically connected to the third semiconductor region and the second electrode, and a first insulating film between the second and electrodes. The fourth electrode is in ohmic contact with the third semiconductor region.. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277650

Semiconductor device

A semiconductor device includes a semiconductor layer provided on a substrate, a drain electrode and a source electrode provided on the semiconductor layer, and a gate electrode provided on the semiconductor layer such that an angle between a lateral surface and the semiconductor layer gradually decreases toward the semiconductor layer.. . ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277643

Semiconductor device, method of manufacturing semiconductor device, inverter circuit, driving device, vehicle, and elevator

A semiconductor device according to an embodiment includes a silicon carbide layer, an insulating layer, and a region provided between the silicon carbide layer and the insulating layer, the region including a plurality of first atoms of one element from the group consisting of nitrogen (n), phosphorus (p), arsenic (as), antimony (sb), and bismuth (bi), at least some of the plurality of first atoms being four-fold coordinated atoms and/or five-fold coordinated atoms.. . ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277640

Semiconductor device and method of manufacturing the same

According to one embodiment, a semiconductor device includes a semiconductor element having a substrate with at least two bending portions formed on a first side surface thereof. The two bending portions are displaced from each other in a first direction that is perpendicular to the first side surface of the substrate and parallel to a front surface of the substrate and in a second direction parallel to the front surface of the substrate and perpendicular to a top surface of the substrate. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277634

Semiconductor device, inverter circuit, drive device, vehicle, and elevating machine

A semiconductor device of an embodiment includes first and second electrodes, a first gate electrode, a semiconductor layer disposed between the first electrode and a band gap of the semiconductor layer being wider than a band gap of silicon, a silicon layer between the semiconductor layer and the first electrode, a metal layer between the semiconductor layer and the silicon layer, a first semiconductor region of a first-conductivity type in the semiconductor layer, a first silicon region of the first-conductivity type in the silicon layer, a second silicon region of a second-conductivity type in the first silicon region, a third silicon region of the second-conductivity type in the first silicon region and separated from the second silicon region, a first gate insulating layer, a fourth silicon region of the first-conductivity type in the second silicon region, and a fifth silicon region in the third silicon region.. . ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277631

Semiconductor device and method for manufacturing same

According to one embodiment, the joint part has a diameter larger than a diameter of the first columnar part and a diameter of the second columnar part. The joint part includes an intermediate semiconductor body continuous with the first semiconductor body and the second semiconductor body. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277625

Semiconductor device

A semiconductor device according to an embodiment includes a semiconductor substrate, source electrodes, drain electrodes provided between the source electrodes, gate electrodes provided between the source electrodes and the drain electrodes, first p-type region in the semiconductor substrate, n-type source regions in the semiconductor substrate extending in a first direction and electrically connected to the source electrodes, n-type drain regions in the semiconductor substrate extending in the first direction and electrically connected to the drain electrodes, and first n-type regions extending in the first direction, the first p-type region interposed between the first n-type regions and the n-type source regions, the first p-type region interposed between the first n-type regions and the n-type drain regions. A distance between one first n-type region among the first n-type regions and the source electrodes is less than a distance between the one first n-type region and the drain electrodes.. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277607

Radiation detector

According to one embodiment, a radiation detector includes a first conductive layer, a second conductive layer, and an intermediate layer. The intermediate layer is provided between the first and second conductive layers. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277603

Memory device and rectifier

A memory device according to an embodiment includes a first conductive layer, a second conductive layer, a variable resistance layer disposed between the first conductive layer and the second conductive layer, and an organic molecular layer disposed between the variable resistance layer and the second conductive layer and containing organic molecules. Each of the organic molecules includes a first fused polycyclic unit having a first homo level, a second fused polycyclic unit having a second homo level higher in energy than the first homo level, and a third fused polycyclic unit disposed between the first fused polycyclic unit and the second fused polycyclic unit. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277598

Semiconductor device

A semiconductor device includes a semiconductor pillar and a control electrode. The semiconductor pillar extends in a first direction, and includes a first region, a second region and an intermediate region provided along the first direction. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277597

Storage device

A storage device includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer. The storage device further includes a first variable resistance layer provided between the first and fifth conductive layers, a second variable resistance layer provided between the second and fifth conductive layers, a third variable resistance layer provided between the third and fifth conductive layers, and a fourth variable resistance layer provided between the first and sixth conductive layers. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277595

Semiconductor storage device

A semiconductor storage device includes first and second wirings that are in a first layer above the substrate, extend along a first direction, and are adjacent to each other along a second direction, third and fourth wirings that are in a second layer above the first layer, extend along the second direction, and are adjacent to each other along the first direction, first and second memory cells on the first wiring, and a third memory cell on the second wiring. The first to third memory cells each include a variable resistance element and a switching element. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277565

Semiconductor memory device

A semiconductor memory device includes wirings arranged in parallel along a first direction, the wirings including first and second wirings that are adjacent and a third wiring adjacent to the second wiring, a first pillar between the first and second wirings and a second pillar between the second and third wirings, the first and second pillars each extending in a second direction crossing the first direction toward the semiconductor substrate, and first and second bit lines connected to the first and second pillars, respectively. A first voltage is applied to the second wiring during a program operation on a first memory cell at an intersection of the second wiring and the first pillar, and a second voltage higher than the first voltage is applied to the second wiring during a program operation on a second memory cell at an intersection of the second wiring and the second pillar.. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277564

Semiconductor memory device and method for manufacturing the same

According to an embodiment, a semiconductor memory device includes a substrate, a stacked body, a circuit section, a first insulating layer, and a first columnar part. The stacked body is provided on the substrate and includes a plurality of electrode layers stacked with spacing from each other. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277563

Semiconductor memory device and method for manufacturing the same

According to an embodiment, a semiconductor memory device includes a substrate, a stacked body, a first insulating film, and a first film. The stacked body is provided on the substrate. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277562

Semiconductor memory device

A semiconductor memory device includes a substrate, electrode films provided on a first direction side of the substrate and arranged with spacing from each other along the first direction, semiconductor members extending in the first direction, a charge storage member provided between each of the electrode films and each of the semiconductor members, and a control circuit. Memory cells are formed in crossing portions of the electrode films and the semiconductor members. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277561

Semiconductor device and method for manufacturing the same

According to an embodiment, a semiconductor device includes a substrate, a stacked body, a first insulating film, a second insulating film and a plurality of contacts. The stacked body is provided on the substrate and includes a plurality of electrode films stacked with spacing from each other. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277560

Semiconductor memory device and manufacturing method of semiconductor memory device

According to an embodiment, a semiconductor memory device includes a stacked body in which insulating layers and electrode films are alternately stacked, a pillar member arranged in a memory hole that is disposed in the stacked body in a thickness direction, and a semiconductor layer provided below the pillar member. The pillar member has a structure in which a memory film and a channel layer are stacked in order from a side of the stacked body. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277559

Semiconductor memory device and method for manufacturing same

A semiconductor memory device includes a stacked body in which electrode films and insulating films are stacked alternately along a first direction, a semiconductor member extending in the first direction, and a charge storage member provided between the semiconductor member and the electrode film. The electrode film includes a first conductive layer and a second conductive layer. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277555

Semiconductor device and method for manufaturing same

According to one embodiment, a semiconductor device includes a foundation layer, a stacked body provided above the foundation layer, a semiconductor body, and a charge storage portion. The stacked body includes a plurality of electrode layers stacked with an air gap interposed, a plurality of select gate layers stacked in a stacking direction of the electrode layers, and an insulating body provided between the select gate layers adjacent to each other in the stacking direction. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277554

Semiconductor device and method of manufacturing the same

A semiconductor device includes a first electrode layer and a second electrode layer formed thereon to be spaced from the first electrode layer, a columnar portion penetrating the first and second electrode layers in a first direction and including a semiconductor layer, a first insulating film between the first and second electrode layers and the semiconductor layer and in contact with the first electrode layer, a charge storage layer between the second electrode layer and the first insulating film, and an insulating film between the second electrode layer and the charge storage layer. The semiconductor layer includes a first portion facing the second electrode layer in a second direction intersecting with the first direction and a second portion in contact with the first portion in the first direction. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277531

Semiconductor device

A semiconductor device according to an embodiment includes a semiconductor substrate having a first plane and a second plane, a plurality of first semiconductor areas provided on the first plane, a plurality of second semiconductor areas provided between the plurality of first semiconductor areas, a plurality of insulator regions provided between the first semiconductor areas and the second semiconductor areas, first-conductivity-type drain regions provided in the first semiconductor areas, first-conductivity-type source regions provided in the second semiconductor areas, gate electrodes, first-conductivity-type first impurity regions that are provided between the first-conductivity-type drain regions and the second plane and have a lower first-conductivity-type impurity concentration than the first-conductivity-type drain regions, and a plurality of second-conductivity-type second impurity regions provided between the first-conductivity-type source regions and the second plane. The width of at least one of the plurality of first semiconductor areas is greater than the width of the other first semiconductor areas.. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277529

Semiconductor package

A semiconductor package includes a substrate having opposing first and second surfaces, first memory chips stacked on the first surface, second memory chips stacked on the first surface, a controller chip for the first and second memory chips, installed on the first surface between the stacked first memory chips and the stacked second memory chips, a sealing portion that seals the first and second memory chips, and the controller chip, and a plurality of solder balls installed on the second surface. The first memory chips are stacked such that a first memory chip located directly above another first memory chip is shifted further toward the controller chip relative to said another first memory chip. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277516

Semiconductor device

A semiconductor device includes a first and a second chips. A first inductor is above a first surface or a second surface located on an opposite side to the first surface. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277515

Semiconductor device and manufacturing method thereof

A device includes a wiring substrate. A first semiconductor-chip has a first face, a second face, and a first side face between an outer edge of the first face and an outer edge of the second face, where the first side face is a first condition plane. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277514

Semiconductor device

A semiconductor device includes a substrate having first and second principal surfaces, and a semiconductor chip disposed on the first principal surface. The substrate includes a first conductor layer disposed on the first principal surface, a second conductor layer disposed on the second principal surface, at least one third conductive layer between the first conductive layer and the second conductive layer, a detection interconnection disposed in either the first conductive layer or the third conductive layer, and first and second pads disposed on the second conductive layer and connected to the detection interconnection. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277499

Semiconductor memory device and method for manufacturing the same

According to an embodiment, a semiconductor memory device includes a substrate, an insulating film, a plurality of conductive films, an insulating member, a plurality of stacked bodies, and a first member. The insulating member is provided on the insulating film, is positioned between the conductive films in a first direction along the substrate, and extends in a second direction along the substrate, the second direction crossing the first direction. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277498

Semiconductor device

A semiconductor device includes a mounting substrate including an interface, which is connectable with a host, and a first ground layer, a surface-mounted component mounted on the mounting substrate, and a plurality of solder balls between the mounting substrate and the surface-mounted component. The surface-mounted component includes a semiconductor chip, a package substrate that is positioned between the semiconductor chip and the solder balls and includes a second ground layer, a sealing portion that covers the semiconductor chip, and has an opening, a first conductive portion on a top surface of the sealing portion, and a second conductive portion on a side surface of the opening and electrically connected to the first conductive portion and the second ground layer. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277497

Semiconductor device and method of manufacturing the same

According to one embodiment, a semiconductor device includes a first semiconductor circuit layer including a first conductive layer, a second semiconductor circuit layer including a second conductive layer, and a third semiconductor circuit layer between the first semiconductor circuit layer and the second semiconductor circuit layer, the third semiconductor circuit layer including a third conductive layer in contact with the first conductive layer, a fourth conductive layer in contact with the second conductive layer, and a fifth conductive layer in contact with the third conductive layer and electrically connected to the fourth conductive layer. The fifth conductive layer has a width that is narrower than a width of the third conductive layer.. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277494

Semiconductor memory device and method for manufacturing the same

According to an embodiment, a semiconductor memory device includes a substrate, a first stacked body, a columnar part, a second insulating film, and a second stacked body. The first stacked body is provided in a first region on the substrate. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277493

Method of manufacturing semiconductor device and semiconductor device

A method of manufacturing a semiconductor device includes stacking a first substrate comprising a first surface having a semiconductor element and an opposing second surface and a second substrate comprising a third surface having a semiconductor element and an opposing fourth surface, forming a first contact hole extending from the second surface to the first surface of the first substrate and forming a first groove inwardly of a first region of the second surface of the first substrate by etching inwardly of the first substrate from the second surface thereof, forming a first patterned mask on the first substrate, so that the first groove is covered by the material of the first patterned mask, forming a first metal electrode in the first contact hole through an opening in the first mask as a mask, and removing the first mask and subsequently cutting through the first substrate in the first groove.. . ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277488

Semiconductor package and semiconductor package manufacturing method

A semiconductor package includes a substrate, a semiconductor element disposed on the substrate, an encapsulating layer covering side surfaces and a top surface of the semiconductor element, an electromagnetic shield layer covering side surfaces of the substrate and side surfaces and a top surface of the encapsulating layer, and a titanium oxide layer formed above a top surface of the electromagnetic shield layer, and including a first portion containing divalent titanium oxide and a second portion containing tetravalent titanium oxide.. . ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277487

Graphene wiring structure, semiconductor device, method for manufacturing graphene wiring structure, and method for manufacturing wiring structure

A graphene wiring structure of an embodiment has: an amorphous or polycrystalline insulating film; and a multilayer graphene on the insulating film. The multilayer graphene including a plurality of graphene crystals having a zigzag direction is oriented at 17 degrees or less with respect to an electric conduction direction on the insulating film.. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277484

Semiconductor device

A semiconductor device includes a first chip having a through via, a second chip having a first terminal that is electrically connected to the through via, and a substrate having a second terminal disposed on a first surface thereof and electrically connected to the first terminal. When viewed along a straight line that intersects a center axis that is perpendicular to the first surface and intersects a center point of the substrate, the first terminal is disposed further towards the center axis than the second terminal and the through via is disposed further towards the center axis than the first terminal.. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277477

Storage device

A storage device includes a first wiring layer, a second wiring layer spaced from the first wiring layer in a first direction, and a plurality of electrode layers stacked in the first direction between the first wiring layer and the second wiring layer. A semiconductor pillar penetrates the plurality of electrode layers in the first direction. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277476

Semiconductor memory device and method for manufacturing same

A semiconductor memory device includes a first electrode film, a second electrode film group composed of a plurality of electrode films provided on the first electrode film, a third electrode film group composed of a plurality of electrode films provided on the first electrode film and spaced from the second electrode film group, a semiconductor member extending in a first direction in which the first electrode film and the second electrode film group are arranged, a charge storage member provided between the first electrode film and the semiconductor member, a first conductive film connecting the plurality of electrode films of the second electrode film group to each other and a second conductive film connecting the plurality of electrode films of the third electrode film group to each other.. . ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277467

Semiconductor device

A semiconductor device includes field-effect transistor having a gate, a drain, and a source. A first clamping circuit is connected between the drain and the gate. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277466

Semiconductor device and method of manufacturing the same

To reduce a package size of a semiconductor device. According to embodiments, there is a semiconductor device comprising: a first die pad; a first inner lead arranged inside a molded resin; a second die pad; and a second inner lead arranged inside the resin, wherein a part of the first inner lead and a part of the second inner lead are adhered and electrically connected to each other, a first semiconductor chip mounted on the first die pad is electrically connected to a second semiconductor chip mounted on the second die pad via the first inner lead and the second inner lead, and an end face of one end of the first inner lead and the second inner lead that are adhered to each other is exposed to a side surface of the resin.. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277451

Manufacturing system for semiconductor device, method of manufacturing semiconductor device, and control device

According to an embodiment, a manufacturing system for a semiconductor device includes a first processing device and a second processing device, a measurement section, and an analysis section. The first processing device and the second processing device are adapted to perform a film formation process on a substrate in a wafer. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277436

Method of manufacturing semiconductor device

According to an embodiment, a method of manufacturing a semiconductor device includes forming a first modified zone in a wafer by irradiating the wafer with a laser having transmissivity with respect to the wafer along a part of a dicing line on the wafer, and forming a second modified zone in the wafer by irradiating the wafer with the laser along the dicing line on the wafer. The first modified zone is partially formed between a surface of the wafer and the second modified zone, a semiconductor interconnect layer being formed on the surface of the wafer.. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277435

Dicing method and laser processing apparatus

According to one embodiment, a dicing method is provided. The dicing method includes detecting a first distance between a first portion of a substrate and a first substrate information detection unit. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277407

Substrate processing device and method of manufacturing semiconductor device

A substrate processing device capable of stabilizing an etching amount of a metal film provided on a substrate is provided. The substrate processing device includes a first container, a second container and a control unit. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277406

Substrate treatment apparatus and manufacturing method of semiconductor device

According to an embodiment, a substrate treatment apparatus includes a vacuum chamber, a cylindrical member, a gas feed member, a support member and a plurality of plate members. The cylindrical member is disposed in the vacuum chamber and includes a gas outlet. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277400

Semiconductor manufacturing apparatus

According to an embodiment, a semiconductor manufacturing apparatus includes a process chamber, a load lock chamber, a gas purge mechanism and a movement mechanism. The process chamber treats a substrate using process gas in a vacuum state. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277390

Metal pattern forming method

A metal pattern forming method according to an embodiment includes forming a metal film on a surface of a substrate by an electroless plating method, the substrate including a first layer including a protrusion and a recess, and a film thickness of the metal film being a half or more of a width of the recess; and performing wet etching, the metal film in the recess removed by the wet etching and the metal film on the protrusion remained after the wet etching.. . ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277388

Manufacturing method of semiconductor device and semiconductor manufacturing apparatus

A manufacturing method of a semiconductor device according to an embodiment implants impurities into a central portion of a polishing target film or an outer peripheral portion of the central portion of the polishing target film to cause an impurity concentration in the outer peripheral portion of the polishing target film and an impurity concentration in the central portion thereof to be different from each other, thereby modifying a surface of the polishing target film. The modified surface of the polishing target film is polished by a cmp method.. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277274

Method for decontaminating nickel-based alloy

A method for decontaminating the nickel-based alloy includes oxidization of an oxide film accumulating radioactive nuclides with a first oxidizing agent to elute nickel into a solvent and thus to transform into a low-nickel film (s13 to s15). Elution amounts of nickel, chromium, and iron in the solvent are measured in the step s15 of the first oxidation step. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277231

Semiconductor storage device

A word-line controller applies a voltage to a selected word-line. A bit-line controller applies voltages to bit-lines. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277230

Memory device and memory system

According to one embodiment, a memory device comprises a first memory cell configured to store data, a first word line connected to the first memory cell, a first circuit configured to supply a voltage to the first word line, a second circuit configured to control the first circuit, and a sequencer configured to control the first circuit and the second circuit. The sequencer, when data is written to the first memory cell, determines whether a condition is satisfied or not. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277229

Memory system and method for controlling memory system

According to one embodiment, a memory system includes a memory device and a controller. The controller is configured to make the memory device apply a first verify voltage to a first word line for determining whether writing of a first data value into a first cell transistor has been completed. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277228

Memory system

According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory is configured to execute a first to third read operations. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277227

Semiconductor memory device and read control method thereof

A semiconductor memory device includes a nonvolatile memory and a controller. The nonvolatile memory has a plurality of memory cells that are connected to word lines to which a read voltage is applied at the time of reading data stored in the memory cells. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277226

Memory system

According to an embodiment, a semiconductor memory, on receiving a first command, applies a voltage within a first range and a voltage within a second range to a word line and reads a first bit from a memory cell, and, on receiving a second command, applies a voltage within a third range to the word line and reads a second bit from the memory cell. The controller issues the first command a plurality of times and changes the voltages to be applied to the word line within the first range and the second range in accordance with the plurality of first commands, specifies a first and second voltage within the first and the second range, respectively, and estimates a third voltage within the third range. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277224

Memory device and information processing system

According to one embodiment, a memory device is connected to one or more information processing devices. The memory device includes a shared memory and a memory controller. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277223

Semiconductor memory device

A semiconductor memory device includes a memory cell array, a temperature sensor that generates a first voltage which is based on a temperature of the semiconductor memory device, compares the first voltage with a second voltage that is based on a result of previous temperature measurement, and generates a voltage generation signal based on a result of comparing the first voltage with the second voltage, and a voltage generating circuit that generates a voltage applied to the memory cell array based on the voltage generation signal.. . ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277221

Method for controlling memory device

A memory device includes stacked word lines stacked and a semiconductor channel passing through the word lines in a first direction. Memory cells are disposed along the semiconductor channel in the first direction. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277220

Semiconductor memory device

A semiconductor memory device includes memory cell transistors, a word line connected to the plurality of memory cell transistors, bit lines that are respectively connected to the memory cell transistors, and a control circuit. The control circuit carries out a write operation on the memory cell transistors connected to the word line by performing, in sequence, a first loop of operations, including a first program operation followed by at least one verification operation, that are carried out until all memory cell transistors targeted by the first program operation have passed the at least one verification operation, a second loop of operations, including a second program operation and no verification operation, that are carried out for a fixed number of loops and a third loop of operations, including a third program operation and no verification operation, that are carried out for a fixed number of loops.. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277219

Semiconductor memory device

The present embodiment discloses a semiconductor memory device which includes a memory cell array, a signal pad, a first voltage pad, a first regulation circuit and a first operation circuit. The signal pad supplies an output signal associated with the memory cell array. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277218

Semiconductor storage device

A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277217

Semiconductor memory device

A semiconductor memory device includes a plurality of blocks of memory cells, including first, second, and third blocks of a first group of blocks and fourth fifth and sixth blocks of a second group of blocks, a plurality of word lines for each of the blocks, a first decode circuit for the first group, and a second decode circuit for the second group. When the first block is selected, the first decode circuit transfers a first voltage to the word lines of the first block, transfers a second voltage lower than the first voltage to the word lines of the second block, and causes the word lines of the third block to go into an electrically floating state, and the second decode circuit causes the words lines of the fourth block, the fifth block, and the sixth block into the electrically floating state.. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277216

Semiconductor device

According to one embodiment, a semiconductor device includes: a first memory cell provided in a first semiconductor chip; a first output buffer circuit configured to output data of the first memory cell outside, the first output buffer circuit provided in the first semiconductor chip; a first calibration control circuit configured to calibrate an impedance of the first output buffer circuit, a first terminal connected to the first calibration control circuit, the first calibration control circuit provided in the first semiconductor chip; and a first resistance element connected to the first terminal, the first resistance element provided in the first semiconductor chip.. . ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277213

Semiconductor integrated circuit

According to one embodiment, a semiconductor integrated circuit includes a rom, an sram, a memory and a selector. The rom stores initialization data. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277207

Variable resistance memory

A semiconductor device according to an embodiment includes a memory cell array and a drive circuit section. The memory cell array includes memory cells. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277205

Memory device and control method thereof

A memory device includes a control circuit configured to (i) start a first application of a first voltage between a first conductive layer and a third conductive layer, (ii) start a second application of the first voltage between a second conductive layer and the third conductive layer after a lapse of a first delay time since the start of the first application of the first voltage, and (iii) start an application of a second voltage, which is smaller than the first voltage, between the first conductive layer and the third conductive layer after a lapse of a second delay time since the start of the second application of the first voltage between the second conductive layer and the third conductive layer.. . ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277204

Memory system

A memory system according to one embodiment includes a memory device including a memory cell with a variable resistance value and a first controller, and a second controller. The first controller is configured to compare first read data read from the memory cell when a first voltage is applied to the memory cell with second read data read from the memory cell when a second voltage is applied to the memory cell. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277203

Storage device and control method thereof

A storage device includes a first conductive layer, a second conductive layer, a first variable resistance layer, and a control circuit. The control circuit is configured to apply a first voltage between the first conductive layer and the second conductive layer for a first time and apply a second voltage less than the first voltage for a second time longer than the first time after the application of the first voltage when the first variable resistance layer is in a first high resistance state. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277202

Semiconductor memory device

A semiconductor memory device includes a first conductor extending in a first direction and a second conductor extending in a second direction and disposed above the first conductor in a third direction. Third and fourth conductors extend in the first direction and adjacent to each other in the second direction. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277201

Semiconductor memory device

A semiconductor memory device includes a first memory cell having a first end connected to a first wiring and a second end connected to a second wiring and a second memory cell having a first end connected to the first wiring and a second end connected to a third wiring. A sense amplifier is configured to: sense a first current flowing in the first wiring when a first voltage is applied to the second and third wirings and a second voltage, larger than the first voltage, is applied to the first wiring; and sense a second current flowing in the first wiring when a third voltage larger than the second voltage is applied to the first wiring, the first voltage to the second wiring, and the second voltage to the third wiring. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277192

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes a memory cell including a transistor formed of an oxide semiconductor, an insulation film, and a control electrode, and a capacitance element configured to store a charge, the memory cell being configured to store a coupling weight of a neuron model by a charge amount accumulated in the capacitance element; and a control circuit configured to output a signal as a sum of a product between input data of the memory cell and the coupling weight.. . ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277189

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes a first memory cell having a first variable resistance element, a second memory cell having a second variable resistance element, and a first circuit which controls writing to the first memory cell and the second memory cell. The first circuit receives a fir command instructing writing to the first memory cell, after receiving the first command, receives a second command instructing writing to the second memory cell, and after receiving the second command, performs writing to the second memory cell when performing writing to the first memory cell.. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277188

Memory device

According to one embodiment, a memory device includes a memory cell; and a first circuit configured to perform first read for the memory cell and generate a first voltage, write first data to the memory cell that has undergone the first read, perform second read for the memory cell to which the first data written and generate a second voltage, generate a first current based on the first voltage, generate a second current based on the second voltage, and add a third current to one of the first current and the second current, thereby determining data stored in the memory cell at the time of the first read.. . ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277187

Computer system and memory device

According to one embodiment, a system includes: a device including a memory cell array, the device configured to execute first read operation of a first read method and second read operation of a second read method on the memory cell array; a processor configured to receive a first data from the device, the first data from a selected region in the memory cell array by the first read operation, configured to execute first calculation processing using the first data during the second read operation to the selected region, and configured to acquire a result of the first calculation processing by a first signal based on a comparison result of the first data and a second data, the first signal indicating that the first data is valid, and the second data from the selected region by the second read operation.. . ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277186

Memory device

According to one embodiment, a memory device includes a memory cell; and a first circuit configured to perform first read for the memory cell and generate a first voltage, write first data to the memory cell that has undergone the first read, perform second read for the memory cell to which the first data is written and generate a second voltage, and determine data stored in the memory cell at the time of the first read based on the first voltage and the second voltage, wherein when writing the first data, the first circuit electrically sets a generation unit configured to generate the second voltage in a floating state.. . ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277185

Magnetic memory device

According to one embodiment, a magnetic memory device includes a conductive layer, a first magnetic layer, a first nonmagnetic layer, a second magnetic layer, a first conductive region, a first insulating region, and a controller. The conductive layer includes a first element. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277183

Memory device

According to one embodiment, a memory includes a first mtj element having a first area along a first plane; and second mtj elements each having a second area along the first plane. The second area is larger than or equal to twice the first area and smaller than or equal to five times the first area. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277182

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes a first memory cell including a first resistance change memory element and a first transistor, a first word line electrically coupled to a control terminal of the first transistor, and a first circuit configured to, in a reading, apply a first voltage to the first word line during a first period and apply a second voltage higher than the first voltage to the first word line during a second period after the first period.. . ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277180

Memory system

A memory system includes a semiconductor memory and a controller. The controller is configured to perform a read operation on the semiconductor memory in response to a read instruction received from a host. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277177

Memory device and memory system

According to one embodiment, a memory device includes: a memory cell; a read driver configured to supply a read pulse to the memory cell at the time of a read operation for the memory cell; a filter circuit configured to output a second signal in a first frequency domain from a first signal, the first signal being outputted from the memory cell by the read pulse; a hold circuit configured to hold a peak value of the second signal; and a sense amplifier circuit configured to read data from the memory cell based on the peak value.. . ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277173

Control system

According to one embodiment, a control system includes: a memory device; and a controller. The memory device includes a first cell transistor. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277171

Semiconductor memory device

A semiconductor memory device includes a power source pad, a first bank including a plurality of memory cells, a second bank including a plurality of memory cells, the first bank being sandwiched between the power source pad and the second bank, first power supply lines connected to the power source pad and supplying power to the first bank and not to the second bank, and second power supply lines connected to the power source pad, passing over the first bank, and supplying power to the second bank and not to the first bank.. . ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277170

Semiconductor device and electronic equipment

According to one embodiment, a semiconductor device includes an input/output circuit to which a signal is input or from which a signal is output; a first terminal connected to a power line of the input/output circuit; a second terminal connected to the power line; a resistance element connected between the second terminal and the power line; and a first capacitance element connected between the second terminal and a ground terminal.. . ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277169

Disk apparatus

A disk apparatus includes a base including a bottom wall and a sidewall disposed along a peripheral portion of the bottom wall, a cover including a ceiling plate and a side plate disposed along a periphery of the ceiling plate, the ceiling plate being fixed to the sidewall and the side plate facing an outer surface of the sidewall, and a rotatable recording medium disposed between the cover and the bottom wall. The sidewall of the base includes a first portion adjacent to the recording medium and a protruding portion that protrudes from the first portion outward and away from the recording medium, and at least a portion of a sidewall of the protruding portion faces an opening formed in the side plate.. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277168

Disk device and method of manufacturing disk device

According to one embodiment, a disk device includes a disk-shaped recording medium, a head which processes data on the recording medium, and a housing accommodating the recording medium and the head. The housing includes a base with a side wall, and a cover having a welded portion welded to the side wall by laser welding. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277167

Video reproduction device and method

A video reproduction device includes a store computer configured to acquire a video data from a video data storage device. The video data is from multiple cameras. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277158

Storage device and controller

A storage device includes a recording medium, a first memory storing first data read from the recording medium, and a controller. The controller searches for read target data in the first data by executing a parity check on second data that is in the first data and starts at a first position, while executing the parity check, determining whether or not an interruption condition is satisfied, storing the second data in a second memory when the parity check completes without the interruption condition being satisfied and a result of a completed parity check satisfies a first condition, and executing a parity check on third data that is in the first data and starts at a second position, responsive to the interruption condition being satisfied and responsive to the result of the completed parity check not satisfying the first condition.. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277151

Magnetic disk device, controller, and method

A magnetic disk device includes a magnetic disk that includes a plurality of tracks, a magnetic head for reading data from the magnetic disk, and a controller. The controller begins controlling the magnetic head to move to a second track of the plurality of tracks from a first track of the plurality of tracks before decoding of a first track signal output from the magnetic head is completed, wherein the first track signal is output from the magnetic head while the magnetic head is positioned over the first track.. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277150

Suspension assembly, head suspension assembly and disk device provided with the same

A magnetic head suspension assembly includes a support plate coupled to a magnetic head, and a flexible wiring member disposed on the support plate. The flexible wiring member includes a metal plate fixed to the support plate, an insulating layer disposed on the metal plate, a conductive layer disposed on the insulating layer and forming a plurality of conductive lines and connection terminals, and a cover layer on the conductive layer. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277141

Signal processing apparatus, signal processing method and labeling apparatus

According to one embodiment, a signal processing apparatus includes a processer. The processor separates a plurality of signals, which are received at different positions and come from different directions, by a separation filter. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277140

Signal processing system, signal processing method and storage medium

According to one embodiment, a signal processing system senses and receives generated signals of a plurality of signal sources, estimates a separation filter based on the received signals of the sensor for each frame, separates the received signals based on the filter to obtain separated signals, computes a directional characteristics distribution for each of the separated signals, obtains a cumulative distribution indicating the directional characteristics distribution for each of the separated signals output in a previous frame, computes a similarity of the cumulative distribution to the directional characteristics distribution of the separated signals of a current frame, and connects to a signal selected from the separated signals based on the similarity.. . ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277120

Signal processing apparatus, signal processing method and audio association presentation apparatus

According to one embodiment, a signal processing apparatus includes a memory and a processes electrically coupled to the memory. The processor separates a plurality of signals by a separation filter, and outputs a plurality of separate signals. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277109

Edit assisting system, edit assisting device and edit assisting method

According to one embodiment, an edit assisting system includes a server device and a client device. The client device displays a first object, which indicates first speech of a user and a first portion of the first speech, and a second object, which indicates second speech generated by the server device and a second portion of the second speech, on a screen based on a scenario indicated in scenario data. ... Kabushiki Kaisha Toshiba

09/27/18 / #20180277106

Verification system, verification method, and computer program product

According to an embodiment, a verification system includes a storage controller, first and second receivers, a comparator, a response constructor, a response generator, and an output controller. The storage controller stores, in a storage, first response data and first situation data associated with the first response data. ... Kabushiki Kaisha Toshiba








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