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Knuedge Inc patents


Recent patent applications related to Knuedge Inc. Knuedge Inc is listed as an Agent/Assignee. Note: Knuedge Inc may have other listings under different names/spellings. We're not affiliated with Knuedge Inc, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "K" | Knuedge Inc-related inventors


Dedicated fifos in a multiprocessor system

A semiconductor chip with a first processing element, a state machine, a first read first-in first-out (fifo) memory component, and a second read fifo memory component. The state machine receives a request from the first processing element for a first value from the first read fifo memory component and a second value from the second read fifo memory component. ... Knuedge Inc

Network processor inter-device packet source id tagging for domain security

Systems and techniques for routing and application domain security are described. A described technique includes receiving, at an internal ingress port of a router of a first chip, a first processing packet that includes a first destination identifier from a computing resource of the first chip; obtaining a first source identifier from the first chip's secured register; and routing the first processing packet to a first egress port of the router based on a determination that the first source identifier and the first destination identifier are a first authorized communication pair. ... Knuedge Inc

Router path selection and creation in a single clock cycle

Systems, devices, and techniques for routing packets are described. A described router includes ingress ports to receive packets; egress ports; ingress switch fabric coupled with the ingress ports; egress switch fabric coupled with the egress ports; floating buffers coupled between the ingress switch fabric and the egress switch fabric; and a controller. ... Knuedge Inc

Arbitrating access to a resource that is shared by multiple processors

In an illustrative example, a system includes a resource and a first processor. The first processor is configured to access the resource based on a first physical address space and to generate a request for access to the resource. ... Knuedge Inc

Application domain security

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for application domain security. One of the methods includes maintaining, for each ingress port of a plurality of ingress ports of each top-level router of each processing device in a system, information representing one or more valid destination device ids for packets arriving at the ingress port. ... Knuedge Inc

Encoding for frameless packet transmissions

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for encoding frameless packets. One of the methods includes receiving a data payload to be transmitted. ... Knuedge Inc

Performing a synchronization operation on an electronic device

In an illustrative example, a method of operation of an electronic device includes identifying a plurality of threads. Each thread of the plurality of threads is configured to execute a plurality of instructions including a barrier instruction corresponding to a target of a synchronization operation. ... Knuedge Inc

Network on chip with task queues

A network on a chip architecture uses hardware queues to distribute multiple-instruction tasks to processors dedicated to performing that task. By repeatedly using the same processors to perform the same task, the frequency at which the processors access memory to retrieve instructions is reduced. ... Knuedge Inc

Content addressable memory (cam) implemented tuple spaces

A multi-processor system with a portion of content-addressable memory (cam) configured as a tuple space to control data flow between processing element. A writing processor may write to a tuple space followed by a reading processor reading from the tuple space. ... Knuedge Inc

Compute unit including thread dispatcher and event register and method of operating same to enable communication

An apparatus includes a set of one or more processing cores, a thread dispatcher, and an event register of a first compute unit. The set of one or more processing cores is configured to execute a set of threads. ... Knuedge Inc

Estimating pitch of harmonic signals

A time-varying pitch of a signal may be estimated by processing a sequence of frames of the speech signal. An estimated fractional chirp rate may be computed for each frame of the sequence of frames, and the estimated fractional chirp rates may be used to compute a pitch template for the sequence, where the pitch template indicates the time-varying pitch of the signal subject to a scale factor. ... Knuedge Inc

Classifying signals using mutual information

Input data may be classified using one or both of mutual information between segments and expected class scores. Input data to be classified may be segmented into an input sequence of segments. ... Knuedge Inc

Segmentation using prior distributions

The technology described in this document can be embodied in a computer-implemented method that includes obtaining a speech signal, and estimating a first set and a second set of segment boundaries using the speech signal. The first and second set of segment boundaries are determined using a first and second segmentation process, respectively. ... Knuedge Inc

Segmenting utterances within speech

The technology described in this document can be embodied in a computer-implemented method that includes obtaining a plurality of portions of a speech signal, and obtaining a plurality of frequency representations by computing a frequency representation of each portion of the speech signal. The method also includes generating, by one or more processing devices, a time-varying data set using the plurality of frequency representations by computing an entropy of each frequency representation of the plurality of frequency representations, and determining, by the one or more processing devices, boundaries of a speech segment using the time-varying data set. ... Knuedge Inc

09/28/17 / #20170279714

Chained packet sequences in a network on a chip architecture

Systems and techniques for network on a chip based computer architectures and communications therein are described. A described technique includes generating, at a first computing resource of a computer system, a chained packet sequence. ... Knuedge Inc

09/14/17 / #20170262318

Synchronization in a multi-processor computing system

In one aspect, a method implemented by a first sync controller includes receiving sync information, wherein the sync information (i) identifies a first sync process, (ii) indicates that the first sync controller is not a master controller of the first sync process, and (iii) identifies a group of components executing the first sync process, the group comprising a first processing device; receiving a first sync indication from the first processing device; storing an indication, associated with the first sync process, that the first sync indication was received from the first processing device; determining that a sync indication has been received from all components of the first group of components; and transmitting a second sync indication to a second sync controller.. . ... Knuedge Inc

08/17/17 / #20170236520

Generating models for text-dependent speaker verification

In one aspect, a method includes receiving a prompt for use with text-dependent speaker verification; generating a linguistic representation of the prompt, wherein the linguistic representation comprises a sequence of speech units; obtaining a plurality of feature vectors or a plurality of acoustic models; generating a universal background model for the prompt using the plurality of feature vectors or the plurality of acoustic models; receiving audio enrollment data of a first speaker speaking the prompt; and creating a first speaker verification model for the first speaker by adapting the universal background model using the audio enrollment data.. . ... Knuedge Inc

08/17/17 / #20170235511

Memory-attached computing resource in network on a chip architecture

A computing system includes a plurality of computing resources that communicate with each other using network on a chip architecture. One of the plurality of computing resources is attached to memory external to the computing system through an external memory interface. ... Knuedge Inc

08/10/17 / #20170228194

Data routing and buffering in a processing system

In a computing system where an incoming packet can be written directly into one or more local registers of a processing unit, a packet interface routes packets arriving at a computing system to the local registers of the processing unit or to a memory shared by multiple processing units. The shared memory includes a portion configured as a first-in, first-out (fifo) buffer for storing packets arriving for the processing unit when its local registers are full. ... Knuedge Inc

08/03/17 / #20170220520

Determining an operation state within a computing system with multi-core processing devices

Systems and methods for operating a processing device are provided. A method may comprise transmitting data on the processing device, monitoring state information for a plurality of buffers on the processing device for the transmitted data, aggregating the monitored state information, starting a timer in response to determining that all buffers of the plurality of buffers are empty and asserting a drain state for the plurality of buffers in response to all buffers of the plurality of buffers remained empty for the duration of the timer.. ... Knuedge Inc

07/20/17 / #20170206904

Classifying signals using feature trajectories

An input signal may be classified by comparing a trajectory of a sequence of feature vectors of the input signal to sequences of feature vectors of reference signals, wherein the reference signals correspond to classes. For a class, a score may be computed that indicates a match between the trajectory of the input signal with trajectories of reference sequences corresponding to the class. ... Knuedge Inc

07/06/17 / #20170195259

Flow control through packet router

A router requests a reservation for an egress port prior to dequeuing data from an ingress port data queue. A request is also made for the allocation of a buffer. ... Knuedge Inc

07/06/17 / #20170195248

Packet router buffer management

A router that requests a reservation for an egress port prior to dequeuing a received packet. A reservation is granted only if there is space on the egress port for at least a maximum size packet. ... Knuedge Inc

07/06/17 / #20170192901

Disjointed virtual memory scheme with block bypass

An improved virtual memory scheme designed for multi-processor environments that uses processor registers and a small amount of dedicated logic to eliminate the overhead that is associated with the use of page tables. The virtual addressing provides a contiguous virtual address space where the actual real memory is distributed across multiple memories. ... Knuedge Inc

06/08/17 / #20170161069

Microprocessor including permutation instructions

Combinational circuits in a microprocessor execute instructions to perform permutations on bits of a source byte in a single clock cycle. Each bit in the source byte is permuted in accordance with a permutation map. ... Knuedge Inc

06/01/17 / #20170153993

Smart dma engine for a network-on-a-chip processor

A multiprocessor architecture utilizing direct memory access (dma) processors that execute programmed code to feed data to one or more processor cores in advance of those cores requesting data. Stalls of the processor cores are minimized by continually feeding new data directly into the data registers within the cores. ... Knuedge Inc

05/04/17 / #20170125073

Affinity data collection in a computing system

A data collecting instrument including an input coupled with an output network port of a processing device, the input configured to receive a destination address of each data packet transmitted from the output network port, where the processing device is connected to a plurality of processing devices and is configured to transmit data packets from output network ports of the processing device to other devices of the plurality; one or more address registers configured to store information about a destination address range; a counter register configured to store a counter value; and digital circuitry coupled with the input, the one or more address registers, and the counter register; the digital circuitry configured to (i) determine, based on the information stored in the one or more address registers, that the destination address is within the destination address range; and (ii) increment the counter value stored in the counter register.. . ... Knuedge Inc

03/23/17 / #20170083477

Memory controller for a network on a chip device

Systems and methods may be provided to support memory access by packet communication and/or direct memory access. In one aspect, a memory controller may be provided for a processing device containing a plurality of computing resources. ... Knuedge Inc

03/02/17 / #20170060420

Performing write operations in a network on a chip device

Systems and methods are provided for performing write-with-response operations in a network on a chip architecture. In response to receiving an instruction to perform a write-with-response operation, a writer computing resource of a computing system (implemented using the network on a chip architecture) executes this instruction by performing a write operation for writing data to a memory location followed by a response operation for notifying a notification target computing resource of the computing system that the data has been written to the memory location.. ... Knuedge Inc








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