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Mentor Graphics Corporation patents


Recent patent applications related to Mentor Graphics Corporation. Mentor Graphics Corporation is listed as an Agent/Assignee. Note: Mentor Graphics Corporation may have other listings under different names/spellings. We're not affiliated with Mentor Graphics Corporation, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "M" | Mentor Graphics Corporation-related inventors


Lithography model calibration via genetic algorithms with adaptive deterministic crowding and dynamic niching

A set of original model candidates are first grouped into pairs of original model candidates. A pair of child model candidates is generated for each of the pairs of original model candidates by performing mutation, crossover, or both on the each of the pairs of original model candidates. ... Mentor Graphics Corporation

Multi-stage test response compactors

Disclosed herein are exemplary embodiments of a so-called “x-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. ... Mentor Graphics Corporation

Interconnect reuse resolution with bump compensation in a package design

This application discloses a computing system to export route data and connectivity data from a layout design of a package device. The route data describes a structure of an interconnect in the package device. ... Mentor Graphics Corporation

Selective per-cycle masking of scan chains for system level test

Built-in self-test techniques for integrated circuits that address the issue of unknown states. Some implementations use a specialized scan chain selector coupled to a time compactor. ... Mentor Graphics Corporation

Cloud services platform

Embodiments of the disclosed technology comprise a cloud-hosted central service platform that interfaces and enables access to both central and distributed resources and peripherals for connected mobile applications. For example, this platform allows service providers and application developers to create a large number of new classes of applications, leveraging web access to devices, sensors, and/or actuators of any kind. ... Mentor Graphics Corporation

Worst case eye for multi-level pulse amplitude modulated links

This application discloses a computing system to perform a fast evaluation of a worst case eye diagram for a channel capable of communicating signals encoding data in more than two value levels. The computing system can identify multiple step responses of the channel, each corresponding to a transition between a plurality of the value levels. ... Mentor Graphics Corporation

Object recognition and classification using multiple sensor modalities

Object recognition and classification based on data from multiple sensor modalities is disclosed. A computing system can detect an event in a monitored portion of an environment coordinate field associated with a vehicle. ... Mentor Graphics Corporation

Map building with sensor measurements

This application discloses a computing system to implement map building in an assisted or automated driving system. The computing system can track movement of a vehicle based on sensor measurement data populated in an environmental model and vehicle movement measurements. ... Mentor Graphics Corporation

Event-driven region of interest management

This application discloses a computing system to implement event-driven region of interest management in an assisted or automated driving system of a vehicle. The computing system can identify a portion of an environmental model for a vehicle that corresponds to a region of interest for a driving functionality system. ... Mentor Graphics Corporation

Multi-level sensor fusion

This application discloses a computing system to implement multi-level sensor fusion in an assisted or automated driving system of a vehicle. The computing system can populate an environment model with raw measurement data captured by sensors mounted in a vehicle and with data corresponding to a possible object in an coordinate field associated with the environmental model. ... Mentor Graphics Corporation

Event classification and object tracking

This application discloses a computing system to implement object tracking in an assisted or automated driving system of a vehicle. The computing system can assign a pre-classification to a detection event in an environmental model, update the environmental model with new sensor measurements and corresponding detection events over time, and track the detection event in the updated environmental model. ... Mentor Graphics Corporation

Pre-tracking sensor event detection and fusion

This application discloses a computing system to implement pre-tracking sensor event detection and fusion in an assisted or automated driving system of a vehicle. The computing system can receive an environmental model including sensor measurement data from different types of sensors in the vehicle. ... Mentor Graphics Corporation

Low-level sensor fusion

This application discloses a computing system to implement low-level sensor fusion in an assisted or automated driving system of a vehicle. The low-level sensor fusion can include receiving raw measurement data from sensors in the vehicle and temporally aligning the raw measurement data based on a time of capture. ... Mentor Graphics Corporation

Situational awareness determination based on an annotated environmental model

Determining a situational annotation of a vehicle based on an annotated environmental model is disclosed. A computing system receives an annotated environmental model for a vehicle. ... Mentor Graphics Corporation

03/08/18 / #20180067463

Sensor event detection and fusion

This application discloses a computing system to implement sensor event detection and fusion system in an assisted or automated driving system of a vehicle. The computing system can monitor an environmental model to identify spatial locations in the environmental model populated with temporally-aligned measurement data. ... Mentor Graphics Corporation

03/08/18 / #20180066954

Vehicle localization with map-matched sensor measurements

This application discloses a computing system to implement vehicle localization in an assisted or automated driving system. The computing system can receive an environmental model populated with measurement data captured by sensors mounted in a vehicle. ... Mentor Graphics Corporation

02/22/18 / #20180052951

Acceleration of voltage propagation based on device chain reduction

Aspects of the disclosed technology relate to techniques of voltage propagation-based reliability verification. A circuit design is analyzed to identify circuit component chains. ... Mentor Graphics Corporation

02/22/18 / #20180052950

Acceleration of voltage propagation based on local iteration

Aspects of the disclosed technology relate to techniques of voltage propagation-based reliability verification. Voltage values are propagated across components of a circuit design through global iterations until voltage values on nets of the circuit design are not changed from one global iteration to a next global iteration or one preset condition is met. ... Mentor Graphics Corporation

02/15/18 / #20180045780

Timing-aware test generation and fault simulation

Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (atpg) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. ... Mentor Graphics Corporation

02/01/18 / #20180032357

Debug environment for a multi user hardware assisted verification system

Technologies for debugging hardware errors discovered during hardware assisted software verification processes are provided. For example, in one embodiment, a concurrent emulation debug environment including a concurrent emulation system, an emulation trace module and a model state module is provided. ... Mentor Graphics Corporation

01/18/18 / #20180017622

Continuous application and decompression of test patterns and selective compaction of test responses

A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. ... Mentor Graphics Corporation

01/11/18 / #20180011956

Data injection in emulation without rebooting

An emulator is configured with a circuit design model for a circuit design comprising a processor and is running with an operating system. Data are transferred from a computer to a memory in the emulator through a design-independent interface or a transaction-level interface. ... Mentor Graphics Corporation

01/04/18 / #20180004888

Pattern matching using edge-driven dissected rectangles

Aspects of the disclosed technology relate to techniques of pattern matching. Matching rectangles in a layout design that match rectangle members of a search pattern are identified based on edge operations. ... Mentor Graphics Corporation

01/04/18 / #20180004887

Homotopy optimized parasitic extraction

Aspects of the disclosed technology relate to techniques of parasitic extraction. A signature for a set of geometric elements of a layout design is computed based on contour-related information. ... Mentor Graphics Corporation

12/07/17 / #20170351795

Virtual ethernet mutable port group transactor

Disclosed herein are example embodiments of methods, apparatus, and systems for transactors configured for use in a hardware emulation environment and designed to adapt to speed changes dynamically at runtime in addition to providing dynamic port mapping. Among the embodiments disclosed herein is an emulation system comprising one or more configurable hardware components (e.g., configurable logic blocks) configured to implement a mutable port group transactor in communication with a design under test being emulated by the emulation system. ... Mentor Graphics Corporation

11/23/17 / #20170337309

Target capture and replay in emulation

An emulation process is performed with an emulator coupled to one or more targets. During a part or a whole of the emulation process, input signals to the emulator from the one or more targets are being captured, streamed out of the emulator and stored in one or more processor-readable media. ... Mentor Graphics Corporation

11/23/17 / #20170337300

Logic-driven layout pattern analysis

A user or other source may specify one or more components in logical design data, such as schematic netlist design data. Based upon the provided logical component, portions of the physical design data that correspond to the logical component are selected. ... Mentor Graphics Corporation

11/16/17 / #20170329997

Secure mechanism for finite provisioning of an integrated circuit

This application discloses an electronic system including active circuitry configured to be selectively enabled for authorized number of times. The electronic system also includes security circuitry to detect an enablement event associated with the electronic system. ... Mentor Graphics Corporation

11/16/17 / #20170328952

Wide-range clock signal generation for speed grading of logic cores

An integrated circuit for on-chip speed grading comprises test circuitry comprising scan chains and a test controller; and wide-range clock signal generation circuitry comprising phase-locked loop circuitry and frequency divider circuitry. The wide-range clock signal generation circuitry is configured to generate a wide-range test clock signal for the test circuitry to conduct a structural delay test for on-chip speed grading. ... Mentor Graphics Corporation

10/12/17 / #20170293706

Graphical analysis of complex clock trees

This application discloses a computing system to implement a place and route tool to synthesize a clock tree in a layout design of an integrated circuit based on timing constraints for the integrated circuit. The computing system can select a portion of the clock tree to present in a schematic connectivity presentation based on a conformance of the portion of the clock tree to timing constraints for the clock tree. ... Mentor Graphics Corporation

10/05/17 / #20170286592

Automatic axial thrust analysis of turbomachinery designs

Various aspects of the disclosed technology relate to axial thrust analysis of turbomachinery designs. A cavity of a turbomachinery design is divided into sub-cavities. ... Mentor Graphics Corporation

10/05/17 / #20170286588

Full-chip assessment of time-dependent dielectric breakdown

Aspects of the disclosed technology relate to techniques of full-chip assessment of time-dependent dielectric breakdown. A layout design is analyzed to identify matching patterns that match a pre-calculated pattern in a pattern database. ... Mentor Graphics Corporation

10/05/17 / #20170285490

Correcting euv crosstalk effects for lithography simulation

Disclosed are techniques for correcting the euv crosstalk effects. Isolated mask feature component diffraction signals associated with individual layout feature components are determined based on a component-based mask diffraction modeling method such as a domain decomposition method. ... Mentor Graphics Corporation

09/28/17 / #20170277822

Printed circuit board design for manufacturing across multiple suppliers

This application discloses a computing system to parse a product model definition that includes a layout design of a printed circuit board assembly, which identifies physical design characteristics of the layout design of the printed circuit board assembly. The computing system can identify one or more manufacturing processes capable of manufacturing at least a portion of the printed circuit board assembly having the identified physical design characteristics. ... Mentor Graphics Corporation

09/21/17 / #20170270235

Fragmentation point and simulation site adjustment for resolution enhancement techniques

A method of performing a resolution enhancement technique such as opc on an initial layout description involves fragmenting a polygon that represents a feature to be created into a number of edge fragments. One or more of the edge fragments is assigned an initial simulation site at which the image intensity is calculated. ... Mentor Graphics Corporation

09/14/17 / #20170264718

Communication circuitry in an electronic control unit

This application discloses an electronic control unit coupled to a bus in a vehicle communication network. The electronic control unit includes a processing system configured to generate an instruction including an identifier of a type of signal exchanged through a vehicle communication network and including a command associated with exchange of a signal value corresponding to the type of the signal. ... Mentor Graphics Corporation

09/14/17 / #20170262570

Layout design repair using pattern classification

Geometric elements within regions needing lithographic repair are examined to identify characteristics of the patterns formed by those geometric elements. Repair regions with common pattern characteristics then are categorized into classes. ... Mentor Graphics Corporation

09/14/17 / #20170262324

Event queue management for embedded systems

An event management structure for an embedded system, which supports multiple waiters waiting on the same event without replicating the events for each waiter, is provided. Notifications of events are received from entities within an embedded system. ... Mentor Graphics Corporation

08/24/17 / #20170242953

Preserving hierarchy and coloring uniformity in multi-patterning layout design

Layout design data is seeded with sampling markers. The sampling markers are used to determine patterning scores for patterning clusters in the layout design data, such that a patterning score corresponds to a particular coloring arrangement, and the value of a patterning score corresponds to how many of the sampling markers have a given color. ... Mentor Graphics Corporation

08/03/17 / #20170221197

Video inspection system with augmented display content

This application discloses a video inspection system for a rework station, which includes multiple image capture devices to capture multiple images or videos of a printed circuit board assembly, a presentation tool to merge the captured images or video into a image or video, and a display device to present the image video. The presentation tool also can augment the captured video of the printed circuit board assembly with information from a layout design of the printed circuit board assembly. ... Mentor Graphics Corporation

08/03/17 / #20170220729

Directed self-assembly-aware layout decomposition for multiple patterning

Aspects of the disclosed technology relate to techniques of combining directed self-assembly lithography and multiple patterning lithography. A coloring/grouping graph is first generated from layout data of a layout design. ... Mentor Graphics Corporation

08/03/17 / #20170220455

Test case generation using a constraint graph solver

The application discloses a computing system to analyze a program to generate a control flow graph representing paths capable of being traversed through the program during execution. The computing system can translate the control flow graph into a constraint graph representation of the program. ... Mentor Graphics Corporation

07/27/17 / #20170213043

Security hardened controller area network transceiver

This application discloses a controller area network node including a controller and a transceiver. The transceiver includes security circuitry to perform various security checks on messages the controller area network node intends to have transmitted over a shared bus in a controller area network. ... Mentor Graphics Corporation

07/20/17 / #20170205702

Pattern correction in multiple patterning steps

This application discloses a computing system to simulate a wafer image based on a mandrel mask and a block mask to be utilized to print a final wafer image on a substrate. To simulate the wafer image the computing system can estimate dummy sidewalls based on the mandrel mask, estimate contours of the block mask, and determine the simulated wafer image based on differences between the dummy sidewalls and the estimated contours of the block mask. ... Mentor Graphics Corporation

07/20/17 / #20170205462

Power-on self-test and in-system test

An integrated circuit comprises a plurality of built-in self-test circuits, a plurality of sibs (segment insertion bits) coupled to a plurality of registers that are associated with the plurality of built-in self-test circuits, one or more storage devices, and a controller coupled to a part or a whole of an ijtag (ieee 1687) network and to the one or more storage devices. The plurality of sibs and the plurality of registers form the part or the whole of the ijtag network. ... Mentor Graphics Corporation

07/06/17 / #20170193155

Transition test generation for detecting cell internal defects

Aspects of the disclosed technology relate to techniques of test pattern generation based on the cell transition fault model. An assignment for two consecutive clock cycles at inputs of a complex cell in a circuit design is determined based on a gate-level representation of the circuit design. ... Mentor Graphics Corporation

06/29/17 / #20170185710

Testbench restoration based on capture and replay

Messages transmitted from an emulator to a testbench of a part of the testbench are recorded from a starting point of an emulation operation to a checkpoint of the emulation operation. State information of the emulator at the checkpoint is captured and stored. ... Mentor Graphics Corporation

06/29/17 / #20170185708

Controlling real time during embedded system development

Disclosed herein are representative embodiments of methods, systems, and apparatus that can used to control real-time events (e.g., the real-time clock) during the design, simulation, or verification of an embedded system. In one exemplary embodiment disclosed herein, for example, a real-time clock signal is generated and tasks defined by an embedded software application are triggered with the real-time clock signal. ... Mentor Graphics Corporation

06/08/17 / #20170161408

Topology recognition

This application discloses tools to build a topology library including one or more topologies, each of which includes a description of multiple transistors, their parameters, and associated connectivity, and also includes rules or criteria to be utilized in downstream design flow processes. The tools can analyze a circuit design describing an electronic device to recognize a subset of transistors in the electronic device has a pre-defined circuit topology, and identify layout rules or simulation criteria for the transistors in the recognized circuit topology. ... Mentor Graphics Corporation

06/08/17 / #20170161403

Assertion statement check and debug

This application discloses a computing system to check and generate an assertion statement. The assertion statement, when executed during a simulation of a circuit design, can verify a simulated behavior of the circuit design. ... Mentor Graphics Corporation

05/18/17 / #20170141930

Test point-enhanced hardware security

Various aspects of the disclosed technology relate to techniques of using control test points to enhance hardware security. The design-for-security circuitry reuses control test points, a part of design-for-test circuitry. ... Mentor Graphics Corporation

05/18/17 / #20170140084

Low power corruption of memory in emulation

Aspects of the disclosed technology relate to techniques for corrupting memories in emulation. After a power domain in a circuit design being emulated in an emulator is powered down, a main memory model for a memory in the power domain is corrupted and a cache memory model for the memory is invalidated. ... Mentor Graphics Corporation

05/18/17 / #20170140083

Modeling memory in emulation based on cache

Aspects of the disclosed technology relate to techniques for modeling memories in emulation. An emulator is configured to implement an emulation model for a circuit design and a cache memory model for a memory accessible by the circuit design. ... Mentor Graphics Corporation

05/18/17 / #20170140082

Target capture and replay in emulation

An emulation process is performed with an emulator coupled to one or more targets. During a part or a whole of the emulation process, input signals to the emulator from the one or more targets are being captured, streamed out of the emulator and stored in one or more processor-readable media. ... Mentor Graphics Corporation

05/11/17 / #20170134175

Tolerant of absolute offsets physical unclonable function device

This application discloses a physical unclonable function device including physical unclonable function units, each capable of generating an output. The physical unclonable function device can utilize transforms to derive bits from the outputs and utilize the derived bits to generate an identifier for the physical unclonable function device. ... Mentor Graphics Corporation

05/11/17 / #20170132434

Measure variation tolerant physical unclonable function device

This application discloses a physical unclonable function device including physical unclonable function units, each capable of generating an output. The physical unclonable function device can extract bits from the outputs at various inspection locations and utilize the extracted bits to generate an identifier for the physical unclonable function device. ... Mentor Graphics Corporation

04/20/17 / #20170109459

Simultaneous retargeting of layout features based on process window simulation

Various aspects of the disclosed technology relate to techniques of retargeting layout features. A process window simulation on a layout design is performed to generate process window information that comprises predicted print positions of layout features computed under various process conditions. ... Mentor Graphics Corporation

04/13/17 / #20170103158

Generating root cause candidates for yield analysis

Aspects of the invention relate to yield analysis techniques for generating root cause candidates for yield analysis. With various implementations of the invention, points of interest are first identified in a layout design. ... Mentor Graphics Corporation

04/13/17 / #20170103156

Hybrid compilation for fpga prototyping

Aspects of the disclosed technology relate to techniques of design implementation for fpga prototyping. An initial fpga-mapped netlist and a generic rtl design associated with the initial fpga-mapped netlist are generated based on an original rtl (register-transfer level) design for a circuit design and optionally on verification-related features. ... Mentor Graphics Corporation

03/30/17 / #20170091356

Subtractive design for heat sink improvement

Aspects of the disclosed technology relate to techniques of improving heat sink designs based on systematic mass removal. A thermal simulation is performed to determine thermal property values for a heat sink design. ... Mentor Graphics Corporation

03/02/17 / #20170063821

Secure protocol for chip authentication

This application discloses a supply chain security technique that enrolls an integrated circuit with a security server and subsequently utilizes the enrollment to authenticate the integrated circuit. The integrated circuit can include security circuitry to enroll the integrated circuit with the security server by generating an enrollment message—including a fingerprint code having an encoded version of a private value generated by the security circuitry—for transmission to the security server. ... Mentor Graphics Corporation

02/23/17 / #20170053052

Multi-fpga prototyping of an asic circuit

The invention concerns a method of designing a prototype comprising a plurality of programmable chips, such as fpga chips, for modelling an asic circuit, said asic circuit being intended to implement a logic design comprising a hierarchy of logic modules communicating together. The method according to the invention comprises the steps of:—partitioning the hierarchy of logic modules into regions each comprising one or a plurality of programmable chips, while minimising:—inter-region communications in a manner correlated to the physical connections available between each pair of programmable chips;—and the number of crossings of programmable chips of a critical combinatorial path;—establishing a routing of the signals between programmable chips using the physical resources available.. ... Mentor Graphics Corporation

02/23/17 / #20170052227

Selective per-cycle masking of scan chains for system level test

Built-in self-test techniques for integrated circuits that address the issue of unknown states. Some implementations use a specialized scan chain selector coupled to a time compactor. ... Mentor Graphics Corporation

01/12/17 / #20170011139

Physically-aware circuit design partitioning

This application discloses a computing system implementing a synthesis tool to synthesize a circuit design of an electronic system into a gate-level netlist having a logical hierarchy, utilize the gate-level netlist to generate a physical representation of the circuit design, and partition the circuit design into sub-designs based on the physical representation of the circuit design. The computing system can generate physical modules having self-contained physical definitions from the sub-designs, and reassemble the physical modules into a gate-level netlist having a physical hierarchy corresponding to the partitions of the circuit design. ... Mentor Graphics Corporation

01/05/17 / #20170004250

Integrated circuit layout design methodology with process variation bands

A system for analyzing ic layouts and designs by calculating variations of a number of objects to be created on a semiconductor wafer as a result of different process conditions. The variations are analyzed to determine individual feature failures or to rank layout designs by their susceptibility to process variations. ... Mentor Graphics Corporation








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