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Micron Technology Inc patents


Recent patent applications related to Micron Technology Inc. Micron Technology Inc is listed as an Agent/Assignee. Note: Micron Technology Inc may have other listings under different names/spellings. We're not affiliated with Micron Technology Inc, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "M" | Micron Technology Inc-related inventors


 new patent  Computerized apparatus with a high speed data bus

A computerized apparatus configured for high-speed data transactions between components thereof. In one embodiment, the computerized apparatus includes a high-speed ring data bus apparatus with a plurality of nodes, and associated application apparatus in data communication with at least one of the nodes. ... Micron Technology Inc

 new patent  Memory cells, semiconductor devices including the memory cells, and methods of operation

Memory cells are disclosed, which cells include a cell material and an ion-source material over the cell material. A discontinuous interfacial material is included between the cell material and the ion-source material. ... Micron Technology Inc

 new patent  Integrated memory

Some embodiments include an integrated memory having an array of capacitors. The array has edges. ... Micron Technology Inc

 new patent  Methods of forming an array of capacitors, methods of forming an array of memory cells individually comprising a capacitor and a transistor, arrays of capacitors, and arrays of memory cells individually comprising a capacitor and a transistor

A method of forming an array of capacitors comprises forming elevationally-extending and longitudinally-elongated capacitor electrode lines over a substrate. Individual of the capacitor electrode lines are common to and a shared one of two capacitor electrodes of individual capacitors longitudinally along a line of capacitors being formed. ... Micron Technology Inc

 new patent  Memory cells and methods of forming a capacitor

A memory cell comprises a capacitor having a first conductive capacitor electrode having laterally-spaced walls that individually have a top surface. A second conductive capacitor electrode is laterally between the walls of the first capacitor electrode, and comprises a portion above the first capacitor electrode. ... Micron Technology Inc

 new patent  Methods of forming an array comprising pairs of vertically opposed capacitors and arrays comprising pairs of vertically opposed capacitors

A method of forming an array comprising pairs of vertically opposed capacitors comprises forming a conductive lining in individual capacitor openings in support material. An elevational mid-portion of individual of the conductive linings is removed to form an upper capacitor electrode lining and a lower capacitor electrode lining that are elevationally separate and spaced from one another in the individual capacitor openings. ... Micron Technology Inc

 new patent  Memory cells, arrays of two transistor-one capacitor memory cells, methods of forming an array of two transistor-one capacitor memory cells, and methods used in fabricating integrated circuitry

A two transistor-one capacitor memory cell comprises first and second transistors laterally displaced relative one another. A capacitor is above the first and second transistors. ... Micron Technology Inc

 new patent  Memory cell, an array of memory cells individually comprising a capacitor and a transistor with the array comprising rows of access lines and columns of digit lines, a 2t-1c memory cell, and methods of forming an array of capacitors and access transistors there-above

A method of forming an array of capacitors and access transistors there-above comprises forming access transistor trenches partially into insulative material. The trenches individually comprise longitudinally-spaced masked portions and longitudinally-spaced openings in the trenches longitudinally between the masked portions. ... Micron Technology Inc

 new patent  Silicon chalcogenate precursors and methods of forming the silicon chalcogenate precursors

A silicon chalcogenate precursor comprising the chemical formula of si(xr1)nr24-n, where x is sulfur, selenium, or tellurium, r1 is hydrogen, an alkyl group, a substituted alkyl group, an alkoxide group, a substituted alkoxide group, an amide group, a substituted amide group, an amine group, a substituted amine group, or a halogen group, each r2 is independently hydrogen, an alkyl group, a substituted alkyl group, an alkoxide group, a substituted alkoxide group, an amide group, a substituted amide group, an amine group, a substituted amine group, or a halogen group, and n is 1, 2, 3, or 4. Methods of forming the silicon chalcogenate precursor, methods of forming silicon nitride, and methods of forming a semiconductor structure are also disclosed.. ... Micron Technology Inc

 new patent  Setting a default read signal based on error correction

The present disclosure includes apparatuses and methods related to setting a default read signal based on error correction. A number of methods can include reading a page of data from a group of memory cells with a first discrete read signal and error correcting at least one codeword of the page of data as read with the first discrete read signal. ... Micron Technology Inc

 new patent  Apparatuses and methods for a memory device with dual common data i/o lines

Apparatuses are presented for a semiconductor device utilizing dual i/o line pairs. The apparatus includes a first i/o line pair coupled to a first local i/o line pair. ... Micron Technology Inc

 new patent  Methods and apparatuses for providing a program voltage responsive to a voltage determination

Apparatuses and methods for providing a program voltage responsive to a voltage determination are described. An example apparatus includes a memory array comprising a plurality of access lines. ... Micron Technology Inc

 new patent  Virtual address table

The present disclosure includes apparatuses and methods related to virtual address tables. An example method comprises generating an object file that comprises: an instruction comprising a number of arguments; and an address table comprising a number of indexed address elements. ... Micron Technology Inc

 new patent  Directed sanitization of memory

The present disclosure includes apparatuses and methods for directed sanitization of memory. One example method comprises, responsive to receiving a sanitization command, performing a deterministic garbage collection operation on a memory, wherein performing the deterministic garbage collection operation results in physical erasure of all invalid data stored on the memory without losing valid data stored on the memory.. ... Micron Technology Inc

07/12/18 / #20180196705

 new patent  Identifying asynchronous power loss

Apparatus include controllers configured to iteratively program a group of memory cells to respective desired data states; determine whether a power loss to the apparatus is indicated while iteratively programming the group of memory cells; and if a power loss to the apparatus is indicated, to change the desired data state of the particular memory cell before continuing with the programming. Apparatus further include controllers configured to read a particular memory cell of a last written page of memory cells, determine whether a threshold voltage of the particular memory cell is less than a particular voltage level, and to mark the last written page of memory cells as affected by power loss during a programming operation of the last written page of memory cells when the threshold voltage of the particular memory cell is determined to be higher than the particular voltage level.. ... Micron Technology Inc

07/12/18 / #20180196614

 new patent  Error correction

An example apparatus for error correction can include an array of memory cells and a controller. The controller can be configured to perform a dummy read on a portion of data stored in the array. ... Micron Technology Inc

07/12/18 / #20180195049

 new patent  Arrays of memory cells individually comprising a capacitor and an elevationally-extending transistor, methods of forming a tier of an array of memory cells, and methods of forming an array of memory cells individually comprising a capacitor and an elevationally-extending transistor

A method of forming a tier of an array of memory cells within an array area, the memory cells individually comprising a capacitor and an elevationally-extending transistor, the method comprising using two, and only two, sacrificial masking steps within the array area of the tier in forming the memory cells. Other methods are disclosed, as are structures independent of method of fabrication.. ... Micron Technology Inc

07/05/18 / #20180192517

Apparatus and methods for via connection with reduced via currents

Apparatuses and methods including conductive vias of a printed circuit board are described. An example apparatus includes a first layer including a first conductive plate; a component on the first layer, a second layer including a second conductive plate that may be coupled to an external power source; a third layer between the first layer and the second layer, the third layer including a third conductive plate; a first via coupling the first conductive plate to the second conductive plate; and a second via coupled to the first conductive plate. ... Micron Technology Inc

07/05/18 / #20180191528

Testing impedance adjustment

Methods of operating integrated circuit devices include generating a voltage level at a particular node in response to a first voltage level applied to a termination device and a second voltage level applied to a reference resistance; determining whether a plurality of available resistance values of the termination device satisfy a criterion that each available resistance value is either less than a resistance value of the reference resistance, or each available resistance value is greater than the resistance value of the reference resistance; and, when the plurality of available resistance values of the termination device satisfy the criterion, determining whether a voltage level generated at the particular node for a particular available resistance value of the plurality of available resistance values is between a voltage level of a first reference voltage and a voltage level of a second reference voltage.. . ... Micron Technology Inc

07/05/18 / #20180190873

Solid state transducer dies having reflective features over contacts and associated systems and methods

Systems and methods for improved light emitting efficiency of a solid state transducer (sst), for example light emitting diodes (led), are disclosed. One embodiment of an sst die in accordance with the technology includes a reflective material disposed over electrical connectors on a front side of the die. ... Micron Technology Inc

07/05/18 / #20180190862

Solid state lighting devices with dielectric insulation and methods of manufacturing

Solid state lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state lighting device includes a first semiconductor material, a second semiconductor material spaced apart from the first semiconductor material, and an active region between the first and second semiconductor materials. ... Micron Technology Inc

07/05/18 / #20180190761

Mim capacitor with enhanced capacitance

A metal-insulator-metal (mim) capacitor is disclosed. The mim capacitor includes a substrate having a first dielectric layer thereon and a bottom electrode embedded in the first dielectric layer. ... Micron Technology Inc

07/05/18 / #20180190717

Memory devices, systems, and methods of forming arrays of memory cells

Memory devices include an array of memory cells including magnetic tunnel junction regions. The array of memory cells includes access lines extending in a first direction and data lines extending in a second direction transverse to the first direction. ... Micron Technology Inc

07/05/18 / #20180190713

Magnetic memory device with grid-shaped common source plate, system, and method of fabrication

Magnetic memory devices include an array of magnetic memory cells including magnetic tunnel junction regions. The array of magnetic memory cells includes access lines extending in a column direction and data/sense lines extending in a row direction transverse to the column direction. ... Micron Technology Inc

07/05/18 / #20180190620

Interconnect structures with intermetallic palladium joints and associated systems and methods

Interconnect structures with intermetallic palladium joints are disclosed herein. In one embodiment, a method of forming an interconnect structure includes depositing a first conductive material comprising nickel on a first conductive surface of a first die, and depositing a second conductive material comprising nickel on a second conductive surface of a second die spaced apart from the first surface. ... Micron Technology Inc

07/05/18 / #20180190613

Wiring with external terminal

Apparatuses for providing external terminals of a semiconductor device are described. An example apparatus includes: a connection wiring of a ring-shape having comprising a hole and a conductive layer surrounding the hole, the conductive layer including a first connection point and a second connection point that are located so that a straight line between the first connection point and the second connection point crosses over the hole; an external terminal coupled to the first connection point of the conductive layer of the connection wiring; and an internal circuit coupled to the second connection point of the conductive layer of the connection wiring.. ... Micron Technology Inc

07/05/18 / #20180190587

Semiconductor device structures including stair step structures, and related semiconductor devices

A method of forming a semiconductor device assembly comprises forming tiers comprising conductive structures and insulating structures in a stacked arrangement over a substrate. Portions of the tiers are selectively removed to form a stair step structure comprising a selected number of steps exhibiting different widths corresponding to variances in projected error associated with forming the steps. ... Micron Technology Inc

07/05/18 / #20180190582

Semiconductor package with embedded mim capacitor, and method of fabricating thereof

An interposer includes a first redistribution layer, an organic substrate, a capacitor, a hard mask layer, a conductive pillar, and a second redistribution layer. The organic substrate is on the first redistribution layer. ... Micron Technology Inc

07/05/18 / #20180190571

Semiconductor device having through-silicon-via and methods of forming the same

Semiconductor devices having a through-silicon-via and methods of forming the same are described herein. As an example, a semiconductor device may include a substrate material, a through-silicon-via protrusion extending from the substrate material, a first dielectric material formed on the substrate material, a second dielectric material formed on the first dielectric material, and an interconnect formed on the through-silicon-via protrusion, where the interconnect formed is in an opening in the second dielectric material.. ... Micron Technology Inc

07/05/18 / #20180190531

Semiconductor package structures including redistribution layers

A package structure and a method for fabricating thereof are provided. The package structure includes a substrate, a first connector, a redistribution layer, a second connector, and a chip. ... Micron Technology Inc

07/05/18 / #20180190368

Timing based arbiter systems and circuits for zq calibration

Systems and apparatuses are provided for an arbiter circuit for timing based zq calibration. An example system includes a resistor and a plurality of chips. ... Micron Technology Inc

07/05/18 / #20180190367

Apparatuses and methods for memory testing and repair

Some embodiments include apparatuses and methods having a first interface to communicate with a processing unit, a second interface to communicate with a memory device, and a module coupled to the first and second interfaces. In at least one of the embodiments, the module can be configured to obtain information stored in the memory device and perform at least one of testing and repairing of a memory structure of the memory device based at least in part on the information.. ... Micron Technology Inc

07/05/18 / #20180190349

Accessing memory cells in parallel in a cross-point array

Methods and structures for accessing memory cells in parallel in a cross-point array include accessing in parallel a first memory cell disposed between a first selected column and a first selected row and a second memory cell disposed between a second selected column different from the first selected column and a second selected row different from the first selected row. Accessing in parallel includes simultaneously applying access biases between the first selected column and the first selected row and between the second selected column and the second selected row. ... Micron Technology Inc

07/05/18 / #20180190347

Programming memories with multi-level pass signal

Methods of operating a memory include applying a first voltage level to control gates of a plurality of memory cells selected to be programmed while applying a second voltage level to a respective data line for each memory cell of the plurality of memory cells; increasing the voltage level applied to the respective data line for memory cells of a first subset of memory cells to a third voltage level then increasing the voltage level applied to the control gates of the plurality of memory cells to a fourth voltage level; increasing the voltage level applied to the respective data line for each memory cell of a second subset of memory cells of the plurality of memory cells to a fifth voltage level then; and after increasing the voltage level applied to the respective data line for each memory cell of the second subset of memory cells to the fifth voltage level, increasing the voltage level applied to the control gates of the plurality of memory cells to a sixth voltage level.. . ... Micron Technology Inc

07/05/18 / #20180190342

Oscillator controlled random sampling method and circuit

Various embodiments comprise methods and apparatuses for selecting a randomly-chosen seed row from among a stream of available data in a memory system. A refresh operation is then performed on at least one selected row of memory in the memory system based on the randomly-chosen seed row. ... Micron Technology Inc

07/05/18 / #20180190337

Ground reference scheme for a memory cell

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ground reference scheme may be employed in a digit line voltage sensing operation. ... Micron Technology Inc

07/05/18 / #20180190334

Apparatuses and methods for performing logical operations using sensing circuitry

The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry comprising a primary latch coupled to a sense line of the array. ... Micron Technology Inc

07/05/18 / #20180189031

Multiplication operations in memory

Examples of the present disclosure provide apparatuses and methods for performing multi-variable bit-length multiplication operations in a memory. An example method comprises performing a multiplication operation on a first vector and a second vector. ... Micron Technology Inc

07/05/18 / #20180188996

Apparatuses and methods for data transfer from sensing circuitry to a controller

The present disclosure describes data transfer in a memory device from sensing circuitry to controller. An example apparatus includes a controller coupled to a memory device. ... Micron Technology Inc

07/05/18 / #20180188965

Write command overlap detection

The present disclosure includes methods and apparatuses that include write command overlap detection. A number of embodiments include receiving an incoming write command and comparing a logical address of the incoming write command to logical addresses of a number of write commands in a queue using a tree data structure, wherein a starting logical address and/or an ending logical address of the incoming write command and a starting logical address and/or an ending logical address of each of the number of write commands are associated with nodes in the tree data structure.. ... Micron Technology Inc

07/05/18 / #20180188647

Methods of forming photonic device structures and electronic devices

A method of forming a photonic device structure comprises forming a photoresist over a photonic material over a substrate. The photoresist is exposed to radiation through a gray-tone mask to form at least one photoexposed region and at least one non-photoexposed region of the photoresist. ... Micron Technology Inc

06/28/18 / #20180182765

Methods of forming memory arrays

Some embodiments include a method of forming a memory array. A wordline is formed to extend along a first direction, and along a rail of semiconductor material. ... Micron Technology Inc

06/28/18 / #20180182764

Memory arrays comprising ferroelectric capacitors

Some embodiments include a memory array which has rows of fins. Each fin has a first pedestal, a second pedestal and a trough between the first and second pedestals. ... Micron Technology Inc

06/28/18 / #20180182763

Memory arrays

Some embodiments include a memory array having memory cells arranged in rows and columns. The rows extend along a first direction and the columns extend along a second direction, with an angle between the first and second directions being less than 90°. ... Micron Technology Inc

06/28/18 / #20180182762

Memory arrays

Some embodiments include a memory array having rows of fins. Each fin has at least one channel region. ... Micron Technology Inc

06/28/18 / #20180182761

Memory devices, memory arrays, and methods of forming memory arrays

Some embodiments include a memory device. The device has a fin with a first source/drain region, a second source/drain region and a channel region. ... Micron Technology Inc

06/28/18 / #20180182457

Apparatuses and methods including memory access in cross point memory

Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch configured to apply a signal to one of the first and second conductive lines. In at least one of such embodiments, the switch can include a phase change material. ... Micron Technology Inc

06/28/18 / #20180181464

Apparatuses and methods for selective determination of data error repair

Apparatuses and methods are described for selective determination of data error repair. An example apparatus includes a memory array and a controller coupled to the memory array. ... Micron Technology Inc

06/21/18 / #20180176443

Method and apparatus providing pixel array having automatic light control pixels and image capture pixels

A pixel array uses two sets of pixels to provide accurate exposure control. One set of pixels provide continuous output signals for automatic light control (alc) as the other set integrates and captures an image. ... Micron Technology Inc

06/21/18 / #20180175145

Memory arrays

The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. ... Micron Technology Inc

06/21/18 / #20180175085

Elevated pocket pixels, imaging devices and systems including the same and method of forming the same

An elevated photosensor for image sensors and methods of forming the photosensor. The photosensor may have light sensors having indentation features including, but not limited to, v-shaped, u-shaped, or other shaped features. ... Micron Technology Inc

06/21/18 / #20180175059

Stack of horizontally extending and vertically overlapping features, methods of forming circuitry components, and methods of forming an array of memory cells

A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The stack has a primary portion and an end portion. ... Micron Technology Inc

06/21/18 / #20180175039

Conductive structures, wordlines and transistors

Some embodiments include a conductive structure which has a first conductive material having a work function of at least 4.5 ev, and a second conductive material over and directly against the first conductive material. The second conductive material has a work function of less than 4.5 ev, and is shaped as an upwardly-opening container. ... Micron Technology Inc

06/21/18 / #20180175017

Apparatuses and methods for semiconductor circuit layout

Apparatuses including circuit layout regions of a semiconductor device and methods of designing the circuit layout regions of a semiconductor device are described. An example apparatus includes a first layout region including a first transistor area including at least one first transistor, at least one contact in proximity to the first transistor area, and a first resistor area comprising at least one first resistor coupled to the at least one first transistor. ... Micron Technology Inc

06/21/18 / #20180174993

Uniform electrochemical plating of metal onto arrays of pillars having different lateral densities and related technology

A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies spaced apart from one another. The first semiconductor die has a major surface with non-overlapping first and second regions. ... Micron Technology Inc

06/21/18 / #20180174960

Memory devices, semiconductor devices and related methods

Conductive structures include a plurality of conductive steps and a contact extending at least partially therethrough in communication with at least one of the plurality of conductive steps and insulated from at least another one of the conductive steps. Devices may include such conductive structures. ... Micron Technology Inc

06/21/18 / #20180174943

Semiconductor die assembly having heat spreader that extends through underlying interposer and related technology

A semiconductor die assembly in accordance with an embodiment of the present technology includes a first semiconductor die, a package substrate underlying the first semiconductor die, an interposer between the package substrate and the first semiconductor die, and a second semiconductor die between the package substrate and the interposer. The semiconductor die assembly further comprises a heat spreader including a cap thermally coupled to the first semiconductor die at a first elevation, and a pillar thermally coupled to the second semiconductor die at a second elevation different than the first elevation. ... Micron Technology Inc

06/21/18 / #20180174926

Semiconductor devices comprising nitrogen-doped gate dielectric, and methods of forming semiconductor devices

Some embodiments include semiconductor devices having first transistors of a first channel type and having second transistors of a second channel type. The first transistors include a first gate electrode, a first nitrogen-doped gate dielectric layer and a first high-k material. ... Micron Technology Inc

06/21/18 / #20180174902

Conductive interconnect structures incorporating negative thermal expansion materials and associated systems, devices, and methods

Semiconductor devices having interconnects incorporating negative expansion (nte) materials are disclosed herein. In one embodiment a semiconductor device includes a substrate having an opening that extends at least partially through the substrate. ... Micron Technology Inc

06/21/18 / #20180174630

Modified decode for corner turn

Examples of the present disclosure provide apparatuses and methods for performing a corner turn using a modified decode. An example apparatus can comprise an array of memory cell and decode circuitry coupled to the array and including logic configured to modify an address corresponding to at least one data element in association with performing a corner turn operation on the at least one data element. ... Micron Technology Inc

06/21/18 / #20180174625

Apparatuses, circuits, and methods for biasing signal lines

Apparatuses, circuits, and methods are disclosed for biasing signal lines in a memory array. In one such example the memory array includes a signal line coupled to a plurality of memory cells and is configured to provide access to the plurality of memory cells responsive to a biasing condition of the signal line. ... Micron Technology Inc

06/21/18 / #20180174622

Power delivery circuitry

A memory device may include a memory system and an energy storage device. Additionally, the energy storage device may supply a first power to the memory system when a second power from a power supply is eliminated or insufficient.. ... Micron Technology Inc

06/21/18 / #20180173621

Unaligned data coalescing

The present disclosure includes methods and systems for coalescing unaligned data. One method includes receiving a first write command associated with a first unaligned portion of data, receiving a second write command associated with a second unaligned portion of data, and coalescing the first unaligned portion of data and the second unaligned portion of data, wherein coalescing includes writing the first unaligned portion of data and the second unaligned portion of data to a page in a memory device.. ... Micron Technology Inc

06/21/18 / #20180173499

Multiplication operations in memory

Examples of the present disclosure provide apparatuses and methods for performing multiplication operations in a memory. An example method comprises performing a multiplication operation on a first element stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array and a second element stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array. ... Micron Technology Inc

06/21/18 / #20180173267

Methods and apparatuses including a process, voltage, and temperature independent current generator circuit

Apparatuses, methods, and current generators that generate current are described. An example apparatus includes a current source configured to provide a current. ... Micron Technology Inc

06/14/18 / #20180167194

Wireless devices and systems including examples of cross correlating wireless transmissions

Examples described herein include systems and methods which include wireless devices and systems with examples of cross correlation including symbols indicative of radio frequency (rf) energy. An electronic device including a statistic calculator may be configured to calculate a statistic including the cross-correlation of the symbols. ... Micron Technology Inc

06/14/18 / #20180167055

Apparatuses and methods for calibrating adjustable impedances of a semiconductor device

Apparatuses and methods for calibrating adjustable impedances of a semiconductor device are disclosed in the present application. An example apparatus includes a register configured to store impedance calibration information and further includes programmable termination resistances having a programmable impedance. ... Micron Technology Inc

06/14/18 / #20180167030

Apparatuses and methods for temperature independent oscillators

Apparatuses and methods for temperature independent oscillator circuits are disclosed herein. An example apparatus may include a pulse generator circuit configured to provide a periodic pulse based on the charging and discharging of a capacitor and further based on a reference voltage. ... Micron Technology Inc

06/14/18 / #20180166811

Board edge connector

Apparatuses and methods for forming serial advanced technology attachment (sata) board edge connectors with electroplated hard gold contacts. One example method can include forming a tie bar on an inner layer of a printed circuit board (pcb), forming a trace on an outer layer of the pcb, forming a via, wherein the via electrically couples the tie bar to the trace, forming a contact coupled to the trace on the outer layer, and sending an electrical charge from the tie bar through the via and the trace to the contact to electroplate the contact.. ... Micron Technology Inc

06/14/18 / #20180166629

Phase change memory stack with treated sidewalls

Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming the memory stack out of a plurality of elements. ... Micron Technology Inc

06/14/18 / #20180166464

Integrated structures and methods of forming vertically-stacked memory cells

Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, vertically-stacked memory cells within the conductive levels, an insulative material over the stack and a select gate material over the insulative material. An opening extends through the select gate material, through the insulative material, and through the stack of alternating dielectric and conductive levels. ... Micron Technology Inc

06/14/18 / #20180166317

Semiconductor with through-substrate interconnect

Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. ... Micron Technology Inc

06/14/18 / #20180166151

Ferroelectric memory cell recovery

Methods, systems, and devices for recovering fatigued ferroelectric memory cells are described. Recovery voltages may be applied to a ferroelectric memory cell that is fatigued due to repeated access (read or write) operations. ... Micron Technology Inc

06/14/18 / #20180166138

Resistance variable element methods and apparatuses

Apparatus and methods are disclosed, including a method that performs a first operation on a first resistance variable element using a common source voltage, a first data line voltage and a first control gate voltage, and then performs a second operation on a second resistance variable element using the common source voltage, a second data line voltage and a second control gate voltage. Additional apparatus and methods are described.. ... Micron Technology Inc

06/14/18 / #20180165440

System and method for controlling user access to an electronic device

A method and system for authenticating a user to access a computer system. The method comprises communicating security information to the computer system, and providing the computer system with an implicit input. ... Micron Technology Inc

06/07/18 / #20180159933

Memory network methods, apparatus, and systems

Apparatus and systems may include a first node group include a first network node coupled to a memory, the first network node including a first port, a second port, a processor port, and a hop port. Network node group may include a second network node coupled to a memory, the second network node including a first port, a second port, a processor port, and a hop port, the hop port of the second network node coupled to the hop port of the first network node and configured to communicate between the first network node and the second network node. ... Micron Technology Inc

06/07/18 / #20180159692

Solid state storage device with command and control access

Several embodiments of memory devices and systems with command and control access are described herein. In one embodiment, a memory device includes a controller having a processor and a memory component operably coupled to the processor. ... Micron Technology Inc

06/07/18 / #20180158800

Apparatus and method of power transmission sensing for stacked devices

Apparatuses for supplying power supply voltage in a plurality of dies are described. An example apparatus includes: a circuit board; a regulator on the circuit board that regulates a first voltage; a semiconductor device on the circuit board that receives the first voltage through a power line in the circuit board. ... Micron Technology Inc

06/07/18 / #20180158778

Packaged semiconductor assemblies and methods for manufacturing such assemblies

Packaged semiconductor assemblies including interconnect structures and methods for forming such interconnect structures are disclosed herein. One embodiment of a packaged semiconductor assembly includes a support member having a first bond-site and a die carried by the support member having a second bond-site. ... Micron Technology Inc

06/07/18 / #20180158751

Semiconductor device packages with direct electrical connections and related methods

Semiconductor device packages in accordance with this disclosure may include a substrate and a stack of semiconductor dice attached to the substrate. An uppermost semiconductor die of the stack of semiconductor dice located on a side of the stack of semiconductor dice opposite the substrate may be a heat-generating component configured to generate more heat than each other semiconductor die of the stack of semiconductor dice. ... Micron Technology Inc

06/07/18 / #20180158527

Volatile memory architecutre in non-volatile memory devices and related controllers

In some embodiments, one register of a non-volatile memory can be used for read operations and another register of the non-volatile memory can be used for programming operations. For instance, a cache register of a nand flash memory can be used in connection with read operations and a data register of the nand flash memory can be used in connection with programming operations. ... Micron Technology Inc

06/07/18 / #20180158504

Apparatuses and methods for controlling refresh operations

An apparatus includes a first word line, a second word line and a control. The second word line is contiguous to the first word line. ... Micron Technology Inc

06/07/18 / #20180158502

Dynamic reference voltage determination

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A first value may be written to a first memory cell and a second value may be written to a second memory cell. ... Micron Technology Inc

06/07/18 / #20180158501

Dynamic adjustment of memory cell digit line capacitance

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ferroelectric memory cell may be used to store a logic state. ... Micron Technology Inc

06/07/18 / #20180157439

Memory protocol

The present disclosure includes apparatuses and methods related to a memory protocol. An example apparatus can execute a read command that includes a first chunk of data and a second chunk of data by assigning a first read identification (rid) number to the first chunk of data and a second rid number to the second chunk of data, sending the first chunk of data and the first rid number to a host, and sending the second chunk of data and the second rid number to the host. ... Micron Technology Inc

05/31/18 / #20180152330

Wireless devices and systems including examples of mixing input data with coefficient data

Examples described herein include systems and methods which include wireless devices and systems with examples of mixing input data with coefficient data. For example, a computing system with processing units may mix the input data for a transmission in a radio frequency (rf) wireless domain with the coefficient data to generate output data that is representative of the transmission being processed according to the wireless protocol in the rf wireless domain. ... Micron Technology Inc

05/31/18 / #20180151798

Multiferroic magnetic tunnel junction devices

Some embodiments include a magnetic tunnel junction device having a first magnetic electrode, a second magnetic electrode, and a tunnel insulator material between the first and second magnetic electrodes. A tungsten-containing material is directly against one of the magnetic electrodes. ... Micron Technology Inc

05/31/18 / #20180151415

Forming array contacts in semiconductor memories

Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. ... Micron Technology Inc

05/31/18 / #20180151207

Memory device with write data bus control

Apparatuses and methods for transmitting data between a plurality of chips are described. An example apparatus includes: a first chip, wherein the first chip includes a receiver that receives a data strobe signal and further generates an internal strobe signal responsive, at least in part, to the data strobe signal, the internal strobe signal including a first edge and a second edge following the first edge; a buffer circuit coupled to a set of input terminals and captures first data at the set of input terminals responsive, at least in part, to the first edge of the internal strobe signal and further captures second data at the set of input terminals responsive, at least in part, to the second edge of the internal strobe signal; a driver coupled between the buffer circuit and a set of data terminals and configured to be activated to provide the first and second data from the buffer circuit to the set of data terminals responsive, at least in part, to a control signal; and a width expanding circuit that provides the control signal responsive, at least in part, to the internal strobe signal.. ... Micron Technology Inc

05/31/18 / #20180151206

Apparatuses for modulating threshold voltages of memory cells

Apparatuses for increasing the voltage budget window of a memory array are described. One or more pre-bias voltages may be applied across a selected cell by providing voltages to memory access lines coupled to the selected cell. ... Micron Technology Inc

05/31/18 / #20180151201

Interconnections for 3d memory

Apparatuses and methods for interconnections for 3d memory are provided. One example apparatus can include a stack of materials including a plurality of pairs of materials, each pair of materials including a conductive line formed over an insulation material. ... Micron Technology Inc

05/31/18 / #20180150625

System and method for controlling user access to an electronic device

A method and system for authenticating a user to access a computer system. The method comprises communicating security information to the computer system, and providing the computer system with an implicit input. ... Micron Technology Inc

05/24/18 / #20180146146

Method, apparatus and system providing a storage gate pixel with high dynamic range

A method, apparatus and system are described providing a high dynamic range pixel. An integration period has multiple sub-integration periods during which charges are accumulated in a photosensor and repeatedly transferred to a storage node, where the charges are accumulated for later transfer to another storage node for output.. ... Micron Technology Inc

05/24/18 / #20180145254

Methods of forming resistive memory elements

A resistive memory element comprises a first electrode, an active material over the first electrode, a buffer material over the active material and comprising longitudinally extending, columnar grains of crystalline material, an ion reservoir material over the buffer material, and a second electrode over the ion reservoir material. A memory cell, a memory device, an electronic system, and a method of forming a resistive memory element are also described.. ... Micron Technology Inc

05/24/18 / #20180145250

Method, system, and device for l-shaped memory component

Embodiments disclosed herein may relate to forming reduced size storage components in a cross-point memory array. In an embodiment, a storage cell comprising an l-shaped storage component having an approximately vertical portion extending from a first electrode positioned below the storage material to a second electrode positioned above and/or on the storage component. ... Micron Technology Inc

05/24/18 / #20180145112

Semiconductor devices with seed and magnetic regions and methods of fabrication

A magnetic cell core includes a seed region with a plurality of magnetic regions and a plurality of nonmagnetic regions thereover. The seed region provides a template that enables formation of an overlying nonmagnetic region with a microstructure that enables formation of an overlying free region with a desired crystal structure. ... Micron Technology Inc

05/24/18 / #20180145029

Methods of forming semiconductor device structures including staircase structures

A semiconductor device structure comprises stacked tiers each comprising a conductive structure and an insulating structure longitudinally adjacent the at least one conductive structure, at least one staircase structure having steps comprising lateral ends of the stacked tiers, and an opening laterally adjacent a first side of the at least one staircase structure and extending through the stacked tiers and continuously across an entire length of the at least one staircase structure. Conductive structures of the stacked tiers laterally extend from the steps of the at least one staircase structure completely across a second side of the at least one staircase structure opposing the first side to form continuous conductive paths laterally extending completely across the stacked tiers. ... Micron Technology Inc

05/24/18 / #20180144937

Methods of patterning a target layer

A method of forming patterns includes the steps of providing a substrate on which a target layer and a hard mask layer are formed; forming a plurality of first resist patterns on the hard mask layer; performing a tilt-angle ion implant process to form a first doped area and a second doped area in the hard mask layer between adjacent first resist patterns; removing the first resist patterns; coating a directed self-assembly (dsa) material layer onto the hard mask layer; performing a self-assembling process of the dsa material layer to form repeatedly arranged block copolymer patterns in the dsa material layer; removing undesired portions from the dsa material layer to form second patterns on the hard mask layer; transferring the second patterns to the hard mask layer to form third patterns; and etching the target layer through the third patterns.. . ... Micron Technology Inc

05/24/18 / #20180144927

Semiconductor structures comprising silicon nitride and related methods

Methods of forming silicon nitride. Silicon nitride is formed on a substrate by atomic layer deposition at a temperature of less than or equal to about 275° c. ... Micron Technology Inc

05/24/18 / #20180144796

Memory and electronic devices with reduced operational energy in chalcogenide material

Methods of forming and operating phase change memory devices include adjusting an activation energy barrier between a metastable phase and a stable phase of a phase change material in a memory cell. In some embodiments, the activation energy barrier is adjusted by applying stress to the phase change material in the memory cell. ... Micron Technology Inc

05/24/18 / #20180144795

Variable resistance memory stack with treated sidewalls

Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming a memory stack out of a plurality of elements. ... Micron Technology Inc

05/24/18 / #20180144792

Memory cells, memory systems, and memory programming methods

Memory cells, memory systems and methods are described. In one embodiment, a memory cell includes electrodes and a memory element, and a first electrically conductive structure is formed within dielectric material providing the memory element in a low resistance state as a result of a first voltage of a first polarity being applied across the electrodes. ... Micron Technology Inc

05/24/18 / #20180144791

Determining soft data for fractional digit memory cells

Apparatuses and methods for determining soft data for fractional digit memory cells are provided. One example apparatus can include a controller to determine states of memory cells of a group of memory cells operated as fractional digit memory cells, and determine soft data based, at least partially, on dimensions to which particular memory cells correspond with respect to the group of memory cells, determined states of the memory cells with respect to a state adjacent a state corresponding to a swapping shell, and whether a particular memory cell is a candidate for swapping.. ... Micron Technology Inc

05/24/18 / #20180144783

Cell-based reference voltage generation

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A first ferroelectric memory cell may be initialized to a first state and a second ferroelectric memory cell may be initialized to a different state. ... Micron Technology Inc

05/24/18 / #20180144779

Control lines to sensing components

Examples of the present disclosure provide apparatuses and methods related to performing a loop structure for operations performed in memory. An example apparatus might include an array of memory cells. ... Micron Technology Inc

05/24/18 / #20180143908

Continuous page read for memory

Subject matter disclosed herein relates to techniques to read memory in a continuous fashion.. . ... Micron Technology Inc

05/24/18 / #20180143875

Monitoring error correction operations performed in memory

The present disclosure includes apparatuses and methods for monitoring error correction operations performed in memory. A number of embodiments include a memory and circuitry configured to determine a quantity of erroneous data corrected during an error correction operation performed on soft data associated with a sensed data state of a number of memory cells of the memory, determine a quality of soft information associated with the erroneous data corrected during the error correction operation performed on the soft data, and determine whether to take a corrective action on the sensed data based on the quantity of the erroneous data corrected during the error correction operation and the quality of the soft information associated with the erroneous data corrected during the error correction operation.. ... Micron Technology Inc

05/24/18 / #20180143784

Buffer operations in memory

Apparatuses and methods for performing buffer operations in memory are provided. One example method can include storing second page data and third page data on a buffer while programming first page data during a first pass programming operation and programming the second page data and the third page data from the buffer to the array of memory cells during a second pass programming operation.. ... Micron Technology Inc

05/24/18 / #20180143765

Data storage management

A method of managing a plurality of storage devices. The method comprises at a first device connected to the plurality of storage devices via a switch, receiving an indication of a plurality of logical disks, each logical disk being provided by a respective one of the plurality of storage devices. ... Micron Technology Inc

05/17/18 / #20180138406

Dual resistive-material regions for phase change memory devices

In various examples, dual resistive-material regions for a phase change material region are fabricated by initially forming a resistive material. Prior to forming the phase change material region over the resistive material, at least an upper portion of the resistive material is exposed to an implantation or plasma that increases the resistance of an upper portion of the resistive material relative to the remainder, or bulk, of the resistive material. ... Micron Technology Inc

05/17/18 / #20180138400

Conductive hard mask for memory device formation

Methods, systems, and devices for memory arrays that use a conductive hard mask during formation and, in some cases, operation are described. A hard mask may be used to define features or components during the numerous material formation and removal steps used to create memory cells within a memory array. ... Micron Technology Inc

05/17/18 / #20180138399

Phase change memory cell with constriction structure

Some embodiments include methods of forming memory cells. Such methods can include forming a first electrode, a second electrode, and a memory element directly contacting the first and second electrodes. ... Micron Technology Inc

05/17/18 / #20180138398

Phase change memory cell with constriction structure

Some embodiments include methods of forming memory cells. Such methods can include forming a first electrode, a second electrode, and a memory element directly contacting the first and second electrodes. ... Micron Technology Inc

05/17/18 / #20180138242

Cross-point memory and methods for fabrication of same

The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a memory device of the memory array comprises a substrate and a memory cell stack formed between and electrically connected to first and second conductive lines. ... Micron Technology Inc

05/17/18 / #20180138241

Three-dimensional memory apparatus and method of manufacturing the same

A three dimensional (3d) memory array and method of manufacturing the same are described. The 3d memory array may include an electrode plane and a memory material disposed through and coupled to the electrode plane. ... Micron Technology Inc

05/17/18 / #20180138240

Three-dimensional memory apparatuses and methods of use

A three dimensional (3d) memory array is disclosed. The 3d memory array may include an electrode plane and a memory material disposed through and coupled to the electrode plane. ... Micron Technology Inc

05/17/18 / #20180138239

Array of cross point memory cells and methods of forming an array of cross point memory cells

An array of cross point memory cells comprises spaced elevationally inner first lines, spaced elevationally outer second lines which cross the first lines, and a multi-resistive state region elevationally between the first and second lines where such cross. Individual of the multi-resistive state regions comprise elevationally outer multi-resistive state material and elevationally inner multi-resistive state material that are electrically coupled to one another. ... Micron Technology Inc

05/17/18 / #20180138238

Memory arrays and methods of forming memory arrays

Some embodiments include a memory array which has a first series of access/sense lines extending along a first direction, and a second series of access/sense lines over the first series of access/sense lines and extending along a second direction which crosses the first direction. Memory cells are vertically between the first and second series of access/sense lines. ... Micron Technology Inc

05/17/18 / #20180138196

Apparatuses and methods for forming multiple decks of memory cells

Some embodiments include apparatuses and methods having multiple decks of memory cells and associated control gates. A method includes forming a first deck having alternating conductor materials and dielectric materials and a hole containing materials extending through the conductor materials and the dielectric materials. ... Micron Technology Inc

05/17/18 / #20180138182

Conductive structures, wordlines and transistors

Some embodiments include a conductive structure which has a first conductive material having a work function of at least 4.5 ev, and a second conductive material over and directly against the first conductive material. The second conductive material has a work function of less than 4.5 ev, and is shaped as an upwardly-opening container. ... Micron Technology Inc

05/17/18 / #20180138033

Removal of metal

Methods of removing metal from a portion of a substrate include exposing the substrate to a reducing environment comprising at least one reducing agent and at least one oxidizing agent, determining whether metal remaining on the portion of the substrate is less than or equal to a particular level, and exposing the substrate to an oxidizing environment comprising at least one oxidizing agent and at least one reducing agent if the metal remaining on the portion of the substrate is deemed to be greater than the particular level.. . ... Micron Technology Inc

05/17/18 / #20180137922

Apparatus and methods including establishing a negative body potential in a memory cell

Apparatus and methods of operating such apparatus include establishing a negative potential in a body of a memory cell prior to initiating a sensing operation on the memory cell, in response to a timer, or during an access operation of another memory cell.. . ... Micron Technology Inc

05/17/18 / #20180137921

Access line management in a memory device

Memory devices including an array of memory cells, a plurality of access lines selectively coupled to respective pluralities of memory cells of the array of memory cells, a plurality of first registers, a second register, a first multiplexer, a second multiplexer, and a decoder configured to selectively connect a corresponding access line to a selected voltage source of a plurality of voltage sources in response to the output of the second multiplexer, wherein the second multiplexer is configured to pass a selected one of the output of the second register and the output of the first multiplexer to its output, and wherein the first multiplexer is configured to pass a selected one of the outputs of the plurality of first registers to its output.. . ... Micron Technology Inc

05/17/18 / #20180137917

Sequential write and sequential write verify in memory device

Some embodiments include apparatuses and methods for performing a first stage of an operation of storing information in a first memory cell and a second memory cell, and performing a second stage of the operation after the first stage to determine whether each of the first and second memory cells reaches a target state. The first memory cell is included in a first memory cell string coupled to a data line through a first select transistor. ... Micron Technology Inc

05/17/18 / #20180137908

Writing to cross-point non-volatile memory

Methods, systems, and devices for preventing disturb of untargeted memory cells during repeated access operations of target memory cells are described for a non-volatile memory array. Multiple memory cells may be in electronic communication with a common conductive line, and each memory cell may have an electrically non-linear selection component. ... Micron Technology Inc

05/17/18 / #20180137907

Parallel access techniques within memory sections through section independence

A memory device having a plurality sections of memory cells, such as ferroelectric memory cells (hybrid ram (hram) cells) may provide for concurrent access to memory cells within independent sections of the memory device. A first memory cell may be activated, and it may be determined that a second memory cell is independent of the first memory cell. ... Micron Technology Inc

05/17/18 / #20180137906

Techniques for sensing logic values stored in memory cells using sense amplifiers that are selectively isolated from digit lines

Methods, systems, and devices for operating a an electronic memory apparatus are described. A logic value stored in a ferroelectric random access memory (feram) cell is read onto a first sensing node of a sense amplifier. ... Micron Technology Inc

05/17/18 / #20180137905

Memory cells and semiconductor devices including ferroelectric materials

Methods of operating a ferroelectric memory cell. The method comprises applying one of a positive bias voltage and a negative bias voltage to a ferroelectric memory cell comprising a capacitor including a top electrode, a bottom electrode, a ferroelectric material between the top electrode and the bottom electrode, and an interfacial material between the ferroelectric material and one of the top electrode and the bottom electrode. ... Micron Technology Inc

05/17/18 / #20180137899

Two-step data-line precharge scheme

Apparatus and methods are disclosed, including an apparatus having a first transistor configured to be coupled to a first bit line, and a control circuit configured to supply a gate of the first transistor with a first voltage to turn on the first transistor, and to supply the gate of the first transistor with a second voltage higher than the first voltage to strengthen a current drive capability of the first transistor.. . ... Micron Technology Inc

05/17/18 / #20180137416

Methods and systems for data analysis in a state machine

A device includes a match element that includes a first data input configured to receive a first result, wherein the first result is of an analysis performed on at least a portion of a data stream by an element of a state machine. The match element also includes a second data input configured to receive a second result, wherein the second result is of an analysis performed on at least a portion of the data stream by another element of the state machine. ... Micron Technology Inc

05/17/18 / #20180136873

Data transfer techniques for multiple devices on a shared bus

Direct data transfer between devices having a shared bus may be implemented with reduced involvement from a controller associated with the devices. A controller, a source memory device, and a target memory device may be coupled with a shared bus. ... Micron Technology Inc

05/17/18 / #20180136871

Apparatuses and methods for memory alignment

The present disclosure includes apparatuses and methods related to memory alignment. An example method comprises performing an alignment operation on a first byte-based memory element and a second byte-based memory element such that a padding bit of the first byte-based memory element is logically adjacent to a padding bit of the second byte-based memory element and a data bit of the first byte-based memory element is logically adjacent to a data bit of the second byte-based memory element.. ... Micron Technology Inc

05/17/18 / #20180136855

Searching data in parallel using processor-in-memory devices

A method includes comparing, in parallel, a data pattern with data stored into a plurality of columns of memory cells, and in response to detecting the data pattern in the data stored into a particular column of memory cells of the plurality of columns of memory cells, storing in a memory cell of the particular column a value indicative of at least one of an occurrence of the data pattern or a position of the data pattern in the data stored into the particular column.. . ... Micron Technology Inc

05/17/18 / #20180136845

Apparatuses and methods for concurrently accessing multiple memory planes of a memory during a memory access operation

Apparatuses and methods for performing concurrent memory access operations for multiple memory planes are disclosed herein. An example method may include receiving first and second command and address pairs associated with first and second plane, respectively, of a memory. ... Micron Technology Inc

05/17/18 / #20180136707

Power management

Apparatus facilitating peak power management include a plurality of dies, with each such die comprising an array of memory cells, a controller for performing access operations on the array of memory cells, and a counter configured to be responsive to a clock signal. A particular die of a first subset of dies of the plurality of dies comprises a clock generator for generating the clock signal. ... Micron Technology Inc

05/10/18 / #20180130948

Apparatuses including electrodes having a conductive barrier material and methods of forming same

Apparatuses and methods of manufacture are disclosed for phase change memory cell electrodes having a conductive barrier material. In one example, an apparatus includes a first chalcogenide structure and a second chalcogenide structure stacked together with the first chalcogenide structure. ... Micron Technology Inc

05/10/18 / #20180130815

Transistors having dielectric material containing non-hydrogenous ions and methods of their fabrication

Methods for fabricating a transistor include forming a dielectric material adjacent to a semiconductor, introducing non-hydrogenous ions into the dielectric material, and forming a control gate adjacent to the dielectric material. Transistors include source/drain regions in a semiconductor, a dielectric material adjacent to the semiconductor and containing non-hydrogenous ions, and a control gate adjacent to the dielectric material. ... Micron Technology Inc

05/10/18 / #20180130807

Transistors and memory arrays

Some embodiments include a transistor having a semiconductor material with a trench extending downwardly therein. The semiconductor material has a first post region on one side of the trench and a second post region on an opposing side of the trench. ... Micron Technology Inc

05/10/18 / #20180130773

Semiconductor die assemblies having molded underfill structures and related technology

A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies and a package substrate carrying the first and second semiconductor dies. The second semiconductor die includes a first peripheral portion extending laterally outward beyond a first edge surface of the first semiconductor die. ... Micron Technology Inc

05/10/18 / #20180130739

Wiring with external terminal

Apparatuses for providing external terminals of a semiconductor device are described. An example apparatus includes: a pad formation area including a plurality of pads disposed at an edge of the apparatus; a peripheral circuit area including a plurality of circuit blocks coupled to a memory cell array, each circuit block of the plurality of circuit blocks including a via disposed at a side opposite to the pad formation area with respect to each circuit block; and a plurality of conductors, each conductor coupling the via to the corresponding pad, and crossing over, at least in part, an area in the peripheral circuit area that is outside the circuit block comprising the via.. ... Micron Technology Inc

05/10/18 / #20180130738

Apparatuses including stair-step structures and methods of forming the same

Methods for forming semiconductor structures are disclosed, including a method that involves forming sets of conductive material and insulating material, forming a first mask over the sets, forming a first number of contact regions, forming a second mask over a first region of the sets, and removing material from the sets in a second, exposed region laterally adjacent the first region to form a second number of contact regions. Another method includes forming first and second contact regions on portions of sets of conductive materials and insulating materials, each of the second contact regions more proximal to an underlying substrate than each of the first contact regions. ... Micron Technology Inc

05/10/18 / #20180130700

Stair step formation using at least two masks

Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. ... Micron Technology Inc

05/10/18 / #20180130536

Methods and apparatuses including an asymmetric assist device

Apparatuses and methods have been disclosed. One such apparatus includes a plurality of memory cells that can be formed at least partially surrounding a semiconductor pillar. ... Micron Technology Inc

05/10/18 / #20180130530

Systems, methods and devices for programming a multilevel resistive memory cell

Embodiments disclosed herein may relate to programming a multi-level memory cell with programming pulse sequences that comprise forward-biased and reverse-biased programming pulses.. . ... Micron Technology Inc

05/10/18 / #20180130515

Apparatuses and methods for compute components formed over an array of memory cells

The present disclosure includes apparatuses and methods related to compute components formed over an array of storage elements. An example apparatus comprises a base substrate material and an array of memory cells formed over the base substrate material. ... Micron Technology Inc

05/10/18 / #20180130513

Multi-level storage in ferroelectric memory

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. In some examples, multi-level accessing, sensing, and other operations for ferroelectric memory may be based on sensing multiple charges, including a first charge associated with a dielectric of the memory cell and a second charge associated with a polarization of the memory cell. ... Micron Technology Inc

05/10/18 / #20180130508

Apparatuses and methods for power efficient driver circuits

An apparatus comprising is disclosed. The apparatus a driver circuit configured to selectively provide a first supply voltage to an output node in a first operating mode and to selectively provide a second supply voltage to the output node in a second operating mode, based on one or more enable signals.. ... Micron Technology Inc

05/10/18 / #20180129575

Memory management

The present disclosure includes apparatuses and methods related to hybrid memory management. An example apparatus can include a first memory array, a number of second memory arrays, and a controller coupled to the first memory array and the number of second memory arrays configured to execute a write operation, wherein execution of the write operation writes data to the first memory array starting at a location indicated by a write cursor, and place the write cursor at an updated location in the first memory array upon completing execution of the write operation, wherein the updated location is a next available location in the first memory array.. ... Micron Technology Inc

05/10/18 / #20180129450

Non-volatile memory module architecture to support memory error correction

Apparatus and methods are provided for operating a non-volatile memory module. In an example, a method can include filling a first plurality of pages of a first non-volatile memory with first data from a first data lane that includes a first volatile memory device, and filling a second plurality of pages of the first non-volatile memory device with second data from a second data lane that includes a second volatile memory device. ... Micron Technology Inc

05/10/18 / #20180129442

Systems and methods for providing file information in a memory system protocol

A controller of a memory device controls placement of data blocks by receiving, from a host electronic device, one or more commands of a memory system protocol. The commands include a write command with blocks of data to be stored in the memory device and contextual file system data for the blocks of data. ... Micron Technology Inc








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