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Micron Technology Inc patents


Recent patent applications related to Micron Technology Inc. Micron Technology Inc is listed as an Agent/Assignee. Note: Micron Technology Inc may have other listings under different names/spellings. We're not affiliated with Micron Technology Inc, we're just tracking patents.

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Methods and apparatuses for signal translation in a buffered memory

According to one embodiment, a data buffer is described. The data buffer comprises a first input/output circuit configured to receive and provide a first signal encoded according to a first communications protocol, a second input/output circuit configured to receive and provide a second signal encoded according to a second communications protocol, and a conversion circuit coupled to the first and second input/output circuits and configured to convert the first signal to the second signal and to convert the second signal to the first signal.. ... Micron Technology Inc

Apparatuses and methods for adding offset delays to signal lines of multi-level communication architectures

Apparatuses and methods for adding offset delays to signal lines of multi-level communication architectures are disclosed herein. An example method may include comparing a current channel state of a channel of a multi-level communication bus with a next channel state of the channel. ... Micron Technology Inc

Semiconductor devices with magnetic and attracter materials and methods of fabrication

A magnetic cell includes an attracter material proximate to a magnetic region (e.g., a free region). The attracter material is formulated to have a higher chemical affinity for a diffusible species of a magnetic material, from which the magnetic region is formed, compared to a chemical affinity between the diffusible species and at least another species of the magnetic material. ... Micron Technology Inc

Memory arrays and methods of forming an array of memory cells

A method of forming an array of memory cells includes forming lines of covering material that are elevationally over and along lines of spaced sense line contacts. Longitudinal orientation of the lines of covering material is used in forming lines comprising programmable material and outer electrode material that are between and along the lines of covering material. ... Micron Technology Inc

Memory including a selector switch on a variable resistance memory cell

Embodiments include but are not limited to apparatuses and systems including memory having a memory cell including a variable resistance memory layer, and a selector switch in direct contact with the memory cell, and configured to facilitate access to the memory cell. Other embodiments may be described and claimed.. ... Micron Technology Inc

Semiconductor device structures including two-dimensional material structures, and related semiconductor devices and electronic systems

A method of forming a semiconductor device structure comprises forming at least one 2d material over a substrate. The at least one 2d material is treated with at least one laser beam having a frequency of electromagnetic radiation corresponding to a resonant frequency of crystalline defects within the at least one 2d material to selectively energize and remove the crystalline defects from the at least one 2d material. ... Micron Technology Inc

Methods of verifying data path integrity

Methods for verifying data path integrity are provided. One such method includes reading a partially programmed first set of data from an array of memory cells of the memory device into a page register of the memory device, loading the partially programmed first set of data into a cache register of the memory device, writing a partial set of test data to a portion of the cache register not containing the partially programmed first set of data during a read of a second set of data from the array of memory cells to the page register, reading the partial set of test data from the cache register during the read of the second set of data from the array of memory cells to the page register, and comparing the partial set of test data read from the cache register to the original partial set of test data.. ... Micron Technology Inc

Methods of operating a memory with redistribution of received data

Methods of operating a memory include receiving data for programming to a plurality of memory cells of the memory, redistributing the received data in a reversible manner, programming the redistributed data to the plurality of memory cells, and programming respective second data to each memory cell of the plurality of memory cells containing the redistributed data, wherein the respective second data for any memory cell of the plurality of memory cells has a same data value as the respective second data for each remaining memory cell of the plurality of memory cells.. . ... Micron Technology Inc

Timing control for input receiver

Apparatuses for receiving an input signal in a semiconductor device are described. An example apparatus includes a signal receiver that receives information signal; a control circuit that provides a plurality of control signals; and a signal receiver replica circuit that receives a first reference signal. ... Micron Technology Inc

Multiple plate line architecture for multideck memory array

Methods, systems, and devices for multiple plate line architecture for multideck memory arrays are described. A memory device may include two or more three-dimensional arrays of ferroelectric memory cells overlying a substrate layer that includes various components of support circuitry, such as decoders and sense amplifiers. ... Micron Technology Inc

Semiconductor layered device with data bus

Apparatuses and methods of data communication between semiconductor chips are described. An example apparatus includes: a first die including a first switch circuit that receives a plurality of data signals, and further provides the plurality of data signals to a plurality of corresponding first ports among a plurality of first data ports and a first data redundancy port; and a second die including a second switch circuit that receives the plurality of data signals from the first die at a plurality of corresponding second ports among a plurality of second data ports and a second data redundancy port and further provides the plurality of data signals to a memory array.. ... Micron Technology Inc

Apparatuses and methods for operating neural networks

The present disclosure includes apparatuses and methods for operating neural networks. An example apparatus includes a plurality of neural networks, wherein the plurality of neural networks are configured to receive a particular portion of data and wherein each of the plurality of neural networks are configured to operate on the particular portion of data during a particular time period to make a determination regarding a characteristic of the particular portion of data.. ... Micron Technology Inc

Enabling a secure boot from non-volatile memory

A system may include a host that may include a processor coupled to a non-volatile memory over a secure communication protocol, as a result, prior to release for manufacturing, a binding code may k established between the host and the non-volatile memory, in some embodiments, this binding code may be stored on the non-volatile memory and not on the host. Then during a boot up of the system, the boot up process may be initiated by the host using code associated with the host, followed by secure booting using the secure protocol using code stored on the non-volatile memory.. ... Micron Technology Inc

Apparatus and methods for in data path compute operations

The present disclosure includes apparatuses and methods for in data path compute operations. An example apparatus includes an array of memory cells. ... Micron Technology Inc

09/27/18 / #20180275964

Apparatuses and methods for random number generation

The present disclosure includes apparatuses and methods for random number generation. An example method includes operating a sense amplifier of a memory device to perform sensing a first voltage on a first sense line coupled to the sense amplifier and sensing a second voltage on a complementary second sense line coupled to the sense amplifier. ... Micron Technology Inc

09/27/18 / #20180275883

Apparatuses and methods for in-memory data switching networks

The present disclosure includes apparatuses and methods for in-memory data switching networks. An example apparatus includes an array of memory cells. ... Micron Technology Inc

09/27/18 / #20180275239

Memory arrays

Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines extending perpendicularly from the global bitlines, and wordlines extending along a second horizontal direction which is perpendicular to the first horizontal direction. ... Micron Technology Inc

09/20/18 / #20180269904

Error correction code (ecc) operations in memory for providing redundant error correction

Apparatuses and methods for performing an error correction code (ecc) operation are provided. One example method can include encoding data by including parity data for a number of cross-over bits, wherein the number of cross-over bits are bits located at intersections of column codewords and row codewords.. ... Micron Technology Inc

09/20/18 / #20180269875

Apparatuses and methods for partial bit de-emphasis

Apparatuses and methods for partial bit de-emphasis are provided. An example apparatus includes an output driver and control circuit. ... Micron Technology Inc

09/20/18 / #20180269365

Solid state lighting devices having improved color uniformity and associated methods

Solid state lighting (ssl) devices and methods of manufacturing ssl devices are disclosed herein. In one embodiment, an ssl device comprises a support having a surface and a solid state emitter (sse) at the surface of the support. ... Micron Technology Inc

09/20/18 / #20180269356

Epitaxial formation support structures and associated methods

Epitaxial formation support structures and associated methods of manufacturing epitaxial formation support structures and solid state lighting devices are disclosed herein. In several embodiments, a method of manufacturing an epitaxial formation support substrate can include forming an uncured support substrate that has a first side, a second side opposite the first side, and coefficient of thermal expansion substantially similar to n-type gallium nitride. ... Micron Technology Inc

09/20/18 / #20180269350

Light-emitting metal-oxide-semiconductor devices and associated systems, devices, and methods

Various embodiments of solid state transducer (“sst”) devices are disclosed. In several embodiments, a light emitter device includes a metal-oxide-semiconductor (mos) capacitor, an active region operably coupled to the mos capacitor, and a bulk semiconductor material operably coupled to the active region. ... Micron Technology Inc

09/20/18 / #20180269283

Integrated memory, integrated assemblies, and methods of forming memory arrays

Some embodiments include an integrated memory having an array of capacitors. The array has edges. ... Micron Technology Inc

09/20/18 / #20180269254

Memory devices, systems, and methods of fabrication

Memory devices include an array of memory cells including magnetic tunnel junction regions. The array of memory cells includes access lines extending in a first direction and data lines extending in a second direction transverse to the first direction. ... Micron Technology Inc

09/20/18 / #20180269227

Memory cells and integrated structures

A memory cell comprises, in the following order, channel material, a charge-passage structure, charge-storage material, a charge-blocking region, and a control gate. The charge-passage structure comprises a first material closest to the channel material, a third material furthest from the channel material, and a second material between the first material and the third material. ... Micron Technology Inc

09/20/18 / #20180268909

Memory devices having source lines directly coupled to body regions and methods

Memory devices, memory cell strings and methods of operating memory devices are shown. Configurations described include directly coupling an elongated body region to a source line. ... Micron Technology Inc

09/20/18 / #20180268899

Enhancing nucleation in phase-change memory cells

Various embodiments disclosed herein comprise methods and apparatuses for placing phase-change memory (pcm) cells of a memory array into a temperature regime where nucleation probability of the pcm cells is enhanced prior to applying a subsequent set programming signal. In one embodiment, the method includes applying a nucleation signal to the pcm cells to form nucleation sites within the memory array where the nucleation signal has a non-zero rising-edge. ... Micron Technology Inc

09/20/18 / #20180268896

Memory cell state in a valley between adjacent data states

The present disclosure includes apparatuses and methods related to memory cell state in a valley between adjacent data states. A number of methods can include determining whether a state of a memory cell is in a valley between adjacent distributions of states associated with respective data states. ... Micron Technology Inc

09/20/18 / #20180268883

Devices, methods, and systems supporting on unit termination

The present disclosure includes devices, methods, and systems supporting on unit termination. A number of embodiments include a number of memory units, wherein a memory unit includes termination circuitry, and a memory unit does not include termination circuitry.. ... Micron Technology Inc

09/20/18 / #20180268876

Apparatuses and methods for sharing transmission vias for memory devices

Apparatuses and methods for transmitting die state information between a plurality of dies are described. An example apparatus includes: a plurality of dies, wherein each die of the plurality of dies includes a first through electrode and a second through electrode; a first path including the first electrodes of the plurality of dies in series; and a second path including the first electrodes of the plurality of dies in series. ... Micron Technology Inc

09/20/18 / #20180267851

Tiered error correction code (ecc) operations in memory

Apparatuses and methods for performing an error correction code (ecc) operation are provided. One example method can include performing a first error code correction (ecc) operation on a portion of data, performing a second ecc operation on the portion of data in response to the first ecc operation failing, and performing a third ecc operation on the portion of data in response to the second ecc operation failing.. ... Micron Technology Inc

09/20/18 / #20180267738

Apparatuses and methods for data movement

The present disclosure includes apparatuses and methods for data movement. An example apparatus includes a memory device that includes a plurality of subarrays of memory cells and sensing circuitry coupled to the plurality of subarrays. ... Micron Technology Inc

09/06/18 / #20180255552

Wireless devices and systems including examples of configuration modes for baseband units and remote radio heads

Examples described herein include systems and methods which include wireless devices and systems with examples of configuration modes for baseband units (bbu) and remote radio heads (rrh). For example, a computing system including a bbu and a rrh may receive a configuration mode selection including information indicative of a configuration mode for respective processing units of the bbu and the rrh. ... Micron Technology Inc

09/06/18 / #20180255546

Wireless devices and systems including examples of configuration modes for baseband units and remote radio heads

Examples described herein include systems and methods which include wireless devices and systems with examples of configuration modes for baseband units (bbu) and remote radio heads (rrh). For example, a computing system including a bbu and a rrh may receive a configuration mode selection including information indicative of a configuration mode for respective processing units of the bbu and the rrh. ... Micron Technology Inc

09/06/18 / #20180255001

Methods and apparatuses for processing multiple communications signals with a single integrated circuit chip

An apparatus is disclosed. The apparatus comprises a plurality of antennas and an integrated circuit chip coupled to the plurality of antennas, and is configured to process cellular signals received from the plurality of antennas in accordance with a cellular communication protocol and to process radio frequency identification (rfid) signals received from the plurality of antennas in accordance with an rfd protocol.. ... Micron Technology Inc

09/06/18 / #20180254930

Wireless devices and systems including examples of full duplex transmission

Examples described herein include systems and methods which include wireless devices and systems with examples of full duplex compensation with a self-interference noise calculator. The self-interference noise calculator may be coupled to antennas of a wireless device and configured to generate adjusted signals that compensate self-interference. ... Micron Technology Inc

09/06/18 / #20180254413

Methods of forming and using materials containing silicon and nitrogen

Some embodiments include methods utilizing atomic layer deposition to form material containing silicon and nitrogen (e.g., silicon nitride). The atomic layer deposition uses sii4 as one precursor and uses a nitrogen-containing material as another precursor. ... Micron Technology Inc

09/06/18 / #20180254334

Methods of forming nand cell units and nand cell units

Some embodiments include methods of forming charge storage transistor gates and standard fet gates in which common processing is utilized for fabrication of at least some portions of the different types of gates. Fet and charge storage transistor gate stacks may be formed. ... Micron Technology Inc

09/06/18 / #20180254283

Integrated structures, capacitors and methods of forming capacitors

Some embodiments include an integrated structure having a semiconductor base and an insulative frame over the semiconductor base. The insulative frame has vertically-spaced sheets of first insulative material, and pillars of second insulative material between the vertically-spaced sheets. ... Micron Technology Inc

09/06/18 / #20180254282

Memory device including pass transistors in memory tiers

Some embodiments include apparatuses and methods of using such apparatuses. One of the apparatuses includes a semiconductor material, a pillar extending through the semiconductor material, a select gate located along a first portion of the pillar, memory cells located along a second portion of the pillar, and transistors coupled to the select gate through a portion of the semiconductor material. ... Micron Technology Inc

09/06/18 / #20180254245

Wiring with external terminal

Apparatuses for providing external terminals of a semiconductor device are described. An example apparatus includes: a pad formation area including a plurality of pads disposed at an edge of the apparatus; a peripheral circuit area including a plurality of circuit blocks coupled to a memory cell array, each circuit block of the plurality of circuit blocks including a via disposed at a side opposite to the pad formation area with respect to each circuit block; and a plurality of conductors, each conductor coupling the via to the corresponding pad, and crossing over, at least in part, an area in the peripheral circuit area that is outside the circuit block comprising the via.. ... Micron Technology Inc

09/06/18 / #20180254214

Integrated circuits having parallel conductors and their formation

Integrated circuits, as well as methods of their formation, include a first conductive structure at a first level of the integrated circuit, a second conductive structure at a second level of the integrated circuit, a first conductor at a third level of the integrated circuit between the first level and the second level, a second conductor at the third level and parallel to the first conductor, and a third conductor at the third level and parallel to the first conductor and to the second conductor. The first conductive structure is in physical and electrical contact with the first conductor and the second conductor. ... Micron Technology Inc

09/06/18 / #20180254086

Apparatus having memory arrays and having trim registers associated with memory array access operation commands

Apparatus include an external controller, a memory storing trim settings corresponding to a plurality of modes of operation, and a memory device. The memory device includes an array of memory cells, an internal controller, and a trim register array. ... Micron Technology Inc

09/06/18 / #20180254075

Apparatuses and methods for providing an indicator of operational readiness of various circuits of a semiconductor device following power up

Apparatuses and methods for providing an indicator of operational readiness of various circuits of a semiconductor device following power up are described in the present disclosure. An example apparatus includes a first circuit configured to receive a supply voltage and further configured to provide an active first signal responsive to the supply voltage exceeding a threshold voltage. ... Micron Technology Inc

09/06/18 / #20180254074

Apparatuses and methods for chip identification in a memory package

Apparatuses, methods, memory packages, and semiconductor chips are disclosed. An example apparatus includes a semiconductor chip including a layer identification setting path circuit configured to receive respective input signals from a plurality of input layer identification setting paths. ... Micron Technology Inc

09/06/18 / #20180254071

Apparatuses and methods for storing a data value in a sensing circuitry element

The present disclosure includes apparatuses and methods related to storing a data value in a sensing circuitry element. An example method comprises sensing a first data value with a sense amplifier of a sensing circuitry element, moving a second data value from a first storage location of a compute component to a second storage location of the compute component, and storing, in the first storage location, a third data value resulting from a logical operation performed on the first data value and the second data value. ... Micron Technology Inc

09/06/18 / #20180253679

Methods and apparatuses for determining real-time location information of rfid devices

An apparatus is described. The apparatus includes an antenna array configured to detect one or more radio frequency signals from one or more radio emitters and an integrated circuit chip coupled to the array of antennas. ... Micron Technology Inc

09/06/18 / #20180253243

Obfuscation-enhanced memory encryption

The present disclosure includes apparatuses and methods for obfuscation-enhanced memory encryption. An example method comprises performing a write operation, wherein the write operation includes transmitting a number of write transactions received from a host along with a number of spurious transactions to a memory, and wherein the number of spurious transactions are transmitted at a particular rate among the number of received write transactions.. ... Micron Technology Inc

08/23/18 / #20180241383

Apparatuses and methods for duty cycle adjustment

Apparatuses, duty cycle adjustment circuits, adjustment circuits, and methods for duty cycle adjustment are disclosed herein. An example duty cycle adjustment circuit may be configured to receive a signal and adjust a duty cycle of the signal a first amount using a coarse adjustment. ... Micron Technology Inc

08/23/18 / #20180240785

Stacked semiconductor die assemblies with die support members and associated systems and methods

Stacked semiconductor die assemblies with die support members and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first semiconductor die attached to the package substrate, and a support member attached to the package substrate. ... Micron Technology Inc

08/23/18 / #20180240782

Stacked semiconductor die assemblies with die substrate extensions

Stacked semiconductor die assemblies with die substrate extensions are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first die mounted to the package substrate, and a second die mounted to the first die. ... Micron Technology Inc

08/23/18 / #20180240534

Memory apparatus with post package repair

Apparatuses for memory repair for a memory device are described. An example apparatus includes: a non-volatile storage element that stores information; a storage latch circuit coupled to the non-volatile storage element and stores latch information; and a control circuit that, in a first repair mode, receives first repair address information, provides the first repair address information to the non-volatile storage element, and further transmits the first repair address information from the non-volatile storage element to the storage latch circuit. ... Micron Technology Inc

08/23/18 / #20180240511

Semiconductor device

Apparatuses and methods for refreshing memory cells of a semiconductor device are described. An example apparatus includes: a memory cell array including a plurality of memory groups each having a plurality of memory cells, the memory groups being selected by mutually different addresses; a first control circuit periodically executing a refresh operation on the memory groups in response to a first refresh command; and a second control circuit setting a cycle of executing the refresh operation by the first control circuit. ... Micron Technology Inc

08/23/18 / #20180240510

Apparatuses and methods for compute in data path

The present disclosure includes apparatuses and methods for compute in data path. An example apparatus includes an array of memory cells. ... Micron Technology Inc

08/23/18 / #20180240509

Apparatuses and methods to reverse data stored in memory

Apparatuses and methods are provided for reversing data stored in memory. An example apparatus comprises an array of memory cells, a first plurality of sensing components corresponding to a respective first plurality of columns of the array, a second plurality of sensing components corresponding to a respective second plurality of columns of the array, and a plurality of shared input/output (i/o) lines (which may be referred to as sio lines). ... Micron Technology Inc

08/23/18 / #20180239712

Memory array page table walk

An example memory array page table walk can include using an array of memory cells configured to store a page table. The page table walk can include using sensing circuitry coupled to the array. ... Micron Technology Inc

08/23/18 / #20180239672

Error code calculation on sensing circuitry

Examples of the present disclosure provide apparatuses and methods for error code calculation. The apparatus can include an array of memory cells that are coupled to sense lines. ... Micron Technology Inc

08/23/18 / #20180239531

Apparatuses and methods for in-memory operations

The present disclosure includes apparatuses and methods for in-memory operations. An example apparatus includes a memory device including a plurality of subarrays of memory cells, where the plurality of subarrays includes a first subset of the respective plurality of subarrays and a second subset of the respective plurality of subarrays. ... Micron Technology Inc

08/16/18 / #20180233657

Magnetoresistive structures, semiconductor devices, and related systems

Magnetic memory cells, methods of fabrication, semiconductor device structures, and memory systems are disclosed. A magnetic cell core includes at least one magnetic region (e.g., a free region or a fixed region) configured to exhibit a vertical magnetic orientation, at least one oxide-based region, which may be a tunnel junction region or an oxide capping region, and at least one magnetic interface region, which may comprise or consist of iron (fe). ... Micron Technology Inc

08/16/18 / #20180233200

Apparatus, systems, and methods to operate a memory

Various embodiments, disclosed herein, include apparatus and methods to read a logic level in a selected memory cell in a selected string of a memory by sensing the logic level in response to a read current flowing through the selected string to a data line. Additional apparatus, systems, and methods are disclosed.. ... Micron Technology Inc

08/16/18 / #20180233198

Memory device and method having on-board processing logic for facilitating interface with multiple processors, and computer system using same

A memory device includes an on-board processing system that facilitates the ability of the memory device to interface with a plurality of processors operating in a parallel processing manner. The processing system includes circuitry that performs processing functions on data stored in the memory device in an indivisible manner. ... Micron Technology Inc

08/16/18 / #20180233197

Efficient utilization of memory die area

Methods, systems, and apparatus that support efficient utilization of die area for cross-point memory architecture are described. A memory array may include active memory cells overlying each portion of the substrate that includes certain types of support circuitry, such as decoders and sense amplifiers. ... Micron Technology Inc

08/16/18 / #20180233180

Input buffer circuit

Apparatuses for receiving an input signal in a semiconductor device are described. An example apparatus includes: a first amplifier that provides first and second intermediate voltages responsive to first and second input voltages; first and second voltage terminals; a circuit node; a first transistor coupled between the first voltage terminal and the circuit node and is turned on responsive to at least one of the first and second intermediate voltages; a second amplifier including first and second inverters, at least one of the first and second inverters being coupled between the circuit node and the second voltage terminal; and first and second output nodes, the first output node being coupled to an input node of the first inverter and an output node of the second inverter, and the second output node being coupled to an output node of the first inverter and an input node of the second inverter.. ... Micron Technology Inc

08/16/18 / #20180233177

Active boundary quilt architecture memory

Methods, systems, and apparatus that increase available memory or storage using active boundary areas in quilt architecture are described. A memory array may include memory cells overlying each portion of a substrate layer that includes certain types of support circuitry, such as decoders and sense amplifiers. ... Micron Technology Inc

08/16/18 / #20180232289

Data encoding using spare channels

Implementations of encoding techniques are disclosed. The encoding technique, such as a data bus inversion (dbi) technique, is implementable in a vertically-stacked memory module, but is not limited thereto. ... Micron Technology Inc

08/16/18 / #20180232169

Solid state storage device with quick boot from nand media

Several embodiments of memory devices and related methods for initializing such memory devices based on initialization information on stored in nand-based memory media. In one embodiment, a memory device can include a controller operably coupled to the memory media. ... Micron Technology Inc

08/16/18 / #20180229421

Molding compound including a carbon nano-tube dispersion

A molding compound comprising a resin, a filler, and a carbon nano-tube dispersion is disclosed. The carbon nano-tube dispersion achieves a low average agglomeration size in the molding compound thereby providing desirable electro-mechanical properties and laser marking compatibility. ... Micron Technology Inc

08/09/18 / #20180227158

Wireless devices and systems including examples of mixing coefficient data specific to a processing mode selection

Examples described herein include systems and methods which include wireless devices and systems with examples of mixing input data with coefficient data specific to a processing mode selection. For example, a computing system with processing units may mix the input data for a transmission in a radio frequency (rf) wireless domain with the coefficient data to generate output data that is representative of the transmission being processed according to a specific processing mode selection. ... Micron Technology Inc

08/09/18 / #20180226570

Semiconductor structures and devices and methods of forming semiconductor structures and magnetic memory cells

A magnetic cell includes a magnetic region formed from a precursor magnetic material comprising a diffusive species and at least one other species. An amorphous region is proximate to the magnetic region and is formed from a precursor trap material comprising at least one attracter species having at least one trap site and a chemical affinity for the diffusive species. ... Micron Technology Inc

08/09/18 / #20180226428

Memory cells comprising a programmable field effect transistor having a reversibly programmable gate insulator

A memory cell comprises an elevationally extending programmable field effect transistor comprising a gate insulator that is reversibly programmable into two programmable states characterized by two different vt's of the programmable transistor. The programmable transistor comprises a top source/drain region and a bottom source/drain region. ... Micron Technology Inc

08/09/18 / #20180226427

Integrated structures comprising vertical channel material and having conductively-doped semiconductor material directly against lower sidewalls of the channel material, and methods of forming integrated structures

Some embodiments include an integrated structure having vertically-stacked conductive levels. Upper conductive levels are memory cell levels, and a lower conductive level is a select device level. ... Micron Technology Inc

08/09/18 / #20180226406

Apparatuses including buried digit lines

Methods of forming semiconductor device structures include forming trenches in an array region and in a buried digit line end region, forming a metal material in the trenches, filling the trenches with a mask material, removing mask the mask material in the trenches to expose a portion of the metal material, and removing the exposed portion of the metal material. A plurality of conductive contacts is formed in direct contact with the metal material in the buried digit line end region. ... Micron Technology Inc

08/09/18 / #20180226387

Semiconductor device assembly with through-package interconnect and associated systems, devices, and methods

Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a spacer material on an encapsulant such that the encapsulant separates the spacer material from an active surface of a semiconductor device and at least one interconnect projecting away from the active surface. ... Micron Technology Inc

08/09/18 / #20180226333

Semiconductor package and method for fabricating the same

A semiconductor package including at least one semiconductor device, a first redistribution layer, a first molding compound, a second molding compound, conductive vias and a second redistribution layer. The first redistribution layer is disposed beneath the semiconductor device and electrically connected to the semiconductor device. ... Micron Technology Inc

08/09/18 / #20180226127

Apparatuses and methods for comparing data patterns in memory

The present disclosure includes apparatuses and methods related to comparing data patterns in memory. An example method can include comparing a number of data patterns stored in a memory array to a target data pattern. ... Micron Technology Inc

08/09/18 / #20180226121

Apparatuses and methods for refresh control

Apparatuses and methods of for refresh control of a semiconductor device are described. An example apparatus includes a command control circuit that provides a plurality of pulses on a first control signal in series responsive to a plurality of refresh commands issued in series; a signal generation circuit that produces a plurality of pulses on a second control signal in sequence; and a refresh control circuit that receives two or more of the plurality of pulses on the first control signal during a period of time between one pulse and a succeeding pulse of the plurality of pulses on the second control signal, disables refresh operations responsive to at least one of the two or more of the plurality of first control signal and executes a refresh operation responsive to remaining one or more pulses of the two or more of the plurality of pulses on the first control signal.. ... Micron Technology Inc

08/09/18 / #20180226116

Pre-writing memory cells of an array

Methods, systems, and devices for operating a memory cell or memory cells are described. Cells of a memory array may be pre-written, which may include writing the cells to one state while a sense component is isolated from digit lines of the array. ... Micron Technology Inc

08/09/18 / #20180226107

Voltage generation circuit

Disclosed are apparatuses and methods for controlling gate-induced drain leakage current in a transistor device. An apparatus may include a first biasing circuit stage configured to provide a biasing voltage on a biasing signal line, the biasing voltage based on a current through a first resistor associated with the first biasing circuit stage, a voltage generation circuit stage coupled to the first biasing circuit stage, the voltage generation circuit stage having an output transistor that is coupled to the biasing signal line through a gate terminal of the output transistor, and an output line coupled to the voltage generation circuit stage and configured to provide an output voltage signal having a steady-state voltage that is less than a power supply voltage by an amount that corresponds to a voltage drop across the first resistor associated with the first biasing circuit stage.. ... Micron Technology Inc

08/09/18 / #20180225322

Merge tree modifications for maintenance operations

Systems and techniques for merge tree modifications for maintenance operations are described herein. A request for a kvs tree is received. ... Micron Technology Inc

08/09/18 / #20180225321

Merge tree garbage metrics

Systems and techniques for collecting and using merge tree garbage metrics are described herein. A kvset is created for a node in a kvs tree. ... Micron Technology Inc

08/09/18 / #20180225316

Stream selection for multi-stream storage devices

Systems and techniques for stream selection from multi-stream storage devices. Notification of a kvs tree write request for a multi-stream storage device is received. ... Micron Technology Inc

08/09/18 / #20180225315

Kvs tree

A kvs tree and operations thereon are described herein. A key-value set (kvset) is received to store in a key-value data structure on at least one machine readable medium. ... Micron Technology Inc

08/09/18 / #20180225056

Configurable operating mode memory device and methods of operation

Memory devices, and methods of operating similar memory devices, include an array of memory cells comprising a plurality of access lines each configured for biasing control gates of a respective plurality of memory cells of the array of memory cells, wherein the respective plurality of memory cells for one access line of the plurality of access lines is mutually exclusive from the respective plurality of memory cells for each remaining access line of the plurality of access lines, and a controller having a plurality of selectively-enabled operating modes and configured to selectively operate the memory device using two or more concurrently enabled operating modes of the plurality of selectively-enabled operating modes for access of the array of memory cells, with each of the enabled operating modes of the two of more concurrently enabled operating modes utilizing an assigned respective portion of the array of memory cells.. . ... Micron Technology Inc

08/09/18 / #20180224614

Apparatus providing simplified alignment of optical fiber in photonic integrated circuits

A structure for optically aligning an optical fiber to a photonic device and method of fabrication of same. The structure optically aligns an optical fiber to the photonic device using a lens between the two which is moveable by actuator heads. ... Micron Technology Inc

08/02/18 / #20180219153

Semiconductor constructions, methods of forming memory, and methods of forming vertically-stacked structures

Some embodiments include constructions having electrically conductive bitlines within a stack of alternating electrically conductive wordline levels and electrically insulative levels. Cavities extend into the electrically conductive wordline levels, and phase change material is within the cavities. ... Micron Technology Inc

08/02/18 / #20180219021

Memory arrays, and methods of forming memory arrays

Some embodiments include a memory array which has a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control gate regions. ... Micron Technology Inc

08/02/18 / #20180219020

Integrated structures and nand memory arrays

Some embodiments include an integrated structure having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include primary regions of a first vertical thickness, and terminal projections of a second vertical thickness which is greater than the first vertical thickness. ... Micron Technology Inc

08/02/18 / #20180219017

Nand memory arrays

Some embodiments include a nand memory array which has a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control gate regions. ... Micron Technology Inc

08/02/18 / #20180219002

Semiconductor device assembly with through-mold cooling channel formed in encapsulant

Semiconductor device assemblies having stacked semiconductor dies and thermal transfer devices that include vapor chambers are disclosed herein. In one embodiment, a semiconductor device assembly includes a first semiconductor die having a base region, at least one second semiconductor die at the base region, and a thermal transfer device attached to the first and second dies. ... Micron Technology Inc

08/02/18 / #20180218767

Apparatuses and methods for distributing row hammer refresh events across a memory device

Apparatuses and methods for distributing row hammer refresh events across a memory device is disclosed. In one embodiment, the present disclosure is directed to an apparatus that includes a first memory configured to receive a sequential series of refresh commands and to replace a first of the sequential refresh commands with a row hammer refresh operation once during a refresh steal cycle, a second memory configured to receive the sequential series of refresh commands at to replace a second of the sequential refresh command with a row hammer refresh operation once during a refresh steal cycle, wherein the first of the sequential refresh commands and the second of the sequential refresh commands are different commands.. ... Micron Technology Inc

08/02/18 / #20180218765

Integrated memory assemblies comprising multiple memory array decks

Some embodiments include an integrated memory assembly having a first memory array deck over a second memory array deck. A first series of conductive lines extends across the first memory array deck, and a second series of conductive lines extends across the second memory array deck. ... Micron Technology Inc

08/02/18 / #20180217960

Methods and apparatuses for differential signal termination

According to one embodiment, an apparatus comprises a differential signaling bus, a tristate transmitter connected with the differential signaling bus, the tristate transmitter configured to provide a signal on the differential signaling bus responsive to a corresponding control signal, a receiver, a pair of differential inputs of the receiver connected with the differential signaling bus and configured to receive the signal from the differential signaling bus, and a termination circuit configured to couple a first differential input of the pair of differential inputs to a first voltage source and to couple a second differential input of the pair of differential inputs to a second voltage source, wherein the first and second voltage sources have different voltage levels.. . ... Micron Technology Inc

08/02/18 / #20180217782

Buffer operations in memory

Apparatuses and methods for performing buffer operations in memory are provided. One example method can include storing second page data and third page data on a buffer while programming first page data during a first pass programming operation and programming the second page data and the third page data from the buffer to the array of memory cells during a second pass programming operation.. ... Micron Technology Inc

08/02/18 / #20180217773

Memory device configuration commands

Apparatuses and methods for configuring a memory device using configuration commands are provided. One example method can include executing a first command while the memory device is in a ready state to configure the memory device to a particular mode and executing a second command to perform a first operation while the memory device is in the particular mode.. ... Micron Technology Inc

07/26/18 / #20180212516

Charge pumps and methods of operating charge pumps

Methods of operating a charge pump, and charge pumps configured to perform similar methods, involve monitoring a level of a supply voltage of the charge pump, and turning off an oscillator of the charge pump responsive to the level of the supply voltage dropping below a certain level, wherein turning off the oscillator comprises setting an inverter in a ring oscillator loop of the oscillator to a steady state output.. . ... Micron Technology Inc

07/26/18 / #20180211896

Packaged semiconductor components having substantially rigid support members and methods of packaging semiconductor components

Packaged semiconductor components having substantially rigid support member are disclosed. The packages can include a semiconductor die and a support member proximate to the semiconductor die. ... Micron Technology Inc

07/26/18 / #20180211868

Methods for isolating portions of a loop of pitch-multiplied material and related structures

Different portions of a continuous loop of semiconductor material are electrically isolated from one another. In some embodiments, the end of the loop is electrically isolated from mid-portions of the loop. ... Micron Technology Inc

07/26/18 / #20180211714

Apparatus configured to program memory cells using an intermediate level for multiple data states

Apparatus including an array of memory cells and a controller configured to apply a particular programming pulse to a plurality of memory cells having a first subset of memory cells having respective desired data states that are lower than a particular data state and a second subset of memory cells having respective desired data states that are higher than or equal to the particular data state, to at least partially inhibit each memory cell of the first subset of memory cells from programming while not inhibiting any memory cell of the second subset of memory cells from programming and while applying the particular programming pulse, then to apply a subsequent programming pulse while not inhibiting any memory cell of the first subset of memory cells from programming other than any memory cell of the first subset of memory cells having its respective desired data state equal to a lowest data state, and while not inhibiting any memory cell of the second subset of memory cells from programming.. . ... Micron Technology Inc

07/26/18 / #20180211711

Apparatus and methods of operating memory for negative gate to body conditions

Methods of operating a memory, and apparatus so configured, include applying a first voltage level to a first voltage node connected to a first end of a string of series-connected memory cells, applying a second voltage level to a second voltage node connected to a second end of the string, applying a third voltage level less than the first and second voltage levels to a control gate of a first memory cell of the string while applying the first and second voltage levels to the first and second voltage nodes, and applying a fourth voltage level less than the third voltage level to a control gate of a second memory cell of the string while applying the third voltage level to the control gate of the first memory cell, wherein the first memory cell is closer to the first voltage node than the second memory cell.. . ... Micron Technology Inc

07/26/18 / #20180211710

Memory device including multiple gate-induced drain leakage current generator circuits

Some embodiments include apparatuses and methods of using and forming such apparatuses. An apparatus among the apparatuses includes first and second conductive materials located in respective first and second levels of the apparatus, a pillar including a length extending between the first and second conductive materials, memory cells and control lines located along the pillar, a first select gate and a first select line located along the pillar between the first conductive material and the memory cells, a second select gate and a second select line located along the pillar between the first conductive material and the first select line, a first transistor and a first transistor gate line located along the pillar between the first conductive material and the first select line, and a second transistor and a second transistor gate line located along the pillar between the first conductive material and the first transistor.. ... Micron Technology Inc

07/26/18 / #20180211695

Apparatuses and methods for storing and writing multiple parameter codes for memory operating parameters

Apparatuses and methods for writing and storing parameter codes for operating parameters, and selecting between the parameter codes to set an operating condition for a memory are disclosed. An example apparatus includes a first mode register and a second mode register. ... Micron Technology Inc

07/26/18 / #20180210847

Memory protocol with command priority

The present disclosure includes apparatuses and methods related to a memory protocol with command priority. An example apparatus can execute a command that includes a read identification (rid) number based on a priority assigned to the rid number in a register. ... Micron Technology Inc

07/26/18 / #20180210660

Multidimensional contiguous memory allocation

The present disclosure is related to multidimensional contiguous memory allocation. Multidimensional contiguous memory allocation can include receiving an allocation request for an amount of memory that is contiguous in a multiple dimensions of the memory and determining whether the memory includes a region corresponding to the requested amount that is a candidate as being unallocated based on information indicating a maximum number of contiguous unallocated allocable portions of the memory. ... Micron Technology Inc

07/26/18 / #20180210655

Hybrid memory drives, computer system, and related method for operating a multi-mode hybrid drive

A multi-mode hybrid memory drive comprises a bulk memory device and a removable cache memory device. A controller of the bulk memory device may be configured to operate the bulk memory device in either a stand-alone mode or a hybrid mode responsive to detecting the removable cache memory device being coupled with a cache port of the bulk memory device. ... Micron Technology Inc

07/26/18 / #20180210653

Partially written block treatment

The present disclosure relates to partially written block treatment. An example method comprises maintaining, internal to a memory device, a status of a last written page corresponding to a partially written block. ... Micron Technology Inc

07/19/18 / #20180204880

Thermal insulation for three-dimensional memory arrays

Methods, systems, and devices for a three-dimensional memory array are described. Memory cells may transform when exposed to elevated temperatures, including elevated temperatures associated with a read or write operation of a neighboring cell, corrupting the data stored in them. ... Micron Technology Inc

07/19/18 / #20180204879

Thermal insulation for three-dimensional memory arrays

Methods, systems, and devices for a three-dimensional memory array are described. Memory cells may transform when exposed to elevated temperatures, including elevated temperatures associated with a read or write operation of a neighboring cell, corrupting the data stored in them. ... Micron Technology Inc

07/19/18 / #20180204851

Memory arrays and methods of fabricating integrated structures

Some embodiments include a memory array which has a stack of alternating first and second levels. Channel material pillars extend through the stack, and vertically-stacked memory cell strings are along the channel material pillars. ... Micron Technology Inc

07/19/18 / #20180204849

Memory cells, integrated structures and memory arrays

Some embodiments include a memory cell which has, in the following order; a control gate, charge-blocking material, charge-trapping material, a first oxide, a charge-passage structure, a second oxide, and channel material. The charge-passage structure has a central region sandwiched between first and second regions. ... Micron Technology Inc

07/19/18 / #20180204803

Interconnect structure with nitrided barrier

Semiconductor device interconnect structures comprising nitrided barriers are disclosed herein. In one embodiment, an interconnect structure includes a conductive material at least partially filling an opening in a semiconductor substrate, and a nitrided barrier between the conductive material and a sidewall in the opening. ... Micron Technology Inc

07/19/18 / #20180204799

Conductive structures, systems and devices including conductive structures and related methods

Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. ... Micron Technology Inc

07/19/18 / #20180204630

Apparatuses and methods for high speed writing test mode for memories

Apparatuses and methods are provided for a high speed writing test mode for memories. An example apparatus includes a memory core, a data terminal coupled to a data receiver, a read buffer coupled between the data terminal and the memory core, and a write buffer coupled between the data receiver and the memory core. ... Micron Technology Inc

07/19/18 / #20180204608

Apparatuses and methods for providing internal clock signals of different clock frequencies in a memory device

Apparatuses and methods for providing internal clock signals of different clock frequencies in a semiconductor device are described in the present application. An example apparatus includes a read command buffer and a read data output circuit. ... Micron Technology Inc

07/19/18 / #20180203671

Signed division in memory

Examples of the present disclosure provide apparatuses and methods for performing signed division operations. An apparatus can include a first group of memory cells coupled to a first access line and a number of sense lines. ... Micron Technology Inc

07/19/18 / #20180203613

Memory device including mixed non-volatile memory cell types

Some embodiments include apparatuses, and methods of forming and operating the apparatuses. Some of the apparatuses include a conductive line, non-volatile memory cells of a first memory cell type, the non-volatile memory cells coupled in series among each other, and an additional non-volatile memory cell of a second memory cell type coupled to the conductive line and coupled in series with the non-volatile memory cells of the first memory cell type. ... Micron Technology Inc

07/12/18 / #20180198642

Computerized apparatus with a high speed data bus

A computerized apparatus configured for high-speed data transactions between components thereof. In one embodiment, the computerized apparatus includes a high-speed ring data bus apparatus with a plurality of nodes, and associated application apparatus in data communication with at least one of the nodes. ... Micron Technology Inc

07/12/18 / #20180198063

Memory cells, semiconductor devices including the memory cells, and methods of operation

Memory cells are disclosed, which cells include a cell material and an ion-source material over the cell material. A discontinuous interfacial material is included between the cell material and the ion-source material. ... Micron Technology Inc

07/12/18 / #20180197949

Integrated memory

Some embodiments include an integrated memory having an array of capacitors. The array has edges. ... Micron Technology Inc

07/12/18 / #20180197942

Methods of forming an array of capacitors, methods of forming an array of memory cells individually comprising a capacitor and a transistor, arrays of capacitors, and arrays of memory cells individually comprising a capacitor and a transistor

A method of forming an array of capacitors comprises forming elevationally-extending and longitudinally-elongated capacitor electrode lines over a substrate. Individual of the capacitor electrode lines are common to and a shared one of two capacitor electrodes of individual capacitors longitudinally along a line of capacitors being formed. ... Micron Technology Inc

07/12/18 / #20180197870

Memory cells and methods of forming a capacitor

A memory cell comprises a capacitor having a first conductive capacitor electrode having laterally-spaced walls that individually have a top surface. A second conductive capacitor electrode is laterally between the walls of the first capacitor electrode, and comprises a portion above the first capacitor electrode. ... Micron Technology Inc

07/12/18 / #20180197869

Methods of forming an array comprising pairs of vertically opposed capacitors and arrays comprising pairs of vertically opposed capacitors

A method of forming an array comprising pairs of vertically opposed capacitors comprises forming a conductive lining in individual capacitor openings in support material. An elevational mid-portion of individual of the conductive linings is removed to form an upper capacitor electrode lining and a lower capacitor electrode lining that are elevationally separate and spaced from one another in the individual capacitor openings. ... Micron Technology Inc

07/12/18 / #20180197864

Memory cells, arrays of two transistor-one capacitor memory cells, methods of forming an array of two transistor-one capacitor memory cells, and methods used in fabricating integrated circuitry

A two transistor-one capacitor memory cell comprises first and second transistors laterally displaced relative one another. A capacitor is above the first and second transistors. ... Micron Technology Inc

07/12/18 / #20180197862

Memory cell, an array of memory cells individually comprising a capacitor and a transistor with the array comprising rows of access lines and columns of digit lines, a 2t-1c memory cell, and methods of forming an array of capacitors and access transistors there-above

A method of forming an array of capacitors and access transistors there-above comprises forming access transistor trenches partially into insulative material. The trenches individually comprise longitudinally-spaced masked portions and longitudinally-spaced openings in the trenches longitudinally between the masked portions. ... Micron Technology Inc

07/12/18 / #20180197735

Silicon chalcogenate precursors and methods of forming the silicon chalcogenate precursors

A silicon chalcogenate precursor comprising the chemical formula of si(xr1)nr24-n, where x is sulfur, selenium, or tellurium, r1 is hydrogen, an alkyl group, a substituted alkyl group, an alkoxide group, a substituted alkoxide group, an amide group, a substituted amide group, an amine group, a substituted amine group, or a halogen group, each r2 is independently hydrogen, an alkyl group, a substituted alkyl group, an alkoxide group, a substituted alkoxide group, an amide group, a substituted amide group, an amine group, a substituted amine group, or a halogen group, and n is 1, 2, 3, or 4. Methods of forming the silicon chalcogenate precursor, methods of forming silicon nitride, and methods of forming a semiconductor structure are also disclosed.. ... Micron Technology Inc

07/12/18 / #20180197620

Setting a default read signal based on error correction

The present disclosure includes apparatuses and methods related to setting a default read signal based on error correction. A number of methods can include reading a page of data from a group of memory cells with a first discrete read signal and error correcting at least one codeword of the page of data as read with the first discrete read signal. ... Micron Technology Inc

07/12/18 / #20180197595

Apparatuses and methods for a memory device with dual common data i/o lines

Apparatuses are presented for a semiconductor device utilizing dual i/o line pairs. The apparatus includes a first i/o line pair coupled to a first local i/o line pair. ... Micron Technology Inc

07/12/18 / #20180197583

Methods and apparatuses for providing a program voltage responsive to a voltage determination

Apparatuses and methods for providing a program voltage responsive to a voltage determination are described. An example apparatus includes a memory array comprising a plurality of access lines. ... Micron Technology Inc

07/12/18 / #20180196757

Virtual address table

The present disclosure includes apparatuses and methods related to virtual address tables. An example method comprises generating an object file that comprises: an instruction comprising a number of arguments; and an address table comprising a number of indexed address elements. ... Micron Technology Inc

07/12/18 / #20180196743

Directed sanitization of memory

The present disclosure includes apparatuses and methods for directed sanitization of memory. One example method comprises, responsive to receiving a sanitization command, performing a deterministic garbage collection operation on a memory, wherein performing the deterministic garbage collection operation results in physical erasure of all invalid data stored on the memory without losing valid data stored on the memory.. ... Micron Technology Inc

07/12/18 / #20180196705

Identifying asynchronous power loss

Apparatus include controllers configured to iteratively program a group of memory cells to respective desired data states; determine whether a power loss to the apparatus is indicated while iteratively programming the group of memory cells; and if a power loss to the apparatus is indicated, to change the desired data state of the particular memory cell before continuing with the programming. Apparatus further include controllers configured to read a particular memory cell of a last written page of memory cells, determine whether a threshold voltage of the particular memory cell is less than a particular voltage level, and to mark the last written page of memory cells as affected by power loss during a programming operation of the last written page of memory cells when the threshold voltage of the particular memory cell is determined to be higher than the particular voltage level.. ... Micron Technology Inc

07/12/18 / #20180196614

Error correction

An example apparatus for error correction can include an array of memory cells and a controller. The controller can be configured to perform a dummy read on a portion of data stored in the array. ... Micron Technology Inc

07/12/18 / #20180195049

Arrays of memory cells individually comprising a capacitor and an elevationally-extending transistor, methods of forming a tier of an array of memory cells, and methods of forming an array of memory cells individually comprising a capacitor and an elevationally-extending transistor

A method of forming a tier of an array of memory cells within an array area, the memory cells individually comprising a capacitor and an elevationally-extending transistor, the method comprising using two, and only two, sacrificial masking steps within the array area of the tier in forming the memory cells. Other methods are disclosed, as are structures independent of method of fabrication.. ... Micron Technology Inc

07/05/18 / #20180192517

Apparatus and methods for via connection with reduced via currents

Apparatuses and methods including conductive vias of a printed circuit board are described. An example apparatus includes a first layer including a first conductive plate; a component on the first layer, a second layer including a second conductive plate that may be coupled to an external power source; a third layer between the first layer and the second layer, the third layer including a third conductive plate; a first via coupling the first conductive plate to the second conductive plate; and a second via coupled to the first conductive plate. ... Micron Technology Inc

07/05/18 / #20180191528

Testing impedance adjustment

Methods of operating integrated circuit devices include generating a voltage level at a particular node in response to a first voltage level applied to a termination device and a second voltage level applied to a reference resistance; determining whether a plurality of available resistance values of the termination device satisfy a criterion that each available resistance value is either less than a resistance value of the reference resistance, or each available resistance value is greater than the resistance value of the reference resistance; and, when the plurality of available resistance values of the termination device satisfy the criterion, determining whether a voltage level generated at the particular node for a particular available resistance value of the plurality of available resistance values is between a voltage level of a first reference voltage and a voltage level of a second reference voltage.. . ... Micron Technology Inc

07/05/18 / #20180190873

Solid state transducer dies having reflective features over contacts and associated systems and methods

Systems and methods for improved light emitting efficiency of a solid state transducer (sst), for example light emitting diodes (led), are disclosed. One embodiment of an sst die in accordance with the technology includes a reflective material disposed over electrical connectors on a front side of the die. ... Micron Technology Inc

07/05/18 / #20180190862

Solid state lighting devices with dielectric insulation and methods of manufacturing

Solid state lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state lighting device includes a first semiconductor material, a second semiconductor material spaced apart from the first semiconductor material, and an active region between the first and second semiconductor materials. ... Micron Technology Inc

07/05/18 / #20180190761

Mim capacitor with enhanced capacitance

A metal-insulator-metal (mim) capacitor is disclosed. The mim capacitor includes a substrate having a first dielectric layer thereon and a bottom electrode embedded in the first dielectric layer. ... Micron Technology Inc

07/05/18 / #20180190717

Memory devices, systems, and methods of forming arrays of memory cells

Memory devices include an array of memory cells including magnetic tunnel junction regions. The array of memory cells includes access lines extending in a first direction and data lines extending in a second direction transverse to the first direction. ... Micron Technology Inc

07/05/18 / #20180190713

Magnetic memory device with grid-shaped common source plate, system, and method of fabrication

Magnetic memory devices include an array of magnetic memory cells including magnetic tunnel junction regions. The array of magnetic memory cells includes access lines extending in a column direction and data/sense lines extending in a row direction transverse to the column direction. ... Micron Technology Inc

07/05/18 / #20180190620

Interconnect structures with intermetallic palladium joints and associated systems and methods

Interconnect structures with intermetallic palladium joints are disclosed herein. In one embodiment, a method of forming an interconnect structure includes depositing a first conductive material comprising nickel on a first conductive surface of a first die, and depositing a second conductive material comprising nickel on a second conductive surface of a second die spaced apart from the first surface. ... Micron Technology Inc

07/05/18 / #20180190613

Wiring with external terminal

Apparatuses for providing external terminals of a semiconductor device are described. An example apparatus includes: a connection wiring of a ring-shape having comprising a hole and a conductive layer surrounding the hole, the conductive layer including a first connection point and a second connection point that are located so that a straight line between the first connection point and the second connection point crosses over the hole; an external terminal coupled to the first connection point of the conductive layer of the connection wiring; and an internal circuit coupled to the second connection point of the conductive layer of the connection wiring.. ... Micron Technology Inc

07/05/18 / #20180190587

Semiconductor device structures including stair step structures, and related semiconductor devices

A method of forming a semiconductor device assembly comprises forming tiers comprising conductive structures and insulating structures in a stacked arrangement over a substrate. Portions of the tiers are selectively removed to form a stair step structure comprising a selected number of steps exhibiting different widths corresponding to variances in projected error associated with forming the steps. ... Micron Technology Inc

07/05/18 / #20180190582

Semiconductor package with embedded mim capacitor, and method of fabricating thereof

An interposer includes a first redistribution layer, an organic substrate, a capacitor, a hard mask layer, a conductive pillar, and a second redistribution layer. The organic substrate is on the first redistribution layer. ... Micron Technology Inc

07/05/18 / #20180190571

Semiconductor device having through-silicon-via and methods of forming the same

Semiconductor devices having a through-silicon-via and methods of forming the same are described herein. As an example, a semiconductor device may include a substrate material, a through-silicon-via protrusion extending from the substrate material, a first dielectric material formed on the substrate material, a second dielectric material formed on the first dielectric material, and an interconnect formed on the through-silicon-via protrusion, where the interconnect formed is in an opening in the second dielectric material.. ... Micron Technology Inc

07/05/18 / #20180190531

Semiconductor package structures including redistribution layers

A package structure and a method for fabricating thereof are provided. The package structure includes a substrate, a first connector, a redistribution layer, a second connector, and a chip. ... Micron Technology Inc

07/05/18 / #20180190368

Timing based arbiter systems and circuits for zq calibration

Systems and apparatuses are provided for an arbiter circuit for timing based zq calibration. An example system includes a resistor and a plurality of chips. ... Micron Technology Inc

07/05/18 / #20180190367

Apparatuses and methods for memory testing and repair

Some embodiments include apparatuses and methods having a first interface to communicate with a processing unit, a second interface to communicate with a memory device, and a module coupled to the first and second interfaces. In at least one of the embodiments, the module can be configured to obtain information stored in the memory device and perform at least one of testing and repairing of a memory structure of the memory device based at least in part on the information.. ... Micron Technology Inc

07/05/18 / #20180190349

Accessing memory cells in parallel in a cross-point array

Methods and structures for accessing memory cells in parallel in a cross-point array include accessing in parallel a first memory cell disposed between a first selected column and a first selected row and a second memory cell disposed between a second selected column different from the first selected column and a second selected row different from the first selected row. Accessing in parallel includes simultaneously applying access biases between the first selected column and the first selected row and between the second selected column and the second selected row. ... Micron Technology Inc

07/05/18 / #20180190347

Programming memories with multi-level pass signal

Methods of operating a memory include applying a first voltage level to control gates of a plurality of memory cells selected to be programmed while applying a second voltage level to a respective data line for each memory cell of the plurality of memory cells; increasing the voltage level applied to the respective data line for memory cells of a first subset of memory cells to a third voltage level then increasing the voltage level applied to the control gates of the plurality of memory cells to a fourth voltage level; increasing the voltage level applied to the respective data line for each memory cell of a second subset of memory cells of the plurality of memory cells to a fifth voltage level then; and after increasing the voltage level applied to the respective data line for each memory cell of the second subset of memory cells to the fifth voltage level, increasing the voltage level applied to the control gates of the plurality of memory cells to a sixth voltage level.. . ... Micron Technology Inc

07/05/18 / #20180190342

Oscillator controlled random sampling method and circuit

Various embodiments comprise methods and apparatuses for selecting a randomly-chosen seed row from among a stream of available data in a memory system. A refresh operation is then performed on at least one selected row of memory in the memory system based on the randomly-chosen seed row. ... Micron Technology Inc








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