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Micron Technology Inc patents (2015 archive)


Recent patent applications related to Micron Technology Inc. Micron Technology Inc is listed as an Agent/Assignee. Note: Micron Technology Inc may have other listings under different names/spellings. We're not affiliated with Micron Technology Inc, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "M" | Micron Technology Inc-related inventors


12/31/15 / #20150381199

Comparators for delta-sigma modulators

Methods, systems and devices are disclosed, such as an electronic device that includes a plurality of data locations and a delta-sigma modulator. In some embodiments, the delta-sigma modulator includes a preamplifier coupled to the data locations and a latch coupled to the preamplifier.. ... Micron Technology Inc

12/31/15 / #20150381189

Die location compensation

Embodiments are described that compensate for a difference in a characteristic (e.g., of performance or operation) of a semiconductor device that is a function of the location of a die in a device. In one embodiment, a clock circuit may generate a clock signal having a timing that varies with the location of a die so that signals are coupled from the die to a substrate at the same time despite differences in the signal propagation time between the substrate and the various die. ... Micron Technology Inc

12/31/15 / #20150380647

Buried low-resistance metal word lines for cross-point variable-resistance material memories

Variable-resistance material memories include a buried salicide word line disposed below a diode. Variable-resistance material memories include a metal spacer spaced apart and next to the diode. ... Micron Technology Inc

12/31/15 / #20150380646

Resistive memory cell

Semiconductor memory devices, resistive memory devices, memory cell structures, and methods of forming a resistive memory cell are provided. One example method of a resistive memory cell can include a number of dielectric regions formed between two electrodes, and a barrier dielectric region formed between each of the dielectric regions. ... Micron Technology Inc

12/31/15 / #20150380645

Memory cells and methods of forming memory cells

Some embodiments include a memory cell having an electrode and a switching material over the electrode. The electrode is a first composition which includes a first metal and a second metal. ... Micron Technology Inc

12/31/15 / #20150380432

Methods of forming a charge-retaining transistor

A charge-retaining transistor includes a control gate and an inter-gate dielectric alongside the control gate. A charge-storage node of the transistor includes first semiconductor material alongside the inter-gate dielectric. ... Micron Technology Inc

12/31/15 / #20150380307

Methods of forming openings in semiconductor structures

A method of forming a semiconductor structure comprises forming pools of acidic or basic material in a substrate structure. A resist is formed over the pools of acidic or basic material and the substrate structure. ... Micron Technology Inc

12/31/15 / #20150380260

Semiconductor structures including self-assembled polymer domains registered to the underlying self-assembled polymer domains, templates comprising the same, and methods of forming the same

A semiconductor structure comprises a first self-assembled block copolymer material within a trench in a substrate and a second self-assembled block copolymer material overlying the first self-assembled block copolymer material. The first self-assembled block copolymer material comprises self-assembled polymer domains registered to sidewalls of the trench and extending a length of the trench. ... Micron Technology Inc

12/31/15 / #20150380240

Gallium lanthanide oxide films

Electronic apparatus and methods of forming the electronic apparatus include a gallium lanthanide oxide film for use in a variety of electronic systems. The gallium lanthanide oxide film may be structured as one or more monolayers. ... Micron Technology Inc

12/31/15 / #20150380109

Apparatuses and methods for memory testing and repair

Some embodiments include apparatuses and methods having a first interface to communicate with a processing unit, a second interface to communicate with a memory device, and a module coupled to the first and second interfaces. In at least one of the embodiments, the module can be configured to obtain information stored in the memory device and perform at least one of testing and repairing of a memory structure of the memory device based at least in part on the information.. ... Micron Technology Inc

12/31/15 / #20150380108

Systems and methods involving managing a problematic memory cell

Subject matter described pertains to managing problematic memory cells in a memory array.. . ... Micron Technology Inc

12/31/15 / #20150380098

Continuous adjusting of sensing voltages

The present disclosure includes apparatuses and methods for continuous adjusting of sensing voltages. A number of embodiments include continuously monitoring an error rate associated with sense operations performed on a group of memory cells, and continuously adjusting a sensing voltage used to determine a state of the memory cells of the group based, at least partially, on the error rate.. ... Micron Technology Inc

12/31/15 / #20150380091

Methods of programming memories

Methods of programming memories include applying a first plurality of programming pulses to the group of memory cells to program first data to the group of memory cells, determining an upper limit of a resulting threshold voltage distribution for the group of memory cells following a particular programming pulse of the first plurality of programming pulses, and applying a second plurality of programming pulses to the group of memory cells to program second data to the group of memory cells, wherein a characteristic of at least one of the programming pulses of the second plurality of programming pulses is at least partially based on the determined upper limit of the threshold voltage distribution. Methods of programming memories further include programming information indicative of usage of memory cells of a page of memory cells to the page of memory cells during a portion of a programming operation.. ... Micron Technology Inc

12/31/15 / #20150380084

Memory devices with reduced operational energy in phase change material and methods of operation

Methods of forming and operating phase change memory devices include adjusting an activation energy barrier between a metastable phase and a stable phase of a phase change material in a memory cell. In some embodiments, the activation energy barrier is adjusted by applying stress to the phase change material in the memory cell. ... Micron Technology Inc

12/31/15 / #20150378889

Persistent content in nonvolatile memory

Applications may request persistent storage in nonvolatile memory. The persistent storage is maintained across power events and application instantiations. ... Micron Technology Inc

12/31/15 / #20150378826

Circuits, apparatuses, and methods for correcting data errors

One example apparatus includes a first circuit configured to receive first and second data words, to correct one or more errors in the first data word, to merge the corrected first data word and the second data word responsive to a control signal to generate a final merged data word, and to provide the final merged data word to a write circuit. The apparatus also includes a second circuit configured to also receive the first and second data words, to preliminarliy merge the first and second data words responsive to the control signal to generate an initial merged data word, to generate an initial parity code for the initial merged data word, to correct the initial parity code, and to provide the corrected parity code to the write circuit.. ... Micron Technology Inc

12/31/15 / #20150378427

Apparatuses and methods of entering unselected memories into a different power mode during multi-memory operation

Disclosed are examples of apparatuses including memory devices and systems comprising memories sharing a common enable signal, wherein the memories may be put into different power modes. Example methods for setting the different power modes of the memories are disclosed. ... Micron Technology Inc

12/24/15 / #20150372685

Semiconductor device including oscillator

According to the present invention, a ring oscillator coupled to an output node operable to output a clock signal including a first logic level generated by a first odd number of delay circuits, and a second logic level different from the first logic level generated by a second odd number of delay circuits different from the first odd number of delay circuits.. . ... Micron Technology Inc

12/24/15 / #20150372227

Memory cells

Memory cells useful in phase change memory include a phase change material between first and second electrode and having a surface facing a surface of the second electrode. The second electrode comprises a plurality of portions of material, each portion having a respective distance from the surface of the phase change material and each portion having a respective resistivity. ... Micron Technology Inc

12/24/15 / #20150371969

Methods of processing wafer-level assemblies to reduce warpage, and related assemblies

Wafer-level methods of processing semiconductor devices may involve forming grooves partially through a molding material, the molding material located in streets and at least surrounding stacks of semiconductor dice located on a wafer. Wafer-level methods of preparing semiconductor devices may involve attaching a wafer to a carrier substrate and forming stacks of laterally spaced semiconductor dice on die locations of the wafer. ... Micron Technology Inc

12/24/15 / #20150371706

Memory systems and memory programming methods

Memory systems and memory programming methods are described. According to one aspect, a memory system includes program circuitry configured to provide a program signal to a memory cell to program the memory cell from a first memory state to a second memory state, detection circuitry configured to detect the memory cell changing from the first memory state to the second memory state during the provision of the program signal to the memory cell to program the memory cell, and wherein the program circuitry is configured to alter the program signal as a result of the detection and to provide the altered program signal to the memory cell to continue to program the memory cell from the first memory state to the second memory state.. ... Micron Technology Inc

12/24/15 / #20150371688

Memory devices having special mode access

Memory devices are provided that include special operating modes accessible upon receipt of a particular message from a host. One device includes a memory array, a special mode enable register, and a controller. ... Micron Technology Inc

12/24/15 / #20150370750

Memory device for a hierarchical memory architecture

A hierarchical memory device having multiple interfaces with different memory formats includes a phase change memory (pcm). An input port and an output port connect the hierarchical memory device in a daisy-chain hierarchy or a hierarchical tree structure with other memories. ... Micron Technology Inc

12/17/15 / #20150365614

Image sensor defect identification using optical flare

Embodiments described herein may operate to compare an illuminance corresponding to a signal from an image sensor array (isa) element in a production imaging system with an illuminance associated with optical flare incident to an isa from which the isa element is selected. The isa element may be identified as unusable if the illuminance corresponding to the signal from the isa element is less than the illuminance associated with the optical flare incident to the isa.. ... Micron Technology Inc

12/17/15 / #20150365579

Method and apparatus providing pixel array having automatic light control pixels and image capture pixels

A pixel array uses two sets of pixels to provide accurate exposure control. One set of pixels provide continuous output signals for automatic light control (alc) as the other set integrates and captures an image. ... Micron Technology Inc

12/17/15 / #20150365091

Boolean logic in a state machine lattice

Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may includes a programmable boolean logic cell that may be programmed to perform various logic functions on a data stream. ... Micron Technology Inc

12/17/15 / #20150365077

Semiconductor device having output buffers and voltage path coupled to output buffers

An apparatus includes first and second data pads arranged adjacently to each other in a first direction without an intervention of a pad therebetween, first and second output transistors coupled correspondingly to the first and second data pads and arranged adjacently to each other in the first direction and at least one contact plug through which a voltage is supplied to each of the first and second output transistors. The at least one contact plug is arranged between the first and second output transistors.. ... Micron Technology Inc

12/17/15 / #20150364683

Memory cells with recessed electrode contacts

Memory cells with recessed electrode contacts and methods of forming the same are provided. An example memory cell can include an electrode contact formed in a substrate. ... Micron Technology Inc

12/17/15 / #20150364565

Memory cell and an array of memory cells

A memory cell includes a first electrode and a second electrode. A select device and a programmable device are in series with each other between the first and second electrodes. ... Micron Technology Inc

12/17/15 / #20150364557

Gettering agents in memory charge storage structures

Methods of forming memory cells including a charge storage structure having a gettering agent therein can be useful for non-volatile memory devices. Providing for gettering of oxygen from a charge-storage material of the charge storage structure can facilitate a mitigation of detrimental oxidation of the charge-storage material.. ... Micron Technology Inc

12/17/15 / #20150364483

Conductors having a variable concentration of germanium for governing removal rates of the conductor during control gate formation

An embodiment of a method of forming a control gate includes forming a conductor having a concentration of germanium that varies with a thickness of the conductor, and removing portions of the conductor at a variable rate that is governed, at least in part, by the concentration of the germanium.. . ... Micron Technology Inc

12/17/15 / #20150364414

Array of conductive vias, methods of forming a memory array, and methods of forming conductive vias

A method of forming conductive vias comprises forming at least three parallel line constructions elevationally over a substrate. The line constructions individually comprise a dielectric top and dielectric sidewalls. ... Micron Technology Inc

12/17/15 / #20150364403

Packaged semiconductor components having substantially rigid support members and methods of packaging semiconductor components

Packaged semiconductor components having substantially rigid support member are disclosed. The packages can include a semiconductor die and a support member proximate to the semiconductor die. ... Micron Technology Inc

12/17/15 / #20150364400

Semiconductor structures and die assemblies including conductive vias and thermally conductive elements and methods of forming such structures

A semiconductor structure comprises conductive vias extending from an active surface of a substrate to a back side of the substrate and surrounded by a dielectric material. The conductive vias are surrounded by recessed isolation structures formed within the back side of the substrate. ... Micron Technology Inc

12/17/15 / #20150364379

Methods of forming gated devices

Some embodiments include methods of forming gated devices. An upper region of a semiconductor material is patterned into a plurality of walls that extend primarily along a first direction. ... Micron Technology Inc

12/17/15 / #20150364377

Methods of forming transistors

Some embodiments include methods of forming transistors. Recesses are formed to extend into semiconductor material. ... Micron Technology Inc

12/17/15 / #20150364214

Reclaimable semiconductor device package and associated systems and methods

Several embodiments of reclaimable semiconductor device packages and assemblies are disclosed herein. A semiconductor device assembly (100) includes a package (101) having a housing (102) and a package contact (104) arranged to receive a signal indicative of a reclamation state. ... Micron Technology Inc

12/17/15 / #20150364213

Program operations with embedded leak checks

Methods of operating a memory device having embedded leak checks may mitigate data loss events due to access line defects, and may facilitate improved power consumption characteristics. Such methods might include applying a program pulse to a selected access line coupled to a memory cell selected for programming, verifying whether the selected memory cell has reached a desired data state, bringing the selected access line to a first voltage, applying a second voltage to an unselected access line, applying a reference current to the selected access line, and determining if a current flow between the selected access line and the unselected access line is greater than the reference current.. ... Micron Technology Inc

12/17/15 / #20150364175

Volume select for affecting a state of a non-selected memory volume

Apparatuses and methods of operating memory are described. One such method can include receiving a select command at a plurality of memory volumes of a memory device, the select command indicating a targeted memory volume of the plurality of memory volumes. ... Micron Technology Inc

12/17/15 / #20150363313

Sense operation flags in a memory device

Memory devices, methods for programming sense flags, methods for sensing flags, and memory systems are disclosed. In one such memory device, the odd bit lines of a flag memory cell array are connected with a short circuit to a dynamic data cache. ... Micron Technology Inc

12/17/15 / #20150363260

Data bus inversion usable in a memory system

Implementations of data bus inversion (dbi) techniques within a memory system are disclosed. In one embodiment, a set of random access memory (ram) integrated circuits (ics) is separated from a logic system by a bus. ... Micron Technology Inc

12/17/15 / #20150363120

On demand block management

Methods and memories for embedded systems, and systems with managed memories, are provided. In one such method, a managed memory determines when housekeeping operations are indicated, conveys that information to a host, and the host initiates the housekeeping operation at a time determined by the host not to affect real-time system operation.. ... Micron Technology Inc

12/10/15 / #20150357568

Resistive ram devices and methods

The present disclosure includes a high density resistive random access memory (rram) device, as well as methods of fabricating a high density rram device. One method of forming an rram device includes forming a resistive element having a metal-metal oxide interface. ... Micron Technology Inc

12/10/15 / #20150357565

Memory cells and memory cell formation methods using sealing material

Memory cells, arrays of memory cells, and methods of forming the same with sealing material on sidewalls thereof are disclosed herein. One example of forming a memory cell includes forming a stack of materials, forming a trench to a first depth in the stack of materials such that a portion of at least one of the active storage element material and the active select device material is exposed on sidewalls of the trench. ... Micron Technology Inc

12/10/15 / #20150357564

Phase change memory cells

A phase change memory cell has first and second electrodes having phase change material there-between. The phase change memory cell is devoid of heater material as part of either of the first and second electrodes and being devoid of heater material between either of the first and second electrodes and the phase change material. ... Micron Technology Inc

12/10/15 / #20150357563

Method for fabricating a phase-change memory cell

A method for fabricating a phase-change memory cell is described. The method includes forming a dielectric layer (228) on a metal layer (226) above a substrate. ... Micron Technology Inc

12/10/15 / #20150357465

Threshold voltage adjustment of a transistor

A threshold voltage adjusted long-channel transistor fabricated according to short-channel transistor processes is described. The threshold-adjusted transistor includes a substrate with spaced-apart source and drain regions formed in the substrate and a channel region defined between the source and drain regions. ... Micron Technology Inc

12/10/15 / #20150357380

Memory arrays with polygonal memory cells having specific sidewall orientations

Some embodiments include a memory array having a first series of access/sense lines which extend along a first direction, a second series of access/sense lines over the first series of access/sense lines and which extend along a second direction substantially orthogonal to the first direction, and memory cells vertically between the first and second series of access/sense lines. Each memory cell is uniquely addressed by a combination of an access/sense line from the first series and an access/sense line from the second series. ... Micron Technology Inc

12/10/15 / #20150357344

Memory having memory cell string and coupling components

Some embodiments include apparatuses and methods having a conductive line, a memory cell string including memory cells located in different levels the apparatus, and a select circuit including a select transistor and a coupling component coupled between the conductive line and the memory cell string. Other embodiments including additional apparatuses and methods are described.. ... Micron Technology Inc

12/10/15 / #20150357334

Arrays comprising vertically-oriented transistors and integrated circuitry comprising a conductive line buried in silicon-comprising semiconductor material

An array includes vertically-oriented transistors, rows of access lines, and columns of data/sense lines. Individual of the rows include an access line interconnecting transistors in that row. ... Micron Technology Inc

12/10/15 / #20150357314

Discontinuous patterned bonds for semiconductor devices and associated systems and methods

Discontinuous bonds for semiconductor devices are disclosed herein. A device in accordance with a particular embodiment includes a first substrate and a second substrate, with at least one of the first substrate and the second substrate having a plurality of solid-state transducers. ... Micron Technology Inc

12/10/15 / #20150357284

Semiconductor devices comprising interconnect structures and methods of fabrication

Semiconductor devices comprise at least one integrated circuit layer, at least one conductive trace and an insulative material adjacent at least a portion of the at least one conductive trace. At least one interconnect structure extends through a portion of the at least one conductive trace and a portion of the insulative material, the at least one interconnect structure comprising a transverse cross-sectional dimension through the at least one conductive trace which differs from a transverse cross-sectional dimension through the insulative material.. ... Micron Technology Inc

12/10/15 / #20150357233

Method and apparatus for fabricating a memory device with a dielectric etch stop layer

The present technique relates to a method and apparatus to provide a dielectric etch stop layer that prevents shorts for a buried digit layer as an interconnect. In a memory device, such as dram or sram, various layers are deposited to form structures, such as pmos gates, nmos gates, memory cells, p+ active areas, and n+ active areas. ... Micron Technology Inc

12/10/15 / #20150357049

Short-checking methods

In an embodiment, a short-checking method includes charging a data line to an initial voltage while activating a memory cell coupled to the data line, allowing the data line to float while continuing to activate the memory cell, sensing a resulting voltage on the data line after a certain time, and determining whether a short exists in response to a level of the resulting voltage.. . ... Micron Technology Inc

12/10/15 / #20150357047

Comparison operations in memory

Examples of the present disclosure provide apparatuses and methods related to performing comparison operations in a memory. An example apparatus might include a first group of memory cells coupled to a first access line and configured to store a first element. ... Micron Technology Inc

12/10/15 / #20150357045

Chunk definition for partial-page read

The present disclosure is related to chunk definition for partial-page read. A number of methods can include setting a chunk size for a partial-page read of a page of memory cells. ... Micron Technology Inc

12/10/15 / #20150357038

Methods, devices and systems using over-reset state in a memory cell

Memory cells, devices and methods are disclosed, including those that involve applying a waveform to a resistive memory cell to program the memory cell to an over-reset state representing a logic value.. . ... Micron Technology Inc

12/10/15 / #20150357031

Programming memories with stepped programming pulses

Memories and methods for programming memories with multi-step programming pulses are provided. One method includes applying a plurality of programming pulses to cells of the memory device to be programmed, with each programming pulse of the plurality of programming pulses being configured to contribute towards programming a cell of the plurality of cells to each data state of a plurality of programmed data states. ... Micron Technology Inc

12/10/15 / #20150357024

Apparatuses and methods for performing logical operations using sensing circuitry

The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. ... Micron Technology Inc

12/10/15 / #20150357023

Performing logical operations using sensing circuitry

The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells, sensing circuitry coupled to the array of memory cells via a sense line, and a controller coupled to the array of memory cells and the sensing circuitry. ... Micron Technology Inc

12/10/15 / #20150357022

Performing logical operations using sensing circuitry

The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array an array of memory cells via a sense line. ... Micron Technology Inc

12/10/15 / #20150357021

Performing logical operations using sensing circuitry

The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array of memory cells. ... Micron Technology Inc

12/10/15 / #20150357020

Apparatuses and methods for performing an exclusive or operation using sensing circuitry

The present disclosure includes apparatuses and methods related to determining an xor value in memory. An example method can include performing a nand operation on a data value stored in a first memory cell and a data value stored in a second memory cell. ... Micron Technology Inc

12/10/15 / #20150357019

Comparison operations in memory

One example of the present disclosure includes performing a comparison operation in memory using a logical representation of a first value stored in a first portion of a number of memory cells coupled to a sense line of a memory array and a logical representation of a second value stored in a second portion of the number of memory cells coupled to the sense line of the memory array. The comparison operation compares the first value to the second value, and the method can include storing a logical representation of a result of the comparison operation in a third portion of the number of memory cells coupled to the sense line of the memory array.. ... Micron Technology Inc

12/10/15 / #20150357010

Memory device power managers and methods

Memory devices and methods are described that include a stack of memory dies and an attached logic die. Method and devices described provide for power management of portions of a stack of memory dies. ... Micron Technology Inc

12/10/15 / #20150357008

Apparatuses and methods for performing logical operations using sensing circuitry

The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. ... Micron Technology Inc

12/10/15 / #20150357007

Apparatuses and methods for parity determination using sensing circuitry

The present disclosure includes apparatuses and methods related to parity determinations using sensing circuitry. An example method can include protecting, using sensing circuitry, a number of data values stored in a respective number of memory cells coupled to a sense line of an array by determining a parity value corresponding to the number of data values without transferring data from the array via an input/output line. ... Micron Technology Inc

12/10/15 / #20150356048

Method and apparatus for controlling access to a common bus by multiple components

Apparatuses and methods for controlling access to a common bus including a plurality of memory devices coupled to a common bus, wherein individual ones of the plurality of memory devices are configured to access the common bus responsive to a strobe signal, and a strobe line driver programmed with a first delay associated with a combination of a first command type and a first one of the plurality of memory devices to provide a first strobe signal to the first one of the plurality of memory devices, and further programmed with a second delay associated with a combination of a second command type and a second one of the plurality of memory devices to provide a second strobe signal to the second one of the plurality of memory devices.. . ... Micron Technology Inc

12/10/15 / #20150356047

Apparatuses and methods for performing a databus inversion operation

Apparatuses and methods for performing a data bus inversion operation (dbi) are described. An example apparatus includes a dbi circuit configured to, in parallel, determine preliminary dbi bits based on a block of data. ... Micron Technology Inc

12/10/15 / #20150356022

Virtual address table

The present disclosure includes apparatuses and methods related to virtual address tables. An example method comprises generating an object file that comprises: an instruction comprising a number of arguments; and an address table comprising a number of indexed address elements. ... Micron Technology Inc

12/10/15 / #20150356009

Data storage layout

Examples of the present disclosure provide apparatuses and methods for determining a data storage layout. An example apparatus comprising a first address space of a memory array comprising a first number of memory cells coupled to a plurality of sense lines and to a first select line. ... Micron Technology Inc

12/10/15 / #20150355986

Cooperative memory error detection and repair

Some embodiments include apparatuses and methods having a memory structure included in a memory device and a control unit included in the memory device. The control unit can provide information obtained from the memory structure during a memory operation to a host device (e.g., a processor) in response to a command from the host device. ... Micron Technology Inc

12/10/15 / #20150355849

Sensing operations in a memory device

Methods for sensing, method for programming, memory devices, and memory systems are disclosed. In one such method for sensing, a counting circuit generates a count output and a translated count output. ... Micron Technology Inc

12/10/15 / #20150355844

Remapping in a memory device

Methods for remapping and/or compacting data in memory devices, memory devices, and systems are disclosed. One such method of remapping and/or compacting data includes reducing a first quantity of write operations that are received from a host to a second quantity of write operations for programming to a page of a memory device that are within the specifications of partial page write operations for the memory device. ... Micron Technology Inc

12/10/15 / #20150355843

Write command overlap detection

The present disclosure includes methods and apparatuses that include write command overlap detection. A number of embodiments include receiving an incoming write command and comparing a logical address of the incoming write command to logical addresses of a number of write commands in a queue using a tree data structure, wherein a starting logical address and/or an ending logical address of the incoming write command and a starting logical address and/or an ending logical address of each of the number of write commands are associated with nodes in the tree data structure.. ... Micron Technology Inc

12/03/15 / #20150350114

Differential delay compensation

In one embodiment, a method comprises receiving a plurality of data frames representing at least one virtually concatenated data stream, storing the plurality of data frames in a memory; and recording, for each of a plurality of data frames, a physical write address that indicates a position in the memory and a virtual write address that includes a multiframe indicator and a byte number indicator.. . ... Micron Technology Inc

12/03/15 / #20150350082

Systems and methods for throttling packet transmission in a scalable memory system protocol

A method may include transmitting, via a processor, a plurality of packets to a receiving component, such that the plurality of packets corresponds to a plurality of data operations configured to access a memory component. The plurality of packets is stored in a buffer of the receiving component upon receipt. ... Micron Technology Inc

12/03/15 / #20150349255

Array of cross point memory cells and methods of forming an array of cross point memory cells

An array of cross point memory cells comprises spaced elevationally inner first lines, spaced elevationally outer second lines which cross the first lines, and a multi-resistive state region elevationally between the first and second lines where such cross. Individual of the multi-resistive state regions comprise elevationally outer multi-resistive state material and elevationally inner multi-resistive state material that are electrically coupled to one another. ... Micron Technology Inc

12/03/15 / #20150349249

Memory cells having a number of conductive diffusion barrier materials and manufacturing methods

Memory cells having a select device material located between a first electrode and a second electrode, a memory element located between the second electrode and a third electrode, and a number of conductive diffusion barrier materials located between a first portion of the memory element and a second portion of the memory element. Memory cells having a select device comprising a select device material located between a first electrode and a second electrode, a memory element located between the second electrode and a third electrode, and a number of conductive diffusion barrier materials located between a first portion of the select device and a second portion of the select device. ... Micron Technology Inc

12/03/15 / #20150349248

Phase change memory structures and methods

A method of forming a phase change material memory cell includes forming a number of memory structure regions, wherein the memory structure regions include a bottom electrode material and a sacrificial material, forming a number of insulator regions between the number of memory structure regions, forming a number of openings between the number of insulator regions and forming a contoured surface on the number of insulator regions by removing the sacrificial material and a portion of the number of insulator regions, forming a number of dielectric spacers on the number of insulator regions, forming a contoured opening between the number of insulator regions and exposing the bottom electrode material by removing a portion of the number of dielectric spacers, and forming a phase change material in the opening between the number of insulator regions.. . ... Micron Technology Inc

12/03/15 / #20150349204

Epitaxial devices

Epitaxial growth methods and devices are described that include a textured surface on a substrate. Geometry of the textured surface provides a reduced lattice mismatch between an epitaxial material and the substrate. ... Micron Technology Inc

12/03/15 / #20150349126

Field effect transistors having a fin

An embodiment of a transistor has a semiconductor fin, a dielectric over the semiconductor fin, a control gate over the dielectric, and source/drains in the semiconductor fin and having upper surfaces below an uppermost surface of the semiconductor fin. Another embodiment of a transistor has first and second semiconductor fins, a first source/drain region in the first semiconductor fin and extending downward from an uppermost surface of the first semiconductor fin, a second source/drain region in the second semiconductor fin and extending downward from an uppermost surface of the second semiconductor fin, a dielectric between the first and second semiconductor fins and adjacent to sidewalls of the first and second semiconductor fins, and a control gate over the dielectric and between the first and second semiconductor fins and extending to a level below upper surfaces of the first and second source/drain regions.. ... Micron Technology Inc

12/03/15 / #20150349082

Semiconductor structures comprising aluminum oxide

A semiconductor structure comprising aluminum oxide. The semiconductor structure comprises a dielectric material overlying a substrate. ... Micron Technology Inc

12/03/15 / #20150348991

Methods of fabricating integrated structures, and methods of forming vertically-stacked memory cells

Some embodiments include a method of fabricating integrated structures. A metal-containing material is formed over a stack of alternating first and second levels. ... Micron Technology Inc

12/03/15 / #20150348989

Memory array with a pair of memory-cell strings to a single conductive pillar

An array of memory cells has a conductive pillar and a plurality of first and second memory cells coupled in series by the conductive pillar. Each first memory cell has a respective portion of a first charge trap adjacent to the conductive pillar and a respective first control gate adjacent to the respective portion of the first charge trap. ... Micron Technology Inc

12/03/15 / #20150348956

Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods

Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. ... Micron Technology Inc

12/03/15 / #20150348954

Interconnect structure with redundant electrical connectors and associated systems and methods

Semiconductor die assemblies having interconnect structures with redundant electrical connectors are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die, a second semiconductor die, and an interconnect structure between the first and the second semiconductor dies. ... Micron Technology Inc

12/03/15 / #20150348790

Methods and apparatuses including memory cells with air gaps and other low dielectric constant materials

Various embodiments include methods of forming memory cells. In one embodiment, a first dielectric material and a second dielectric material are formed on a substrate. ... Micron Technology Inc

12/03/15 / #20150348785

Semiconductor device structures with doped elements and methods of formation

Methods of forming doped elements of semiconductor device structures include forming trenches having undercut portions separating stem portions of a substrate. The stem portions extend between a base portion of the substrate and overlying broader portions of the substrate material. ... Micron Technology Inc

12/03/15 / #20150348647

Via stack fault detection

A method and apparatus are disclosed. One such method includes selecting a die of a plurality of dies that are coupled together through a via stack. ... Micron Technology Inc

12/03/15 / #20150348643

Dynamic program window determination in a memory device

A memory device has an array of memory cells and a controller coupled to the array of memory cells. The controller is configured to determine a program window after a portion of a particular programing operation performed on the memory device is performed and before a subsequent portion of the particular programing operation performed on the memory device is performed. ... Micron Technology Inc

12/03/15 / #20150348619

Determining soft data

The present disclosure includes apparatuses and methods for determining soft data. A number of embodiments include determining soft data associated with a data state of a memory cell. ... Micron Technology Inc

12/03/15 / #20150348599

Providing power availability information to memory

The present disclosure includes apparatuses and methods for providing power availability information to memory. A number of embodiments include a memory and a controller. ... Micron Technology Inc

12/03/15 / #20150347315

Transactional memory

Subject matter disclosed herein relates to techniques to perform transactions using a memory device.. . ... Micron Technology Inc

12/03/15 / #20150347307

Cache architecture

The present disclosure includes apparatuses and methods for a cache architecture. An example apparatus that includes a cache architecture according to the present disclosure can include an array of memory cells configured to store multiple cache entries per page of memory cells; and sense circuitry configured to determine whether cache data corresponding to a request from a cache controller is located at a location in the array corresponding to the request, and return a response to the cache controller indicating whether cache data is located at the location in the array corresponding to the request.. ... Micron Technology Inc

12/03/15 / #20150347226

Systems and methods for packing data in a scalable memory system protocol

A memory device includes a memory component that store data and a processor. The processor may receive requests from a requesting component to perform a plurality of data operations, generate a plurality of packets associated with the plurality of data operations, and continuously transmit each of the plurality of packets until each of the plurality of packets are transmitted. ... Micron Technology Inc

12/03/15 / #20150347225

Systems and methods for improving efficiencies of a memory system

A memory device includes a memory component that store data. The memory device also includes a processor that receives a signal indicating that the memory component is coupled to the processor and retrieves information from the memory component. ... Micron Technology Inc

12/03/15 / #20150347048

Systems and methods for reordering packet transmissions in a scalable memory system protocol

A memory device includes a plurality of memory components that store data and a processor communicatively coupled to the plurality of memory components. The processor may receive a plurality of packets associated with a plurality of data operations, such that each of the plurality of packets includes a transaction window field indicating a type of memory component associated with a respective data operation of the respective packet. ... Micron Technology Inc

12/03/15 / #20150347038

Apparatuses and methods for performing wear leveling operations

Apparatuses and methods for commands to perform wear leveling operations are described herein. An example apparatus may include a memory configured to receive a wear leveling command and to perform a wear leveling operation responsive to the wear leveling command. ... Micron Technology Inc

12/03/15 / #20150347019

Systems and methods for segmenting data structures in a memory system

A memory device may include a memory component that stores data and a processor. The processor may map one or more banks or one or more virtual banks in the memory component based on one or more properties associated with the memory component and an expected random access rate for the memory component.. ... Micron Technology Inc

12/03/15 / #20150347015

Systems and methods for transmitting packets in a scalable memory system protocol

A memory device includes a memory component that store data and a processor. The processor may generate one or more data packets associated with the memory component. ... Micron Technology Inc

11/26/15 / #20150341033

Apparatus and methods for leakage current reduction in integrated circuits

This disclosure relates to leakage current reduction in integrated circuits (ics). In one aspect, an ic can include a digital logic circuit and a polarization circuit. ... Micron Technology Inc

11/26/15 / #20150341021

Apparatuses, methods, and circuits including a duty cycle adjustment circuit

Apparatuses, methods, and duty cycle correction circuits are described. An example apparatus includes a duty cycle correction (dcc) adjustment circuit configured to receive an input signal, and to adjust a duty cycle of the input signal to provide an output signal. ... Micron Technology Inc

11/26/15 / #20150341001

Semiconductor device including amplifier

Disclosed here is an apparatus that comprises an amplifier having first and second input nodes, first and second resistors, a first electrostatic discharge protection circuit coupled between the first input node and the first resistor, and a second electrostatic discharge protection circuit coupled between the second input node and the second resistor.. . ... Micron Technology Inc

11/26/15 / #20150340408

Phase change memory apparatuses and methods of forming such apparatuses

Phase change memory apparatuses include memory cells including phase change material, bit lines electrically coupled to aligned groups of at least some of the memory cells, and heating elements electrically coupled to the phase change material of the memory cells. The heating elements include vertical portions extending in a bit line direction. ... Micron Technology Inc

11/26/15 / #20150340372

Polar, chiral, and non-centro-symmetric ferroelectric materials, memory cells including such materials, and related devices and methods

A ferroelectric memory device includes a plurality of memory cells. Each of the memory cells comprises at least one electrode and a ferroelectric crystalline material disposed proximate the at least one electrode. ... Micron Technology Inc

11/26/15 / #20150340328

Methods of forming semiconductor device assemblies and interconnect structures, and related semiconductor device assemblies and interconnect structures

A method of forming a semiconductor device assembly comprises forming on a first substrate, at least one bond pad comprising a first nickel material over the first substrate, a first copper material on the first nickel material, and a solder-wetting material on the first copper material. On a second substrate is formed at least one conductive pillar comprising a second nickel material, a second copper material directly contacting the second nickel material, and a solder material directly contacting the second copper material. ... Micron Technology Inc

11/26/15 / #20150340320

Semiconductor devices including bulb-shaped trenches

A method of creating a trench having a portion of a bulb-shaped cross-section in silicon is disclosed. The method comprises forming at least one trench in silicon and forming a liner in the at least one trench. ... Micron Technology Inc

11/26/15 / #20150340311

Semiconductor device including plural semiconductor chips stacked on substrate

A semiconductor chip at least includes a row of first electrode pad group, which includes at least one first independent electrode pad and multiple first common electrode pads. The interval between the first independent electrode pad and an electrode pad adjacent thereto is defined as “first pitch”, and the interval between adjacent electrode pads making up the multiple first common electrode pads is defined as “second pitch”. ... Micron Technology Inc

11/26/15 / #20150340282

Conductive interconnect structures incorporating negative thermal expansion materials and associated systmes, devices, and methods

Semiconductor devices having interconnects incorporating negative expansion (nte) materials are disclosed herein. In one embodiment a semiconductor device includes a substrate having an opening that extends at least partially through the substrate. ... Micron Technology Inc

11/26/15 / #20150340209

Focus ring replacement method for a plasma reactor, and associated systems and methods

A focus ring replacement method for a plasma reactor, and associated systems and methods are disclosed herein. In one embodiment, a plasma processing system includes a plasma reactor and a wafer handler. ... Micron Technology Inc

11/26/15 / #20150340095

Interconnections for 3d memory

Apparatuses and methods for interconnections for 3d memory are provided. One example apparatus can include a stack of materials including a plurality of pairs of materials, each pair of materials including a conductive line formed over an insulation material. ... Micron Technology Inc

11/26/15 / #20150340086

Threshold voltage analysis

Apparatuses and methods for threshold voltage analysis are described. One or more methods for threshold voltage analysis include storing expected state indicators corresponding to a group of memory cells, applying a first sensing voltage to a selected access line to which the group of memory cells is coupled, sensing whether at least one of the memory cells of the group conducts responsive to the first sensing voltage, determining whether a discharge indicator for the at least one of the memory cells has changed responsive to application of the first sensing voltage, and determining that the first sensing voltage is the threshold voltage for a particular program state of the at least one of the memory cells.. ... Micron Technology Inc

11/26/15 / #20150340077

Apparatuses and methods for controlling refresh operations

An apparatus includes a first word line, a second word line and a control. The second word line is contiguous to the first word line. ... Micron Technology Inc

11/26/15 / #20150340072

Apparatuses and methods for timing provision of a command to input circuitry

Apparatuses and methods for providing a command to a data block are described. An example apparatus includes a command circuit configured to provide a command signal in an internal clock time domain based at least in part on a memory access command received in an external clock time domain. ... Micron Technology Inc

11/26/15 / #20150340069

Device having multiple channels with calibration circuit shared by multiple channels

An apparatus includes a first channel, a second channel and a calibration circuit. The first channel includes a first command control circuit. ... Micron Technology Inc

11/26/15 / #20150339064

Read cache memory

The present disclosure includes methods and apparatuses for read cache memory. One apparatus includes a read cache memory apparatus comprising a first dram array, a first and a second nand array, and a controller configured to manage movement of data between the dram array and the first nand array, and between the first nand array and the second nand array.. ... Micron Technology Inc

11/26/15 / #20150338863

Device having internal voltage generating circuit

A device includes an amplifying circuit having first and second input terminals and an output terminal, a ground terminal, a variable resistance circuit, and a resistance selecting circuit coupled in series to the variable resistance circuit between the output terminal and the ground terminal. The resistance selecting circuit includes a first node coupled to the second input terminal, a plurality of resistors coupled in series to each other and a plurality of gate circuits each coupled between the first node and one end of a corresponding one of the resistors.. ... Micron Technology Inc

11/19/15 / #20150333774

Stopping criteria for layered iterative error correction

The present disclosure includes apparatuses and methods related to stopping criteria for layered iterative error correction. A number of methods can include receiving a codeword with an error correction circuit, iteratively error correcting the codeword with the error correction circuit including parity checking the codeword on a layer-by-layer basis and updating the codeword after each layer. ... Micron Technology Inc

11/19/15 / #20150333257

Resistive memory elements, resistive memory cells, and resistive memory devices

A method of forming a resistive memory element comprises forming an oxide material over a first electrode. The oxide material is exposed to a plasma process to form a treated oxide material. ... Micron Technology Inc

11/19/15 / #20150333143

Memory arrays

Some embodiments include a memory array which has a stack of alternating first and second levels. Channel material pillars extend through the stack, and vertically-stacked memory cell strings are along the channel material pillars. ... Micron Technology Inc

11/19/15 / #20150333104

Resistive memory cell structures and methods

Resistive memory cell structures and methods are described herein. One or more memory cell structures comprise a first resistive memory cell comprising a first resistance variable material and a second resistive memory cell comprising a second resistance variable material that is different than the first resistance variable material.. ... Micron Technology Inc

11/19/15 / #20150333038

Semiconductor device including filling material provided in space defined by three semiconductor chips

A semiconductor device comprises a wiring substrate, first and second semiconductor chips mounted on the wiring substrate so as to be spaced apart from each other, a third semiconductor chip mounted on the first and second semiconductor chips, first and second adhesive layers that are provided between the first and second semiconductor chips and the wiring substrate so as to bond the first and second semiconductor chips to the wiring substrate, and a third adhesive layer that is provided between the third semiconductor chip and the first and second semiconductor chips so as to bond the third semiconductor chip to the first and second semiconductor chips, with its thickness being made thicker than that of the first and second adhesive layers, a sealing layer covering the wiring substrate, and a filling layer that is provided between the first and second semiconductor chips and is different from the sealing layer.. . ... Micron Technology Inc

11/19/15 / #20150333026

Interconnect structure with improved conductive properties and associated systems and methods

Interconnect structures with improved conductive properties are disclosed herein. In one embodiment, an interconnect structure can include a first conductive member coupled to a first semiconductor die and a second conductive member coupled to second semiconductor die. ... Micron Technology Inc

11/19/15 / #20150333014

Semiconductor devices and methods for backside photo alignment

Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for aligning an electronic feature to a through-substrate via includes forming a self-aligned alignment feature having a wall around at least a portion of the tsv and aligning a photolithography tool to the self-aligned alignment feature. ... Micron Technology Inc

11/19/15 / #20150333001

Multiple data line memory and methods

Apparatuses and methods are disclosed, including an apparatus with rows of vertical strings of memory cells coupled to a common source and multiple data lines associated with each row of vertical strings. Each data line associated with a row is coupled to at least one of the vertical strings in the row. ... Micron Technology Inc

11/19/15 / #20150332986

Semiconductor device including semiconductor chip covered with sealing resin

A semiconductor device includes a wiring substrate, a sealing resin layer formed on the wiring substrate out of a filler-containing resin and having a one-sided filler content ratio, and at least one semiconductor chip mounted on the wiring substrate such that the semiconductor chip is located offset to be closer to an area where the filler content ratio is relatively low in the sealing resin layer and is sealed in its offset location in the sealing resin layer.. . ... Micron Technology Inc

11/19/15 / #20150332913

Semiconductor processing methods, and methods for forming silicon dioxide

Some embodiments include methods for semiconductor processing. A semiconductor substrate may be placed within a reaction chamber. ... Micron Technology Inc

11/19/15 / #20150332762

Memory array plane select

Memory arrays and methods of forming the same are provided. An example memory array can include at least one plane having a plurality of memory cells arranged in a matrix and a plurality of plane selection devices. ... Micron Technology Inc

11/19/15 / #20150332740

Apparatuses and methods for accessing memory including sense amplifier sections and coupled sources

Apparatuses and methods for accessing memory are described. An example method includes accessing memory cells of a memory section, and sharing a source of an inactive sense amplifier section with an active sense amplifier section coupled to the memory cells of the memory section during a memory access operation to the memory section coupled to the active sense amplifier section. ... Micron Technology Inc

11/19/15 / #20150331811

Secure compact flash

Methods and apparatus are provided, such as a memory card with a processor and nonvolatile memory coupled thereto. The nonvolatile memory has a secure area configured to store a user password and a serial number in encrypted form. ... Micron Technology Inc

11/19/15 / #20150331792

Memory devices with register banks storing actuators that cause operations to be performed on a memory core

A bus controller has a displacer, an arithmetic logic unit coupled to the displacer, and a replacer selectively coupled to the displacer and the arithmetic logic unit.. . ... Micron Technology Inc

11/19/15 / #20150330845

Semiconductor device including sensor

Disclosed here is an apparatus that comprises a sensor including a plurality of sense nodes, a plurality of first latch circuits including a plurality of first input nodes and a plurality of first output nodes, respectively, the plurality of first input nodes coupled to the plurality of sense nodes, respectively, a plurality of second latch circuits including a plurality of second input nodes and a plurality of second output nodes, respectively, the plurality of second input nodes coupled to the plurality of first output nodes, respectively, and a selector including a plurality of third input nodes coupled respectively to the plurality of first output nodes, a plurality of fourth input nodes coupled respectively to the plurality of second output nodes and a plurality of third output nodes.. . ... Micron Technology Inc

11/12/15 / #20150326213

Apparatuses and methods for timing domain crossing

Apparatuses and methods for a timing domain transfer circuit are disclosed. Disclosed embodiments may be configured to receive an event from one timing domain, output the event to another timing domain, and further configured to mark the event as transferred. ... Micron Technology Inc

11/12/15 / #20150325791

Methods for forming arrays of small, closely spaced features

Methods of forming arrays of small, densely spaced holes or pillars for use in integrated circuits are disclosed. Various pattern transfer and etching steps can be used, in combination with pitch-reduction techniques, to create densely-packed features. ... Micron Technology Inc

11/12/15 / #20150325645

Method providing an epitaxial growth having a reduction in defects and resulting structure

Disclosed are methods and resulting structures which provide an opening for epitaxial growth, the opening having an associated projection for reducing the size of the contact area on a substrate at which growth begins. During growth, the epitaxial material grows vertically from the contact area and laterally over the projection. ... Micron Technology Inc

11/12/15 / #20150325627

Memory cells, memory arrays, and methods of forming memory cells and arrays

Some embodiments include methods of forming memory cells. Heater structures are formed over an array of electrical nodes, and phase change material is formed across the heater structures. ... Micron Technology Inc

11/12/15 / #20150325589

Semiconductor constructions, methods of forming vertical memory strings, and methods of forming vertically-stacked structures

Some embodiments include methods of forming vertical memory strings. A trench is formed to extend through a stack of alternating electrically conductive levels and electrically insulative levels. ... Micron Technology Inc

11/12/15 / #20150325554

Packaged integrated circuit devices with through-body conductive vias, and methods of making same

A device is disclosed which includes at least one integrated circuit die, at least a portion of which is positioned in a body of encapsulant material, and at least one conductive via extending through the body of encapsulant material.. . ... Micron Technology Inc

11/12/15 / #20150325459

Pitch multiplication spacers and methods of forming the same

Spacers in a pitch multiplication process are formed without performing a spacer etch. Rather, the mandrels are formed over a substrate and then the sides of the mandrels are reacted, e.g., in an oxidization, nitridation, or silicidation step, to form a material that can be selectively removed relative to the unreacted portions of the mandrel. ... Micron Technology Inc

11/12/15 / #20150325309

Memory apparatus, systems, and methods

Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed aggressor memory cells reduces the threshold voltage uncertainty in a flash memory system. ... Micron Technology Inc

11/12/15 / #20150325295

Devices and methods to program a memory cell

Subject matter disclosed herein relates to memory devices and, more particularly, to programming a memory cell.. . ... Micron Technology Inc

11/12/15 / #20150325293

Program-disturb decoupling for adjacent wordlines of a memory device

Subject matter disclosed herein relates to memory operations regarding programming bits into a memory array.. . ... Micron Technology Inc

11/12/15 / #20150325289

Apparatuses and methods for bi-directional access of cross-point arrays

The disclosed technology generally relates to apparatuses and methods of operating the same, and more particularly to cross point memory arrays and methods of accessing memory cells in a cross point memory array. In one aspect, an apparatus comprises a memory array. ... Micron Technology Inc

11/12/15 / #20150325288

Apparatuses and methods for performing multiple memory operations

The disclosed technology relates to a memory device configured to perform multiple access operations in response to a single command received through a memory controller and a method of performing the multiple access operations. In one aspect, the memory device includes a memory array comprising a plurality of memory cells and a memory controller. ... Micron Technology Inc

11/12/15 / #20150325277

Channel skewing

Methods and systems for channel skewing are described. One or more methods for channel skewing includes providing a number of groups of data signals to a memory component, each of the number of groups corresponding to a respective channel, and adjusting a phase of a group of data signals corresponding to at least one of the number of channels such that the group of data signals are skewed with respect to a group of data signals corresponding to at least one of the other respective channels.. ... Micron Technology Inc

11/12/15 / #20150324575

Intelligent controller system and method for smart card memory modules

A storage device contains a smart-card device and a memory device, both of which are accessed though a controller. The storage device may be used in the same manner as a conventional smart-card device, or it may be used to store a relatively large amount of data in various partitions corresponding to the protection level of the data stored therein. ... Micron Technology Inc

11/12/15 / #20150324319

Interconnect systems and methods using hybrid memory cube links

System on a chip (soc) devices include two packetized memory busses for conveying local memory packets and system interconnect packets. In an in-situ configuration of a data processing system two or more socs are coupled with one or more hybrid memory cubes (hmcs). ... Micron Technology Inc

11/12/15 / #20150324285

Virtualized physical addresses for reconfigurable memory systems

Systems and methods define a memory system using an abstracted memory protocol that enables virtual to physical mapping of memory address requests at an abstracted memory module. A memory abstraction unit abstracts timing and naming of memory requests from one or more clients to timing and naming at one or more memory devices. ... Micron Technology Inc

11/12/15 / #20150324261

Data encoding using spare channels in a memory system

Implementations of encoding techniques are disclosed. The encoding technique, such as a data bus inversion (dbi) technique, is implementable in a vertically-stacked memory module, but is not limited thereto. ... Micron Technology Inc

11/12/15 / #20150324252

Codewords that span pages of memory

The present disclosure includes apparatuses and methods for codewords that span pages of memory. A number of methods include writing a first portion of a primary codeword to a first page in a first block of memory and writing a second portion of the primary codeword to a second page in a second block of memory. ... Micron Technology Inc

11/12/15 / #20150324142

Memory device, electronic system, and methods associated with modifying data and a file of a memory device

A memory device, system and method of editing a file in a non-volatile memory device is described. The memory device includes a controller and a memory array configured to copy an existing first file into a second file during editing and to maintain the first file while applying edits to the second file. ... Micron Technology Inc

11/12/15 / #20150324129

Results generation for state machine engines

A state machine engine includes a storage element, such as a (e.g., match) results memory. The storage element is configured to receive a result of an analysis of data. ... Micron Technology Inc

11/12/15 / #20150323971

Semiconductor memory device including output buffer

An apparatus includes an external terminal, an output circuit having an impedance corresponding to a code signal, and a calibration circuit configured to produce the code signal responsive to a comparison of a voltage at the external terminal with a reference voltage, the comparison performed by a first cycle period in a first mode and by a second cycle which is longer than the first cycle period in a second mode.. . ... Micron Technology Inc

11/12/15 / #20150321447

Substrates and methods of forming a pattern on a substrate

Substrates and methods of forming a pattern on a substrate. The pattern includes a repeating pattern region and a pattern-interrupting region adjacent to the repeating pattern region. ... Micron Technology Inc

11/05/15 / #20150319860

Electronic device assemblies including conductive vias having two or more conductive elements

Electronic devices include a substrate with first and second pairs of conductive traces extending in or on the substrate. A first conductive interconnecting member extends through a hole in the substrate and communicates electrically with a first trace of each of the first and second pairs, while a second conductive interconnecting member extends through the hole and communicates electrically with the second trace of each of the first and second pairs. ... Micron Technology Inc

11/05/15 / #20150318470

Memory cells and methods of forming memory cells

Some embodiments include methods of forming memory cells. Programmable material may be formed directly adjacent another material. ... Micron Technology Inc

11/05/15 / #20150318468

Phase change memory stack with treated sidewalls

Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming the memory stack out of a plurality of elements. ... Micron Technology Inc

11/05/15 / #20150318467

Phase change memory stack with treated sidewalls

Memory devices and methods for fabricating memory devices have been disclosed. One such memory device includes a first electrode material formed on a word line material. ... Micron Technology Inc

11/05/15 / #20150318388

Devices, systems, and methods related to removing parasitic conduction in semiconductor devices

Semiconductor devices and methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a stack of semiconductor materials from an epitaxial substrate, where the stack of semiconductor materials defines a heterojunction, and where the stack of semiconductor materials and the epitaxial substrate further define a bulk region that includes a portion of the semiconductor stack adjacent the epitaxial substrate. ... Micron Technology Inc

11/05/15 / #20150318369

Conductive nanoparticles

Isolated conductive nanoparticles on a dielectric layer and methods of fabricating such isolated conductive nanoparticles provide charge storage units in electronic structures for use in a wide range of electronic devices and systems. The isolated conductive nanoparticles may be used as a floating gate in a flash memory. ... Micron Technology Inc

11/05/15 / #20150318331

Method, system and device for recessed contact in memory array

Embodiments disclosed herein may relate to forming a contact region for an interconnect between a selector transistor and a word-line electrode in a memory device.. . ... Micron Technology Inc

11/05/15 / #20150318203

Stair step formation using at least two masks

Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. ... Micron Technology Inc

11/05/15 / #20150318047

Memory devices configured to apply different weights to different strings of memory cells coupled to a data line and methods

Memory devices and methods are disclosed. One such method compares input data to stored data in a memory device and includes applying a first weight factor to a first string of memory cells coupled to a data line, where a first bit of the stored data is stored in the first string of memory cells; applying a second weight factor to a second string of memory cells coupled to the data line, where a second bit of the stored data is stored in the second string of memory cells; comparing a first bit of input data to the first bit of the stored data while the first weight factor is applied to the first string of memory cells; and comparing a second bit of the input data to the second bit of the stored data while the second weight factor is applied to the second string of memory cells.. ... Micron Technology Inc

11/05/15 / #20150318038

Phase change memory stack with treated sidewalls

Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming a memory stack out of a plurality of elements. ... Micron Technology Inc

11/05/15 / #20150318033

Memory devices having a read function of data stored in a plurality of reference cells

A semiconductor device is provided with normal memory cells constituted so as to store user data, reference memory cells constituted so as to generate a reference signal for reading out the normal memory cells, and a control circuit that carries out a defect detecting operation for detecting whether or not the reference memory cell and data stored in the reference memory cell are coincident with expected values on the stored data read out from the reference memory cells. Moreover, it is also provided with a control circuit for executing a defect correcting operation for correcting data to be stored in the reference memory cells that are detected as defective. ... Micron Technology Inc

11/05/15 / #20150318032

Apparatuses and methods for controlling a clock signal provided to a clock tree

Apparatuses, sense circuits, and methods for controlling a clock signal to a clock tree is described. An example apparatus includes a consecutive write command detection circuit configured to detect whether a next write command is received within a consecutive write command period of a current write command responsive to the current write command provided at an output of the write command register. ... Micron Technology Inc

11/05/15 / #20150317080

Apparatus including memory system controllers and related methods

Memory system controllers can include non-volatile memory control circuitry including a plurality of channel control circuits. Each of the plurality of channel control circuits can be configured to be coupled to a respective number of logical units (luns). ... Micron Technology Inc

11/05/15 / #20150316969

Apparatuses supporting multiple interface types and methods of operating the same

Apparatuses supporting multiple interface types and methods operating the same are described. One such method can include providing, to a memory device, a first input/output (i/o) supply voltage corresponding to a first interface type and subsequently determining whether the memory device supports a second interface type having a second i/o supply voltage corresponding thereto. ... Micron Technology Inc

10/29/15 / #20150311437

Methods of forming a memory cell material, and related methods of forming a semiconductor device structure, memory cell materials, and semiconductor device structures

A method of forming a memory cell material comprises forming a first portion of a dielectric material over a substrate by atomic layer deposition. Discrete conductive particles are formed on the first portion of the dielectric material by atomic layer deposition. ... Micron Technology Inc

10/29/15 / #20150311436

Switching device structures and methods

Switching device structures and methods are described herein. A switching device can include a vertical stack comprising a material formed between a first and a second electrode. ... Micron Technology Inc

10/29/15 / #20150311349

Ferroelectric field effect transistors, pluralities of ferroelectric field effect transistors arrayed in row lines and column lines, and methods of forming a plurality of ferroelectric field effect transistors

A ferroelectric field effect transistor comprises a semiconductive channel comprising opposing sidewalls and an elevationally outermost top. A source/drain region is at opposite ends of the channel. ... Micron Technology Inc

10/29/15 / #20150311254

Memory cells having a common gate terminal

Arrays of memory cells having a common gate terminal and methods of operating and forming the same are described herein. As an example, an array of memory cells may include a group of memory cells each having a resistive storage element coupled to a select device. ... Micron Technology Inc

10/29/15 / #20150311217

Ferroelectric memory and methods of forming the same

Ferroelectric memory and methods of forming the same are provided. An example memory cell can include a buried recessed access device (brad) formed in a substrate and a ferroelectric capacitor formed on the brad.. ... Micron Technology Inc

10/29/15 / #20150311186

Stacked semiconductor die assemblies with die support members and associated systems and methods

Stacked semiconductor die assemblies with die support members and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first semiconductor die attached to the package substrate, and a support member attached to the package substrate. ... Micron Technology Inc

10/29/15 / #20150311185

Stacked semiconductor die assemblies with support members and associated systems and methods

Stacked semiconductor die assemblies with support members and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first semiconductor die attached to the package substrate, and a plurality of support members also attached to the package substrate. ... Micron Technology Inc

10/29/15 / #20150311115

Methods of forming memory arrays

Some embodiments include methods of forming memory arrays. An assembly is formed which has an upper level over a lower level. ... Micron Technology Inc

10/29/15 / #20150310992

Structure comprising multiple capacitors and methods for forming the structure

Capacitors, apparatus including a capacitor, and methods for forming a capacitor are provided. One such capacitor may include a first conductor a second conductor above the first conductor, and a dielectric between the first conductor and the second conductor. ... Micron Technology Inc

10/29/15 / #20150310926

Semiconductor device including fuse circuit

Disclosed here is a semiconductor device that comprises a plurality of input nodes configured to be supplied with input signals, a decoder coupled to the input nodes, the decoder configured to decode the input signals and output decoded signals, and a plurality of fuse circuits provided correspondingly with the decoded signals and configured to be programmed responsive to the decoded signals, respectively.. . ... Micron Technology Inc

10/29/15 / #20150310911

Determining whether a memory cell state is in a valley between adjacent data states

The present disclosure includes apparatuses and methods related to memory cell state in a valley between adjacent data states. A number of methods can include determining whether a state of a memory cell is in a valley between adjacent distributions of states associated with respective data states. ... Micron Technology Inc

10/29/15 / #20150310907

Semiconductor memory device including power supply line

A semiconductor apparatus disclosed in this disclosure includes a first channel formed in a first area and including a first power supply pad, a first clock pad, a first command address pad, a first data input/output pad and a first memory cell array; a second channel formed in a second area and including a second power supply pad, a second clock pad, a second command address pad, a second data input/output pad and a second memory cell array, the first and second channels being independently controllable from each other; and mesh structure lines straddling the first area and second area and connected to the first and second power supply pads.. . ... Micron Technology Inc

10/29/15 / #20150310905

Field effect transistor constructions and methods of programming field effect transistors to one of at least three different programmed states

A field effect transistor construction includes a semiconductive channel core. A source/drain region is at opposite ends of the channel core. ... Micron Technology Inc

10/29/15 / #20150309931

Persistent memory for processor main memory

Subject matter disclosed herein relates to a system of one or more processors that includes persistent memory.. . ... Micron Technology Inc

10/29/15 / #20150309868

Method and apparatus to perform concurrent read and write memory operations

Subject matter disclosed herein relates to read and write processes of a memory device. During a write process to a particular partition in a memory array, a response to a read request of contents of the particular partition may be delayed. ... Micron Technology Inc

10/29/15 / #20150309741

Apparatuses and methods for memory management

Some embodiments include apparatuses and methods to select a target memory portion in a first memory location to store information. One such method can conditionally store the information in a second memory location when the information is stored in the target memory portion. ... Micron Technology Inc

10/29/15 / #20150307778

Sulfur dioxide etch chemistries

Methods of forming a semiconductor device structure and sulfur dioxide etch chemistries. The methods and chemistries, which may be plasma chemistries, include use of sulfur dioxide and a halogen-based compound to form a trimmed pattern of a patterning material, such as a resist material, at a critical dimension with low feature width roughness, with low space width roughness, without excessive height loss, and without substantial irregularities in the elevational profile, as compared to trimmed features formed using conventional chemistries and trimming methods.. ... Micron Technology Inc

10/22/15 / #20150303899

Apparatuses and methods for duty cycle adjustments

Apparatuses and methods have been disclosed. One such apparatus includes a plurality of gates coupled together in series. ... Micron Technology Inc

10/22/15 / #20150303374

Spin transfer torque memory cells

Spin transfer torque memory cells and methods of forming the same are described herein. As an example, spin transfer torque memory cells may include an amorphous material, a storage material formed on the amorphous material, wherein the storage material is substantially boron free, an interfacial perpendicular magnetic anisotropy material formed on the storage material, a reference material formed on the interfacial perpendicular magnetic anisotropy material, wherein the reference material is substantially boron free, a buffer material formed on the reference material and a pinning material formed on the buffer material.. ... Micron Technology Inc

10/22/15 / #20150303372

Memory cells, methods of fabrication, and semiconductor devices

A magnetic cell includes a magnetic tunnel junction that comprises magnetic and nonmagnetic materials exhibiting hexagonal crystal structures. The hexagonal crystal structure is enabled by a seed material, proximate to the magnetic tunnel junction, that exhibits a hexagonal crystal structure matching the hexagonal crystal structure of the adjoining magnetic material of the magnetic tunnel junction. ... Micron Technology Inc

10/22/15 / #20150303255

Semiconductor device structures including a rectilinear array of openings

A method of forming an array of openings in a substrate. The method comprises forming a template structure comprising a plurality of parallel features and a plurality of additional parallel features perpendicularly intersecting the plurality of additional parallel features of the plurality over a substrate to define wells, each of the plurality of parallel features having substantially the same dimensions and relative spacing as each of the plurality of additional parallel features. ... Micron Technology Inc

10/22/15 / #20150303250

Semiconductor device having shallow trench isolation and method of forming the same

A device includes a first dielectric film formed in a first trench along a first bottom surface portion and a first side surface portion with leaving a first gap in the first trench and a second dielectric film formed in a second trench along a second bottom surface portion and a second side surface portion with leaving a second gap in the second trench. The first bottom surface portion is covered approximately conformably with a first part of the first dielectric film, the first side surface portion is covered approximately conformably with a second part of the first dielectric film, and the first part is larger in thickness than the second part. ... Micron Technology Inc

10/22/15 / #20150303239

Memory device having self-aligned cell structure

Some embodiments include apparatus and methods having a memory device with diodes coupled to memory elements. Each diode may be formed in a recess of the memory device. ... Micron Technology Inc

10/22/15 / #20150303206

Methods of forming ferroelectric capacitors

A method of forming a ferroelectric capacitor includes forming inner conductive capacitor electrode material over a substrate. After forming the inner electrode material, an outermost region of the inner electrode material is treated to increase carbon content in the outermost region from what it was prior to the treating. ... Micron Technology Inc

10/22/15 / #20150303176

Multi-chip modules including stacked semiconductor dice

An assembly method that includes providing a first semiconductor device and positioning a second semiconductor device at least partially over the first semiconductor device is disclosed. Spacers space the active surface of the first semiconductor device substantially a predetermined distance apart from the back side of the second semiconductor device. ... Micron Technology Inc

10/22/15 / #20150303147

Semiconductor constructions, methods of forming conductive structures and methods of forming dram cells

Some embodiments include methods of forming conductive structures. An electrically conductive material may be deposited with a first deposition method. ... Micron Technology Inc

10/22/15 / #20150303110

Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods

Microfeature workpieces having interconnects and conductive backplanes and associated systems and methods are disclosed herein. One such device includes a semiconductor substrate having integrated circuitry and terminals electrically coupled to the integrated circuitry. ... Micron Technology Inc

10/22/15 / #20150303100

Semiconductor constructions and methods of forming electrically conductive contacts

Some embodiments include methods of forming electrically conductive contacts. An opening is formed through an insulative material to a conductive structure. ... Micron Technology Inc

10/22/15 / #20150303095

Semiconductor with through-substrate interconnect

Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. ... Micron Technology Inc

10/22/15 / #20150302931

Level compensation in multilevel memory

Some embodiments include apparatuses and methods having a compensation unit to provide a compensation value based at least in part on a threshold voltage value of a memory cell. At least one of such embodiments includes a controller to select a code during an operation of retrieving information from the memory cell to represent a value of information stored in the memory cell. ... Micron Technology Inc

10/22/15 / #20150302924

Refresh architecture and algorithm for non-volatile memories

Methods and systems to refresh a nonvolatile memory device, such as a phase change memory. In an embodiment, as a function of system state, a memory device performs either a first refresh of memory cells using a margined read reference level or a second refresh of error-corrected memory cells using a non-margined read reference level.. ... Micron Technology Inc

10/22/15 / #20150302907

Apparatuses and methods for implementing masked write commands

Apparatuses and methods for implementing masked write commands are disclosed herein. An example apparatus may include a memory bank, a local buffer circuit, and an address control circuit. ... Micron Technology Inc

10/22/15 / #20150302898

Techniques for providing a direct injection semiconductor memory device

Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a first region coupled to a source line, a second region coupled to a bit line. ... Micron Technology Inc

10/22/15 / #20150301937

Wear leveling for a memory device

Methods of operating a memory device are useful in managing wear leveling operations. Such methods include receiving an instruction from a host device in communication with the memory device, wherein the instruction comprises a command portion indicating a desire to identify portions of the memory device to be excluded from wear leveling operations and an argument portion comprising information identifying a particular group of one or more blocks of the plurality of blocks; storing the information identifying the particular group of one or more blocks to a non-volatile memory of the memory device as a portion of information identifying blocks to be excluded from wear leveling operations; and performing one or more wear leveling operations only on a subset of the plurality of blocks responsive to the information identifying blocks to be excluded from wear leveling operation. ... Micron Technology Inc

10/22/15 / #20150301746

State change in systems having devices coupled in a chained configuration

The present disclosure includes methods, devices, and systems for state change in systems having devices coupled in a chained configuration. A number of embodiments include a host and a number of devices coupled to the host in a chained configuration. ... Micron Technology Inc

10/22/15 / #20150301283

Method and apparatus providing compensation for wavelength drift in photonic structures

A method and apparatus are described which provide for wavelength drift compensation in a photonic waveguide by application of an electric field to a waveguide having a strained waveguide core.. . ... Micron Technology Inc

10/01/15 / #20150280912

System and method for updating read-only memory in smart card memory modules

A storage device contains a smart-card device and a memory device, both connected to a controller. The storage device may be used in the same manner as a conventional smart-card device, or it may be used to store a relatively large amount of data in various partitions. ... Micron Technology Inc

10/01/15 / #20150280123

Forming resistive random access memories together with fuse arrays

A resistive random access memory array may be formed on the same substrate with a fuse array. The random access memory and the fuse array may use the same active material. ... Micron Technology Inc

10/01/15 / #20150280118

Replacement materials processes for forming cross point memory

Methods of forming memory cells comprising phase change and/or chalcogenide materials are disclosed. In one aspect, the method includes providing a lower line stack extending in a first direction, the lower line stack comprising a sacrificial line over a lower conductive line. ... Micron Technology Inc

10/01/15 / #20150280117

Memory arrays and methods of forming memory arrays

Some embodiments include memory arrays having a plurality of memory cells vertically between bitlines and wordlines. The memory cells contain phase change material. ... Micron Technology Inc

10/01/15 / #20150280116

Semiconductor structures and devices including conductive lines and peripheral conductive pads

Semiconductor devices and structures, such as phase change memory devices, include peripheral conductive pads coupled to peripheral conductive contacts in a peripheral region. An array region may include memory cells coupled to conductive lines. ... Micron Technology Inc

10/01/15 / #20150279906

Memory arrays

Some embodiments include a memory array which has a first series of access/sense lines extending along a first direction, and a second series of access/sense lines over the first series of access/sense lines and extending along a second direction which crosses the first direction. Memory cells are vertically between the first and second series of access/sense lines. ... Micron Technology Inc

10/01/15 / #20150279845

Semiconductor memory devices including support film supporting capacitor electrodes

The semiconductor storage device includes a lower electrode that are vertically extended from a semiconductor substrate, a beam including a first portion extending in a horizontal direction to support the lower electrode and a second portion that is vertically extended along the exterior wall of the electrode from the first portion.. . ... Micron Technology Inc

10/01/15 / #20150279828

Stacked semiconductor die assemblies with improved thermal performance and associated systems and methods

Stacked semiconductor die assemblies with improved thermal performance and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a stack of semiconductor dies and a thermally conductive casing at least partially enclosing the stack of semiconductor dies within an enclosure. ... Micron Technology Inc

10/01/15 / #20150279820

Semiconductor device including semiconductor chips mounted over both surfaces of substrate

A semiconductor chip 10 flip-chip mounted on a first surface 32 of a wiring substrate 30, a semiconductor chip 20 flip-chip mounted on a second surface 33 of the wiring substrate 30, a sealing resin 71 covering the semiconductor chip 10, a sealing resin 72 covering the semiconductor chip 20, a plurality of conductive posts provided to penetrate through the sealing resin 72, and a plurality of solder balls mounted on second ends of the plurality of conductive posts exposed from the sealing resin 72 are provided; and the mounting directions of the semiconductor chips 10 and 20 are mutually different by 90°. Both of the planar shapes of the semiconductor chips 10 and 20 are rectangular shapes, the semiconductor chip 10 is mounted so that the long sides thereof are parallel to the long sides of the wiring substrate 30, and the semiconductor chip 20 is mounted so that the long sides thereof are perpendicular to the long sides of the wiring substrate 30.. ... Micron Technology Inc

10/01/15 / #20150279694

Dram cells and methods of forming silicon dioxide

Some embodiments include methods of forming silicon dioxide in which silicon dioxide is formed across silicon utilizing a first treatment temperature of no greater than about 1000° c., and in which an interface between the silicon dioxide and the silicon is annealed utilizing a second treatment temperature which is at least about 1050° c. Some embodiments include methods of forming transistors in which a trench is formed to extend into monocrystalline silicon. ... Micron Technology Inc

10/01/15 / #20150279466

Apparatuses and methods for comparing data patterns in memory

The present disclosure includes apparatuses and methods related to comparing data patterns in memory. An example method can include comparing a number of data patterns stored in a memory array to a target data pattern. ... Micron Technology Inc

10/01/15 / #20150279460

Cross-point memory compensation

The apparatuses and methods described herein may operate to measure a voltage difference between a selected access line and a selected sense line associated with a selected cell of a plurality of memory cells of a memory array. The voltage difference may be compared with a reference voltage specified for a memory operation. ... Micron Technology Inc

10/01/15 / #20150279459

Configurable reference current generation for non volatile memory

This disclosure relates to generating a reference current for a memory device. In one aspect, a non-volatile memory device, such as a phase change memory device, can determine a value of a data digit, such as a bit, stored in a non-volatile memory cell based at least partly on the reference current. ... Micron Technology Inc

10/01/15 / #20150279432

Memory devices with local and global devices at substantially the same level above stacked tiers of memory cells and methods

In an embodiment, a memory device includes a stack of tiers of memory cells, a tier of local devices at a level above the stack of tiers of memory cells, and a tier of global devices at substantially a same level as the tier of local devices. A local device may provide selective access to a data line. ... Micron Technology Inc

10/01/15 / #20150279431

Stacked semiconductor die assemblies with partitioned logic and associated systems and methods

Stacked semiconductor die assemblies having memory dies stacked between partitioned logic dies and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a first logic die, a second logic die, and a thermally conductive casing defining an enclosure. ... Micron Technology Inc

10/01/15 / #20150277907

Instruction insertion in state machine engines

State machine engines are disclosed, including those having an instruction insertion register. One such instruction insertion register may provide an initialization instruction, such as to prepare a state machine engine for data analysis. ... Micron Technology Inc

09/24/15 / #20150270855

Determining soft data using a classification code

Apparatuses and methods for determining soft data using a classification code are provided. One example apparatus can include a classification code (cc) decoder and an outer code decoder coupled to the cc decoder. ... Micron Technology Inc

09/24/15 / #20150270851

Low density parity check circuit

Generally discussed herein are low density parity check (ldpc) circuit layouts. An example ldpc circuit can include combinational logic and a plurality of memory units. ... Micron Technology Inc

09/24/15 / #20150270480

Memory cells having a self-aligning polarizer

Spin torque transfer memory cells and methods of forming the same are described herein. As an example, spin torque transfer memory cells may include a self-aligning polarizer, a pinned polarizer, and a storage material formed between the self-aligning polarizer and the pinned polarizer.. ... Micron Technology Inc

09/24/15 / #20150270015

Memory mapping

The present disclosure includes apparatuses, electronic device readable media, and methods for memory mapping. One example method can include testing a memory identifier against an indication corresponding to a set of mapped memory identifiers, and determining a memory location corresponding to the memory identifier responsive to testing.. ... Micron Technology Inc

09/24/15 / #20150269999

Apparatuses and methods for providing set and reset voltages at the same time

Apparatuses and methods are described, such as those involving driver circuits that are configured to provide reset and set voltages to different variable state material memory cells in an array at the same time. Additional apparatuses, and methods are described.. ... Micron Technology Inc

09/24/15 / #20150269986

Device having multiple switching buffers for data paths controlled based on io configuration modes

A device includes a first data terminal, a second data terminal, a first switching buffer coupled between a data node and the first data terminal and a second switching buffer coupled between the data node and the second data terminal. The first switching buffer and the second switching buffer are arranged such that a distance between the first switching buffer and the second data terminal is shorter than a distance between the second switching buffer and the second data terminal and that a distance between the first switching buffer and the first data terminal is shorter than a distance between the second switching buffer and the first data terminal.. ... Micron Technology Inc

09/24/15 / #20150268888

Recycled version number values in flash memory

Various embodiments include methods, apparatus, and systems for assigning a plurality of version number values to instances of a logical entity of a memory device. Each version number value of the plurality version number values may be separately assigned to one of the instances of the logical entity. ... Micron Technology Inc

09/24/15 / #20150268875

Apparatuses and methods having memory tier structure

Some embodiments include apparatuses and methods having a memory unit and a controller device. The controller device can be configured to receive a request from a host device and access a data structure in the memory unit to determine whether information associated with the request is in the data structure. ... Micron Technology Inc

09/17/15 / #20150263281

Phase change memory cells including nitrogenated carbon materials, and related methods

A phase change memory cell comprising a first chalcogenide compound on a first electrode, a first nitrogenated carbon material directly on the first chalcogenide compound, a second chalcogenide compound directly on the first nitrogenated carbon material, and a second nitrogenated carbon material directly on the second chalcogenide compound and directly on a second electrode. Other phase change memory cells are described. ... Micron Technology Inc

09/17/15 / #20150263269

Memory cells and methods of fabrication

Memory cells are disclosed. Magnetic regions within the memory cells include an alternating structure of magnetic sub-regions and coupler sub-regions. ... Micron Technology Inc

09/17/15 / #20150262867

Forming array contacts in semiconductor memories

Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. ... Micron Technology Inc

09/17/15 / #20150262717

Methods, apparatus, and systems to repair memory

Methods, apparatus and systems pertain to performing read, write functions in a memory which is coupled to a repair controller. One such repair controller could receive a row address and a column address associated with the memory and store a first plurality of tag fields indicating a type of row/column repair to be performed for at least a portion of a row/column of memory cells, and a second plurality of tag fields to indicate a location of memory cells used to perform the row/column repair.. ... Micron Technology Inc

09/17/15 / #20150262716

Methods of operating memory involving identifiers indicating repair of a memory cell

Method of operating memory including storing and/or using an identifier indicating repair of a memory cell.. . ... Micron Technology Inc

09/17/15 / #20150262695

Methods, devices, and systems for data sensing

The present disclosure includes methods and devices for data sensing. One such method includes performing a number of successive sense operations on a number of memory cells using a number of different sensing voltages, determining a quantity of the number memory cells that change states between consecutive sense operations of the number of successive sense operations, and determining, based at least partially on the determined quantity of the number of memory cells that change states between consecutive sense operations, whether to output hard data corresponding to one of the number of successive sense operations.. ... Micron Technology Inc

09/17/15 / #20150262673

Apparatuses and methods for coupling load current to a common source

Apparatuses and methods are disclosed, including an apparatus with a string of charge storage devices coupled to a common source, a first switch coupled between the string of charge storage devices and a load current source, and a second switch coupled between the load current source and the common source. Additional apparatuses and methods are described.. ... Micron Technology Inc

09/17/15 / #20150262657

Two-part programming methods

Programming a memory in two parts to reduce cell disturb is disclosed. In at least one embodiment, data is programmed in two or more sequences of programming pulses with data requiring higher programming voltages programmed first. ... Micron Technology Inc

09/17/15 / #20150262654

Digital filters with memory

A memory device that, in certain embodiments, includes a memory element coupled to a bit-line and a quantizing circuit coupled to the memory element via the bit-line. In some embodiments, the quantizing circuit includes an analog-to-digital converter having an input and output and a digital filter that includes memory. ... Micron Technology Inc

09/17/15 / #20150262650

Semiconductor memory device having sense amplifier

An apparatus includes a memory cell, a bit line coupled to the memory cell, and a sense amplifier configured to amplify a data signal on the bit line read out from the memory cell. The sense amplifier is operated in a first mode with a first power source voltage difference and operated in a second mode with a second power source voltage difference smaller than the first power source voltage difference.. ... Micron Technology Inc

09/17/15 / #20150262643

Vertical transistor, memory cell, device, system and method of forming same

A memory device, system and fabrication method relating to a vertical memory cell including a semiconducting pillar extending outwardly from an integrally connected semiconductor substrate are disclosed. A first source/drain region is formed in the semiconductor substrate and a body region and a second source/drain region are formed within the semiconductor pillar. ... Micron Technology Inc

09/17/15 / #20150262636

Enable/disable of memory chunks during memory access

Apparatuses and methods involving accessing memory cells are described. In one such method, chunks of memory cells in a memory array are enabled to be accessed and then one or more of the chunks are disabled from being accessed. ... Micron Technology Inc

09/17/15 / #20150262628

Method of dynamically selecting memory cell capacity

Subject matter disclosed herein relates to techniques to use a memory device. A method includes receiving a memory instruction comprising at least one parameter representative of at least one threshold voltage value and a read command to read at least one cell of the memory device. ... Micron Technology Inc

09/17/15 / #20150261902

Time-domain signal generation

Methods and apparatuses disclose various embodiments of time-domain signal generation. In one embodiment a method includes receiving an input waveform having a plurality of cycles with aspects of the input waveform being input and controllable by an end-user. ... Micron Technology Inc

09/17/15 / #20150261669

Devices and methods for operating a solid state drive

The present disclosure includes methods and devices for operating a solid state drive. One method embodiment includes receiving an indication of a desired number of write input/output operations (iops) per unit time performed by the solid state drive. ... Micron Technology Inc

09/10/15 / #20150256175

Semiconductor apparatus including output buffer

An output circuit includes first, second and third transistors. The first transistor includes first and second diffusion layers. ... Micron Technology Inc

09/10/15 / #20150255599

Vertical memory devices, memory arrays, and related methods

Vertical memory devices comprise vertical transistors, buried digit lines extending in a first direction in an array region, and word lines extending in a second direction different from the first direction. Portions of the word lines in a word line end region have a first vertical length greater than a second vertical length of portions of the word lines in the array region. ... Micron Technology Inc

09/10/15 / #20150255502

Semiconductor devices and methods for forming patterned radiation blocking on a semiconductor device

Several embodiments for semiconductor devices and methods for forming semiconductor devices are disclosed herein. One embodiment is directed to a method for manufacturing a microelectronic imager having a die including an image sensor, an integrated circuit electrically coupled to the image sensor, and electrical connectors electrically coupled to the integrated circuit. ... Micron Technology Inc

09/10/15 / #20150255478

Apparatuses including memory arrays with source contacts adjacent edges of sources

Various apparatuses, including three-dimensional (3d) memory devices and systems including the same, are described herein. In one embodiment, a 3d memory device can include at least two sources; at least two memory arrays respectively formed over and coupled to the at least two sources; and a source conductor electrically respectively coupled to the at least two sources using source contacts adjacent one or more edges of the source. ... Micron Technology Inc

09/10/15 / #20150255169

Semiconductor device including fuse circuit

Disclosed herein is an apparatus that includes a fuse circuit including a fuse element, the fuse circuit configured to provide a first output signal having a first voltage or a second voltage responsive to a state of the fuse element, and a sense circuit configured to provide a second output signal having the first voltage or a third voltage responsive to the first output signal, the third voltage different from the second voltage.. . ... Micron Technology Inc

09/10/15 / #20150255163

Determining and using soft data in memory devices and systems

The present disclosure includes methods, devices, and systems for determining and using soft data in memory devices and systems. One or more embodiments include an array of memory cells and control circuitry coupled to the array. ... Micron Technology Inc

09/10/15 / #20150255154

Non-volatile memory including reference signal path

Some embodiments include apparatuses and methods having a first memory element and a first select component coupled to the first memory element, a second memory element and a second select component coupled to the second memory element, and an access line shared by the first and second select components. At least one of the embodiments can include a circuit to generate a signal indicating a state of the second memory element based on a first signal developed from a first signal path through the first memory element and a second signal developed from a second signal path through the second memory element.. ... Micron Technology Inc

09/10/15 / #20150255153

Resistive memory sensing

The present disclosure includes apparatuses and methods for sensing a resistive memory cell. A number of embodiments include performing a sensing operation on a memory cell to determine a current value associated with the memory cell, applying a programming signal to the memory cell, and determining a data state of the memory cell based on the current value associated with the memory cell before applying the programming signal and a current value associated with the memory cell after applying the programming signal.. ... Micron Technology Inc

09/10/15 / #20150255152

Resistance variable memory sensing

The present disclosure includes apparatuses and methods for sensing a resistance variable memory cell. A number of embodiments include programming a memory cell to an initial data state and determining a data state of the memory cell by applying a programming signal to the memory cell, the programming signal associated with programming memory cells to a particular data state, and determining whether the data state of the memory cell changes from the initial data state to the particular data state during application of the programming signal.. ... Micron Technology Inc

09/10/15 / #20150255146

Semiconductor device including subword driver circuit

The present invention is provided with: subword drivers swd for driving subword lines swl, a selection circuit for supplying either negative potential vkk1 or vkk2 to the subword drivers swd, and memory cells mc that are selected in the case when the subword line swl is set to an active potential vpp and are not selected in the case when the subword line swl is either a negative potential vkk1 or vkk2.. . ... Micron Technology Inc

09/10/15 / #20150255145

Device and apparatus having address and command input paths

A device includes a plurality of input terminals, a control circuit, and a plurality of signal buses. Each of the signal buses is coupled between the control circuit and an associated one of the plurality of input terminals and includes one or more first buffers, one or more second buffers and at least one latch circuit coupled between the one or more first buffers and the one or more second buffers. ... Micron Technology Inc

09/10/15 / #20150254178

Control arrangements and methods for accessing block oriented nonvolatile memory

A read/write arrangement is described for use in accessing at least one nonvolatile memory device in read/write operations with the memory device being made up of a plurality of memory cells which memory cells are organized as a set of pages that are physically and sequentially addressable with each page having a page length such that a page boundary is defined between successive ones of the pages in the set. The read/write arrangement includes a control arrangement that is configured to store and access a group of data blocks that is associated with a given write operation in a successive series of pages of the memory such that at least an initial page in the series is filled and each block includes a block length that is different than the page length.. ... Micron Technology Inc

09/10/15 / #20150253755

Counter operation in a state machine lattice

Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may include a counter suitable for counting a number of times a programmable element in the lattice detects a condition. ... Micron Technology Inc

09/03/15 / #20150250060

Method for forming a circuit board via structure for high speed signaling

One embodiment of the invention comprises an improved method for making a via structure for use in a printed circuit board (pcb). The via allows for the passage of a signal from one signal plane to another in the pcb, and in so doing transgresses the power and ground planes between the signal plane. ... Micron Technology Inc

09/03/15 / #20150249383

Charge pump

One charge pump includes at least one delay element, a number of inverters, and a flip flop coupled in series, with an output of one inverter coupled in a feedback loop to one of the delay elements. The charge pump monitors a first supply voltage level, and turns off an oscillator of the charge pump when the first supply voltage drops below a certain level. ... Micron Technology Inc

09/03/15 / #20150249202

Memory cells, methods of fabrication, and semiconductor devices

A magnetic cell includes a magnetic region formed from a precursor magnetic material comprising a diffusible species and at least one other species. An oxide region is disposed between the magnetic region and another magnetic region, and an amorphous region is proximate to the magnetic region. ... Micron Technology Inc

09/03/15 / #20150249092

Memory arrays with a memory cell adjacent to a smaller size of a pillar having a greater channel length than a memory cell adjacent to a larger size of the pillar and methods

The disclosure is related to memory arrays and methods. One such memory array has a substantially vertical pillar. ... Micron Technology Inc

09/03/15 / #20150249089

Memory cells and methods of forming memory cells

A memory cell includes a transistor device comprising a pair of source/drains, a body comprising a channel, and a gate construction operatively proximate the channel. The memory cell includes a capacitor comprising a pair of capacitor electrodes having a capacitor dielectric there-between. ... Micron Technology Inc

09/03/15 / #20150249032

Methods of forming one or more covered voids in a semiconductor substrate

Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. ... Micron Technology Inc

09/03/15 / #20150248937

Non-volatile memory programming

Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method includes applying voltages to data lines associated with different groups of memory cells during a programming operation. ... Micron Technology Inc

09/03/15 / #20150248324

Validating persistent memory content for processor main memory

Subject matter disclosed herein relates to validating memory content in persistent main memory of a processor.. . ... Micron Technology Inc

09/03/15 / #20150247236

Methods for depositing material onto microfeature workpieces in reaction chambers and systems for depositing materials onto microfeature workpieces

Methods for depositing material onto microfeature workpieces in reaction chambers and systems for depositing materials onto microfeature workpieces are disclosed herein. In one embodiment, a method includes depositing molecules of a gas onto a microfeature workpiece in the reaction chamber and selectively irradiating a first portion of the molecules on the microfeature workpiece in the reaction chamber with a selected radiation without irradiating a second portion of the molecules on the workpiece with the selected radiation. ... Micron Technology Inc

09/03/15 / #20150246479

Forming a carbon nano-tube dispersion

Various embodiments disclose a molding compound comprising a resin, a filler, and a carbon nano-tube dispersion and methods of forming a package using the molding compound is disclosed. The carbon non-tube dispersion has a number of carbon nano-tubes with surfaces that are chemically modified by a functional group to chemically bridge the surfaces of the carbon nano-tubes and the resin, improving adhesion between the carbon nano-tubes and the resin and reducing agglomeration between various ones of the carbon nano-tubes. ... Micron Technology Inc

08/27/15 / #20150243885

Cross-point memory and methods for fabrication of same

The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a memory device of the memory array comprises a substrate and a memory cell stack formed between and electrically connected to first and second conductive lines. ... Micron Technology Inc

08/27/15 / #20150243835

Solid-state transducer devices with optically-transmissive carrier substrates and related systems, methods, and devices

Semiconductor device assemblies having solid-state transducer (sst) devices and associated semiconductor devices, systems, and are disclosed herein. In one embodiment, a method of forming a semiconductor device assembly includes forming a support substrate, a transfer structure, and a plurality semiconductor structures between the support substrate and the transfer structure. ... Micron Technology Inc

08/27/15 / #20150243782

Transistor-containing constructions and memory arrays

Some embodiments include transistor-containing constructions having gate material within an opening in a semiconductor material and spaced from the semiconductor material by gate dielectric material. The opening has a wide lower region beneath a narrow upper region. ... Micron Technology Inc

08/27/15 / #20150243748

Vertical access devices, semiconductor device structures, and related methods

A vertical access device comprises a semiconductive base comprising a first source/drain region, a semiconductive pillar extending vertically from the semiconductive base, and a gate electrode adjacent a sidewall of the semiconductive pillar. The semiconductive pillar comprises a channel region overlying the first source/drain region, and a second source/drain region overlying the channel region. ... Micron Technology Inc

08/27/15 / #20150243734

Methods of forming transistors

Some embodiments include methods of forming transistors. Recesses are formed to extend into semiconductor material. ... Micron Technology Inc

08/27/15 / #20150243709

Semiconductor structures including liners comprising alucone and related methods

A semiconductor device including stacked structures. The stacked structures include at least two chalcogenide materials or alternating dielectric materials and conductive materials. ... Micron Technology Inc

08/27/15 / #20150243708

Cross-point memory and methods for fabrication of same

The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a method of fabricating cross-point memory arrays comprises forming a memory cell material stack which includes a first active material and a second active material over the first active material, wherein one of the first and second active materials comprises a storage material and the other of the first and second active materials comprises a selector material. ... Micron Technology Inc

08/27/15 / #20150243671

Methods for forming a string of memory cells and apparatuses having a vertical string of memory cells including metal

A method for forming a string of memory cells, a memory device having a string of memory cells, and a system are disclosed. The string of memory cells can include a string of planar memory cells formed as recesses in each of a plurality of control gate material formed as a vertical stack of alternating insulator and control gate material. ... Micron Technology Inc

08/27/15 / #20150243583

Interconnect assemblies with through-silicon vias and stress-relief features

A semiconductor device in accordance with some embodiments includes a substrate structure and a conductive interconnect extending through at least a portion of the substrate structure. The conductive interconnect can include a through-silicon via and a stress-relief feature that accommodates thermal expansion and/or thermal contraction of material to manage internal stresses in the semiconductor device. ... Micron Technology Inc

08/27/15 / #20150243546

Semiconductor substrate for photonic and electronic structures and method of manufacture

A method of forming a substrate with isolation areas suitable for integration of electronic and photonic devices is provided. A common reticle and photolithographic technique is used to fabricate a mask defining openings for etching first and second trench isolation areas in a substrate, with the openings for the second trench isolation areas being wider than the openings for the first trench isolation areas. ... Micron Technology Inc

08/27/15 / #20150243364

Apparatuses and methods including memory array data line selection

Some embodiments include an apparatus having data lines coupled to memory cell strings and a selector configured to selectively couple one of the data lines to a node. The memory cell strings and the selector can be formed in the same memory array of the apparatus. ... Micron Technology Inc

08/27/15 / #20150243351

Threshold voltage compensation in a memory

Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed “aggressor” memory cells reduces the threshold voltage uncertainty in a flash memory system. ... Micron Technology Inc

08/27/15 / #20150243339

Apparatuses and methods for selective row refreshes

Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. ... Micron Technology Inc

08/27/15 / #20150242664

Systems and methods using single antenna for multiple resonant frequency ranges

A radio frequency device utilizing an antenna having a single antenna structure resonant on multiple resonant frequency ranges. The antenna can be configured to operate within multiple frequency ranges for communication according to respective protocols associated with the respective frequency ranges.. ... Micron Technology Inc

08/20/15 / #20150236259

Switching components and memory units

Some embodiments include a switching component which includes a selector region between a pair of electrodes. The selector region contains silicon doped with one or more of nitrogen, oxygen, germanium and carbon. ... Micron Technology Inc

08/20/15 / #20150236164

Semiconductor device structures and arrays of vertical transistor devices

A semiconductor device structure is disclosed. The semiconductor device structure includes a mesa extending above a substrate. ... Micron Technology Inc

08/20/15 / #20150236023

Vertical transistor devices, memory arrays, and methods of forming vertical transistor devices

A vertical transistor device includes a line of active area adjacent a line of dielectric isolation. A buried data/sense line obliquely angles relative to the line of active area and the line of dielectric isolation. ... Micron Technology Inc

08/20/15 / #20150235938

Patterning methods and methods of forming electrically conductive lines

Some embodiments include methods of forming electrically conductive lines. Photoresist features are formed over a substrate, with at least one of the photoresist features having a narrowed region. ... Micron Technology Inc

08/20/15 / #20150235904

Integrated circuitry and methods of forming transistors

Some embodiments include integrated circuits having first and second transistors. The first transistor is wider than the second transistor. ... Micron Technology Inc

08/20/15 / #20150235841

Methods of forming semiconductor structures comprising aluminum oxide

A semiconductor structure comprising aluminum oxide. The semiconductor structure comprises a dielectric material overlying a substrate. ... Micron Technology Inc

08/20/15 / #20150235713

Memory devices comprising magnetic tracks individually comprising a plurality of magnetic domains having domain walls and methods of forming a memory device comprising magnetic tracks individually comprising a plurality of magnetic domains having domain walls

A method of forming a memory device having magnetic tracks individually comprising a plurality of magnetic domains having domain walls, includes forming an elevationally outer substrate material of uniform chemical composition. The uniform composition material is partially etched into to form alternating regions of elevational depressions and elevational protrusions in the uniform composition material. ... Micron Technology Inc

08/20/15 / #20150235699

Apparatuses including cross point memory arrays and biasing schemes

Memory devices comprise a plurality of memory cells, each memory cell including a memory element and a selection device. A plurality of first (e.g., row) address lines can be adjacent (e.g., under) a first side of at least some cells of the plurality. ... Micron Technology Inc

08/20/15 / #20150235691

Methods and apparatuses for controlling timing paths and latency based on a loop delay

Apparatuses and methods for controlling timing circuit locking and/or latency during a change in clock frequency (e.g. Gear down mode) are described herein. ... Micron Technology Inc

08/20/15 / #20150235682

Method and apparatus for pre-charging data lines in a memory cell array

Memories, pre-charge circuits, and methods for pre-charging memory are described. One such method includes providing a voltage to a data line and adjusting the voltage provided to the data line based at least in part on a voltage difference between a target voltage and a voltage of the data line being pre-charged. ... Micron Technology Inc

08/20/15 / #20150235680

Semiconductor memory device including output buffer

An apparatus includes a first terminal configured to communicate data with an outside of the apparatus, a second terminal configured to receive a first power source potential, a third terminal configured to receive a second power source potential lower than the first power source potential, a fourth terminal configured to be coupled to a calibration resistor, an output buffer including first to third nodes coupled to the first to third terminals respectively, and a replica circuit including fourth and fifth nodes coupled to the second and third terminals respectively, and sixth node coupled to the fourth terminal.. . ... Micron Technology Inc

08/20/15 / #20150235677

Power management

Methods, and apparatus configured to perform such methods, providing peak power management are useful in mitigating excessive current levels within a multi-die package. For example, a method might include providing a clock signal, counting primary clock cycles of the clock signal in a counter, monitoring an indication of high current demand for each die of the multi-die package, and determining a total unit consumption of current. ... Micron Technology Inc

08/20/15 / #20150235676

Apparatus and methods to provide power management for memory devices

An apparatus, such as a nonvolatile solid-state memory device, may, in some implementations, include access line bias circuitry to set a bias level associated with a deselected access line(s) of a memory core in response to mode information. In one approach, access line bias circuitry may use linear down regulation to change a voltage level on deselected access lines of a memory core. ... Micron Technology Inc

08/20/15 / #20150234704

Memory controller supporting rate-compatible punctured codes

Apparatus and methods store data in a non-volatile solid state memory device according to a rate-compatible code, such as a rate-compatible convolutional code (rpcc). An example of such a memory device is a flash memory device. ... Micron Technology Inc

08/20/15 / #20150234601

Command queuing

The present disclosure includes apparatuses and methods for command queuing. A number of embodiments include receiving a queued command request at a memory system from a host, sending a command response from the memory system to the host that indicates the memory system is ready to receive a command in a command queue of the memory system, and receiving, in response to sending the command response, a command descriptor block for the command at the memory system from the host.. ... Micron Technology Inc

08/13/15 / #20150228659

Data line arrangement and pillar arrangement in apparatuses

Some embodiments include an apparatus having semiconductor pillars in a substantially hexagonally closest packed arrangement. The hexagonally closest packed arrangement includes a repeating pillar pattern which has at least portions of 7 different pillars. ... Micron Technology Inc

08/13/15 / #20150228603

Semiconductor constructions and methods of planarizing across a plurality of electrically conductive posts

Some embodiments include a planarization method. A liner is formed across a semiconductor substrate and along posts that extending upwardly from the substrate. ... Micron Technology Inc

08/13/15 / #20150228317

Apparatuses, memories, and methods for facilitating splitting of internal commands using a shared signal path

Apparatuses, memories, and methods for facilitating splitting of internal commands using a shared signal path are described. In an example shared signal path, a command circuit is configured to receive a command and an indicator signal. ... Micron Technology Inc

08/13/15 / #20150227770

Systems and methods to determine kinematical parameters using rfid tags

Systems and methods to determine kinematical parameters of physical objects using radio frequency identification (rfid) tags attached to the objects. In one embodiment, one of a population of rfid tags is selectively instructed by an rfid reader to backscatter the interrogating electromagnetic wave and thus allow the rfid reader to measure the position, speed, acceleration, jerk of the object to which the tag is attached. ... Micron Technology Inc

08/13/15 / #20150227474

Enabling a secure boot from non-volatile memory

A system may include a host that may include a processor coupled to a non-volatile memory over a secure communication protocol. As a result, prior to release for manufacturing, a binding code may be established between the host and the non-volatile memory. ... Micron Technology Inc

08/13/15 / #20150227471

Password accessible microelectronic memory

A microelectronic memory may be password access protected. A controller may maintain a register with requirements for accessing particular memory locations to initiate a security protocol. ... Micron Technology Inc

08/13/15 / #20150227441

Correcting recurring errors in memory

The present disclosure includes apparatuses and methods for correcting recurring errors in memory. A number of embodiments include determining whether a first subset of a group of memory cells has a recurring error associated therewith using a second subset of the group of memory cells, and responsive to a determination that the first subset of the group of memory cells has a recurring error associated therewith, correcting the recurring error using the second subset of the group of memory cells.. ... Micron Technology Inc

08/06/15 / #20150221866

Horizontally oriented and vertically stacked memory cells

Horizontally oriented and vertically stacked memory cells are described herein. One or more method embodiments include forming a vertical stack having a first insulator material, a first memory cell material on the first insulator material, a second insulator material on the first memory cell material, a second memory cell material on the second insulator material, and a third insulator material on the second memory cell material, forming an electrode adjacent a first side of the first memory cell material and a first side of the second memory cell material, and forming an electrode adjacent a second side of the first memory cell material and a second side of the second memory cell material.. ... Micron Technology Inc

08/06/15 / #20150221864

Memory cells and memory cell arrays

Some embodiments include memory cells. The memory cells may have a first electrode, and a trench-shaped programmable material structure over the first electrode. ... Micron Technology Inc

08/06/15 / #20150221832

Gallium nitride wafer substrate for solid state lighting devices, and associated systems and methods

Gallium nitride wafer substrate for solid state lighting devices, and associated systems and methods. A method for making an ssl device substrate in accordance with one embodiment of the disclosure includes forming multiple crystals carried by a support member, with the crystals having an orientation selected to facilitate formation of gallium nitride. ... Micron Technology Inc

08/06/15 / #20150221612

Thermal pads between stacked semiconductor dies and associated systems and methods

Systems and methods are described for improved heat dissipation of the stacked semiconductor dies by including metallic thermal pads between the dies in the stack. In one embodiment, the thermal pads may be in direct contact with the semiconductor dies. ... Micron Technology Inc

08/06/15 / #20150221540

Devices, systems and methods for electrostatic force enhanced semiconductor bonding

Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for enhancing wafer bonding includes positioning a substrate assembly on a unipolar electrostatic chuck in direct contact with an electrode, electrically coupling a conductor to a second substrate positioned on top of the first substrate, and applying a voltage to the electrode, thereby creating a potential differential between the first substrate and the second substrate that generates an electrostatic force between the first and second substrates.. ... Micron Technology Inc

08/06/15 / #20150221384

Methods of operating memory devices

Methods of operating a memory device include applying an increasing sense voltage to a plurality of memory cells, wherein memory cells of the plurality of memory cells each store data states representing two or more digits of data. The methods further include, in response to the increasing sense voltage reaching a particular level, initiating a transfer of data values of a particular digit of data for each memory cell of the plurality of memory cells while continuing to apply the increasing sense voltage to the plurality of memory cells.. ... Micron Technology Inc

08/06/15 / #20150221378

Program and read trim setting

A method and apparatus for setting trim parameters in a memory device provides multiple trim settings that are assigned to portions of the memory device according to observed or tested programming speed and reliability.. . ... Micron Technology Inc

08/06/15 / #20150221366

Metallization scheme for integrated circuit

For multi-level interconnect metallization, each metal level maintains a parallel line arrangement within a region, and the lines of each adjacent metal level are orthogonal or otherwise cross with one another. Vertical shunting among levels for routing in different directions employs short paddles that stay within the parallel scheme, and multiple paddles within a region at the same metal level can be co-linear. ... Micron Technology Inc

08/06/15 / #20150221355

Apparatuses and methods to delay memory commands and clock signals

An example delay circuit may include a delay block configured to receive a command signal and/or a bank address signal, a first clock signal, and a second clock signal and further configured to add an intrinsic delay to the command signal or the bank address signal and add a forward path delay greater than the intrinsic delay to the first and second clock signals.. . ... Micron Technology Inc

08/06/15 / #20150221347

Methods and apparatuses including an asymmetric assist device

Apparatuses and methods have been disclosed. One such apparatus includes a plurality of memory cells that can be formed at least partially surrounding a semiconductor pillar. ... Micron Technology Inc

08/06/15 / #20150220441

Block addressing for parallel memory arrays

Apparatus and methods provide associative mapping of the blocks of two or more memory arrays such that data, such as pages of data, from the good blocks of the two or more memory arrays can be read in an alternating manner for speed or can be read in parallel for providing data to relatively wide data channels. This obviates the need for processor intervention to access data and can increase the throughput of data by providing, where configured, the ability to alternate reading of data from two or more arrays. ... Micron Technology Inc

08/06/15 / #20150220431

Execute-in-place mode configuration for serial non-volatile memory

Example embodiments for configuring a serial non-volatile memory device for an execute-in-place mode may comprise a non-volatile configuration register to store an execute-in-place mode value that may be read at least in part in response to power being applied to the memory device.. . ... Micron Technology Inc

08/06/15 / #20150220395

Error control in memory storage systems

A method includes calculating a first syndrome of a codeword read from a memory location under a first set of conditions and calculating a second syndrome of the codeword read from the memory location under a second set of conditions. The method also includes analyzing the first and second syndromes and applying one of the first and second syndromes to the codeword to find the codeword having a minimum number of errors.. ... Micron Technology Inc

08/06/15 / #20150220386

Data integrity in memory controllers and methods

The present disclosure includes methods, devices, and systems for data integrity in memory controllers. One memory controller embodiment includes a host interface and first error detection circuitry coupled to the host interface. ... Micron Technology Inc

08/06/15 / #20150220344

Memory systems and memory control methods

Memory systems and memory control methods are described. According to one aspect, a memory system includes a plurality of memory cells individually configured to store data, program memory configured to store a plurality of first executable instructions which are ordered according to a first instruction sequence and a plurality of second executable instructions which are ordered according to a second instruction sequence, substitution circuitry configured to replace one of the first executable instructions with a substitute executable instruction, and a control unit configured to execute the first and second executable instructions to control reading and writing of the data with respect to the memory, wherein the control unit is configured to execute the first executable instructions according to the first instruction sequence, to execute the substitute executable instruction after the execution of the first executable instructions, and to execute the second executable instructions according to the second instruction sequence as a result of execution of the substitute executable instruction.. ... Micron Technology Inc

07/30/15 / #20150215557

Antiblooming imaging apparatus, systems, and methods

Apparatus, systems, and methods are described to assist in reducing dark current in an active pixel sensor. In various embodiments, a potential barrier arrangement is configured to block the flow of charge carriers generated outside a photosensitive region. ... Micron Technology Inc

07/30/15 / #20150214481

Memory device constructions, memory cell forming methods, and semiconductor construction forming methods

Memory device constructions include a first column line extending parallel to a second column line, the first column line being above the second column line; a row line above the second column line and extending perpendicular to the first column line and the second column line; memory material disposed to be selectively and reversibly configured in one of two or more different resistive states; a first diode configured to conduct a first current between the first column line and the row line via the memory material; and a second diode configured to conduct a second current between the second column line and the row line via the memory material. In some embodiments, the first diode is a schottky diode having a semiconductor anode and a metal cathode and the second diode is a schottky diode having a metal anode and a semiconductor cathode.. ... Micron Technology Inc

07/30/15 / #20150214477

Memory cells and methods of fabrication

Memory cells are disclosed, which cells include a cell material and an ion-source material over the cell material. A discontinuous interfacial material is included between the cell material and the ion-source material. ... Micron Technology Inc

07/30/15 / #20150214472

Magnetic memory cells and methods of formation

Memory cells including cell cores having free regions are disclosed. The free regions exhibit a strain that affects a magnetization orientation within the cell core. ... Micron Technology Inc

07/30/15 / #20150214363

N-type field effect transistors, arrays comprising n-type vertically-oriented transistors, methods of forming an n-type field effect transistor, and methods of forming an array comprising vertically-oriented n-type transistors

An n-type field effect transistor includes silicon-comprising semiconductor material comprising a pair of source/drain regions having a channel region there-between. At least one of the source/drain regions is conductively doped n-type with at least one of as and p. ... Micron Technology Inc

07/30/15 / #20150214185

Methods and systems for releasably attaching support members to microfeature workpieces

Methods and apparatuses for releasably attaching support members to microfeature workpieces to support members are disclosed herein. In one embodiment, for example, a method for processing a microfeature workpiece including a plurality of microelectronic dies comprises forming discrete blocks of material at a first side of a support member. ... Micron Technology Inc

07/30/15 / #20150214160

Semiconductor structures comprising at least one through-substrate via filled with conductive materials

A method for selective removing material from a substrate without damage to copper filling a via and extending at least partially through the substrate. The method comprises oxidizing a semiconductor structure comprising a substrate and at least one copper feature and removing a portion of the substrate using an etchant comprising sf6 without forming copper sulfide on the at least one copper feature. ... Micron Technology Inc

07/30/15 / #20150214135

Semiconductor device including conductive layer with conductive plug

Some embodiments include a semiconductor device which includes a first conductive layer formed on the semiconductor substrate and a first contact plug connected to the first conductive layer. The first conductive layer includes a plurality of loops of conductive material over the semiconductor substrate. ... Micron Technology Inc

07/30/15 / #20150214107

Apparatuses including stair-step structures and methods of forming the same

Methods for forming semiconductor structures are disclosed, including a method that involves forming sets of conductive material and insulating material, forming a first mask over the sets, forming a first number of contact regions, forming a second mask over a first region of the sets, and removing material from of the sets in a second, exposed region laterally adjacent the first region to form a second number of contact regions. Another method includes forming first and second contact regions on portions of sets of conductive materials and insulating materials, each of the second contact regions more proximal to an underlying substrate than each of the first contact regions. ... Micron Technology Inc

07/30/15 / #20150214100

Methods of forming a substrate opening

A method of forming a substrate opening includes forming a plurality of side-by-side openings in a substrate. At least some of immediately adjacent side-by-side openings are formed in the substrate to different depths relative one another. ... Micron Technology Inc

07/30/15 / #20150213891

Methods and apparatuses for programming memory cells

Methods and apparatus for programming memory cells in a memory array are disclosed. A most recent programming time is determined, the most recent programming time being a time when a most recent programming operation was applied to a reference memory cell in the memory array. ... Micron Technology Inc

07/30/15 / #20150213888

Memory device with reduced neighbor memory cell disturbance

In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes a memory cell, digit line driver, access line driver, clamping element, and control circuit. ... Micron Technology Inc

07/30/15 / #20150213872

Apparatuses and methods for address detection

Apparatuses and methods for address detection are disclosed herein. An example apparatus includes an address filter and an address tracking circuit. ... Micron Technology Inc

07/30/15 / #20150213863

Sub-block disabling in 3d memory

Some embodiments relate to apparatuses and methods associated with blocks of memory cells. The blocks of memory cells may include two or more sub-blocks of memory cells. ... Micron Technology Inc

07/30/15 / #20150213862

Memory decoding

Memories, and methods of operating such memories, having a memory cell, sense circuitry having a gate, program circuitry and a decoder having a first signal line connected to the gate of the sense circuitry, a second signal line connected to the program circuitry, and an output selectively connected to the memory cell. The decoder is configured to selectively connect the output to the first signal line responsive to a first control signal and to selectively connect the output to the second signal line responsive to the first control signal and a second control signal. ... Micron Technology Inc

07/30/15 / #20150213860

Semiconductor device including spiral data path

A semiconductor device disclosed in this disclosure includes a first terminal formed above a first surface of a semiconductor substrate, a second terminal formed above a second surface of the semiconductor substrate opposite to the first surface, a first through substrate via (tsv) penetrating the semiconductor substrate, and a first-in first-out (fifo) circuit, wherein the first tsv and the fifo circuit are coupled in series between the first terminal and the second terminal.. . ... Micron Technology Inc

07/30/15 / #20150213848

Methods and apparatuses for providing a program voltage responsive to a voltage determination

Apparatuses and methods for providing a program voltage responsive to a voltage determination are described. An example apparatus includes a memory array comprising a plurality of access lines. ... Micron Technology Inc

07/30/15 / #20150212882

Physical page, logical page, and codeword correspondence

The present disclosure includes apparatuses and methods for physical page, logical page, and codeword correspondence. A number of methods include error coding a number of logical pages of data as a number of codewords and writing the number of codewords to a number of physical pages of memory. ... Micron Technology Inc

07/30/15 / #20150212871

Selective reading of memory with improved accuracy

This disclosure relates to selectively performing a read with increased accuracy, such as a self-reference read, from a memory. In one aspect, data is read from memory cells, such as magnetoresistive random access memory (mram) cells, of a memory array. ... Micron Technology Inc

07/30/15 / #20150212738

Methods and apparatuses for executing a plurality of queued tasks in a memory

Methods and apparatuses are disclosed for executing a plurality of queued tasks in a memory. One example apparatus includes a memory configured to be coupled to a host. ... Micron Technology Inc

07/30/15 / #20150212734

Memory controllers, memory systems, solid state drives and methods for processing a number of commands

The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. ... Micron Technology Inc

07/23/15 / #20150206906

Memories and methods of forming thin-film transistors using hydrogen plasma doping

Methods of forming thin-film transistors and memories are disclosed. In one such method, polycrystalline silicon is hydrogen plasma doped to form doped polycrystalline silicon. ... Micron Technology Inc

07/23/15 / #20150206886

Methods of forming memory arrays and semiconductor constructions

Some embodiments include methods of forming semiconductor constructions. A heavily-doped region is formed within a first semiconductor material, and a second semiconductor material is epitaxially grown over the first semiconductor material. ... Micron Technology Inc

07/23/15 / #20150206813

Methods and structures for processing semiconductor devices

Methods of processing a semiconductor device include attaching a semiconductor substrate to a carrier substrate, forming a silane material over an exposed portion of the carrier substrate, and curing the silane material to form a hydrophobic coating over the carrier substrate. The hydrophobic coating may reduce or prevent undercut of the semiconductor substrate due to wicking of adhesive from between the semiconductor substrate and the carrier substrate during processing. ... Micron Technology Inc

07/23/15 / #20150206801

Devices, systems, and methods related to planarizing semiconductor devices after forming openings

Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a stop layer and a dielectric liner including dielectric material along sidewalls of openings, e.g., through-substrate openings, of the semiconductor device and excess dielectric material outside the openings. ... Micron Technology Inc

07/23/15 / #20150206761

Methods of forming single crystal silicon structures

A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The single crystal silicon substrate is exposed to an anisotropic etchant that undercuts the single crystal silicon. ... Micron Technology Inc

07/23/15 / #20150206760

Substrate mask patterns, methods of forming a structure on a substrate, methods of forming a square lattice pattern from an oblique lattice pattern, and methods of forming a pattern on a substrate

A method of forming a pattern on a substrate comprises forming spaced, upwardly-open, cylinder-like structures projecting longitudinally outward of a base. Sidewall lining is formed over inner and over outer sidewalls of the cylinder-like structures, and that forms interstitial spaces laterally outward of the cylinder-like structures. ... Micron Technology Inc

07/23/15 / #20150206592

Methods of operating a memory device having a buried boosting plate

Memory devices are disclosed, such as those that include a semiconductor-on-insulator (soi) nand memory array having a boosting plate. The boosting plate may be disposed in an insulator layer of the soi substrate such that the boosting plate exerts a capacitive coupling effect on a p-well of the memory array. ... Micron Technology Inc

07/23/15 / #20150206587

Methods and apparatuses with vertical strings of memory cells and support circuitry

Apparatuses and methods have been disclosed. One such apparatus includes strings of memory cells formed on a topside of a substrate. ... Micron Technology Inc

07/23/15 / #20150206579

Fractional bits in memory cells

The present disclosure includes methods, devices, modules, and systems for programming memory cells. One method embodiment includes storing charges corresponding to a data state that represents an integer number of bits in a set of memory cells. ... Micron Technology Inc

07/23/15 / #20150205530

Autonomous memory subsystem architecture

An autonomous sub-system receives a database downloaded from a host controller. A controller monitors bus traffic and/or allocated resources in the subsystem and re-allocates resources based on the monitored results to dynamically improve system performance.. ... Micron Technology Inc

07/23/15 / #20150204941

Overheat protection circuit and method in an accelerated aging test of an integrated circuit

To include in a device a controller to control operation of the device in a normal-operation mode and in a test mode for performing one or more tests including an accelerated aging test, a temperature sensor to measure operating temperature of the device, and an overheat protection circuit to prevent overheating of the memory device during the test mode. With this overheat protection circuit, a device may undergo an efficient and reliable accelerated aging test with reduced or non-existent, possibility of suffering an overheat damage.. ... Micron Technology Inc

07/23/15 / #20150203754

Compositions for etching polysilicon

Compositions for etching polysilicon including aqueous compositions containing nitric acid and ammonium fluoride.. . ... Micron Technology Inc

07/23/15 / #20150202566

Methods and apparatus for treating fluorinated greenhouse gases in gas streams

A method for removing fluorinated greenhouse gas from a gas stream comprises reacting at least one fluorinated greenhouse gas in a gas stream with at least one of a silane-based and a borane-based compound to provide an abated gas stream. An apparatus for removing fluorinated greenhouse gases from a gas stream comprises a fluorinated gas decomposer unit configured to decompose fluorinated greenhouse gases in a gas stream. ... Micron Technology Inc

07/16/15 / #20150200590

Voltage generator circuit

Embodiments are provided that include a circuit for generating voltage in a memory. One such circuit includes a charge pump circuit including a first transistor, a high-voltage switch circuit, and a cut-off switch circuit arranged to reduce leakage current from the charge pump circuit. ... Micron Technology Inc

07/16/15 / #20150200366

Memory cells having heaters with angled sidewalls

Memory cells having heaters with angled sidewalls and methods of forming the same are described herein. As an example, a method of forming an array of resistive memory cells can include forming a first resistive memory cell having a first heater element angled with respect to a vertical plane, forming a second resistive memory cell adjacent to the first resistive memory cell and having a second heater element angled with respect to the vertical plane and toward the first heater, and forming a third resistive memory cell adjacent to the first resistive memory cell and having a third heater element angled with respect to the vertical plane and away from the first heater element.. ... Micron Technology Inc

07/16/15 / #20150200364

Memory cell structures

The present disclosure includes memory cell structures and method of forming the same. One such memory cell includes a first electrode having sidewalls angled less than 90 degrees in relation to a bottom surface of the first electrode, a second electrode, including an electrode contact portion of the second electrode, having sidewalls angled less than 90 degrees in relation to the bottom surface of the first electrode, wherein the second electrode is over the first electrode, and a storage element between the first electrode and the electrode contact portion of the second electrode.. ... Micron Technology Inc

07/16/15 / #20150200360

Gcib-treated resistive device

The present disclosure includes gcib-treated resistive devices, devices utilizing gcib-treated resistive devices (e.g., as switches, memory cells), and methods for forming the gcib-treated resistive devices. One method of forming a gcib-treated resistive device includes forming a lower electrode, and forming an oxide material on the lower electrode. ... Micron Technology Inc

07/16/15 / #20150200308

Field effect transistor constructions and memory arrays

In some embodiments, a transistor includes a stack having a bottom source/drain region, a first insulative material, a conductive gate, a second insulative material, and a top source/drain region. The stack has a vertical sidewall with a bottom portion along the bottom source/drain region, a middle portion along the conductive gate, and a top portion along the top source/drain region. ... Micron Technology Inc

07/16/15 / #20150200202

Field effect transistor constructions and memory arrays

A field effect transistor construction comprises two source/drain regions and a channel region there-between. The channel region comprises a transition metal dichalcogenide material having a thickness of 1 monolayer to 7 monolayers and having a physical length between the source/drain regions. ... Micron Technology Inc

07/16/15 / #20150200101

Fortification of charge-storing material in high-k dielectric environments and resulting apparatuses

Memories, systems, and methods for forming memory cells are disclosed. One such memory cell includes a charge storage node that includes nanodots over a tunnel dielectric and a protective film over the nanodots. ... Micron Technology Inc

07/16/15 / #20150200007

Apparatus and methods to perform read-while write (rww) operations

Subject matter disclosed herein relates to methods and apparatus, such as memory devices and systems including such memory devices. In one apparatus example, a plurality of block configurations may be employed. ... Micron Technology Inc

07/16/15 / #20150199997

Stacked device detection and identification

Various embodiments include apparatus and methods having circuitry to detect and/or assign identification information to dice arranged in a stack and coupled by conductive paths.. . ... Micron Technology Inc

07/16/15 / #20150199133

Multi-device memory serial architecture

Subject matter disclosed herein relates to memory devices comprising a memory array, a first port to interface with a memory controller directly or indirectly via another memory device, a second port to interface with yet another memory device, and a switch to selectively electrically connect the memory controller to a circuit path leading to the second port or to the memory array, wherein the switch may be responsive to a signal generated by the memory controller.. . ... Micron Technology Inc

07/09/15 / #20150194983

Read threshold calibration for ldpc

Apparatuses and methods for soft read threshold location calibration are provided. One example method can include selecting read threshold sets (rtss), and determining log-likelihood-ratios (llrs) based on a number of decisions that correspond to each bin associated with the selected rtss. ... Micron Technology Inc

07/09/15 / #20150194961

Level shifters, memory systems, and level shifting methods

Level shifters, memory systems, and level shifting methods are described. According to one arrangement, a level shifter includes an input configured to receive an input signal in a first voltage domain, an output configured to output an output signal from the level shifter in a second voltage domain different than the first voltage domain, a plurality of pull-down devices, and wherein one of the pull-down devices is coupled with the input and the output, a plurality of cross-coupled devices coupled with the pull-down devices and configured to provide transitions in the output signal as a result of transitions in the input signal, a plurality of current limiting devices coupled with the cross-coupled devices and configured to limit a flow of current from a source to the cross-coupled devices, and a plurality of dynamic devices configured to selectively provide charging current from the source to the cross-coupled devices.. ... Micron Technology Inc

07/09/15 / #20150194478

Capacitors and methods of forming capacitors

A method of forming a capacitor includes forming an elevationally elongated and elevationally inner capacitor electrode that comprises different composition laterally-outermost and laterally-innermost conductive portions that have different respective intrinsic residual mechanical stress. The innermost conductive portion is formed to have greater mechanical stress in the compressive direction than the outermost conductive portion. ... Micron Technology Inc

07/09/15 / #20150194430

Semiconductor devices including a recessed access device and methods of forming same

A semiconductor device comprises a recessed access device that includes a first pillar, a second pillar, a channel region connecting the first and second pillars, and a gate disposed over the channel region. The channel region has a width that is narrower than widths of the first pillar and the second pillar. ... Micron Technology Inc

07/09/15 / #20150194415

Semiconductor assemblies, stacked semiconductor devices, and methods of manufacturing semiconductor assemblies and stacked semiconductor devices

Stacked semiconductor devices, semiconductor assemblies, methods of manufacturing stacked semiconductor devices, and methods of manufacturing semiconductor assemblies. One embodiment of a semiconductor assembly comprises a thinned semiconductor wafer having an active side releaseably attached to a temporary carrier, a back side, and a plurality of first dies at the active side. ... Micron Technology Inc

07/09/15 / #20150194341

Methods of forming semiconductor structures including tight pitch contacts and lines

Methods of fabricating semiconductor structures incorporating tight pitch contacts aligned with active area features and of simultaneously fabricating self-aligned tight pitch contacts and conductive lines using various techniques for defining patterns having sublithographic dimensions. Semiconductor structures having tight pitch contacts aligned with active area features and, optionally, aligned conductive lines are also disclosed, as are semiconductor structures with tight pitch contact holes and aligned trenches for conductive lines.. ... Micron Technology Inc

07/09/15 / #20150194336

Isolation trench fill using oxide liner and nitride etch back technique with dual trench depth capability

An oxide layer is formed over a substrate having a smaller isolation trench and a large isolation trench. A nitride layer is formed over the oxide layer such that it completely fills the smaller isolation trench and lines the larger isolation trench. ... Micron Technology Inc

07/09/15 / #20150194321

Methods of processing polysilicon-comprising compositions

A method of processing a polysilicon-comprising composition comprises forming a first wall comprising at least one recess in polysilicon. A second wall comprising polysilicon is formed. ... Micron Technology Inc

07/09/15 / #20150194316

Nanostructures having low defect density and methods of forming thereof

A method of forming nanostructure comprises forming self-assembled nucleic acids on at least a portion of a substrate. The method further comprises contacting the self-assembled nucleic acids on the at least a portion of a substrate with a solution comprising at least one repair enzyme to repair defects in the self-assembled nucleic acids. ... Micron Technology Inc

07/09/15 / #20150194299

Zra1on films

Atomic layer deposition (ald) can be used to form a dielectric layer of zirconium aluminum oxynitride (zralon) for use in a variety of electronic devices. Forming the dielectric layer may include depositing zirconium oxide using atomic layer deposition and precursor chemicals, followed by depositing aluminum nitride using precursor chemicals, and repeating. ... Micron Technology Inc

07/09/15 / #20150194224

Memory devices and methods for managing error regions

Memory devices and methods are described that include a stack of memory dies and a logic die. Method and devices described include those that provide for repartitioning the stack of memory dies and storing the new partitions in a memory map. ... Micron Technology Inc

07/09/15 / #20150194218

Memory cell sensing

This disclosure concerns memory cell sensing. One or more methods include determining a data state of a first memory cell coupled to a first data line, determining a data state of a third memory cell coupled to a third data line, transferring determined data of at least one of the first and the third memory cells to a data line control unit corresponding to a second data line to which a second memory cell is coupled, the second data line being adjacent to the first data line and the third data line, and determining a data state of the second memory cell based, at least partially, on the transferred determined data.. ... Micron Technology Inc

07/09/15 / #20150194212

Memory systems and memory programming methods

Memory systems and memory programming methods are described. According to one arrangement, a memory system includes a memory array comprising a plurality of memory cells individually configured to have a plurality of different memory states, access circuitry configured to apply signals to the memory cells to program the memory cells to the different memory states, and a controller to configured to control the access circuitry to apply a first of the signals to one of the memory cells to program the one memory cell from a first memory state to a second memory state different than the first memory state, to determine that the one memory cell failed to place into the second memory state as a result of the application of the first signal, and to control the access circuitry to apply a second signal to the one memory cell to program the one memory cell from the first memory state to the second memory state as a result of the determination, wherein the first and second signals have a different electrical characteristic.. ... Micron Technology Inc

07/09/15 / #20150194211

Permutational memory cells

Various embodiments include at least one resistance change memory (rcm) cell, in one embodiment, three or more pairs of electrical contacts are coupled to the at least one rcm cell. A first portion of the pairs are arranged laterally to one another in a first grouping and a second opposing portion of the pairs are arranged laterally to one another in a second grouping. ... Micron Technology Inc

07/09/15 / #20150194191

Memory devices, memory device operational methods, and memory device implementation methods

Memory devices, memory device operational methods, and memory device implementation methods are described. According to one arrangement, a memory device includes memory circuitry configured to store data in a plurality of different data states, temperature sensor circuitry configured to sense a temperature of the memory device and to generate an initial temperature output which is indicative of the temperature of the memory device, and conversion circuitry coupled with the temperature sensor circuitry and configured to convert the initial temperature output into a converted temperature output which is indicative of the temperature of the memory device at a selected one of a plurality of possible different temperature resolutions, and wherein the converted temperature output is utilized by the memory circuitry to implement at least one operation with respect to storage of the data.. ... Micron Technology Inc

07/09/15 / #20150192737

Photonic device structure and method of manufacture

Disclosed method and apparatus embodiments provide a photonic device with optical isolation from a supporting substrate. A generally rectangular cavity in cross section is provided below an element of the photonic device and the element may be formed from a ledge of the supporting substrate which is over the cavity.. ... Micron Technology Inc

07/09/15 / #20150192514

Scatterometry metrology methods and methods of modeling formation of a vertical region of a multilayer semiconductor substrate to comprise a scatterometry target

A scatterometry target formed relative to an elevationally outermost surface of a substrate includes features having an optical property that is different from that of spaces between the features. The substrate has spaced-apart parallel elongated blocking lines having an optical property different from that of spaces between the blocking lines. ... Micron Technology Inc

07/09/15 / #20150191034

Stamps, methods of forming stamps, methods of forming a pattern on a substract, and methods of forming a self-assembled block copolymer

Methods for fabricating stamps and systems for patterning a substrate, and devices resulting from those methods are provided.. . ... Micron Technology Inc

07/02/15 / #20150188050

Dual resistance heater for phase change devices and manufacturing method thereof

A dual resistance heater for a phase change material region is formed by depositing a resistive material. The heater material is then exposed to an implantation or plasma which increases the resistance of the surface of the heater material relative to the remainder of the heater material. ... Micron Technology Inc

07/02/15 / #20150188042

Method, system, and device for phase change memory switch wall cell with approximately horizontal electrode contact

Embodiments disclosed herein may include depositing a storage component material over and/or in a trench in a dielectric material, including depositing the storage component material on approximately vertical walls of the trench and a bottom of the trench. Embodiments may also include etching the storage component material so that at least a portion of the storage component material remains on the approximately vertical walls and the bottom of the trench, wherein the trench is contacting an electrode and a selector such that storage component material on the bottom of the trench contacts the electrode.. ... Micron Technology Inc

07/02/15 / #20150188040

Phase change memory cell with self-aligned vertical heater and low resistivity interface

A low resistivity interface material is provided between a self-aligned vertical heater element and a contact region of a selection device. A phase change chalcogenide material is deposited directly on the vertical heater element. ... Micron Technology Inc

07/02/15 / #20150187767

Semiconductor structures providing electrical isolation

Methods of isolating gates in a semiconductor structure. In one embodiment, isolation is achieved using a spacer material in combination with fins. ... Micron Technology Inc

07/02/15 / #20150187417

Apparatuses and methods for efficient write in a cross-point array

A memory circuit, including a memory array (such as a cross-point array), may include circuit elements that may function both as selection elements/drivers and de-selection elements/drivers. A selection/de-selection driver may be used to provide both a selection function as well as an operation function. ... Micron Technology Inc

07/02/15 / #20150187416

State determination in resistance variable memory

An evaluation signal is applied to a memory cell in an array of resistance variable memory cells. The evaluation signal is configured to cause the memory cell to switch from a first state to a second state. ... Micron Technology Inc

07/02/15 / #20150187395

Data shifting

The present disclosure includes apparatuses and methods related to data shifting. An example apparatus comprises a first memory cell coupled to a first sense line of an array, a first isolation device located between the first memory cell and first sensing circuitry corresponding thereto, and a second isolation device located between the first memory cell and second sensing circuitry corresponding to a second sense line. ... Micron Technology Inc

07/02/15 / #20150186131

Method and apparatus for field firmware updates in data storage systems

Data storage devices and methods for updating firmware are disclosed. For example, one such data storage device includes a device firmware and a controller, where the controller operates in accordance with the device firmware. ... Micron Technology Inc

07/02/15 / #20150185798

Power interrupt management

The present disclosure includes methods for operating a memory system, and memory systems. One such method includes updating transaction log information in a transaction log using write look ahead information; and updating a logical address (la) table using the transaction log.. ... Micron Technology Inc

06/25/15 / #20150179936

Memory cells and methods of forming memory cells

Some embodiments include a memory cell having a first electrode, and an intermediate material over and directly against the first electrode. The intermediate material includes stabilizing species corresponding to one or both of carbon and boron. ... Micron Technology Inc

06/25/15 / #20150179931

Resistive memory architectures with multiple memory cells per access device

A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is coupled to a rectifying device to prevent parallel leak current from flowing through non-selected memory cells. ... Micron Technology Inc

06/25/15 / #20150179649

Thyristor-based memory cells, devices and systems including the same and methods for forming the same

Semiconductor devices including a plurality of thyristor-based memory cells, each having a cell size of 4f2, and methods for forming the same are provided. The thyristor-based memory cells each include a thyristor having vertically superposed regions of alternating dopant types, and a control gate. ... Micron Technology Inc

06/25/15 / #20150179493

Methods and structures for processing semiconductor devices

Methods of forming semiconductor structures include providing a polymeric material over a carrier substrate, bonding another substrate to the polymeric material, and lowering a temperature of the polymeric material to below about 15° c. To separate the another substrate from the carrier substrate. ... Micron Technology Inc

06/25/15 / #20150179273

Memory read apparatus and methods

Apparatus and methods are disclosed, including a method that raises an electrical potential of a plurality of access lines to a raised electrical potential, where each access line is associated with a respective charge storage device of a string of charge storage devices. The electrical potential of a selected one of the access lines is lowered, and a data state of the charge storage device associated with the selected access line is sensed while the electrical potential of the selected access line is being lowered. ... Micron Technology Inc

06/25/15 / #20150179256

Memory systems and memory programming methods

Memory systems and memory programming methods are described. According to one arrangement, a memory system includes a plurality of memory cells individually configured to have a plurality of different memory states, a plurality of bitlines coupled with the memory cells, access circuitry coupled with the bitlines and configured to apply a plurality of program signals to the bitlines to program the memory cells between the different memory states, a controller configured to control the access circuitry to provide a first program signal and a second program signal to one of the bitlines coupled with one of the memory cells to program the one memory cell from a first of the memory states to a second of the memory states, wherein the second program signal has an increased electrical characteristic compared with the first program signal, and selection circuitry configure to couple another of the bitlines which is immediately adjacent to the one bitline to a node having a first voltage which is different than a second voltage of the one bitline during the provision of the first and second program signals to the one bitline.. ... Micron Technology Inc

06/25/15 / #20150179255

Voltage stabilizing for a memory cell array

Voltage balancing for a memory cell array is provided. One example method of voltage balancing for a memory array can include activating an access node coupled to a row of a memory array to provide voltage to the row of the memory array, activating a stabilizing transistor coupled to the row of the memory array to create a feedback loop, and activating a driving node coupled to a column of the memory array, wherein activating the driving node deactivates the stabilizing transistor once the column reaches a particular voltage potential.. ... Micron Technology Inc

06/25/15 / #20150179253

Apparatuses, memories, and methods for address decoding and selecting an access line

Apparatuses, memories, and methods for decoding memory addresses for selecting access lines in a memory are disclosed. An example apparatus includes an address decoder circuit coupled to first and second select lines, a polarity line, and an access line. ... Micron Technology Inc

06/25/15 / #20150179240

Sharing resources in multi-dice stacks

Apparatus, systems, and methods for configuring a plurality of stacked semiconductor dice with unique identifiers and identifying a die in the stack using the unique identifier are provided. Additional apparatus and methods are disclosed.. ... Micron Technology Inc

06/25/15 / #20150178158

Shaping codes for memory

Apparatuses and methods associated with shaping codes for memory are provided. One example apparatus comprises an array of memory cells and a shaping component coupled to the array and configured to encode each of a number of received digit patterns according to a mapping of received digit patterns to shaping digit patterns. ... Micron Technology Inc

06/25/15 / #20150177470

Method and apparatus providing a coupled photonic structure

Described embodiments include optical connections for electronic-photonic devices, such as optical waveguides and photonic detectors for receiving optical waves from the optical waveguides and directing the optical waves to a common point. Methods of fabricating such connections are also described.. ... Micron Technology Inc

06/18/15 / #20150171849

Apparatuses and methods for providing clock signals

Apparatuses and methods for providing clock signals are described herein. An example apparatus may include a clock generator circuit. ... Micron Technology Inc

06/18/15 / #20150171321

Methods of forming metal on inhomogeneous surfaces and structures incorporating metal on inhomogeneous surfaces

The disclosed technology relates to integrate circuits, including memory devices. A method of forming an integrated circuit comprises providing a surface comprising a first region and a second region, wherein the first region is formed of a different material than the second region. ... Micron Technology Inc

06/18/15 / #20150171292

Wafer-level packaging for solid-state transducers and associated systems and methods

Wafer-level packaging of solid-state transducers (“ssts”) is disclosed herein. A method in accordance with a particular embodiment includes forming a transducer structure having a first surface and a second surface opposite the first surface, and forming a plurality of separators that extend from at least the first surface of the transducer structure to beyond the second surface. ... Micron Technology Inc

06/18/15 / #20150171165

Bonded strained semiconductor with a desired surface orientation and conductance direction

According to various method embodiments, a semiconductor layer is oriented to a substrate. The semiconductor layer has a surface orientation and is oriented to the substrate to provide a desired direction of conductance for the surface orientation. ... Micron Technology Inc

06/18/15 / #20150171138

Solid state transducer devices, including devices having integrated electrostatic discharge protection, and associated systems and methods

Solid state transducer devices having integrated electrostatic discharge protection and associated systems and methods are disclosed herein. In one embodiment, a solid state transducer device includes a solid state emitter, and an electrostatic discharge device carried by the solid state emitter. ... Micron Technology Inc

06/18/15 / #20150171090

Method for providing electrical connections to spaced conductive lines

An integrated circuit and a method of formation provide a contact area formed at an angled end of at least one linearly extending conductive line. In an embodiment, conductive lines with contact landing pads are formed by patterning lines in a mask material, cutting at least one of the material lines to form an angle relative to the extending direction of the material lines, forming extensions from the angled end faces of the mask material, and patterning an underlying conductor by etching using said material lines and extension as a mask. ... Micron Technology Inc

06/18/15 / #20150171061

Stacked packaged integrated circuit devices, and methods of making same

A device is disclosed which includes a first packaged integrated circuit device, a second packaged integrated circuit device positioned above the first packaged integrated circuit device and a plurality of planar conductive members conductively coupling the first and second packaged integrated circuit devices to one another. A method is also disclosed which includes conductively coupling a plurality of extensions on a leadframe to each of a pair of stacked packaged integrated circuit devices and cutting the leadframe to singulate the extensions from one another.. ... Micron Technology Inc

06/18/15 / #20150170991

Stacked semiconductor die assemblies with thermal spacers and associated systems and methods

Stacked semiconductor die assemblies with thermal spacers and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a thermally conductive casing defining a cavity, a stack of first semiconductor dies within the cavity, and a second semiconductor die stacked relative to the stack of first dies and carried by a package substrate. ... Micron Technology Inc

06/18/15 / #20150170979

Apparatuses and methods for die seal crack detection

Apparatuses and methods can include a die seal between an integrated circuit region of a die and a periphery of the die. A via chain(s) may be arranged around an inner circumference of the die seal between the die seal and the integrated circuit region and/or around an outer circumference of the die seal between the die seal and the periphery of the die. ... Micron Technology Inc

06/18/15 / #20150170905

Methods for device fabrication using pitch reduction and related devices

Embodiments of a method for device fabrication by reverse pitch reduction flow include forming a first pattern of features above a substrate and forming a second pattern of pitch-multiplied spacers subsequent to forming the first pattern of features. In embodiments of the invention the first pattern of features may be formed by photolithography and the second pattern of pitch-multiplied spacers may be formed by pitch multiplication. ... Micron Technology Inc

06/18/15 / #20150170859

Fuses, and methods of forming and using fuses

Some embodiments include a fuse having a tungsten-containing structure directly contacting an electrically conductive structure. The electrically conductive structure may be a titanium-containing structure. ... Micron Technology Inc

06/18/15 / #20150170757

Programming memories and methods

Memory devices and programming methods for memories are disclosed, such as those adapted to program a memory using an increasing channel voltage for a first portion of programming, and an increasing but reduced channel voltage for a second portion of programming.. . ... Micron Technology Inc

06/18/15 / #20150170756

Memory program disturb reduction

Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method can include applying, during a first pass of programming, a first bias voltage value to a source select gate to isolate memory cells from a source, applying a programming voltage to an access line of a page of the memory cells during the first pass of programming, and applying a second bias voltage value to the source select gate to isolate the memory cells from the source during a second pass of programming. ... Micron Technology Inc

06/18/15 / #20150170751

Adjusted read for partially programmed block

The present disclosure is related to an adjusted read for a partially programmed block. A number of methods can include receiving a read request including a logical address, translating the logical address to a physical address and simultaneously determining whether a physical address associated with the read request is in a block that is partially programmed, and in response to the physical address being in the block that is partially programmed, adjusting a read signal level based on a proximity of the physical address to a last written page in the block.. ... Micron Technology Inc

06/18/15 / #20150170750

Methods applying a non-zero voltage differential across a memory cell not involved in an access operation

Methods applying a non-zero voltage differential across a memory cell not involved in an access operation can facilitate improved data retention characteristics.. . ... Micron Technology Inc

06/18/15 / #20150170745

Fast programming memory device

In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line, and wherein said memory cells are adapted to be programmed into at least a first programming state and a second programming state, a method of storing data comprising exploiting a single memory cell for each of the memory cells string for writing the data, wherein said exploiting includes bringing the single memory cell to the second programming state, the remaining memory cells of the string being left in the first programming state.. . ... Micron Technology Inc

06/18/15 / #20150170740

Memory systems and memory programming methods

Memory systems and memory programming methods are described. In one arrangement, a memory system includes a memory cell configured to have a plurality of different memory states, an access circuit coupled with the memory cell and configured to provide a first signal to a memory element of the memory cell to program the memory cell from a first memory state to a second memory state, and a current source coupled with the memory cell and configured to generate a second signal which is provided to the memory element of the memory cell after the first signal to complete programming of the memory cell from the first memory state to the second memory state.. ... Micron Technology Inc

06/18/15 / #20150170731

Apparatuses and methods for writing masked data to a buffer

Disclosed are apparatuses and methods for writing data to a memory array of a buffer. One such apparatus may include a multiplexer that receives data words and a data mask. ... Micron Technology Inc

06/18/15 / #20150170725

Circuit, system and method for controlling read latency

A read latency control circuit is described having a clock synchronization circuit and a read latency control circuit. The clock synchronization circuit includes an adjustable delay line to generate an output clock signal whose phase is synchronized with the phase of the input clock signal. ... Micron Technology Inc

06/18/15 / #20150169404

Apparatus and methods of programming memory cells using adjustable charge state level(s)

Apparatus and methods are disclosed, including a method of programming involving determining an error rate for the memory cells, and programming the memory cells using a charge state level for a charge state that is based at least in part on the determined error rate.. . ... Micron Technology Inc

06/11/15 / #20150162919

Apparatuses and methods for compensating for power supply sensitivities of a circuit in a clock path

Apparatuses and methods for compensating for differing power supply sensitivities of a circuit in a clock path. One such method includes altering signal timing of at least one of reference and feedback clock signals differently according to variations in power supply voltage to compensate for differences in delay power supply sensitivities of delays of a forward clock path and of a feedback clock path. ... Micron Technology Inc

06/11/15 / #20150162531

Method, system and device for phase change memory with shunt

Embodiments disclosed herein may relate to forming a storage component comprising a phase change material and a shunt relative to amorphous portions of the phase change material.. . ... Micron Technology Inc

06/11/15 / #20150162513

Vertical solid-state transducers and high voltage solid-state transducers having buried contacts and associated systems and methods

Solid-state transducers (“ssts”) and vertical high voltage ssts having buried contacts are disclosed herein. An sst die in accordance with a particular embodiment can include a transducer structure having a first semiconductor material at a first side of the transducer structure, and a second semiconductor material at a second side of the transducer structure. ... Micron Technology Inc

06/11/15 / #20150162492

Self-identifying solid-state transducer modules and associated systems and methods

Self-identifying solid-state transducer (sst) modules and associated systems and methods are disclosed herein. In several embodiments, for example, an sst system can include a driver and at least one sst module electrically coupled to the driver. ... Micron Technology Inc

06/11/15 / #20150162302

Methods of forming semiconductor die assemblies

Semiconductor assemblies, structures, and methods of fabrication are disclosed. A coating is formed on an electrically conductive pillar. ... Micron Technology Inc

06/11/15 / #20150162246

Semiconductor devices including wisx

Some embodiments include a semiconductor device having a stack structure including a plurality of alternating tiers of dielectric material and poly-silicon formed on a substrate. Such a semiconductor device may further include at least one opening having a high aspect ratio and extending into the stack structure to a level adjacent the substrate, a first poly-silicon channel formed in a lower portion of the opening adjacent the substrate, a second poly-silicon channel formed in an upper portion of the opening, and wsix material disposed between the first poly-silicon channel and the second poly-silicon channel in the opening. ... Micron Technology Inc

06/11/15 / #20150162090

Sensing memory cells coupled to different access lines in different blocks of memory cells

In an embodiment, a target memory cell in a first block of memory cells of a memory device and a target memory cell in a second block of memory cells of the memory device are sensed concurrently while a read voltage is applied to a selected access line coupled to the target memory cell in the first block of memory cells and while a read voltage is applied to another selected access line coupled to the target memory cell in the second block of memory cells.. . ... Micron Technology Inc

06/11/15 / #20150162089

Mapping between program states and data patterns

The present disclosure includes methods and apparatuses for mapping between program states and data patterns. One method includes: programming a group of g memory cells such that a combination of respective program states of the group maps to a constellation point corresponding to a received n unit data pattern, the group used to store n/g units of data per memory cell; wherein the constellation point is one of a number of constellation points of a constellation associated with mapping respective program state combinations of the group of memory cells to n unit data patterns; and wherein the constellation comprises a first mapping shell and a second mapping shell, the constellation points corresponding to the respective first and second mapping shells determined, at least partially, based on a polynomial expression of order equal to g.. ... Micron Technology Inc

06/11/15 / #20150162084

Architecture for 3-d nand memory

Apparatuses are described that include stacked arrays of memory cell strings and their methods of operation. Apparatuses include architectures that reduce the use of several common components, allowing greater device density and smaller device size for a given semiconductor area.. ... Micron Technology Inc

06/11/15 / #20150162053

Selectively conducting devices, diode constructions, constructions, and diode forming methods

Some embodiments include selectively conducting devices having a first electrode, a second electrode, and dielectric material between the first and second electrodes. The dielectric material may be configured to conduct current from the first electrode to the second electrode when a first voltage is applied across the first electrode and the second electrode. ... Micron Technology Inc

06/11/15 / #20150160874

Integrity of an address bus

A memory device has a controller, an address integrity feature, and an address register. The controller is configured to store error correction data in the address register when the address integrity feature is enabled.. ... Micron Technology Inc

06/11/15 / #20150160712

Apparatus power control

The present disclosure includes apparatuses and methods for apparatus power control. A number of embodiments include determining a power profile for each of a number of commands in a command queue that are ready for execution and selecting a portion of the number of commands in the command queue for execution based on the power profiles of the number of commands to control power consumption in the apparatus.. ... Micron Technology Inc

06/11/15 / #20150160146

Material test structure

Material test structures having cantilever portions and methods of forming the same are described herein. As an example, a method of forming a material test structure includes forming a number of electrode portions in a first dielectric material, forming a second dielectric material on the first dielectric material, wherein the second dielectric material includes a first cantilever portion and a second cantilever portion, and forming a test material on the number of electrode portions, the first dielectric material, and the second dielectric material.. ... Micron Technology Inc

06/04/15 / #20150156908

Computer modules with small thicknesses and associated methods of manufacturing

Computer modules with small thicknesses and associated methods of manufacturing are disclosed. In one embodiment, the computer modules can include a module substrate having a module material and an aperture extending at least partially into the module material. ... Micron Technology Inc

06/04/15 / #20150156022

Critical security parameter generation and exchange system and method for smart-card memory modules

A storage device contains a smart-card device and a memory device, which is connected to a controller. The storage device may be used in the same manner as a conventional smart-card device, or it may be used to store a relatively large amount of data. ... Micron Technology Inc

06/04/15 / #20150155855

Apparatuses and methods for duty cycle adjustments

Apparatuses and methods have been disclosed. One such apparatus includes a plurality of gates coupled together in series. ... Micron Technology Inc

06/04/15 / #20150155484

Method, system, and device for heating a phase change memory cell

Embodiments disclosed herein may relate to heating a phase change memory (pcm) cell.. . ... Micron Technology Inc

06/04/15 / #20150155481

Memory devices including phase change material elements

Memory devices having a plurality of memory cells, with each memory cell including a phase change material having a laterally constricted portion thereof. The laterally constricted portions of adjacent memory cells are vertically offset and positioned on opposite sides of the memory device. ... Micron Technology Inc

06/04/15 / #20150155452

Etched trenches in bond materials for die singulation, and associated systems and methods

Etched trenches in a bond material for die singulation, and associated systems and methods are disclosed. A method for solid state transducer device singulation in accordance with one embodiment includes forming a plurality of trenches by etching through a metallic bond material forming a bond between a carrier substrate and a plurality of the dies and singulating the carrier substrate along the trenches to separate the dies. ... Micron Technology Inc

06/04/15 / #20150155440

Semiconductor growth substrates and associated systems and methods for die singulation

Semiconductor growth substrates and associated systems and methods for die singulation are disclosed. A representative method for manufacturing semiconductor devices includes forming spaced-apart structures at a dicing street located between neighboring device growth regions of a substrate material. ... Micron Technology Inc

06/04/15 / #20150155298

Three-dimensional devices having reduced contact length

Various embodiments comprise apparatuses and methods including a memory array having alternating levels of semiconductor materials and dielectric material with strings of memory cells formed on the alternating levels. One such apparatus includes a memory array formed starting adjacent to a surface of a substrate. ... Micron Technology Inc

06/04/15 / #20150155285

Techniques for providing a semiconductor memory device

Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. ... Micron Technology Inc

06/04/15 / #20150155283

Gated bipolar junction transistors, memory arrays, and methods of forming gated bipolar junction transistors

Some embodiments include gated bipolar junction transistors. The transistors may include a base region between a collector region and an emitter region; with a b-c junction being at an interface of the base region and the collector region, and with a b-e junction being at an interface of the base region and the emitter region. ... Micron Technology Inc

06/04/15 / #20150155034

Apparatus and method for reading a phase-change memory cell

An apparatus and a method for reading a phase-change memory cell are described. A circuit includes a current ramp circuit. ... Micron Technology Inc

06/04/15 / #20150155011

Independent control of stacked electronic modules

Various embodiments of apparatuses are disclosed to allow independent control of stacked modules. In one embodiment, an apparatus may include a plurality of stacked memory dice, with at least some of the plurality of stacked memory dice include a chip enable (ce) signal connection electrically accessible from a surface of a corresponding one of the dice. ... Micron Technology Inc

06/04/15 / #20150154429

Systems and methods to selectively connect antennas to receive and backscatter radio frequency signals

Systems and methods to selectively attach and control antennas via diodes. In one embodiment, a system includes: a reader having a plurality of reader antennas of different polarizations to transmit radio frequency signals; and at least one radio frequency device. ... Micron Technology Inc

06/04/15 / #20150154068

Memory device having address and command selectable capabilities

Subject matter disclosed herein relates to memory management, and more particularly to partitioning a memory based on memory attributes.. . ... Micron Technology Inc

06/04/15 / #20150154060

Error detection or correction of stored signals after one or more heat events in one or more memory devices

Example embodiments described herein may relate to memory devices, and may relate more particularly to error detection or correction of stored signals in memory devices.. . ... Micron Technology Inc

06/04/15 / #20150153963

Methods and systems for autonomous memory

A method, an apparatus, and a system have been disclosed. An embodiment of the method includes an autonomous memory device receiving a set of instructions, the memory device executing the set of instructions, combining the set of instructions with any data recovered from the memory device in response to the set of instructions into a packet, and transmitting the packet from the memory device.. ... Micron Technology Inc

06/04/15 / #20150153956

Methods for controlling host memory access with memory devices and systems

The present disclosure includes methods for controlling host memory access with a memory device, systems, host controllers and memory devices. One embodiment for controlling host memory access with a memory device includes receiving at least one command from a host and controlling execution of the at least one command with the memory device.. ... Micron Technology Inc

06/04/15 / #20150153953

Stacked memory devices, systems, and methods

Memory requests for information from a processor are received in an interface device, and the interface device is coupled to a stack including two or more memory devices. The interface device is operated to select a memory device from a number of memory devices including the stack, and to retrieve some or all of the information from the selected memory device for the processor. ... Micron Technology Inc

05/28/15 / #20150149838

Rearranging programming data to avoid hard errors

This disclosure relates to avoiding a hard error in memory during write time by shifting data to be programmed to memory to mask the hard error. In one implementation, a method of programming data to a memory array includes obtaining error data corresponding to a selected memory cell, shifting a data pattern such that a value to be stored by the selected memory cell matches a value associated with a hard error, and programming the shifted data pattern to memory array such that the value programmed to the selected memory cell matches the value associated with the hard error.. ... Micron Technology Inc

05/28/15 / #20150149738

Continuous page read for memory

Subject matter disclosed herein relates to techniques to read memory in a continuous fashion.. . ... Micron Technology Inc

05/28/15 / #20150149712

Translation layer in a solid state storage device

Solid state storage devices and methods for flash translation layers are disclosed. In one such translation layer, a sector indication is translated to a memory location by a parallel unit look-up table is populated by memory device enumeration at initialization. ... Micron Technology Inc

05/28/15 / #20150146495

Semiconductor device including a clock adjustment circuit

Disclosed herein is an apparatus that includes a clock circuit configured to receive first and second clock signals and perform a phase control operation in which a phase relationship between the first and second clock signals is controlled, the clock circuit configured to initiate the phase control operation each time a first control signal is asserted, the clock circuit including a comparator circuit that is configured to produce a second control signal indicative of a phase difference between the first and second clock signals, and a timing generator configured to assert the first control signal cyclically, the timing generator configured to respond to the second control signal to control a cycle of producing the first control signal.. . ... Micron Technology Inc

05/28/15 / #20150146494

Partial access mode for dynamic random access memory

Some embodiments provide a method to reduce the refresh power consumption by effectively extending the memory cell retention time. Conversion from 1 cell/bit to 2n cells/bit reduces the variation in the retention time among memory cells. ... Micron Technology Inc

05/28/15 / #20150146472

Memory systems and memory programming methods

Memory systems and memory programming methods are described. According to one aspect, a memory system includes program circuitry configured to provide a program signal to a memory cell to program the memory cell from a first memory state to a second memory state, detection circuitry configured to detect the memory cell changing from the first memory state to the second memory state during the provision of the program signal to the memory cell to program the memory cell, and wherein the program circuitry is configured to alter the program signal as a result of the detection and to provide the altered program signal to the memory cell to continue to program the memory cell from the first memory state to the second memory state.. ... Micron Technology Inc

05/28/15 / #20150145593

Redistribution structures for microfeature workpieces

Microfeature dies with redistribution structures that reduce or eliminate line interference are disclosed. The microfeature dies can include a substrate having a bond site and integrated circuitry electrically connected to the bond site. ... Micron Technology Inc

05/28/15 / #20150145146

Methods of exposing conductive vias of semiconductor devices and related semiconductor devices

Methods of exposing conductive vias of semiconductor devices may involve positioning a barrier material over conductive vias extending from a backside surface of a substrate to at least substantially conform to the conductive vias. A self-planarizing isolation material may be positioned on a side of the barrier material opposing the substrate. ... Micron Technology Inc

05/28/15 / #20150145135

Electrically conductive laminate structures

Some embodiments include electrical interconnects. The interconnects may contain laminate structures having a graphene region sandwiched between non-graphene regions. ... Micron Technology Inc

05/28/15 / #20150145044

Floating body transistor constructions, semiconductor constructions, and methods of forming semiconductor constructions

The invention includes floating body transistor constructions containing u-shaped semiconductor material slices. The u-shapes have a pair of prongs joined to a central portion. ... Micron Technology Inc

05/28/15 / #20150144986

Solid state lighting devices with accessible electrodes and methods of manufacturing

Various embodiments of light emitting dies and solid state lighting (“ssl”) devices with light emitting dies, assemblies, and methods of manufacturing are described herein. In one embodiment, a light emitting die includes an ssl structure configured to emit light in response to an applied electrical voltage, a first electrode carried by the ssl structure, and a second electrode spaced apart from the first electrode of the ssl structure. ... Micron Technology Inc

05/28/15 / #20150144864

Memory arrays and methods of forming memory cells

Some embodiments include methods of forming memory cells. A stack includes ovonic material over an electrically conductive region. ... Micron Technology Inc

05/21/15 / #20150143206

Method for performing error corrections of digital information codified as a symbol sequence

A method and system for making error corrections on digital information coded as symbol sequences, for example digital information stored in electronic memory systems or transmitted from and to these systems is described, provides the 5 transmission of sequences incorporating a portion of error corrector code allowing the sequence which is more probably the original transmitted through the calculation of an error syndrome using a parity matrix to be restored when received. Advantageously according to embodiments of the invention, the error code incorporated in the original sequence belongs to a non boolean group.. ... Micron Technology Inc

05/21/15 / #20150143040

Memory device and method having on-board processing logic for facilitating interface with multiple processors, and computer system using same

A memory device includes an on-board processing system that facilitates the ability of the memory device to interface with a plurality of processors operating in a parallel processing manner. The processing system includes circuitry that performs processing functions on data stored in the memory device in an indivisible manner. ... Micron Technology Inc

05/21/15 / #20150140817

Apparatuses facilitating fluid flow into via holes, vents, and other openings communicating with surfaces of substrates of semiconductor device components

A method for removing material from surfaces of at least a portion of at least one recess or at least one aperture extending into a surface of a substrate includes pressurizing fluid so as to cause the fluid to flow into the at least one recess or the at least one aperture. The fluid may be pressurized by generating a pressure differential across the substrate, which causes the fluid to flow into or through the at least one aperture or recess. ... Micron Technology Inc

05/21/15 / #20150140803

Methods of forming semiconductor structures

Methods of forming semiconductor structures that include bodies of a semiconductor material disposed between rails of a dielectric material are disclosed. Such methods may include filling a plurality of trenches in a substrate with a dielectric material and removing portions of the substrate between the dielectric material to form a plurality of openings. ... Micron Technology Inc

05/21/15 / #20150140797

3d memory

Three-dimensional memory cells and methods of making and using the memory cells are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory can include a memory stack. ... Micron Technology Inc

05/21/15 / #20150140781

Semiconductor isolation structure and method of manufacture

A method of formation of an isolation structure for vertical semiconductor devices, the resulting isolation structure, and a memory device to prevent leakage among adjacent vertical semiconductor devices are described.. . ... Micron Technology Inc

05/21/15 / #20150140777

Methods of selectively doping chalcogenide materials and methods of forming semiconductor devices

Methods of selectively forming a metal-doped chalcogenide material comprise exposing a chalcogenide material to a transition metal solution, and incorporating transition metal of the transition solution into the chalcogenide material without substantially incorporating the transition metal into an adjacent material. The chalcogenide material is not silver selenide. ... Micron Technology Inc

05/21/15 / #20150140776

Memory cells and methods of forming memory cells

Some embodiments include a method of forming a memory cell. A first portion of a switching region is formed over a first electrode. ... Micron Technology Inc

05/21/15 / #20150140773

Methods of forming insulative elements

Methods of forming an insulative element are described, including forming a first metal oxide material having a first dielectric constant, forming a second metal oxide material having a second dielectric constant different from the first, and heating at least portions of the structure to crystallize at least a portion of at least one of the first dielectric material and the second dielectric material. Methods of forming a capacitor are described, including forming a first electrode, forming a dielectric material with a first oxide and a second oxide over the first electrode, and forming a second electrode over the dielectric material. ... Micron Technology Inc

05/21/15 / #20150140753

Methods of fabricating integrated structures, and methods of forming vertically-stacked memory cells

Some embodiments include a method of fabricating integrated structures. A metal-containing material is formed over a stack of alternating first and second levels. ... Micron Technology Inc

05/21/15 / #20150140742

Methods of forming gated devices

Some embodiments include methods of forming gated devices. An upper region of a semiconductor material is patterned into a plurality of walls that extend primarily along a first direction. ... Micron Technology Inc

05/21/15 / #20150138896

Apparatuses and methods for performing logical operations using sensing circuitry

The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry comprising a primary latch coupled to a sense line of the array. ... Micron Technology Inc

05/21/15 / #20150138880

Memory cells having a plurality of resistance variable materials

Resistance variable memory cells having a plurality of resistance variable materials and methods of operating and forming the same are described herein. As an example, a resistance variable memory cell can include a plurality of resistance variable materials located between a plug material and an electrode material. ... Micron Technology Inc

05/21/15 / #20150138875

Stabilization of resistive memory

The present disclosure includes apparatuses and methods including stabilization of resistive memory. A number of embodiments include applying a programming signal to a resistive memory cell, wherein the programming signal includes a first portion having a first polarity and a second portion having a second polarity, wherein the second polarity is opposite the first polarity.. ... Micron Technology Inc

05/21/15 / #20150137867

Apparatuses and methods for duty cycle adjustment

Apparatuses and methods for duty cycle adjustment are disclosed herein. An example apparatus may include a node, a phase mixer, and a duty cycle adjuster circuit. ... Micron Technology Inc

05/21/15 / #20150137866

Apparatuses including scalable drivers and methods

Apparatuses and methods are described that include a plurality of drivers corresponding to a single via. A number of drivers can be selected to operate individually or together to drive a signal through a single via. ... Micron Technology Inc

05/21/15 / #20150137365

Semiconductor device assembly with through-package interconnect and associated systems, devices and methods

Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a spacer material on an encapsulant such that the encapsulant separates the spacer material from an active surface of a semiconductor device and at least one interconnect projecting away from the active surface. ... Micron Technology Inc

05/21/15 / #20150137364

Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices

Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices are described herein. In one embodiment, a set of stacked microelectronic devices includes (a) a first microelectronic die having a first side and a second side opposite the first side, (b) a first substrate attached to the first side of the first microelectronic die and electrically coupled to the first microelectronic die, (c) a second substrate attached to the second side of the first microelectronic die, (d) a plurality of electrical couplers attached to the second substrate, (e) a third substrate coupled to the electrical couplers, and (f) a second microelectronic die attached to the third substrate. ... Micron Technology Inc

05/21/15 / #20150137353

Under-bump metal structures for interconnecting semiconductor dies or packages and associated systems and methods

The present technology is directed to manufacturing semiconductor dies with under-bump metal (ubm) structures for die-to-die and/or package-to-package interconnects or other types of interconnects. In one embodiment, a method for forming under-bump metal (ubm) structures on a semiconductor die comprises constructing a ubm pillar by plating a first material onto first areas of a seed structure and depositing a second material over the first material. ... Micron Technology Inc

05/21/15 / #20150137333

Methods of selectively forming a material using a parylene coating and related semiconductor structures

Methods for depositing a material, such as a metal or a transition metal oxide, using an ald (atomic layer deposition) process and resulting structures are disclosed. Such methods include treating a surface of a semiconductor structure periodically throughout the ald process to regenerate a blocking material or to coat a blocking material that enables selective deposition of the material on a surface of a substrate. ... Micron Technology Inc

05/21/15 / #20150137331

Polymeric materials in self-assembled arrays and semiconductor structures and methods comprising such polymeric materials

Methods for fabricating sublithographic, nanoscale microstructures in line arrays utilizing self-assembling block copolymers, and films and devices formed from these methods are provided. Semiconductor structures may include self-assembled block copolymer materials in the form of lines of half-cylinders of a minority block matrix of a majority block of the block copolymer. ... Micron Technology Inc

05/21/15 / #20150137291

Magnetic memory cells and methods of formation

Methods of forming magnetic memory cells are disclosed. Magnetic and non-magnetic materials are formed into a primal precursor structure in an initial stress state of essentially no strain, compressive strain, or tensile strain. ... Micron Technology Inc

05/21/15 / #20150137254

Graded dielectric structures

Graded dielectric layers and methods of fabricating such dielectric layers provide dielectrics in a variety of electronic structures for use in a wide range of electronic devices and systems. In an embodiment, a dielectric layer is graded with respect to a doping profile across the dielectric layer. ... Micron Technology Inc

05/21/15 / #20150137214

Methods of forming semiconductor structures including bodies of semiconductor material

Semiconductor structures that include bodies of a semiconductor material spaced apart from an underlying substrate. The bodies may be physically separated from the substrate by at least one of a dielectric material, an open volume and a conductive material. ... Micron Technology Inc

05/21/15 / #20150137065

Memory cells and methods of forming memory cells

Some embodiments include memory cells which contain, in order; a first electrode material, a first metal oxide material, a second metal oxide material, and a second electrode material. The first metal oxide material has at least two regions which differ in oxygen concentration relative to one another. ... Micron Technology Inc

05/21/15 / #20150137063

Resistive switching in memory cells

Methods, devices, and systems associated with oxide based memory can include a method of forming a resistive switching region of a memory cell. Forming a resistive switching region of a memory cell can include forming a metal oxide material on an electrode and forming a metal material on the metal oxide material, wherein the metal material formation causes a reaction that results in a graded metal oxide portion of the memory cell.. ... Micron Technology Inc

05/21/15 / #20150137061

Cross-point memory and methods for fabrication of same

A method of fabricating a memory device is disclosed. In one aspect, the method comprises patterning a first conductive line extending in a first direction. ... Micron Technology Inc

05/07/15 / #20150127973

Apparatus and methods for providing data integrity

The present disclosure includes apparatus (e.g., computing systems, memory systems, controllers, etc.) and methods for providing data integrity. One or more methods can include, for example: receiving a number of sectors of data to be written to a number of memory devices; appending first metadata corresponding to the number of sectors and including first integrity data to the number of sectors, the first metadata has a particular format; generating second integrity data to be provided in second metadata, the second integrity data corresponding to at least one of the number of sectors (wherein the second metadata has a second format); and generating third integrity data to be provided in the second metadata, the third integrity data including error data corresponding to the second integrity data and the at least one of the number of sectors.. ... Micron Technology Inc

05/07/15 / #20150127892

Metadata storage associated with wear-level operation requests

A method includes responding to a wear-level operation request by copying data from a first portion of a first memory array to a second portion of the first memory array, and copying metadata associated with the data from a third portion of a second memory array to a fourth portion of the second memory array. The first memory array includes a nand or nand-based memory array, and the second memory array includes non-volatile memory including at least one of the group consisting of: phase-change memory, eeprom, and nor flash memory.. ... Micron Technology Inc

05/07/15 / #20150126016

Methods of forming capacitors

A method of forming capacitors includes forming support material over a substrate. A first capacitor electrode is formed within individual openings in the support material. ... Micron Technology Inc

05/07/15 / #20150125966

Stt-mram cell structures

A magnetic cell structure including a nonmagnetic bridge, and methods of fabricating the structure are provided. The magnetic cell structure includes a free layer, a pinned layer, and a nonmagnetic bridge electrically connecting the free layer and the pinned layer. ... Micron Technology Inc

05/07/15 / #20150124517

Apparatus and methods for forming a memory cell using charge monitoring

Apparatus and methods of forming a memory cell are described. In one such method, a forming charge applied to a memory cell, such as a resistive ram (rram) memory cell, is monitored to determine the progress of the forming the cell. ... Micron Technology Inc

05/07/15 / #20150123189

Methods and apparatuses having memory cells including a monolithic semiconductor channel

Methods for forming a string of memory cells, apparatuses having a string of memory cells, and systems are disclosed. One such method for forming a string of memory cells forms a source material over a substrate. ... Micron Technology Inc

05/07/15 / #20150123188

Methods and apparatuses having strings of memory cells including a metal source

Methods for forming a string of memory cells, an apparatus having a string of memory cells, and a system are disclosed. A method for forming the string of memory cells comprises forming a metal silicide source material over a substrate. ... Micron Technology Inc

05/07/15 / #20150123185

Methods for isolating portions of a loop of pitch-multiplied material and related structures

Different portions of a continuous loop of semiconductor material are electrically isolated from one another. In some embodiments, the end of the loop is electrically isolated from mid-portions of the loop. ... Micron Technology Inc

05/07/15 / #20150123070

Arrays of memory cells and methods of forming an array of vertically stacked tiers of memory cells

An array of vertically stacked tiers of memory cells includes a plurality of horizontally oriented access lines within individual tiers of memory cells and a plurality of horizontally oriented global sense lines elevationally outward of the tiers. A plurality of select transistors is elevationally inward of the tiers. ... Micron Technology Inc

05/07/15 / #20150123065

Memory cells and methods of forming memory cells

Some embodiments include a memory cell that has an electrode, a switching material over the electrode, a buffer region over the switching material, and an ion reservoir material over the buffer region. The buffer region includes one or more elements from group 14 of the periodic table in combination with one or more chalcogen elements. ... Micron Technology Inc

05/07/15 / #20150123064

Memory cells and methods of forming memory cells

Some embodiments include a memory cell having an electrode and a switching material over the electrode. The electrode is a first composition which includes a first metal and a second metal. ... Micron Technology Inc

04/30/15 / #20150121163

Memory system data management

. . The present disclosure includes apparatuses and methods for memory system data management. A number of embodiments include writing data from a host to a buffer in the memory system, receiving, at the buffer, a notification from a memory device in the memory system that the memory device is ready to receive data, sending at least a portion of the data from the buffer to the memory device, and writing the portion of the data to the memory device.. ... Micron Technology Inc

04/30/15 / #20150121128

Systems and methods for retrieving data

Apparatus and methods, such as those that read data from non-volatile integrated circuit memory devices, such as nand flash. For example, disclosed techniques can be embodied in a device driver of an operating system. ... Micron Technology Inc

04/30/15 / #20150120997

Semiconductor device including repeater circuit for main data line

A semiconductor memory disclosed in this disclosure includes first and second memory cell arrays, a first main data line that transfers the read data read from the first memory cell array, a second main data line that transfers the read data read from the second memory cell array, a main amplifier coupled to the second main data line, and a repeater circuit coupled to the first main data line and the second main data line.. . ... Micron Technology Inc

04/30/15 / #20150118844

Methods of forming patterns, and methods of forming integrated circuitry

Some embodiments include methods of forming a pattern. First lines are formed over a first material, and second lines are formed over the first lines. ... Micron Technology Inc

04/30/15 / #20150118821

Methods of forming semiconductor device structures, and methods of forming capacitor structures

A method of forming a semiconductor device structure comprises forming a mold template comprising trenches within a mold material. Structures are formed within the trenches of the mold template. ... Micron Technology Inc

04/30/15 / #20150118796

Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices

Microelectronic devices and method of forming a plurality of microelectronic devices on a semiconductor workpiece are disclosed herein. One such method includes placing a plurality of first interconnect elements on a side of a semiconductor workpiece, forming a layer on the side of the workpiece, reshaping the first interconnect elements by heating the first interconnect elements, and coupling a first portion of a plurality of individual second interconnect elements to corresponding first interconnect elements with a second portion of the individual second interconnect elements exposed.. ... Micron Technology Inc

04/30/15 / #20150117124

Data line control for sense amplifiers

Some embodiments include apparatuses and methods having a first data line, a second data line, a first transistor, a sense amplifier, and a circuit. The first transistor can operate to couple the first data line to a first node during a first stage of an operation of obtaining information from a memory cell associated with the first data line. ... Micron Technology Inc

04/30/15 / #20150117084

Multi-bit ferroelectric memory device and methods of forming the same

Multi-bit ferroelectric memory devices and methods of forming the same are provided. One example method of forming a multi-bit ferroelectric memory device can include forming a first ferroelectric material on a first side of a via, removing a material to expose a second side of the via, and forming second ferroelectric material on the second side of the via at a different thickness compared to the first side of the via.. ... Micron Technology Inc

04/30/15 / #20150116034

Input buffer apparatuses and methods

Apparatuses and methods are disclosed, including an apparatus with a first differential amplifier to amplify an input signal into a first output signal, a second differential amplifier to amplify the input signal into a second output signal that is complementary to the first output signal, and a feedback resistance coupled between the first output signal and the second output signal. Additional apparatuses and methods are described.. ... Micron Technology Inc

04/30/15 / #20150115445

Devices, systems and methods for manufacturing through-substrate vias and front-side structures

Methods of manufacturing semiconductor devices and semiconductor devices with through-substrate vias (tsvs). One embodiment of a method of manufacturing a semiconductor device includes forming an opening through a dielectric structure and at least a portion of a semiconductor substrate, and forming a dielectric liner material having a first portion lining the opening and a second portion on an outer surface of the dielectric structure laterally outside of the opening. ... Micron Technology Inc

04/30/15 / #20150115349

Methods of fabricating memory devices having charged species and methods of adjusting flatband voltage in such memory devices

Methods for fabricating memory devices having charged species, and methods for adjusting flatband voltages in such memory devices. In one such method, a dielectric material is formed adjacent to a semiconductor. ... Micron Technology Inc

04/30/15 / #20150114946

Thermal treatment of flash memories

A memory controller can provide current to a heater in a flash memory to reduce cycling induced errors. If necessary, after heating, the memory may be refreshed. ... Micron Technology Inc

04/23/15 / #20150113357

Data streaming for solid-state bulk storage devices

Methods facilitate data streaming in bulk storage devices by generating linked lists containing entries for both user data and metadata. These linked lists containing mixed data types facilitate receiving and outputting user data, and to insert or ignore, respectively, metadata corresponding to that user data without interrupting flow of the user data.. ... Micron Technology Inc

04/23/15 / #20150109867

Leakage measurement systems

Described examples include leakage measurement systems and methods for measuring leakage current between a word line at a boosted voltage and a word line at a supply voltage. The boosted voltage may be generated by charge pump circuitry. ... Micron Technology Inc

04/23/15 / #20150109866

Data paths using a first signal to capture data and a second signal to output data and methods for providing data

Data paths, memories, and methods for providing data from memory are disclosed. An example read data path includes a delay path, and a clocked data register. ... Micron Technology Inc

04/23/15 / #20150109042

Apparatuses and methods for changing signal path delay of a signal path responsive to changes in power

Apparatuses and methods for changing a signal path delay of a signal path responsive to changes in power provided to the signal path are disclosed. An example apparatus includes a signal path and signal path delay compensation circuit. ... Micron Technology Inc

04/23/15 / #20150109036

Methods and apparatuses for duty cycle preservation

Methods and apparatuses are disclosed for preserving duty cycle at voltage domain boundaries. One example apparatus includes a complement generation circuit configured to generate a complementary signal responsive to an input signal. ... Micron Technology Inc

04/23/15 / #20150108658

Self-aligned nano-structures

A method for creating structures in a semiconductor assembly is provided. The method includes etching apertures into a dielectric layer and applying a polymer layer over the dielectric layer. ... Micron Technology Inc

04/23/15 / #20150108637

Semiconductor device including two or more chips mounted over wiring substrate

A semiconductor device includes a composite chip mounted over the a wiring substrate, the composite chip including a first area and a second area that is provided independently from the first area, the first area including a first circuit formed in the first area, and the second area including a second circuit formed in the second area.. . ... Micron Technology Inc

04/23/15 / #20150108600

Method providing an epitaxial growth having a reduction in defects and resulting structure

Disclosed are methods and resulting structures which provide an opening for epitaxial growth, the opening having an associated projection for reducing the size of the contact area on a substrate at which growth begins. During growth, the epitaxial material grows vertically from the contact area and laterally over the projection. ... Micron Technology Inc

04/23/15 / #20150108596

Method providing an epitaxial photonic device having a reduction in defects and resulting structure

A method of forming a photonic device and resulting structure are described in which the photonic device is epitaxially grown over a substrate surface vertically, and laterally over trench isolation regions formed in the substrate surface.. . ... Micron Technology Inc

04/23/15 / #20150108566

Semiconductor device comprising a transistor gate having multiple vertically oriented sidewalls

A method used in fabrication of a recessed access device transistor gate has increased tolerance for mask misalignment. One embodiment of the invention comprises forming a vertical spacing layer over a semiconductor wafer, then etching the vertical spacing layer and the semiconductor wafer to form a recess in the wafer. ... Micron Technology Inc

04/23/15 / #20150108560

Vertical memory cell string with dielectric in a portion of the body

Some embodiments include a memory cell string having a body having a channel extending therein and in contact with a source/drain, a select gate adjacent to the body, a plurality of access lines adjacent to the body, and a dielectric in a portion of the body between the source/drain and a level corresponding to an end of the plurality of access lines most adjacent to the select gate. The dielectric in the portion of the body does not extend along an entire length of the body. ... Micron Technology Inc

04/23/15 / #20150108422

Double patterning method to form sub-lithographic pillars

A method and resulting structure, is disclosed to fabricate vertical bipolar junction transistors including a regular array of base contact pillars and emitter contact pillars with a at least one dimension below the minimum lithographical resolution, f, of the lithographic technique employed. A storage element, such as a phase change storage element, can be formed above the regular array of base contact pillars and emitter contact pillars.. ... Micron Technology Inc

04/16/15 / #20150106547

Distributed memory systems and methods

Apparatuses and methods are disclosed herein, including those that operate to receive memory requests from a processor over a high-speed communication interface and distribute the requests among a plurality of memory storage devices over lower-speed communication interfaces.. . ... Micron Technology Inc

04/16/15 / #20150103613

Memory devices and methods of operating the same

The present disclosure includes memory devices and methods of operating the same. One such device includes an array of groups of memory cells, a group selector configured to select a particular group of memory cells from within the array, and a cell selector configured to select a particular memory cell from within the selected particular group of memory cells.. ... Micron Technology Inc

04/16/15 / #20150103590

Memories and methods of operating memories having memory cells sharing a resistance variable material

Memories and methods of operating memories having memory cells sharing a resistance variable material.. . ... Micron Technology Inc

04/16/15 / #20150103578

Systems with memory segmentation and systems with biasing lines to receive same voltages during accessing

Memory devices, memory arrays, and methods of operation of memory arrays with segmentation. Segmentation elements can scale with the memory cells, and may be uni-directional or bi-directional diodes. ... Micron Technology Inc

04/16/15 / #20150102844

Apparatuses, methods, and circuits including a delay circuit

Apparatuses, methods, and delay circuits for delaying signals are described. An example apparatus includes a fine delay circuit configured to provide an output signal based on a ratio of a first input signal and a second input signal. ... Micron Technology Inc

04/16/15 / #20150102491

Semiconductor device including a contact plug with barrier materials

Disclosed herein is a semiconductor device that comprises a plug including an upper portion, a lower portion and a side surface and comprising tungsten, a barrier metal comprising tungsten nitride and covering the side surface and the lower portion of the contact plug, a conductive layer, and a barrier layer comprising titanium and intervening between the barrier metal and the first conductive layer.. . ... Micron Technology Inc

04/16/15 / #20150102460

Semiconductor structures including molybdenum nitride, molybdenum oxynitride or molybdenum-based alloy material, and method of making such structures

A semiconductor structure may include a first electrode over a substrate, a high-k dielectric material over the first electrode, and a second electrode over the high-k dielectric material, wherein at least one of the first electrode and the second electrode may include a material selected from the group consisting of a molybdenum nitride (moxny) material, a molybdenum oxynitride (mooxny) material, a molybdenum oxide (moox) material, and a molybdenum-based alloy material comprising molybdenum and nitrogen.. . ... Micron Technology Inc

04/09/15 / #20150100853

Apparatuses and methods for storing validity masks and operating apparatuses

Apparatuses and methods for storing a validity mask and operating apparatuses are described. A number of methods for operating an apparatus include storing a validity mask that is associated with a number of pages of memory cells in a group of pages and that provides validity information for the number of pages of memory cells in the group of pages.. ... Micron Technology Inc

04/09/15 / #20150100744

Methods and apparatuses for requesting ready status information from a memory

Methods and apparatuses are disclosed for requesting ready status information from a memory. One example apparatus includes a memory and a host coupled to the memory. ... Micron Technology Inc

04/09/15 / #20150099362

Methods of forming line patterns in substrates

A method including forming a line pattern in a substrate includes using a plurality of longitudinally spaced projecting features formed along respective guide lines as a template in forming a plurality of directed self-assembled (dsa) lines that individually comprise at least one of (a): the spaced projecting features and dsa material longitudinally there-between, and (b): are laterally between and laterally spaced from immediately adjacent of the guide lines. Substrate material elevationally inward of and laterally between the dsa lines may be processed using the dsa lines as a mask.. ... Micron Technology Inc

04/09/15 / #20150098295

Apparatuses and methods including selectively providing a single or separate chip select signals

Apparatus and methods are disclosed herein, including those that operate to initialize registers of a first memory device and a second memory device of a single-rank memory module by providing separate chip select signals to separately select a first memory device and a second memory device. A method may further include, subsequent to sensing that the initializing is completed, for example, providing a single chip select signal to simultaneously select the first memory device and the second memory device.. ... Micron Technology Inc

04/09/15 / #20150098291

Power consumption control

The present disclosure includes apparatuses and methods for power consumption control. A number of embodiments include determining power consumption information for each phase in a combination of phases of a command, and authorizing execution of at least one of the phases in the combination based, at least partially, on the power consumption information determined for the at least one of the phases.. ... Micron Technology Inc

04/09/15 / #20150098285

On-die termination apparatuses and methods

Apparatuses and methods are disclosed herein, including those, performed by a memory die, that operate to detect that a command on a bus connected to the memory die is addressed to another memory die responsive to a chip select signal, and to change the impedance of an on-die termination circuit of the memory die responsive to the detecting.. . ... Micron Technology Inc

04/09/15 / #20150098276

Memory and sense parameter determination methods

Memory devices and methods for operating a memory include filtering a histogram of sensed data of the memory, and adjusting a parameter used to sense the memory using the filtered histogram. Filtering can be accomplished by averaging or summing, and may include weighting the sums or averages.. ... Micron Technology Inc

04/09/15 / #20150098269

Read distribution management for phase change memory

Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a phase change memory.. . ... Micron Technology Inc

04/09/15 / #20150098260

Semiconductor memory device having main word lines and sub-word lines

A plurality of memory mats classified into groups selected by bits of a row address, a main word driver for selecting a main word line based on bits of the row address, an fx driver for selecting a word driver selecting line based on bits regardless of the bits of the row address, and a plurality of sub-word drivers selected by the main word line and the word driver selecting line to drive the corresponding sub-word line are arranged.. . ... Micron Technology Inc

04/09/15 / #20150097609

Apparatuses and methods for controlling delay circuits during an idle state to reduce degradation of an electrical characteristic

Apparatuses and method for controlling delay circuits during an idle state to reduce degradation of an electrical characteristic is disclosed. An example apparatus includes a delay line circuit including a plurality of delay stages, and further includes a delay line control circuit coupled to the delay line circuit. ... Micron Technology Inc

04/09/15 / #20150097604

Semiconductor device including a clock adjustment circuit

Disclosed herein is a semiconductor device that includes a first circuit comprising a plurality of first logic elements coupled in cascade and configured, in response to first and second clock signals and a control signal, to produce control information that indicates a first number of the first logic elements through which the control signal has been propagated during a period defined by a first change in logic level of the first clock signal and by a second change in logic level of the second clock signal, the first and second changes occurring adjacently to each other in same directions as each other, and a second circuit comprising a delay circuit configured to receive the first clock signal and the control information and to produce a third clock signal by delaying the first clock signal by an amount responsive to the control information.. . ... Micron Technology Inc

04/09/15 / #20150097301

Methods and structures for processing semiconductor devices

Methods of forming a semiconductor structure include exposing a carrier substrate to a silane material to form a coating, removing a portion of the coating at least adjacent a periphery of the carrier substrate, adhesively bonding another substrate to the carrier substrate, and separating the another substrate from the carrier substrate. The silane material includes a compound having a structure of (xo)3si(ch2)ny, (xo)2si((ch2)ny)2, or (xo)3si(ch2)ny(ch2)nsi(xo)3, wherein xo is a hydrolyzable alkoxy group, y is an organofunctional group, and n is a nonnegative integer. ... Micron Technology Inc

04/09/15 / #20150097139

Compositions for use in semiconductor devices

An improved composition and method for cleaning a surface of a semiconductor wafer are provided. The composition can be used to selectively remove a low-k dielectric material such as silicon dioxide, a photoresist layer overlying a low-k dielectric layer, or both layers from the surface of the wafer. ... Micron Technology Inc

04/02/15 / #20150095742

Multilevel encoding with error correction

Embodiments of the present disclosure provide methods, systems, and apparatuses related to multilevel encoding with error correction. In some embodiments, a plurality of bits may be encoded into a plurality of memory cells by level-shifting a subset of the plurality of multilevel memory cells for a bit of the plurality of bits. ... Micron Technology Inc

04/02/15 / #20150095560

Program-disturb management for phase change memory

Subject matter disclosed herein relates to a memory device, and more particularly to read or write performance of a phase change memory.. . ... Micron Technology Inc

04/02/15 / #20150095551

Volatile memory architecutre in non-volatile memory devices and related controllers

In some embodiments, one register of a non-volatile memory can be used for read operations and another register of the non-volatile memory can be used for programming operations. For instance, a cache register of a nand flash memory can be used in connection with read operations and a data register of the nand flash memory can be used in connection with programming operations. ... Micron Technology Inc

04/02/15 / #20150093892

Microelectronic devices with through-substrate interconnects and associated methods of manufacturing

Microelectronic devices with through-substrate interconnects and associated methods of manufacturing are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate carrying first and second metallization layers. ... Micron Technology Inc

04/02/15 / #20150093874

Methods of forming capacitors and semiconductor devices including a rutile titanium dioxide material

Methods of forming a capacitor including forming a titanium nitride material within at least one aperture defined by a support material, forming a ruthenium material within the at least one aperture over the titanium nitride material, and forming a first conductive material over the ruthenium material within the at least one aperture. The titanium nitride material may be oxidized to a titanium dioxide material. ... Micron Technology Inc

04/02/15 / #20150093869

Double gated 4f2 dram chc cell and methods of fabricating the same

A semiconductor device is provided that includes a fin having a first gate and a second gate formed on a first sidewall of the fin in a first trench, wherein the first gate is formed above the second gate. The device includes a third gate and a fourth gate formed on a second sidewall of the fin in a second trench, wherein the third gate is formed above the fourth gate. ... Micron Technology Inc

04/02/15 / #20150092503

Method and apparatus for memory command input and control

Memories containing command decoder, chip enable, and signal truncation circuits are disclosed. One such command decoder circuit may include command decoder logic configured to receive command signals and output a decoded command to an interconnect bus responsive to a chip select signal having an active state. ... Micron Technology Inc

04/02/15 / #20150092499

Slew rate modulation

Apparatus and methods may operate so that arrival times of a data signal at gates of transistors are controlled to switch the transistors at different times to modulate the slew rate of a signal on a node. Additional embodiments are also described.. ... Micron Technology Inc

04/02/15 / #20150092483

Modified reset state for enhanced read margin of phase change memory

Subject matter disclosed herein relates to techniques involving a structural relaxation (sr) phenomenon for increasing resistance of a reset state of phase change memory.. . ... Micron Technology Inc

04/02/15 / #20150092470

Configurable reference current generation for non volatile memory

This disclosure relates to generating a reference current for a memory device. In one aspect, a non-volatile memory device, such as a phase change memory device, can determine a value of a data digit, such as a bit, stored in a non-volatile memory cell based at least partly on the reference current. ... Micron Technology Inc

04/02/15 / #20150091624

System and method for an accuracy-enhanced dll during a measure initialization mode

A clock generator having a delay locked loop and a delay control circuit. The delay locked loop receives an input clock signal and adjusts an adjustable delay circuit to generate an output clock signal that is synchronized with received input clock signal. ... Micron Technology Inc

04/02/15 / #20150091189

Apparatuses and methods enabling concurrent communication

Various embodiments include apparatuses having stacked devices and methods of forming dice stacks on an interface die. In one such apparatus, a dice stack includes at least a first die and a second die, and conductive paths coupling the first die and the second die to the common control die. ... Micron Technology Inc

04/02/15 / #20150091166

Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods

Microelectronic die packages, stacked systems of die packages, and methods of manufacturing them are disclosed herein. In one embodiment, a system of stacked packages includes a first die package having a bottom side, a first dielectric casing, and first metal leads; a second die package having a top side attached to the bottom side of the first package, a dielectric casing with a lateral side, and second metal leads aligned with and projecting towards the first metal leads and including an exterior surface and an interior surface region that generally faces the lateral side; and metal solder connectors coupling individual first leads to individual second leads. ... Micron Technology Inc

04/02/15 / #20150091137

Methods of forming nanostructures including metal oxides and semiconductor structures including same

A method of forming nanostructures may include forming a block copolymer composition within a trench in a material on a substrate, wherein the block copolymer composition may comprise a block copolymer material and an activatable catalyst having a higher affinity for a first block of the block copolymer material compared to a second block of the block copolymer material; self-assembling the block copolymer composition into first domains comprising the first block and the activatable catalyst, and second domains comprising the second block; generating catalyst from the activatable catalyst in at least one portion of the first domains to produce a structure comprising catalyst-containing domains and the second domains, the catalyst-containing domains comprising the first block and the catalyst; and reacting a metal oxide precursor with the catalyst in the catalyst-containing domains to produce a metal oxide-containing structure comprising the first block and metal oxide.. . ... Micron Technology Inc

04/02/15 / #20150091128

Forming three dimensional isolation structures

A three dimensional shallow trench isolation structure including sets of parallel trenches extending in two perpendicular directions may be formed by depositing a conformal deposition in a first set of parallel trenches, oxidizing the second set of trenches to enable selective deposition in said second set of trenches and then conformally depositing in said second set of trenches. In some embodiments, only one wet anneal, one etch back, and one high density plasma chemical vapor deposition step may be used to fill both sets of trenches.. ... Micron Technology Inc

04/02/15 / #20150090956

Engineered substrate assemblies with thermally opaque materials, and associated systems, devices, and methods

Engineered substrates having thermally opaque materials for preventing transmission of radiative energy during epitaxial growth processes and for separating substrates from epitaxially grown semiconductor structures and associated systems and methods are disclosed herein. In several embodiments, for example, an engineered substrate can be manufactured by forming a thermally opaque material at an upper surface of a handle substrate and bonding an epitaxial formation structure on the handle substrate such that the thermally opaque material is between the epitaxial formation structure and the handle substrate. ... Micron Technology Inc

03/26/15 / #20150089316

Circuits, apparatuses, and methods for correcting data errors

Circuits, apparatuses, and methods are disclosed for correcting data errors in integrated circuits. One example apparatus includes a first circuit configured to receive first and second data words, to correct one or more errors in the first data word, to merge the corrected first data word and the second data word responsive to a control signal to generate a final merged data word, and to provide the final merged data word to a write circuit. ... Micron Technology Inc

03/26/15 / #20150087147

Methods of forming through substrate interconnects

A method of forming a through substrate interconnect includes forming a via into a semiconductor substrate. The via extends into semiconductive material of the substrate. ... Micron Technology Inc

03/26/15 / #20150085968

Identifying stacked dice

Various embodiments comprise apparatuses to assign unique device identifier values to addressable devices in a stacked package. In one embodiment, an apparatus is disclosed including a stacked package with at least two addressable devices. ... Micron Technology Inc

03/26/15 / #20150085581

Non-volatile memory programming

Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method can include applying a signal to a line associated with a memory cell, the signal being generated based on digital information. ... Micron Technology Inc

03/26/15 / #20150085578

Method and system for programming non-volatile memory cells based on programming of proximate memory cells

A multi-level non-volatile memory device programs cells in each row in a manner that takes into account the coupling from the programming of cells that are proximate the row to be programmed. In one example of the invention, after the row has been programmed, the proximate cells are verified by read, comparison, and, if necessary, reprogramming operations to compensate for charge added to proximate memory cells resulting from programming the row. ... Micron Technology Inc

03/26/15 / #20150085565

Cross-point memory cells, non-volatile memory arrays, methods of reading a memory cell, methods of programming a memory cell, methods of writing to and reading from a memory cell, and computer systems

Cross-point memory cells, non-volatile memory arrays, methods of reading a memory cell, methods of programming a memory cell, and methods of writing to and reading from a memory cell are described. In one embodiment, a cross-point memory cell includes a word line extending in a first direction, a bit line extending in a second direction different from the first direction, the bit line and the word line crossing without physically contacting each other, and a capacitor formed between the word line and the bit line where such cross. ... Micron Technology Inc

03/26/15 / #20150085561

Semiconductor device and write method

A semiconductor device includes a memory cell array including a plurality of first and second memory cells each comprising a variable resistance element that establishes an electrical resistance that changes in response to an application of a write voltage after a forming voltage has been applied, the first memory cell to which the forming voltage is applied, and the second memory cell to which the forming voltage is not applied, and the second memory cell being configured to store one of first and second logic values constituting first information, the first and second logic values being different from each other.. . ... Micron Technology Inc

03/26/15 / #20150084677

Apparatuses and methods for mitigating uneven circuit degradation of delay circuits

Apparatuses and methods for mitigating uneven circuit degradation of delay circuits are disclosed. In an example method, an imbalance in transistor threshold voltages is detected between a transistor of a first delay circuit and a transistor of a second delay circuit that is series coupled to the first delay circuit, and a clock level of an input clock signal to the first delay circuit is switched responsive to detecting the imbalance.. ... Micron Technology Inc

03/26/15 / #20150084187

Methods of forming hydrophobic surfaces on semiconductor device structures, methods of forming semiconductor device structures, and semiconductor device structures

A method of forming a hydrophobic surface on a semiconductor device structure. The method comprises forming at least one structure having at least one exposed surface comprising titanium atoms. ... Micron Technology Inc

03/26/15 / #20150084156

Memory cell with independently-sized electrode

Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element. ... Micron Technology Inc

03/26/15 / #20150084122

Semiconductor device

A semiconductor device has an active region defined by a device isolation region arranged on a surface of a semiconductor substrate, a plurality of transistor pillars arranged along a first direction within the active region, and a first dummy pillar disposed in the device isolation region. The first dummy pillar is arranged on a line extending along the first direction from the transistor pillars. ... Micron Technology Inc

03/26/15 / #20150083986

Methods of forming semiconductor devices and structures with improved planarization uniformity, and resulting structures and semiconductor devices

Semiconductor devices and structures, such as phase change memory devices, include peripheral conductive pads coupled to peripheral conductive contacts in a peripheral region. An array region may include memory cells coupled to conductive lines. ... Micron Technology Inc

03/19/15 / #20150082106

Memory devices, testing systems and methods

Testing systems and methods, as well as memory devices using such testing systems and methods, may facilitate testing of memory devices using a read-modify-write test procedure. One such testing system receives a signal indicative of at least some of a plurality of bits of data read from an address differing from each other, and then masks subsequent write operations at the same address. ... Micron Technology Inc

03/19/15 / #20150082104

Autorecovery after manufacturing/system integration

Memory devices storing particular data, systems containing such memory devices and methods of testing such memory devices. The memory devices include an array of memory cells containing particular data, and control circuitry configured to control operations of the array of memory cells. ... Micron Technology Inc

03/19/15 / #20150081998

Block-based storage device with a memory-mapped interface

Described herein are methods for accessing a block-based storage device having a memory-mapped interface and a block interface. In one embodiment, an apparatus (e.g., block-based storage device) includes a storage array to store data and a memory-mapped interface that is coupled to the storage array. ... Micron Technology Inc

03/19/15 / #20150081957

Outputting a particular data quantization from memory

The present disclosure includes methods, devices, and systems for outputting data particular quantization of data from memory devices and systems. Outputting data particular quantization of data can include enabling a particular one of a plurality of different quantizations of data. ... Micron Technology Inc

03/19/15 / #20150079756

Semiconductor device and fabrication method thereof

The semiconductor device fabrication method of the present invention includes: laminating a plurality of amorphous silicon films on a semiconductor substrate, forming through-holes that pass through the plurality of amorphous silicon films, and subjecting the plurality of amorphous silicon films 301 that include the through-holes to an etching process that uses an alkaline aqueous solution; wherein the plurality of amorphous silicon films is formed to include a first amorphous silicon film and a second amorphous silicon film in which the rate of etching by using the alkaline aqueous solution is slower than that of the first amorphous silicon film and the first amorphous silicon film is interposed between the semiconductor substrate and the second amorphous silicon film.. . ... Micron Technology Inc

03/19/15 / #20150078108

Data shifting via a number of isolation devices

The present disclosure includes apparatuses and methods related to data shifting. An example apparatus comprises a first memory cell coupled to a first sense line of an array, a first isolation device located between the first memory cell and first sensing circuitry corresponding thereto, and a second isolation device located between the first memory cell and second sensing circuitry corresponding to a second sense line. ... Micron Technology Inc

03/19/15 / #20150078101

Methods and apparatuses for alternate clock selection

Apparatuses and methods are disclosed, such as those including an oscillator circuit that generates an alternate clock. A multiplexing circuit can be coupled to the alternate clock and an input clock. ... Micron Technology Inc

03/19/15 / #20150078099

Sensing data stored in memory

The present disclosure includes apparatuses and methods for sensing data stored in memory. A number of embodiments include an array of memory cells, and a controller coupled to the array and configured to sense a page of memory cells coupled to an activated access line by pre-charging only a single subset of a number of data lines coupled to the page, wherein more than two subsets of data lines are coupled to the page and the single subset is coupled to those memory cells storing at least a portion of a single sector of data of the page, and sensing the single subset of the number of data lines to determine the at least a portion of the single sector of data.. ... Micron Technology Inc

03/19/15 / #20150078089

Methods and apparatuses having strings of memory cells and select gates with double gates

An apparatus, a method, and a system are disclosed. The apparatus includes a string of memory cells coupled to a select gate drain transistor that has a front control gate and a back control gate. ... Micron Technology Inc

03/19/15 / #20150078073

Unidirectional spin torque transfer magnetic memory cell structure

Spin torque transfer magnetic random access memory devices configured to be programmed unidirectionally and methods of programming such devices. The devices include memory cells having two pinned layers and a free layer therebetween. ... Micron Technology Inc

03/19/15 / #20150078056

Arrays of nonvolatile memory cells

Disclosed is an array of nonvolatile memory cells includes five memory cells per unit cell. Also disclosed is an array of vertically stacked tiers of nonvolatile memory cells that includes five memory cells occupying a continuous horizontal area of 4f2 within an individual of the tiers. ... Micron Technology Inc

03/19/15 / #20150077182

Apparatuses and methods for input buffer having combined output

Apparatuses and methods are disclosed, including an apparatus that includes a first differential amplifier to amplify a difference between an input signal and a reference signal, and a second differential amplifier to amplify the difference between the input signal and the reference signal. The apparatus may further include an inverter circuit to receive an output signal of the first differential amplifier and another inverter circuit to receive an output signal of the second differential amplifier. ... Micron Technology Inc

03/19/15 / #20150076679

Semiconductor device assemblies including face-to-face semiconductor dice and related methods

Methods of manufacturing semiconductor device assemblies include attaching a back side of a first semiconductor die to a substrate and structurally and electrically coupling a first end of laterally extending conductive elements to conductive terminals on or in a surface of the substrate. Second ends of the laterally extending conductive elements are structurally and electrically coupled to bond pads on or in an active surface of the first semiconductor die. ... Micron Technology Inc

03/19/15 / #20150076663

Patterned bases, and patterning methods

Some embodiments include methods of patterning a base. First and second masking features are formed over the base. ... Micron Technology Inc

03/19/15 / #20150076633

Memory cells, methods of fabrication, and semiconductor devices

A magnetic cell includes an attracter material proximate to a magnetic region (e.g., a free region). The attracter material is formulated to have a higher chemical affinity for a diffusible species of a magnetic material, from which the magnetic region is formed, compared to a chemical affinity between the diffusible species and at least another species of the magnetic material. ... Micron Technology Inc

03/19/15 / #20150076485

Memory cells, methods of fabrication, semiconductor devices, memory systems, and electronic systems

A magnetic cell includes a free region between an intermediate oxide region (e.g., a tunnel barrier) and a secondary oxide region. Both oxide regions may be configured to induce magnetic anisotropy (“ma”) with the free region, enhancing the ma strength of the free region. ... Micron Technology Inc

03/19/15 / #20150076437

Methods of forming a ferroelectric memory cell and related semiconductor device structures

A method of forming a ferroelectric memory cell. The method comprises forming an electrode material exhibiting a desired dominant crystallographic orientation. ... Micron Technology Inc

03/19/15 / #20150076436

Methods of forming semiconductor device structures, and related semiconductor device structures

A method of forming a semiconductor device structure. The method comprises forming a block copolymer assembly comprising at least two different domains over an electrode. ... Micron Technology Inc

03/19/15 / #20150075427

Porous organosilicate layers, and vapor deposition systems and methods for preparing same

A vapor deposition system includes a deposition chamber having a substrate positioned therein. The system includes at least one vessel containing at least one silsequioxane precursor. ... Micron Technology Inc

03/12/15 / #20150074498

Apparatuses and methods for combining error coding and modulation schemes

Methods and apparatuses for combining error coding and modulation schemes are described herein. One or more methods include encoding data using linear error correcting code, modulating the encoded data, writing the modulated data to memory, and decoding the written data using a viterbi algorithm and a linear error correcting code decoder.. ... Micron Technology Inc

03/12/15 / #20150074493

Semiconductor device and error correction method

A device is provided with: memory cell array including plurality of first and second memory cells and one or more third memory cells; judging circuit that judges plurality of data values held by selected first and second memory cells of the first and second memory cells, by referring to reference potential corresponding to reference data held by a selected third memory cell; and error detection and correction circuit that detects whether or not there is error in the judged data values of the first and/or second memory cells, with judged data value of the first and second memory cells as error correcting code. When the error detection and correction circuit detects that there is error exceeding error correction capability in the judged data values, control is performed to write reference data to the selected third memory cell.. ... Micron Technology Inc

03/12/15 / #20150074370

Methods of accessing memory cells, methods of distributing memory requests, systems, and memory controllers

Methods of accessing memory cells, methods of distributing memory requests, systems, and memory controllers are described. In one such method, where memory cells are divided into at least a first region of memory cells and a second region of memory cells, memory cells in the first region are accessed according to a first address definition and memory cells in the second region are accessed according to a second address definition that is different from the first address definition. ... Micron Technology Inc

03/12/15 / #20150074326

Accessing memory cells in parallel in a cross-point array

Methods and structures for accessing memory cells in parallel in a cross-point array include accessing in parallel a first memory cell disposed between a first selected column and a first selected row and a second memory cell disposed between a second selected column different from the first selected column and a second selected row different from the first selected row. Accessing in parallel includes simultaneously applying access biases between the first selected column and the first selected row and between the second selected column and the second selected row. ... Micron Technology Inc

03/12/15 / #20150072523

Methods of forming diodes

Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is deposited along an undulating topography that extends across the pedestal and base, and a second electrode is formed over the least one layer. ... Micron Technology Inc

03/12/15 / #20150072512

Methods and apparatuses including strings of memory cells formed along levels of semiconductor material

Various embodiments include methods and apparatuses including strings of memory cells formed along levels of semiconductor material. One such apparatus includes a stack comprised of a number of levels of single crystal silicon and a number of levels of dielectric material. ... Micron Technology Inc

03/12/15 / #20150071022

Apparatuses and methods for providing active and inactive clock signals to a command path circuit

Apparatuses and methods for providing active and inactive clock signals to a command path circuit are described. An example method includes providing an active clock signal to a command path for a first portion of a command cycle for a command of back-to-back commands. ... Micron Technology Inc

03/12/15 / #20150071012

Supply independent delayer

Electronic apparatus, systems, and methods can include a delayer having an inverter chain, where each inverter of the chain can be operatively regulated using current generators to control variation of the delay time of the delayer. In various embodiments, current generators can be arranged to provide reference voltages to each inverter stage of an inverter chain. ... Micron Technology Inc

03/12/15 / #20150070972

Memory sense amplifiers and memory verification methods

Memory sense amplifiers and memory verification methods are described. According to one aspect, a memory sense amplifier includes a first input coupled with a memory element of a memory cell, wherein the memory element has different memory states at different moments in time, a second input configured to receive a reference signal, modification circuitry configured to provide a data signal at the first input from the memory element having a plurality of different voltages corresponding to respective ones of different memory states of the memory cell at the different moments in time, and comparison circuitry coupled with the modification circuitry and configured to compare the data signal and the reference signal at the different moments in time and to provide an output signal indicative of the memory state of the memory cell at the different moments in time as a result of the comparison to implement a plurality of verify operations of the memory states of the memory cell at the different moments in time.. ... Micron Technology Inc

03/12/15 / #20150070960

Interconnection for memory electrodes

Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central points along adjacent lines that are not terminated are made in the gap, and vertical interconnection through can additionally be made through the gap without contacting the lines of that level.. ... Micron Technology Inc

03/12/15 / #20150070056

Apparatuses and related methods for staggering power-up of a stack of semiconductor dies

An apparatus including semiconductor dies in a stack. The semiconductor dies are configured to power-up in a staggered manner. ... Micron Technology Inc

03/12/15 / #20150070052

Reference voltage generator for single-ended communication systems

An improved reference voltage (vref) generator for a single-ended receiver in a communication system is disclosed. The vref generator in one example comprises a cascoded current source for providing a current, i, to a resistor, rb, to produce the vref voltage (i*rb). ... Micron Technology Inc

03/12/15 / #20150070049

Apparatus and methods for leakage current reduction in integrated circuits

This disclosure relates to leakage current reduction in integrated circuits (ics). In one aspect, an ic can include a digital logic circuit and a polarization circuit. ... Micron Technology Inc

03/12/15 / #20150069630

Memory cell formed by improved cmp process

Memory cell array architectures and methods of forming the same are provided. An example method for forming an array of memory cells can include forming a plurality of vertical structures each having a switch element in series with a memory element in series with a top electrode, and forming an interconnection conductive material between the respective top electrodes of the plurality of vertical structures. ... Micron Technology Inc

03/12/15 / #20150069562

Magnetic tunnel junctions and methods of forming magnetic tunnel junctions

A method of forming a line of magnetic tunnel junctions includes forming magnetic recording material over a substrate, non-magnetic material over the recording material, and magnetic reference material over the non-magnetic material. The substrate has alternating outer regions of reactant source material and insulator material along at least one cross-section. ... Micron Technology Inc

03/12/15 / #20150069519

Semiconductor device

A semiconductor device includes a first transistor having a gate, a source/drain and a drain/source coupled to a first node, a first power and the first node, respectively; a second transistor having a gate, a source/drain and a drain/source coupled to the first node, the first power and a third node, respectively; a third transistor having a gate, a source/drain and a drain/source coupled to a reference, a second node and the first node, respectively; a fourth transistor having a gate, a source/drain and a drain/source coupled to an input, the second node and the third node, respectively; a fifth transistor having a gate, a source/drain and a drain/source coupled to the first node, a second power and the second node, respectively; and a sixth transistor having a gate, a source/drain and a drain/source coupled to the reference, the second power and the second node, respectively.. . ... Micron Technology Inc

03/12/15 / #20150069505

Semiconductor structures

Methods of pitch doubling of asymmetric features and semiconductor structures including the same are disclosed. In one embodiment, a single photolithography mask may be used to pitch double three features, for example, of a dram array. ... Micron Technology Inc

03/12/15 / #20150069502

Semiconductor device

A semiconductor device includes an active region which is surrounded by a device isolation region on a semiconductor substrate and which extends in a first direction; a silicon pillar which separates the active region along the first direction into a first lower diffusion layer and a second lower diffusion layer; a first gate electrode covering a first side face of the silicon pillar which is located on a side of the first lower diffusion layer; a second gate electrode covering a second side face of the silicon pillar which is located on a side of the second lower diffusion layer; a conductive layer provided on a top face of the silicon pillar; and a device isolation insulating film contacting with a third side face of the silicon pillar which is different from the first side face and the second side face.. . ... Micron Technology Inc

03/12/15 / #20150069482

Dram arrays, semiconductor constructions and dram array layouts

Some embodiments include a dram array layout. Wordlines extend along a first direction, and bitlines extend along a second direction that crosses the first direction. ... Micron Technology Inc

03/05/15 / #20150067292

Impedance adjustment in a memory device

Methods and apparatus for impedance adjustment operations in memory devices are disclosed. One such method includes adjusting an impedance of a particular driver circuit of a particular memory device to a desired impedance, determining configuration information corresponding to a configuration of the particular driver circuit adjusted to the desired impedance, transferring the configuration information to a different memory device and configuring an impedance of a driver circuit of the different memory device responsive to the configuration information.. ... Micron Technology Inc

03/05/15 / #20150067254

Multi-interface memory with access control

Subject matter disclosed herein relates to a memory device, and more particularly to a multi-channel memory device and methods of selecting one or more channels of same.. . ... Micron Technology Inc

03/05/15 / #20150067232

Sub-sector wear leveling in memories

Methods and memories for wear leveling by sub-sectors of a block are provided. In one such method, data are transferred from a first block of the memory to a second block of the memory, excluding a sub-sector of the first block that is to be erased, logical addresses for the first block and the second block are swapped with each other, the first block is erased, data are transferred from a third block to the first block, logical addresses for the first block and the third block are swapped with each other, and the third block is erased.. ... Micron Technology Inc

03/05/15 / #20150064871

Forming source/drain zones with a delectric plug over an isolation region between active regions

An embodiment includes forming an isolation region between first and second active regions in a semiconductor, forming an opening between the first and second active regions by removing a portion of the isolation region, and forming a dielectric plug within the opening so that the dielectric plug is between the first and second active regions and so that a portion of the dielectric plug extends below upper surfaces of the first and second active regions. The dielectric plug may be formed of a dielectric material having a lower removal rate than a dielectric material of the isolation region for a particular isotropic removal chemistry.. ... Micron Technology Inc

03/05/15 / #20150063826

Optical waveguide with cascaded modulator circuits

An optical waveguide for transmitting an optical signal input to the optical waveguide with a first frequency. The optical waveguide includes a plurality of modulator circuits configured along an optical transmission channel. ... Micron Technology Inc

03/05/15 / #20150063052

Independently addressable memory array address spaces

Examples of the present disclosure provide devices and methods for accessing a memory array address space. An example memory array comprising a first address space comprising memory cells coupled to a first number of select lines and to a number of sense lines and a second address space comprising memory cells coupled to a second number of select lines and to the number of sense lines. ... Micron Technology Inc

03/05/15 / #20150063043

Apparatuses and methods for providing strobe signals to memories

Apparatuses and methods for providing strobe signals to memories are described herein. An example apparatus may include a plurality of memories and a memory controller. ... Micron Technology Inc

03/05/15 / #20150063035

Memory device biasing method and apparatus

Memory devices and methods are disclosed, such as those facilitating data line shielding by way of capacitive coupling with data lines coupled to a memory string source line. For example, alternating data lines are sensed while adjacent data lines are coupled to a common source line of the data lines being sensed. ... Micron Technology Inc

03/05/15 / #20150063031

Dynamic program window determination in a memory device

A memory device has an array of memory cells and a controller coupled to the array of memory cells. The controller is configured to determine a program window after a portion of a particular programing operation performed on the memory device is performed and before a subsequent portion of the particular programing operation performed on the memory device is performed. ... Micron Technology Inc

03/05/15 / #20150063026

Continuous adjusting of sensing voltages

The present disclosure includes apparatuses and methods for continuous adjusting of sensing voltages. A number of embodiments include continuously monitoring an error rate associated with sense operations performed on a group of memory cells, and continuously adjusting a sensing voltage used to determine a state of the memory cells of the group based, at least partially, on the error rate.. ... Micron Technology Inc

03/05/15 / #20150063024

Memory devices with local and global devices at substantially the same level above stacked tiers of memory cells and methods

In an embodiment, a memory device includes a stack of tiers of memory cells, a tier of local devices at a level above the stack of tiers of memory cells, and a tier of global devices at substantially a same level as the tier of local devices. A local device may provide selective access to a data line. ... Micron Technology Inc

03/05/15 / #20150063022

Apparatuses and methods involving accessing distributed sub-blocks of memory cells

Apparatuses and methods involving accessing distributed sub-blocks of memory cells are described. In one such method, distributed sub-blocks of memory cells in a memory array are enabled to be accessed at the same time. ... Micron Technology Inc

03/05/15 / #20150063020

Semiconductor device

A method includes measuring a first pulse width of a resistance variable memory cell coupled between a first terminal and a second terminal, the first pulse width including a period from starting a first data writing of the resistance variable memory cell by applying a voltage between the first and second terminals to ending the first data writing of the resistance variable memory cell, and measuring a second pulse width of the resistance variable memory cell coupled between the first and the second terminal. The method includes setting longer one of the first and second pulse widths in a first storage area as a pulse width to be used in program.. ... Micron Technology Inc

03/05/15 / #20150063003

Semiconductor device

A semiconductor device including: a resistive memory element; a data line electrically coupled to the resistive memory element; a control line; a power supply line; and a control circuit including a first constant current element, a first transistor, and a second transistor. In the control circuit, the first transistor has a gate coupled to the data line, one of a source and a drain coupled to the first constant current element, and the other one of the source and the drain coupled to the power supply line. ... Micron Technology Inc

03/05/15 / #20150063001

Semiconductor device

Disclosed herein is a semiconductor device that includes a plurality of memory cells assigned with addresses that are different from each other, a redundant memory cell replacing a defective memory cell among the memory cells, a fuse circuit storing an address of the defective memory cell, an access control circuit accessing the redundant memory cell when the address of the defective memory cell stored in the fuse circuit is supplied, and a roll call circuit outputting the address of the defective memory cell to outside the semiconductor device in a serial manner.. . ... Micron Technology Inc

03/05/15 / #20150063000

Semiconductor device and control method of the same

A semiconductor device comprises a bit determination circuit to count the number of bits at a first level in an input address signal formed of a plurality of bits and to output a result indicating whether or not a value of the count exceeds a predetermined determination threshold value, as a bit determination result signal, and a selection control circuit to select a non-volatile program element to be cut off, based on the bit determination result signal and the address signal. Additional apparatus and methods are described.. ... Micron Technology Inc

03/05/15 / #20150061722

Semiconductor device

Disclosed herein is an apparatus that includes a first internal-potential generation circuit that generates a first internal potential from a power supply potential and that outputs the first internal potential to a first node, and an internal-potential force circuit that includes a first switch element provided between the first node and a second external terminal. The internal-potential force circuit causes the first switch element to enter into an off-state when the test signal supplied to a third external terminal is activated and a potential level of a first external terminal is a first level, and causes the first switch element to enter into an on-state when the test signal supplied to the third external terminal is activated and the potential level of the first external terminal is a second level different from the first level.. ... Micron Technology Inc

03/05/15 / #20150061138

Method of forming a memory device

A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication.. ... Micron Technology Inc

03/05/15 / #20150060970

Semiconductor device including contact plugs and conductive layers thereon

Disclosed herein is a device that includes: a semiconductor substrate; a first insulating layer over a surface of the semiconductor substrate; first and second contact plugs each including side and upper surfaces, the side surfaces of the first and second contact plugs being surrounded by the first insulating film, the upper surfaces of the first and second contact plugs being substantially on the same plane with an upper surface of the first insulating layer; a second insulating layer over the first insulating layer; a first conductive layer including a bottom portion on the first contact plug and a side portion surrounded by the second insulating layer; a third insulating layer over the first conductive layer; and a second conductive layer on the second contact plug, apart of a side surface of the second conductive layer being surrounded by both the second and third insulating layers.. . ... Micron Technology Inc

03/05/15 / #20150060754

Memory devices having electrodes comprising nanowires, systems including same and methods of forming same

Memory devices having memory cells comprising variable resistance material include an electrode comprising a single nanowire. Various methods may be used to form such memory devices, and such methods may comprise establishing contact between one end of a single nanowire and a volume of variable resistance material in a memory cell. ... Micron Technology Inc

03/05/15 / #20150060751

Memory cells with recessed electrode contacts

Memory cells with recessed electrode contacts and methods of forming the same are provided. An example memory cell can include an electrode contact formed in a substrate. ... Micron Technology Inc

02/26/15 / #20150058656

Methods and apparatuses for master-slave detection

Apparatuses, master-slave detect circuits, memories, and methods are disclosed. One such method includes performing a master detect phase during which a memory unit in a memory group is determined to be a master memory unit, determining at each memory unit its location relative to other memory units, and determining at each memory unit its location in the memory group based on a total number of slave memory units and its location relative to other memory units.. ... Micron Technology Inc

02/26/15 / #20150058644

Systems, methods and devices for limiting current consumption upon power-up

Embodiments are described including those for controlling peak current consumption of a multi-chip memory package during power-up. In one embodiment, each memory device of the multi-chip package includes a power level detector used to compare an internal voltage signal to a threshold. ... Micron Technology Inc

02/26/15 / #20150056798

Methods of forming metal oxide

Some embodiments include methods of forming memory cells. Metal oxide may be deposited over a first electrode, with the deposited metal oxide having a relatively low degree of crystallinity. ... Micron Technology Inc

02/26/15 / #20150055431

Methods and apparatuses including transmitter circuits

Methods and apparatuses are disclosed for transmitter circuits. One example apparatus includes a pre-driver circuit configured to provide a transition control signal responsive to received data, and a main driver circuit configured to drive an output node responsive to the transition control signal. ... Micron Technology Inc

02/26/15 / #20150055420

Apparatuses and methods for selective row refreshes

Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. ... Micron Technology Inc

02/26/15 / #20150055408

Verify or read pulse for phase change memory and switch

Embodiments disclosed herein may relate to applying verify or read pulses for phase change memory and switch (pcms) devices. The read pulses may be applied at a first voltage for a first period of time. ... Micron Technology Inc

02/26/15 / #20150055394

Semiconductor device

A semiconductor device comprises a semiconductor substrate including first and second regions that have different conductivity types from each other; an isolation region extending continuously over the first and second regions and having a shallow trench covered by a field insulator; first and second active regions placed in respective first and second regions and being each surrounded by the isolation region; a gate electrode disposed in a lower portion of a gate groove that extends continuously from the first active region to the second active region via the isolation region, the gate groove being shallower than the shallow trench; a cap insulating film disposed in an upper portion of the gate groove so as to cover an upper surface of the gate electrode; first and second transistors placed in respective first and second active regions and sharing the gate electrode; and a logic circuit including the first and second transistors connected in series.. . ... Micron Technology Inc

02/26/15 / #20150054168

Single spacer process for multiplying pitch by a factor greater than two and related intermediate ic structures

Single spacer processes for multiplying pitch by a factor greater than two are provided. In one embodiment, n, where n≧2, tiers of stacked mandrels are formed over a substrate, each of the n tiers comprising a plurality of mandrels substantially parallel to one another. ... Micron Technology Inc

02/26/15 / #20150054164

Semiconductor constructions

Some embodiments include semiconductor constructions having first and second electrically conductive lines that intersect with one another at an intersection. The first line has primarily a first width, and has narrowed regions directly against the second line and on opposing sides of the second line from one another. ... Micron Technology Inc

02/26/15 / #20150054160

Semiconductor constructions and methods of forming electrically conductive contacts

Some embodiments include methods of forming electrically conductive contacts. An opening is formed through an insulative material to a conductive structure. ... Micron Technology Inc

02/26/15 / #20150054133

Techniques for providing a direct injection semiconductor memory device

Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for biasing a direct injection semiconductor memory device. ... Micron Technology Inc

02/26/15 / #20150054127

Multi-material structures, semiconductor constructions and methods of forming capacitors

Some embodiments include a method of forming a capacitor. An opening is formed through a silicon-containing mass to a base, and sidewalls of the opening are lined with protective material. ... Micron Technology Inc

02/26/15 / #20150054086

Semiconductor device and method for manufacturing same

A semiconductor device includes a first well and a second well provided within a semiconductor substrate, an isolation region disposed between the first well and the second well within the semiconductor substrate, a first wiring disposed on the first well, a second wiring disposed on the second well, a concave third wiring disposed on the isolation region, a buried insulating film disposed on the third wiring so as to fill the concave portion thereof, a plurality of fourth wirings disposed on the buried insulating film, and a contact plug disposed so as to electrically connect to at least one of the first and second wells.. . ... Micron Technology Inc

02/26/15 / #20150054067

Integrated circuitry comprising nonvolatile memory cells and methods of forming a nonvolatile memory cell

A method of forming a gate construction of a recessed access device includes forming a pair of sidewall spacers laterally over opposing sidewalls of a gate dielectric and elevationally over first conductive gate material. The gate dielectric, the first conductive gate material, and the sidewall spacers are received within a trench formed in semiconductive material. ... Micron Technology Inc

02/26/15 / #20150054063

Apparatuses having a vertical memory cell

Methods, apparatuses, and systems for providing a body connection to a vertical access device. The vertical access device may include a digit line extending along a substrate to a digit line contact pillar, a body connection line extending along the substrate to a body connection line contact pillar, a body region disposed on the body connection line, an electrode disposed on the body region, and a word line extending to form a gate to the body region. ... Micron Technology Inc

02/26/15 / #20150053907

Methods, apparatuses, and circuits for programming a memory device

Subject matter described pertains to methods, apparatuses, and circuits for programming a memory device.. . ... Micron Technology Inc

02/19/15 / #20150052318

Memory apparatuses, computer systems and methods for ordering memory responses

Memory apparatuses that may be used for receiving commands and ordering memory responses are provided. One such memory apparatus includes response logic that is coupled to a plurality of memory units by a plurality of channels and may be configured to receiving a plurality of memory responses from the plurality of memory units. ... Micron Technology Inc

02/19/15 / #20150052317

Systems, devices, memory controllers, and methods for memory initialization

Systems, devices, memory controllers, and methods for initializing memory are described. Initializing memory can include configuring memory devices in parallel. ... Micron Technology Inc

02/19/15 / #20150052300

Data storage management

A method of managing a plurality of storage devices. The method comprises at a first device connected to the plurality of storage devices via a switch, receiving an indication of a plurality of logical disks, each logical disk being provided by a respective one of the plurality of storage devices. ... Micron Technology Inc

02/19/15 / #20150052299

Apparatuses and methods for providing data to a configurable storage area

Apparatuses and methods for providing data to a configurable storage area are disclosed herein. An example apparatus may include an extended address register including a plurality of configuration bits indicative of an offset and a size, an array having a storage area, a size and offset of the storage area based, at least in part, on the plurality of configuration bits, and a buffer configured to store data, the data including data intended to be stored in the storage area. ... Micron Technology Inc

02/19/15 / #20150052288

Apparatuses and methods for providing data from a buffer

Apparatuses and methods for providing data from a buffer are disclosed herein. An example apparatus may include an array, a buffer, and a memory control unit. ... Micron Technology Inc

02/19/15 / #20150052114

Methods and systems for autonomous memory searching

Methods and systems operate to receive a plurality of search requests for searching a database in a memory system. The search requests can be stored in a fifo queue and searches can be subsequently generated for each search request. ... Micron Technology Inc

02/19/15 / #20150050795

Diode for variable-resistance material memories, processes of forming same, and methods of using same

A variable-resistance material memory (vrmm) device includes a container conductor disposed over an epitaxial semiconductive prominence that is coupled to a vrmm. A vrmm device may also include a conductive plug in a recess that is coupled to a vrmm. ... Micron Technology Inc

02/19/15 / #20150049565

Apparatuses and methods for reducing current leakage in a memory

Apparatuses, sense amplifier circuits, and methods for operating a sense amplifier circuit in a memory are described. An example apparatus includes a sense amplifier circuit configured to be coupled to a digit line and configured to, during a memory access operation, drive the digit line to a voltage that indicates the logical value of the charge stored by a memory cell coupled to the digit line. ... Micron Technology Inc

02/19/15 / #20150049558

Dynamic burst length output control in a memory

A memory, a system and a method for controlling dynamic burst length control data can generate clocks for both an upstream counter and a downstream counter by using substantially the same latency delayed received command indications. A downstream clock generation circuit generates a clock signal from a received command indication delayed by both a delay locked loop and latency delays stored in latency control circuits. ... Micron Technology Inc

02/19/15 / #20150049556

Program verify operation in a memory device

Methods for program verifying a memory cell include generating an access line voltage in response to a count and applying the access line voltage to a control gate of the memory cell, and generating a pass signal in response to the access line voltage activating the memory cell. Methods further include comparing at least a portion of the count to an indication of a desired threshold voltage of the memory cell, and when the at least a portion of the count matches the indication of the desired threshold voltage of the memory cell, determining if the pass signal is present. ... Micron Technology Inc

02/19/15 / #20150048301

Engineered substrates having mechanically weak structures and associated systems and methods

Engineered substrates having mechanically weak structures for separating substrates from epitaxially grown semiconductor structures and associated systems and methods are disclosed herein. In several embodiments, for example, an engineered substrate can be manufactured by forming an intermediary material at an upper surface of a structural material and forming a plurality of pores in the intermediary material. ... Micron Technology Inc

02/12/15 / #20150046889

State grouping for element utilization

Embodiments of a system and method for generating an image configured to program a parallel machine from source code are disclosed. One such parallel machine includes a plurality of state machine elements (smes) grouped into pairs, such that smes in a pair have a common output. ... Micron Technology Inc

02/12/15 / #20150046774

Semiconductor device and error correction information writing method

A semiconductor device includes first and second memory cell arrays, each including a plurality of memory cells, each of which is connected between first and second terminals and is configured to be written to a first resistance state by applying a first current in a first direction between the first and second terminals and be written to a second resistance state by applying a second current in a second direction opposite to the first direction between the first and second terminals. The semiconductor device further includes an error-correction circuit and a control circuit. ... Micron Technology Inc

02/12/15 / #20150046631

Apparatuses and methods for configuring i/os of memory for hybrid memory modules

Apparatuses, hybrid memory modules, memories, and methods for configuring i/os of a memory for a hybrid memory module are described. An example apparatus includes a non-volatile memory, a control circuit coupled to the non-volatile memory, and a volatile memory coupled to the control circuit. ... Micron Technology Inc

02/12/15 / #20150046611

Devices, systems, and methods of reducing chip select

Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (id_a and id_m). ... Micron Technology Inc

02/12/15 / #20150044860

Multi-tiered semiconductor apparatuses including residual silicide in semiconductor tier

Methods of forming multi-tiered semiconductor devices are described, along with apparatuses that include them. In one such method, a silicide is formed in a tier of silicon, the silicide is removed, and a device is formed at least partially in a void that was occupied by the silicide. ... Micron Technology Inc

02/12/15 / #20150044850

Resistive memory cell

Semiconductor memory devices, resistive memory devices, memory cell structures, and methods of forming a resistive memory cell are provided. One example method of a resistive memory cell can include a number of dielectric regions formed between two electrodes, and a barrier dielectric region formed between each of the dielectric regions. ... Micron Technology Inc

02/12/15 / #20150044849

Three dimensional memory array architecture

Three dimension memory arrays and methods of forming the same are provided. An example three dimension memory array can include a stack comprising a plurality of first conductive lines separated from one another by at least an insulation material, and at least one conductive extension arranged to extend substantially perpendicular to the plurality of first conductive lines, such that the at least one conductive extension intersects a portion of at least one of the plurality of first conductive lines. ... Micron Technology Inc

02/12/15 / #20150044834

Transistors, semiconductor constructions, and methods of forming semiconductor constructions

Some embodiments include a transistor having a first electrically conductive gate portion along a first segment of a channel region and a second electrically conductive gate portion along a second segment of the channel region. The second electrically conductive gate portion is a different composition than the first electrically conductive gate portion. ... Micron Technology Inc

02/12/15 / #20150044832

Resistive random access memory

A resistive random access memory may include a memory array and a periphery around the memory array. Decoders in the periphery may be coupled to address lines in the array by forming a metallization in the periphery and the array at the same time using the same metal deposition. ... Micron Technology Inc

02/12/15 / #20150044811

Method and apparatus for reducing signal loss in a photo detector

Photonic structures and methods of formation are disclosed in which a photo detector interface having crystalline misfit dislocations is displaced with respect to a waveguide core to reduce effects of dark current on a detected optical signal.. . ... Micron Technology Inc

02/12/15 / #20150044783

Methods of alleviating adverse stress effects on a wafer, and methods of forming a semiconductor device

A method of forming a forming a semiconductor device comprises forming at least one semiconductor device structure over a surface of a wafer. An opposing surface of the wafer is subjected to at least one chemical-mechanical polishing process to form a modified opposing surface of the wafer comprising at least one recessed region and at least one elevated region. ... Micron Technology Inc

02/12/15 / #20150043299

Semiconductor device

A device includes an output circuit, a dll (delay locked loop) circuit including a first delay line receiving a first clock signal and outputting, in response to receiving the clock signal, a second clock signal supplied to the output circuit, and an odt (on die termination) circuit receiving an odt activation signal and outputting, in response to receiving the odt activation signal, an odt output signal supplied to the output circuit to set the output circuit in a resistance termination state, and the odt circuit including a second delay line configured to be set by the dll circuit in an equivalent delay amount that is equivalent to a delay amount of the first delay line, the odt output signal being, in a first time-period during which the odt activation signal is in an active state, generated by being conveyed via the second delay line in which the equivalent delay amount has been set.. . ... Micron Technology Inc

02/12/15 / #20150043285

Interfaces and die packages, and appartuses including the same

A memory device includes a memory die package including a plurality of memory dies, an interface device including an interface circuit, and a memory controller configured to control the interface with control data received from at least one of the plurality of memory dies. The interface device of the memory device is configured to divide and multiplex an io channel between the memory die package and the memory controller into more than one channel using the control data receive from the at least one of the plurality of memory dies. ... Micron Technology Inc

02/12/15 / #20150042398

Charge pump including supply voltage-based control signal level

Some embodiments include apparatuses and methods having an input node to receive a first voltage, an output node to provide an output voltage, and a charge pump to generate the output voltage based on the first voltage. The charge pump can include a control node to receive a control signal for controlling at least one switch of the charge pump, such that the output voltage includes a value greater than a value of the first voltage. ... Micron Technology Inc

02/12/15 / #20150042380

Apparatuses and methods for performing logical operations using sensing circuitry

The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry comprising a primary latch coupled to a sense line of the array. ... Micron Technology Inc

02/12/15 / #20150041879

Semiconductor structures and methods of fabrication of same

Semiconductor structures may include a stack of alternating dielectric materials and control gates, charge storage structures laterally adjacent to the control gates, a charge block material between each of the charge storage structures and the laterally adjacent control gates, and a pillar extending through the stack of alternating oxide materials and control gates. Each of the dielectric materials in the stack has at least two portions of different densities and/or different rates of removal. ... Micron Technology Inc

02/12/15 / #20150041873

Vertical ferroelectric field effect transistor constructions, constructions comprising a pair of vertical ferroelectric field effect transistors, vertical strings of ferroelectric field effect transistors, and vertical strings of laterally opposing pairs of vertical ferroelectric field effect transistors

A vertical ferroelectric field effect transistor construction comprises an isolating core. A transition metal dichalcogenide material encircles the isolating core and has a lateral wall thickness of 1 monolayer to 7 monolayers. ... Micron Technology Inc

02/12/15 / #20150041754

Resistance variable memory device with nanoparticle electrode and method of fabrication

A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a nanoparticle is provided between an electrode and a chalcogenide glass region. The method of forming the nanoparticle utilizes a template over the electrode or random deposition of the nanoparticle.. ... Micron Technology Inc

02/12/15 / #20150041753

Nano-scale electrical contacts, memory devices including nano-scale electrical contacts, and related structures and devices

Electrical contacts may be formed by forming dielectric liners along sidewalk of a dielectric structure, forming sacrificial liners over and transverse to the dielectric liners along sidewalls of a sacrificial structure, selectively removing portions of the dielectric liners at intersections of the dielectric liners and sacrificial liners to form pores, and at least partially filling the pores with a conductive material. Nano-scale pores may be formed by similar methods. ... Micron Technology Inc

02/12/15 / #20150041749

Memory cells and methods of forming memory cells

A method of forming a memory cell includes forming an outer electrode material elevationally over and directly against a programmable material. The programmable material and the outer electrode material contact one another along an interface. ... Micron Technology Inc

02/12/15 / #20150041204

Microelectronic packages with leadframes, including leadframes configured for stacked die packages, and associated systems and methods

Microelectronic packages with leadframes, including leadframes configured for stacked die packages, and associated systems and methods are disclosed. A system in accordance with one embodiment includes a support member having first package bond sites electrically coupled to leadframe bond sites. ... Micron Technology Inc

02/05/15 / #20150039960

Encoding and decoding techniques using low-density parity check codes

Some embodiments include apparatus and methods for encoding message information. Such apparatus and methods can include using a parity check matrix of a low-density parity check (ldpc) code to generate a first matrix having an upper triangular sub-matrix. ... Micron Technology Inc

02/05/15 / #20150039843

Circuits and methods for providing data to and from arrays of memory cells

A memory device uses a global input/output line or a pair of complementary global input/output lines to couple write data signals and read data signals to and from a memory array. The same input/output line or pairs of complementary global input/output lines may be used for coupling both write data signals and read data signals.. ... Micron Technology Inc

02/05/15 / #20150037942

Methods of forming memory cells, memory cells, and semiconductor devices

A memory device and method of making the memory device. Memory device may include a storage transistor at a surface of a substrate. ... Micron Technology Inc

02/05/15 / #20150037914

Method for manufacturing tested apparatus and method for manufacturing system including tested apparatus

Disclosed herein is a method for manufacturing a tested apparatus that includes forming a stacked structure that includes a plurality of first semiconductor chips stacked over a semiconductor wafer. The semiconductor wafer comprises a plurality of second semiconductor chips that are arranged in matrix of a plurality of rows and columns. ... Micron Technology Inc

02/05/15 / #20150036445

Semiconductor device

Disclosed herein is a semiconductor device that includes: a memory cell array including a plurality of memory groups each having a plurality of memory cells, the memory groups being selected by mutually different addresses; a first control circuit periodically executing a refresh operation on the memory groups in response to a first refresh command; and a second control circuit setting a cycle of executing the refresh operation by the first control circuit. The second control circuit sets the cycle to a first cycle until executing the refresh operation to all the memory groups after receiving the first refresh command, and the second control circuit sets the cycle to a second cycle that is longer than the first cycle after executing the refresh operation to all the memory groups.. ... Micron Technology Inc

02/05/15 / #20150036442

Apparatuses and methods for driving a voltage of a wordline of a memory

Apparatuses, global and local wordline drivers, and methods for driving a wordline voltage in a memory is described. An example apparatus includes a memory array including a plurality of sub-arrays. ... Micron Technology Inc

02/05/15 / #20150036425

Memory cell and memory cell array having an electrically floating body transistor, and methods of operating same

Techniques are disclosed for writing, programming, holding, maintaining, sampling, sensing, reading and/or determining a data state of a memory cell of a memory cell array, such as a memory cell array having a plurality of memory cells each comprising an electrically floating body transistor. In one aspect, the techniques are directed to controlling and/or operating a semiconductor memory cell having an electrically floating body transistor in which an electrical charge is stored in the body region of the electrically floating body transistor. ... Micron Technology Inc

02/05/15 / #20150036405

Memory devices

Some embodiments include memory devices having a wordline, a bitline, a memory element selectively configurable in one of three or more different resistive states, and a diode configured to allow a current to flow from the wordline through the memory element to the bitline responsive to a voltage being applied across the wordline and the bitline and to decrease the current if the voltage is increased or decreased. Some embodiments include memory devices having a wordline, a bitline, memory element selectively configurable in one of two or more different resistive states, a first diode configured to inhibit a first current from flowing from the bitline to the wordline responsive to a first voltage, and a second diode comprising a dielectric material and configured to allow a second current to flow from the wordline to the bitline responsive to a second voltage.. ... Micron Technology Inc

02/05/15 / #20150035150

Conductive interconnect structures incorporating negative thermal expansion materials and associated systems, devices, and methods

Semiconductor devices having interconnects incorporating negative expansion (nte) materials are disclosed herein. In one embodiment a semiconductor device includes a substrate having an opening that extends at least partially through the substrate. ... Micron Technology Inc

02/05/15 / #20150035126

Methods and structures for processing semiconductor devices

Methods of forming a semiconductor structure include exposing a carrier substrate to a silane material to form a coating, removing a portion of the coating at least adjacent a periphery of the carrier substrate, adhesively bonding another substrate to the carrier substrate, and separating the another substrate from the carrier substrate. The silane material includes a compound having a structure of (xo)3si(ch2)ny, (xo)2si((ch2)ny)2, or (xo)3si(ch2)ny(ch2)nsi(xo)3, wherein xo is a hydrolyzable alkoxy group, y is an organofunctional group, and n is a nonnegative integer. ... Micron Technology Inc

02/05/15 / #20150035124

Process for improving critical dimension uniformity of integrated circuit arrays

Methods for patterning integrated circuit (ic) device arrays employing an additional mask process for improving center-to-edge cd uniformity are disclosed. In one embodiment, a repeating pattern of features is formed in a masking layer over a first region of a substrate. ... Micron Technology Inc

02/05/15 / #20150035119

Capacitors and methods with praseodymium oxide insulators

Methods of forming and the resulting capacitors formed by these methods are shown. Monolayers that contain praseodymium are deposited onto a substrate and subsequently processed to form praseodymium oxide dielectrics. ... Micron Technology Inc

02/05/15 / #20150035082

Semiconductor device structures including energy barriers, and related methods

A semiconductor device structure includes a transistor with an energy barrier beneath its transistor channel. The energy barrier prevents leakage of stored charge from the transistor channel into a bulk substrate. ... Micron Technology Inc

02/05/15 / #20150035054

Semiconductor device

A device includes a first transistor including a first gate electrode including first and second parallel electrode portions each extending in a first direction, and a first connecting electrode portion extending in a second direction approximately orthogonal to the first direction and connecting one ends of the first and second parallel electrode portions to each other, and first and second diffusion layers separated from each other by a channel region under the first gate electrode, a first output line connected to the first diffusion layer of the first transistor, and a second transistor comprising a second gate electrode extending in the second direction, and the second transistor being configured to use the second diffusion layer of the first transistor as one of two diffusion layers that are separated from each other by a channel region under the second gate electrode.. . ... Micron Technology Inc

02/05/15 / #20150035043

Charge trapping dielectric structures

A dielectric structure may be arranged having a thin nitrided surface of an insulator with a charge blocking insulator over the nitrided surface. The insulator may be formed of a number of different insulating materials such as a metal oxide, a metal oxycarbide, a semiconductor oxide, or oxycarbide. ... Micron Technology Inc

02/05/15 / #20150034908

Semiconductor graphene structures, methods of forming such structures and semiconductor devices including such structures

A semiconducting graphene structure may include a graphene material and a graphene-lattice matching material over at least a portion of the graphene material, wherein the graphene-lattice matching material has a lattice constant within about ±5% of a multiple of the lattice constant or bond length of the graphene material. The semiconducting graphene structure may have an energy band gap of at least about 0.5 ev. ... Micron Technology Inc

02/05/15 / #20150034897

Post deposition adjustment of chalcogenide composition in chalcogenide containing semiconductors

The concentration of a constituent within a chalcogenide film used to form a chalcogenide containing semiconductor may be adjusted post deposition by reacting the chalcogenide film with a material in contact with the chalcogenide film. For example, a chalcogenide film containing tellurium may be coated with a titanium layer. ... Micron Technology Inc

01/29/15 / #20150033096

Memory devices and configuration methods for a memory device

A memory device has a plurality of individually erasable blocks of memory cells and a controller configured to configure a first block of memory cells in a first configuration comprising one or more groups of overhead data memory cells, and to configure a second block of memory cells in a second configuration comprising one or more groups of user data memory cells and at least one group of overhead data memory cells. The first configuration is different than the second configuration. ... Micron Technology Inc

01/29/15 / #20150033087

Resting blocks of memory cells in response to the blocks being deemed to fail

In an embodiment, a block of memory cells is rested in response to the block of memory cells being deemed to fail. For some embodiments, a rested block may be selected for use in response to passing an operation. ... Micron Technology Inc

01/29/15 / #20150032927

Apparatus, electronic devices and methods associated with an operative transition from a first interface to a second interface

Subject matter disclosed herein relates to an apparatus comprising memory and a controller, such as a controller which determines block locking states in association with operative transitions between two or more interfaces that share at least one block of memory. The apparatus may support single channel or multi-channel memory access, write protection state logic, or various interface priority schemes.. ... Micron Technology Inc

01/29/15 / #20150031212

Method for obtaining extreme selectivity of metal nitrides and metal oxides

Methods for etching metal nitrides and metal oxides include using ultradilute hf solutions and buffered, low-ph hf solutions containing a minimal amount of the hydrofluoric acid species h2f2. The etchant can be used to selectively remove metal nitride layers relative to doped or undoped oxides, tungsten, polysilicon, and titanium nitride. ... Micron Technology Inc

01/29/15 / #20150031171

Methods for forming conductive elements and vias on substrates and for forming multi-chip modules

Methods of forming conductive elements on and in a substrate include forming a layer of conductive material over a surface of a substrate prior to forming a plurality of vias through the substrate from an opposing surface of the substrate to the layer of conductive material. In some embodiments, a temporary carrier may be secured to the layer of conductive material on a side thereof opposite the substrate prior to forming the vias. ... Micron Technology Inc

01/29/15 / #20150029806

Voltage control integrated circuit devices

Voltage control in integrated circuits include a first voltage divider coupled to receive a reference voltage and having an output providing an adjusted reference voltage; an operational amplifier having a first input coupled to receive the output of the first voltage divider, a second input coupled to receive a feedback voltage, and an output; a voltage generation circuit responsive to the output of the operational amplifier and having an output providing an output voltage; and a second voltage divider coupled to receive the output voltage and having an output providing the feedback voltage. The first voltage divider is responsive to first control signals to adjust a voltage level of the adjusted reference voltage. ... Micron Technology Inc

01/29/15 / #20150029804

Apparatuses and methods for adjusting deactivation voltages

Apparatuses and methods for adjusting deactivation voltages are described herein. An example apparatus may include a voltage control circuit. ... Micron Technology Inc

01/29/15 / #20150029802

Apparatuses, integrated circuits, and methods for measuring leakage current

Methods, apparatuses, and integrated circuits for measuring leakage current are disclosed. In one such example method, a word line is charged to a first voltage, and a measurement node is charged to a second voltage, the second voltage being less than the first voltage. ... Micron Technology Inc

01/29/15 / #20150029798

Apparatuses and methods for performing compare operations using sensing circuitry

The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can include charging an input/output (io) line of a memory array to a voltage. ... Micron Technology Inc

01/29/15 / #20150029781

Method and apparatus for sensing in a memory

A method and a memory for sensing a state of a memory cell while the memory cell capacitor is isolated from a data line are described. An activation device of the memory cell can be enabled to couple the memory cell capacitor to a parasitic capacitance of the active data line for charge sharing. ... Micron Technology Inc

01/29/15 / #20150029776

Semiconductor device having a reduced area and enhanced yield

A device includes a first power supply line supplying a first voltage, first, second, and third nodes, a selection circuit connected between the first power supply line and the first node, a first anti-fuse connected between the first node and the second node, and a second anti-fuse connected between the first node and the third node. The second node and the third node are not connected to each other.. ... Micron Technology Inc

01/29/15 / #20150029775

Memory cell array structures and methods of forming the same

The present disclosure includes memory cell array structures and methods of forming the same. One such array includes a stack structure comprising a memory cell between a first conductive material and a second conductive material. ... Micron Technology Inc

01/29/15 / #20150029774

Stacked device identification assignment

Some embodiments include apparatus and methods having dice arranged in a stack. The dice include at least a first die and a second die, and a connection coupled to the dice. ... Micron Technology Inc

01/29/15 / #20150028928

Phase interpolators and push-pull buffers

Interpolator systems are described utilizing one or more push-pull buffers to generate output clock signals that may be provided as inputs to a phase interpolator. The more linear slope on the output of the push-pull buffer may improve the linearity of a phase interpolator using the dock signals output from the push-pull buffers.. ... Micron Technology Inc

01/29/15 / #20150028921

Methods and apparatuses for driving a node to a pumped voltage

Methods and apparatuses are disclosed for driving a node to one or more elevated voltages. One example apparatus includes a first driver circuit configured to drive a node to a first voltage, and a second driver circuit configured to drive the node to a pumped voltage after the node reaches a voltage threshold. ... Micron Technology Inc

01/29/15 / #20150028476

Devices, systems, and methods related to forming through-substrate vias with sacrificial plugs

Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming one or more openings in a front side of the semiconductor device and forming sacrificial plugs in the openings that partially fill the openings. ... Micron Technology Inc

01/29/15 / #20150028439

Memory cells, methods of fabrication, semiconductor device structures, memory systems, and electronic systems

A magnetic cell core includes a seed region with a plurality of magnetic regions and a plurality of nonmagnetic regions thereover. The seed region provides a template that enables formation of an overlying nonmagnetic region with a microstructure that enables formation of an overlying free region with a desired crystal structure. ... Micron Technology Inc

01/29/15 / #20150028406

Arrays of recessed access gate lines, arrays of conductive lines, arrays of recessed access gate lines and conductive lines, memory circuitry, methods of forming an array of recessed access gate lines, methods of forming an array of conductive lines, and methods of forming an array of recessed access gate lines and an array of conductive lines

An array of recessed access gate lines includes active area regions having dielectric trench isolation material there-between. The trench isolation material comprises dielectric projections extending into opposing ends of individual active area regions under an elevationally outermost surface of material of the active area regions. ... Micron Technology Inc

01/29/15 / #20150028347

Light emitting diodes and associated methods of manufacturing

Light emitting diodes and associated methods of manufacturing are disclosed herein. In one embodiment, a light emitting diode (led) includes a substrate, a semiconductor material carried by the substrate, and an active region proximate to the semiconductor material. ... Micron Technology Inc

01/29/15 / #20150028284

Memory cells having a number of conductive diffusion barrier materials and manufacturing methods

Memory cells having a select device material located between a first electrode and a second electrode, a memory element located between the second electrode and a third electrode, and a number of conductive diffusion barrier materials located between a first portion of the memory element and a second portion of the memory element. Memory cells having a select device comprising a select device material located between a first electrode and a second electrode, a memory element located between the second electrode and a third electrode, and a number of conductive diffusion barrier materials located between a first portion of the select device and a second portion of the select device. ... Micron Technology Inc

01/29/15 / #20150028283

Methods of forming memory cells and arrays

Some embodiments include methods of forming memory cells. Heater structures are formed over an array of electrical nodes, and phase change material is formed across the heater structures. ... Micron Technology Inc

01/29/15 / #20150028280

Memory cell with independently-sized elements

Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element formed in series with the switch element. ... Micron Technology Inc

01/22/15 / #20150026513

Memory buffer having accessible information after a program-fail

A memory device, and a method of operating same, utilize a memory buffer associated with a memory array to maintain information to be available subsequent to a program-fail event associated with the memory array.. . ... Micron Technology Inc

01/22/15 / #20150026484

Smart storage device

A smart storage device can have a smart-card portion with access control circuitry and integrated memory, a controller in selective communication with the smart-card portion, and a memory device in communication with the controller. The memory device can be separate from the smart-card portion and can store one or more smart-card applications.. ... Micron Technology Inc

01/22/15 / #20150026416

Dynamic memory cache size adjustment in a memory device

Methods for dynamic memory cache size adjustment, enabling dynamic memory cache size adjustment, memory devices, and memory systems are disclosed. One such method for dynamic memory cache size adjustment determines available memory space in a memory array and adjusts a size of a memory cache in the memory array responsive to the available memory space.. ... Micron Technology Inc

01/22/15 / #20150024602

Method for positioning spacers in pitch multiplication

Multiple pitch-multiplied spacers are used to form mask patterns having features with exceptionally small critical dimensions. One of each pair of spacers formed mandrels is removed and alternating layers, formed of two mutually selectively etchable materials, are deposited around the remaining spacers. ... Micron Technology Inc

01/22/15 / #20150023386

System and method for automatically calibrating a temperature sensor

There is provided a system and method for automatically calibrating a temperature sensor. More specifically, there is provided a system including a temperature sensor that includes a first resistance configured to indicate a temperature of the temperature sensor and a second resistance, in series with the first resistor, wherein the second resistance is adjustable to calibrate the first resistance, and a calibration circuit, coupled to the temperature sensor and configured to automatically calibrate the first resistance.. ... Micron Technology Inc

01/22/15 / #20150023121

Memory refresh methods, memory section control circuits, and apparatuses

Apparatuses, memory section control circuits, and methods of refreshing memory are disclosed. An example apparatus includes a plurality of memory sections and a plurality of memory section control circuits. ... Micron Technology Inc

01/22/15 / #20150023117

Methods for sensing memory elements in semiconductor devices

A memory device that, in certain embodiments, includes a plurality of memory elements connected to a bit-line and a delta-sigma modulator with a digital output and an analog input, which may be connected to the bit-line. In some embodiments, the delta-sigma modulator includes a circuit with first and second inputs and an output. ... Micron Technology Inc

01/22/15 / #20150023110

Inferring threshold voltage distributions associated with memory cells via interpolation

The present disclosure includes apparatuses and methods for inferring threshold voltage distributions associated with memory cells via interpolation. A number of embodiments include determining soft data for a group of memory cells each programmed to one of a number of data states, wherein the soft data comprises a number of different soft data values, determining a quantity of memory cells associated with each of the different soft data values, and inferring at least a portion of a threshold voltage distribution associated with the group of memory cells via an interpolation process using the determined quantities of memory cells associated with each of the different soft data values.. ... Micron Technology Inc

01/22/15 / #20150023104

Apparatuses and methods for measuring an electrical characteristic of a model signal line and providing measurement information

Apparatuses and methods for measuring an electrical characteristic of a model signal line and providing measurement information based at least in part on the measurement of the electrical characteristic. An example apparatus includes a signal line model including a model signal line configured to model electrical characteristics of a signal line. ... Micron Technology Inc

01/22/15 / #20150023095

Apparatuses including current compliance circuits and methods

Apparatus, devices, systems, and methods are described that include variable state material data storage. Example devices include current compliance circuits that are configured to dynamically adjust a current passing through a variable resistance material during a memory operation. ... Micron Technology Inc

01/22/15 / #20150023089

Resistance variable element methods and apparatuses

Apparatus and methods are disclosed, including a method that performs a first operation on a first resistance variable element using a common source voltage, a first data line voltage and a first control gate voltage, and then performs a second operation on a second resistance variable element using the common source voltage, a second data line voltage and a second control gate voltage. Additional apparatus and methods are described.. ... Micron Technology Inc

01/22/15 / #20150023088

Apparatuses and methods for sensing fuse states

Apparatuses and methods for sensing fuse states are disclosed herein. An apparatus may include an array having a plurality of sense lines. ... Micron Technology Inc

01/22/15 / #20150022383

Methods and apparatuses for low-power multi-level encoded signals

Methods and apparatuses for providing multi-level encoded signals are disclosed. An apparatus may include an encoding circuit and a multi-level encoder. ... Micron Technology Inc

01/22/15 / #20150022282

Semiconductor device and method for adjusting impedance of output circuit

An impedance adjustment circuit includes a counter circuit outputting a count value thereof as a plurality of first impedance adjustment signals, a mode selection circuit setting a second impedance adjustment signal to be in an active/inactive state irrespective of the count value, and a level fixing circuit fixing a third impedance adjustment signal to be in an active state. A pre-stage circuit generates a plurality of first output control signals, a second output control signal, and a third output control signal in response to the first impedance adjustment signals, the second impedance adjustment signal, and the third impedance adjustment signal, respectively, and a data signal. ... Micron Technology Inc

01/22/15 / #20150022238

Apparatuses and methods for line charge sharing

Apparatuses and methods for charge sharing, between signal lines are disclosed. An example apparatus may include first and second lines and a charge sharing circuit the charge sharing circuit may be coupled to the first line and the second line and configured to receive a first data signal and a second data signal. ... Micron Technology Inc

01/22/15 / #20150021769

Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices

Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed. In one embodiment, a method for forming a microelectronic device includes attaching a microelectronic die to a support member by forming an attachment feature on at least one of a back side of the microelectronic die and the support member. ... Micron Technology Inc

01/22/15 / #20150021744

Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same

A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. ... Micron Technology Inc

01/22/15 / #20150021707

Electromagnetic shield and associated methods

Semiconductor devices are described, along with methods and systems that include them. One such device includes a diffusion region in a semiconductor material, a terminal coupled to the diffusion region, and a field plate coupled to the terminal and extending from the terminal over the diffusion region to shield the diffusion region. ... Micron Technology Inc

01/22/15 / #20150021609

Semiconductor apparatus with multiple tiers, and methods

Apparatus and methods are disclosed, including an apparatus that includes a number of tiers of a first semiconductor material, each tier including at least one access line of at least one memory cell and at least one source, channel and/or drain of at least one peripheral transistor, such as one used in an access line decoder circuit or a data line multiplexing circuit. The apparatus can also include a number of pillars of a second semiconductor material extending through the tiers of the first semiconductor material, each pillar including either a source, channel and/or drain of at least one of the memory cells, or a gate of at least one of the peripheral transistors. ... Micron Technology Inc

01/22/15 / #20150021541

Resistive memory having confined filament formation

Resistive memory having confined filament formation is described herein. One or more method embodiments include forming an opening in a stack having a silicon material and an oxide material on the silicon material, and forming an oxide material in the opening adjacent the silicon material, wherein the oxide material formed in the opening confines filament formation in the resistive memory cell to an area enclosed by the oxide material formed in the opening.. ... Micron Technology Inc

01/15/15 / #20150019793

Self-measuring nonvolatile memory devices with remediation capabilities and associated systems and methods

Several embodiments of systems incorporating nonvolatile memory devices are disclosed herein. In one embodiment, a system can include a central processor (cpu) and a nonvolatile memory device operably coupled to the cpu. ... Micron Technology Inc

01/15/15 / #20150019787

Data interleaving module

The present disclosure includes apparatuses and methods related to a data interleaving module. A number of methods can include interleaving data received from a bus among modules according to a selected one of a plurality of data densities per memory cell supported by an apparatus and transferring the interleaved data from the modules to a register.. ... Micron Technology Inc

01/15/15 / #20150017575

Photomasks, methods of forming a photomask, and methods of photolithographically patterning a substrate

A photomask includes a substrate having a device region and an adjacent edge region over transparent material. The device region includes spaced primary features of constant pitch at least adjacent the edge region. ... Micron Technology Inc

01/15/15 / #20150016186

Methods and apparatuses for determining threshold voltage shift

Apparatuses and methods for determining threshold voltage shift are described. A number of methods for determining threshold voltage shift in memory cells include determining changes in threshold voltage for memory cells at each data state of a first number of data states by searching threshold voltage data of memory cells programmed to the first number of data states and determining changes in threshold voltage for memory cells at each data state of a second number of data states by searching threshold voltage data of memory cells programmed to the second number of data states within a range of threshold voltages, wherein the range is shifted from a previous range based on the changes in threshold voltage for memory cells programmed to the first number of data states.. ... Micron Technology Inc

01/15/15 / #20150015860

Reticles, and methods of mitigating asymmetric lens heating in photolithography

A method of mitigating asymmetric lens heating in photolithographically patterning a photo-imageable material using a reticle includes determining where first hot spot locations are expected to occur on a lens when using a reticle to pattern a photo-imageable material. The reticle is then fabricated to include non-printing features within a non-printing region of the reticle which generate additional hot spot locations on the lens when using the reticle to pattern the photo-imageable material. ... Micron Technology Inc

01/15/15 / #20150015319

Devices for shielding a signal line over an active region

A multi-path transistor includes an active region including a channel region and an impurity region. A gate is dielectrically separated from the channel region. ... Micron Technology Inc

01/15/15 / #20150014811

Antifuses and methods of forming antifuses and antifuse structures

Antifuses having two or more materials with differing work function values may be fabricated as recessed access devices and spherical recessed access devices for use with integrated circuit devices and semiconductor devices. The use of materials having different work function values in the fabrication of recessed access device antifuses allows the breakdown areas of the antifuse device to be customized or predicted.. ... Micron Technology Inc

01/15/15 / #20150014766

Memory arrays, semiconductor constructions, and methods of forming semiconductor constructions

Some embodiments include memory arrays. The memory arrays may have digit lines under vertically-oriented transistors, with the digit lines interconnecting transistors along columns of the array. ... Micron Technology Inc

01/15/15 / #20150014758

Memory cells having a folded digit line architecture

Memory arrays having folded architectures and methods of making the same. Specifically, memory arrays having a portion of the transistors in a row that are reciprocated and shifted with respect to other transistors in the same row. ... Micron Technology Inc

01/15/15 / #20150014689

Elevated pocket pixels, imaging devices and systems including the same and method of forming the same

An elevated photosensor for image sensors and methods of forming the photosensor. The photosensor may have light sensors having indentation features including, but not limited to, v-shaped, u-shaped, or other shaped features. ... Micron Technology Inc

01/15/15 / #20150014623

Memory constructions

Some embodiments include memory constructions having a plurality of bands between top and bottom electrically conductive materials. The bands include chalcogenide bands alternating with non-chalcogenide bands. ... Micron Technology Inc

01/08/15 / #20150012717

Memory controlled data movement and timing

The present disclosure includes apparatuses, electronic device readable media, and methods for memory controlled data movement and timing. A number of electronic device readable media can store instructions executable by an electronic device to provide programmable control of data movement operations within a memory. ... Micron Technology Inc

01/08/15 / #20150011085

Method for forming fine pitch structures

A mold having an open interior volume is used to define patterns. The mold has a ceiling, floor and sidewalls that define the interior volume and inhibit deposition. ... Micron Technology Inc

01/08/15 / #20150011063

Methods of fabricating semiconductor structures

Semiconductor structures including an etch stop material between a substrate and a stack of alternating insulating materials and first conductive materials, wherein the etch stop material comprises an amorphous aluminum oxide on the substrate and a crystalline aluminum oxide on the amorphous aluminum oxide; a channel material extending through the stack; and a second conductive material between the channel material and at least one of the first conductive materials in the stack of alternating insulating materials and first conductive materials, wherein the second conductive material is not between the channel material and the etch stop material. Also disclosed are methods of fabricating such semiconductor structures.. ... Micron Technology Inc

01/08/15 / #20150010014

Switching device

A switching device comprising a plurality of ingress ports and a plurality of egress ports. The switching device is arranged to receive data packets through said ingress ports and to forward received data packets to respective ones of said egress ports. ... Micron Technology Inc

01/08/15 / #20150009773

Volume select for affecting a state of a non-selected memory volume

Apparatuses and methods of operating memory are described. One such method can include receiving a select command at a plurality of memory volumes of a memory device, the select command indicating a targeted memory volume of the plurality of memory volumes. ... Micron Technology Inc

01/08/15 / #20150009766

Apparatuses and methods for comparing a current representative of a number of failing memory cells

Apparatuses and methods for comparing a sense current representative of a number of failing memory cells of a group of memory cells and a reference current representative of a reference number of failing memory cells is provided. One such apparatus includes a comparator configured to receive the sense current and to receive the reference current. ... Micron Technology Inc

01/08/15 / #20150009756

Sensing operations in a memory device

Methods and apparatus for sensing operations in memory devices are disclosed. In at least one embodiment, a sensing operation to determine negative threshold voltages in memory cells by an elevated source potential applied to a string of memory cells and an elevated data line potential applied to the string of memory cells is disclosed. ... Micron Technology Inc

01/08/15 / #20150008968

Apparatuses and methods for phase interpolating clock signals and for providing duty cycle corrected clock signals

Apparatuses and methods for phase interpolating clock signals and for providing duty cycle corrected clock signals are described. An example apparatus includes a first inverter configured to receive first and second clock signals and further includes a second inverter configured to receive the first and second clock signals. ... Micron Technology Inc

01/08/15 / #20150008953

Apparatus and methods for through substrate via test

A stack of vertically-connected, horizontally-oriented integrated circuits (ics) may have electrical connections from the front side of one ic to the back side of another ic. Electrical signals may be transferred from the back side of one ic to the front side of the same ic by means of through substrate vias (tsvs), which may include through silicon vias. ... Micron Technology Inc

01/08/15 / #20150008577

Methods of fluxless micro-piercing of solder balls, and resulting devices

A method of establishing conductive connections is disclosed. The method includes providing an integrated circuit die having a plurality of solder balls each of which has an oxide layer on an outer surface of the solder ball. ... Micron Technology Inc

01/08/15 / #20150008535

Devices including fin transistors robust to gate shorts and methods of making the same

Disclosed are methods, systems and devices, including a method that includes the acts of etching an inter-row trench in a substrate, substantially or entirely filling the inter-row trench with a dielectric material, and forming a fin and a insulating projection at least in part by etching a gate trench in the substrate. In some embodiments, the insulating projection includes at least some of the dielectric material in the inter-row trench.. ... Micron Technology Inc

01/08/15 / #20150008441

Solid state lighting devices with selected thermal expansion and/or surface characteristics, and associated methods

Solid state lighting devices with selected thermal expansion and/or surface characteristics, and associated methods are disclosed. A method in accordance with a particular embodiment includes forming an ssl (solid state lighting) formation structure having a formation structure coefficient of thermal expansion (cte), selecting a first material of an interlayer structure to have a first material cte greater than the substrate cte, and selecting a second material of the interlayer structure based at least in part on the second material having a second material cte less than the first material cte. ... Micron Technology Inc

01/08/15 / #20150008387

Self-selecting pcm device not requiring a dedicated selector transistor

A zinc oxide (zno) layer deposited using atomic layer deposition (ald) over a phase-change material forms a self-selected storage device. The diode formed at the zno/gst interface shows both rectification and storage capabilities within the pcm architecture.. ... Micron Technology Inc

01/01/15 / #20150006844

Methods, systems, and devices for management of a memory system

Methods, devices, and systems for a memory management system within an electronic device are disclosed, such as those wherein the memory management system is external to and compatible with architectures of currently existing operating systems. One such memory management system may include a power savings manager configured to be invoked by a memory allocation manager. ... Micron Technology Inc

01/01/15 / #20150006786

Operation management in a memory device

Multiple segment operations having non-volatile state trackers in memory devices are disclosed. Operations are segmented in multiple segments and selectively performed to avoid violating timing requirements within a memory device. ... Micron Technology Inc

01/01/15 / #20150004805

Methods of forming silicon-containing dielectric materials and semiconductor device structures, and related semiconductor device structures

A method of forming a silicon-containing dielectric material. The method includes forming a plasma comprising nitrogen radicals, absorbing the nitrogen radicals onto a substrate, and exposing the substrate to a silicon-containing precursor in a non-plasma environment to form monolayers of a silicon-containing dielectric material on the substrate. ... Micron Technology Inc

01/01/15 / #20150004786

Integrated circuit fabrication

A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. ... Micron Technology Inc

01/01/15 / #20150004764

Methods and apparatuses including a select transistor having a body region including monocrystalline semiconductor material and/or at least a portion of its gate located in a substrate

Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatuses and a select transistor coupled to the memory cell string. In at least one of such apparatuses, the select transistor can include a body region including a monocrystalline semiconductor material. ... Micron Technology Inc

01/01/15 / #20150004729

Light emitting devices with built-in chromaticity conversion and methods of manufacturing

Various embodiments of light emitting devices with built-in chromaticity conversion and associated methods of manufacturing are described herein. In one embodiment, a method for manufacturing a light emitting device includes forming a first semiconductor material, an active region, and a second semiconductor material on a substrate material in sequence, the active region being configured to produce a first emission. ... Micron Technology Inc

01/01/15 / #20150004532

Photomask having a blind region including periodical clear portions

A photo mask includes a plurality of dark patterns disposed on a transparent substrate, a first region, a shield region, and a second region. The first region includes the dark patterns that are disposed with a wider space than a first distance. ... Micron Technology Inc

01/01/15 / #20150003775

Photonic device having a photonic crystal lower cladding layer provided on a semiconductor substrate

An integrated photonic device is provided with a photonic crystal lower cladding on a semiconductor substrate.. . ... Micron Technology Inc

01/01/15 / #20150003177

Semiconductor device suppressing bti deterioration

Disclosed herein is a device includes a command generation circuit that activates first and second command signals, an internal circuit that includes a plurality of transistors that are brought into a first operation state when at least one of the first and second command signals is activated, and an output gate circuit that receives a first signal output from the internal circuit, the output gate circuit being configured to pass the first signal when the second command signal is deactivated and to block the first signal when the second command signal is activated.. . ... Micron Technology Inc

01/01/15 / #20150003164

Content addressable memory

Content addressable memory (cam) devices provide for high density, low cost cam devices. Cam devices include a non-volatile memory array having a plurality of nand memory cell strings, wherein a nand memory cell string of the non-volatile memory array comprises a plurality of cam memory cells, and wherein the cam memory cells comprise non-volatile memory cells of a same nand memory cell string. ... Micron Technology Inc

01/01/15 / #20150003149

Mixed mode programming for phase change memory

Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a phase change memory.. . ... Micron Technology Inc

01/01/15 / #20150002206

Semiconductor device having level shift circuit

Disclosed herein is a device includes; a level conversion circuit coupled to first and third power supply lines, receiving a first signal and an inverted signal of the first signal each having an amplitude between first and second potentials, and output ting a second signal having an amplitude between first and third potentials; a delay circuit coupled to the first and second power supply lines, and output ting a third signal delayed from the first signal; and an output circuit including first and second transistors coupled in series between the first and third power supply lines, the first transistor having a control electrode supplied with the second signal, and the second transistor having a control electrode supplied with the third signal.. . ... Micron Technology Inc

01/01/15 / #20150002201

Semiconductor device having duty correction circuit

Disclosed herein is a device includes a duty correction circuit adjusting a duty ratio of a first clock signal based on a duty control signal to generate a second clock signal; a delay line delaying the second clock signal to generate a third clock signal; and a duty cycle detector detecting the duty ratio of the second clock signal to generate the duty control signal in a first mode, and detecting the duty ratio of the third clock signal to generate the duty control signal in a second mode.. . ... Micron Technology Inc

01/01/15 / #20150002196

Semiconductor device having dll circuit

Disclosed herein is a device includes a first delay circuit delaying a first clock signal according to a count value to generate a second clock signal, a phase determination circuit comparing a phase of the first clock signal with a phase of the second clock signal to generate a phase determination signal, an up-down counter updating the count value according to the phase determination signal each time an update signal is activated, and an update control circuit generating the update signal at a variable interval.. . ... Micron Technology Inc

01/01/15 / #20150001674

Capacitors having dielectric regions that include multiple metal oxide-comprising materials

Capacitors and methods of forming capacitors are disclosed, and which include an inner conductive metal capacitor electrode and an outer conductive metal capacitor electrode. A capacitor dielectric region is received between the inner and the outer conductive metal capacitor electrodes and has a thickness no greater than 150 angstroms. ... Micron Technology Inc

01/01/15 / #20150001673

High dielectric constant transition metal oxide materials

A transition metal oxide dielectric material is doped with a non-metal in order to enhance the electrical properties of the metal oxide. In a preferred embodiment, a transition metal oxide is deposited over a bottom electrode and implanted with a dopant. ... Micron Technology Inc

01/01/15 / #20150001654

Memory cells, methods of operation and fabrication, semiconductor device structures, and memory systems

A magnetic cell core includes at least one stressor structure proximate to a magnetic region (e.g., a free region or a fixed region). The magnetic region may be formed of a magnetic material exhibiting magnetostriction. ... Micron Technology Inc

01/01/15 / #20150001613

Semiconductor devices including stair step structures, and related methods

Semiconductor devices, such as three-dimensional memory devices, include a memory array including a stack of conductive tiers and a stair step structure. The stair step structure is positioned between first and second portions of the memory array and includes contact regions for respective conductive tiers of the stack of conductive tiers. ... Micron Technology Inc

01/01/15 / #20150001605

Gate constructions of recessed access devices and methods of forming gate constructions of recessed access devices

A method of forming a gate construction of a recessed access device includes forming a pair of sidewall spacers laterally over opposing sidewalls of a gate dielectric and elevationally over first conductive gate material. The gate dielectric, the first conductive gate material, and the sidewall spacers are received within a trench formed in semiconductive material. ... Micron Technology Inc

01/01/15 / #20150001602

Semiconductor device having metal bit line

Disclosed herein is a device that includes: a semiconductor substrate including a memory cell region and a peripheral circuit region arranged around the memory cell region; an element isolation region formed in the memory cell region and the peripheral circuit region; a cell active region defined by the element isolation region formed in the memory cell region; a first interlayer insulation film disposed on the cell active region, the first interlayer insulation film having a bit contact hole passing therethrough to expose a portion of an upper surface of the cell active region; and a bit line having a first metal laminated film, the bit line being disposed on the first interlayer insulation film so as to fill the bit contact hole.. . ... Micron Technology Inc

01/01/15 / #20150001461

Semiconductor constructions, memory cells, memory arrays and methods of forming memory cells

Some embodiments include a construction having oxygen-sensitive structures directly over spaced-apart nodes. Each oxygen-sensitive structure includes an angled plate having a horizontal portion along a top surface of a node and a non-horizontal portion extending upwardly from the horizontal portion. ... Micron Technology Inc

01/01/15 / #20150001458

Self-aligned cross-point phase change memory-switch array

Subject matter disclosed herein relates to a memory device, and more particularly to a self-aligned cross-point phase change memory-switch array and methods of fabricating same.. . ... Micron Technology Inc








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