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Micron Technology Inc patents (2016 archive)


Recent patent applications related to Micron Technology Inc. Micron Technology Inc is listed as an Agent/Assignee. Note: Micron Technology Inc may have other listings under different names/spellings. We're not affiliated with Micron Technology Inc, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "M" | Micron Technology Inc-related inventors


Solid state lighting devices with accessible electrodes and methods of manufacturing

Various embodiments of light emitting dies and solid state lighting (“ssl”) devices with light emitting dies, assemblies, and methods of manufacturing are described herein. In one embodiment, a light emitting die includes an ssl structure configured to emit light in response to an applied electrical voltage, a first electrode carried by the ssl structure, and a second electrode spaced apart from the first electrode of the ssl structure. ... Micron Technology Inc

Performing logical operations using sensing circuitry

The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells, sensing circuitry coupled to the array of memory cells via a sense line, and a controller coupled to the array of memory cells and the sensing circuitry. ... Micron Technology Inc

Methods and systems for data analysis in a state machine

A device includes a match element that includes a first data input configured to receive a first result, wherein the first result is of an analysis performed on at least a portion of a data stream by an element of a state machine. The match element also includes a second data input configured to receive a second result, wherein the second result is of an analysis performed on at least a portion of the data stream by another element of the state machine. ... Micron Technology Inc

Vertical light emitting devices with nickel silicide bonding and methods of manufacturing

Various embodiments of light emitting devices, assemblies, and methods of manufacturing are described herein. In one embodiment, a method for manufacturing a lighting emitting device includes forming a light emitting structure, and depositing a barrier material, a mirror material, and a bonding material on the light emitting structure in series. ... Micron Technology Inc

Vertical memory cell string with dielectric in a portion of the body

Some embodiments include a memory cell string having a body having a channel extending therein and in contact with a source/drain, a select gate adjacent to the body, a plurality of access lines adjacent to the body, and a dielectric in a portion of the body between the source/drain and a level corresponding to an end of the plurality of access lines most adjacent to the select gate. The dielectric in the portion of the body does not extend along an entire length of the body. ... Micron Technology Inc

Solid state transducer devices, including devices having integrated electrostatic discharge protection, and associated systems and methods

Solid state transducer devices having integrated electrostatic discharge protection and associated systems and methods are disclosed herein. In one embodiment, a solid state transducer device includes a solid state emitter, and an electrostatic discharge device carried by the solid state emitter. ... Micron Technology Inc

Elevated pocket pixels, imaging devices and systems including the same and method of forming the same

An elevated photosensor for image sensors and methods of forming the photosensor. The photosensor may have light sensors having indentation features including, but not limited to, v-shaped, u-shaped, or other shaped features. ... Micron Technology Inc

Methods and apparatuses having strings of memory cells including a metal source

Methods for forming a string of memory cells, an apparatus having a string of memory cells, and a system are disclosed. A method for forming the string of memory cells comprises forming a metal silicide source material over a substrate. ... Micron Technology Inc

Stacked semiconductor die assemblies with high efficiency thermal paths and associated methods

A semiconductor die assembly having high efficiency thermal paths. In one embodiment, the semiconductor die assembly comprises a package support substrate, a first semiconductor die having a peripheral region and a stacking region, and a second semiconductor die attached to the stacking region of the first die such that the peripheral region is lateral of the second die. ... Micron Technology Inc

Back-to-back solid state lighting devices and associated methods

Solid state lights (ssls) including a back-to-back solid state emitters (sses) and associated methods are disclosed herein. In various embodiments, an ssl can include a carrier substrate having a first surface and a second surface different from the first surface. ... Micron Technology Inc

Boosting channels of memory cells

A method for programming a non-volatile memory device includes concurrently boosting channels of memory cells in a selected memory string and an unselected memory string of the memory device, discharging the boosted channels of the memory cells in the selected memory string, and programming a selected memory cell in the selected memory string after discharging the boosted channels in the selected memory string.. . ... Micron Technology Inc

Apparatuses and methods for performing an exclusive or operation using sensing circuitry

The present disclosure includes apparatuses and methods related to determining an xor value in memory. An example method can include performing a nand operation on a data value stored in a first memory cell and a data value stored in a second memory cell. ... Micron Technology Inc

Apparatuses and methods for chip identification in a memory package

Apparatuses, methods, memory packages, and semiconductor chips are disclosed. An example apparatus includes a semiconductor chip including a layer identification setting path circuit configured to receive respective input signals from a plurality of input layer identification setting paths. ... Micron Technology Inc

Data shifting

The present disclosure includes apparatuses and methods related to data shifting. An example apparatus comprises a first memory cell coupled to a first sense line of an array, a first isolation device located between the first memory cell and first sensing circuitry corresponding thereto, and a second isolation device located between the first memory cell and second sensing circuitry corresponding to a second sense line. ... Micron Technology Inc

12/22/16 / #20160371518

Systems and methods using single antenna for multiple resonant frequency ranges

A radio frequency device utilizing an antenna having a single antenna structure resonant on multiple resonant frequency ranges. The antenna can be configured to operate within multiple frequency ranges for communication according to respective protocols associated with the respective frequency ranges.. ... Micron Technology Inc

12/22/16 / #20160371335

Memory devices for pattern matching

Memory devices for facilitating pattern matching and having an array of memory cells, a plurality of key registers to store a representation of a key word, and a plurality of multiplexers, each multiplexer of the plurality of multiplexers to select a representation of a bit from a key register of the plurality of key registers to compare to data stored in the array of memory cells.. . ... Micron Technology Inc

12/22/16 / #20160371215

Methods and apparatuses for providing data received by a state machine engine

An apparatus can include a first state machine engine configured to receive a first portion of a data stream from a processor and a second state machine engine configured to receive a second portion of the data stream from the processor. The apparatus includes a buffer interface configured to enable data transfer between the first and second state machine engines. ... Micron Technology Inc

12/22/16 / #20160371185

Multiple data channel memory module architecture

According to one example of the present disclosure, a system includes a computing element configured to provide requests for memory access operations and a memory module comprising a plurality of memories, a plurality of independent data channels, each of the independent data channels coupled to one of the plurality of memories, a plurality of internal address/control channels, each of the independent address/control channels coupled to one of the plurality of memories, and control logic coupled to the plurality of internal address/control channels and configured to receive and decode address and control information for a memory access operation, the control logic further configured to selectively provide the decoded address and control information to a selected internal address/control channel for a selected independent data channel of the plurality of independent data channels based on the received address and control information for the memory access operation.. . ... Micron Technology Inc

12/22/16 / #20160371033

Apparatuses and methods for data transfer from sensing circuitry to a controller

The present disclosure describes data transfer in a memory device from sensing circuitry to controller. An example apparatus includes a controller coupled to a memory device. ... Micron Technology Inc

12/15/16 / #20160365860

Clock signal and supply voltage variation tracking

Embodiments disclosed herein provide an apparatus comprising a clock generation circuit configured to generate a first signal for a first time period and a second signal for a second time period, a charge pump circuit coupled to the clock generation circuit and configured to generate a first voltage and a second voltage based, at least in part, on the first time period and the second time period, and a comparison circuit coupled to the charge pump circuit, the comparison circuit configured to compare a difference between the first voltage and the second voltage with a threshold value and generate an active tracking enablement signal in response to determining that the difference between the first and second voltages exceeds the threshold value.. . ... Micron Technology Inc

12/15/16 / #20160365514

Semiconductor structures including liners comprising alucone and related methods

A semiconductor device including stacked structures. The stacked structures include at least two chalcogenide materials or alternating dielectric materials and conductive materials. ... Micron Technology Inc

12/15/16 / #20160365355

Methods of forming memory arrays

A method of forming a memory array includes filling a circular hole that is lined with a charge trapping layer with a conductor, forming a first slot and a second slot so that the conductor is between the first slot and the second slot and so that the first slot cuts through at least a portion of a first portion of the charge trapping layer and the second slot cuts through at least a portion of a second portion of the charge trapping layer, and filling the first slot with a dielectric to form a first isolation region and the second slot with the dielectric to form a second isolation region.. . ... Micron Technology Inc

12/15/16 / #20160365152

Programming methods and memories

A method of programming a memory includes boosting a channel voltage while a first portion of a plurality of increasing programming pulses is applied to a selected access line, and when a criteria is met, reducing the channel voltage to a reduced voltage level and subsequently boosting the channel voltage, starting from the reduced voltage level, while a second portion of the plurality of increasing programming pulses is applied to the selected access line. Differences between the channel voltage boosted while the first portion of the plurality of increasing programming pulses is applied and voltages of the first portion of the plurality of increasing programming pulses are substantially the same as differences between the channel voltage boosted while the second portion of the plurality of increasing programming pulses is applied and voltages of the second portion of the plurality of increasing programming pulses.. ... Micron Technology Inc

12/15/16 / #20160365142

Memory cells having a plurality of resistance variable materials

Resistance variable memory cells having a plurality of resistance variable materials and methods of operating and forming the same are described herein. As an example, a resistance variable memory cell can include a plurality of resistance variable materials located between a plug material and an electrode material. ... Micron Technology Inc

12/15/16 / #20160365141

Apparatuses, devices and methods for sensing a snapback event in a circuit

Example subject matter disclosed herein relates to apparatuses and/or devices, and/or various methods for use therein, in which an application of an electric potential to a circuit may be initiated and subsequently changed in response to a determination that a snapback event has occurred in a circuit. For example, a circuit may comprise a memory cell that may experience a snapback event as a result of an applied electric potential. ... Micron Technology Inc

12/15/16 / #20160365129

Simulating access lines

Examples of the present disclosure provide apparatuses and methods for simulating access lines in a memory. An example method can include receiving a first bit-vector and a second bit-vector in a format associated with storing the first bit-vector in memory cells coupled to a first access line and a first number of sense lines and storing the second bit-vector in memory cells coupled to a second access line and the first number of sense lines. ... Micron Technology Inc

12/15/16 / #20160365128

Apparatuses and methods for compensating for process, voltage, and temperature variation in a memory

Systems and methods are described for compensating for variations in process, voltage, temperature, or combinations thereof in an apparatus. An example apparatus may be a memory circuit. ... Micron Technology Inc

12/15/16 / #20160364337

Memory having a static cache and a dynamic cache

The present disclosure includes memory having a static cache and a dynamic cache. A number of embodiments include a memory, wherein the memory includes a first portion configured to operate as a static single level cell (slc) cache and a second portion configured to operate as a dynamic slc cache when the entire first portion of the memory has data stored therein.. ... Micron Technology Inc

12/15/16 / #20160364294

Data storage error protection

Apparatuses and methods for data storage error protection are described. One example apparatus for data storage error protection includes an array of memory cells arranged in a first dimension and a second dimension. ... Micron Technology Inc

12/15/16 / #20160364293

Apparatuses and methods for encoding using error protection codes

Subject matter disclosed herein relates to error protection of data stored in and/or read from a memory device.. . ... Micron Technology Inc

12/15/16 / #20160364181

Stripe mapping in memory

Examples of the present disclosure provide apparatuses and methods related to redundant array of independent disks (raid) stripe mapping in memory. An example method comprises writing data in a number of stripes across a storage volume of a plurality of memory devices according to a stripe map; wherein each of the number of stripes includes a number of elements; and wherein the stripe map includes a number of stripe indexes to identify the number of stripes and a number of element identifiers to identify elements included in each of the number of stripes.. ... Micron Technology Inc

12/15/16 / #20160364179

Command queuing

The present disclosure includes apparatuses and methods for command queuing. A number of embodiments include receiving a queued command request at a memory system from a host, sending a command response from the memory system to the host that indicates the memory system is ready to receive a command in a command queue of the memory system, and receiving, in response to sending the command response, a command descriptor block for the command at the memory system from the host.. ... Micron Technology Inc

12/15/16 / #20160363662

Systems and methods to use radar in rfid systems

Systems and methods to use radar systems for radio frequency identification (rfid) applications. In one embodiment, radar systems are adapted to use rfid communications protocols and methods to enhance the usefulness of radar systems beyond the determination of the presence, distance, direction and/or speed of a vehicle or object, to additionally include the transmission of data such as object identification and additional messages or data.. ... Micron Technology Inc

12/08/16 / #20160360128

Method, apparatus, and system providing an imager with pixels having extended dynamic range

The dynamic range of a pixel is increased by using selective photosensor resets during a frame time of image capture at a timing depending on the light intensity that the pixel will be exposed to during the frame time. Pixels that will be exposed to high light intensity are reset later in the frame than pixels that will be exposed to lower light intensity.. ... Micron Technology Inc

12/08/16 / #20160359486

Apparatus and methods for leakage current reduction in integrated circuits

This disclosure relates to leakage current reduction in integrated circuits (ics). In one aspect, an ic can include a digital logic circuit and a polarization circuit. ... Micron Technology Inc

12/08/16 / #20160359105

Methods of forming magnetic memory cells and semiconductor devices

A magnetic cell includes a free region between an intermediate oxide region (e.g., a tunnel barrier) and a secondary oxide region. Both oxide regions may be configured to induce magnetic anisotropy (“ma”) with the free region, enhancing the ma strength of the free region. ... Micron Technology Inc

12/08/16 / #20160358898

Methods of manufacturing multi die semiconductor device packages and related assemblies

Methods of making semiconductor device packages may involve attaching a first semiconductor die to a carrier wafer, an inactive surface of the first semiconductor die facing the carrier wafer. One or more additional semiconductor die may be stacked on the first semiconductor die on a side of the first semiconductor die opposite the carrier wafer to form a stack of semiconductor dice. ... Micron Technology Inc

12/08/16 / #20160358831

Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices

Stacked microelectronic devices and methods for manufacturing such devices are disclosed herein. In one embodiment, a stacked microelectronic device assembly can include a first known good packaged microelectronic device including a first interposer substrate. ... Micron Technology Inc

12/08/16 / #20160358661

Methods of operating memory

Methods of operating memory include generating a data value indicative of a level of a property sensed from a data line while applying potentials to control gates of memory cells of more than one string of series-connected memory cells connected to that data line. Methods of operating memory further include generating data values indicative of levels of a property sensed from data lines while applying potentials to control gates of memory cells of strings of series-connected memory cells connected to those data lines, performing a logical operation on a set of data values comprising those data values, and determining a potential to be applied to control gates of different memory cells of those strings of series-connected memory cells in response to an output of the logical operation on the set of data values.. ... Micron Technology Inc

12/08/16 / #20160358650

Multi-function resistance change memory cells and apparatuses including the same

Various embodiments comprise apparatuses having a number of memory cells including drive circuitry to provide signal pulses of a selected time duration and/or amplitude, and an array of resistance change memory cells electrically coupled to the drive circuitry. The resistance change memory cells may be programmed for a range of retention time periods and operating speeds based on the received signal pulse. ... Micron Technology Inc

12/08/16 / #20160358647

Threshold voltage analysis

Apparatuses and methods for threshold voltage analysis are described. One or more methods for threshold voltage analysis include storing expected state indicators corresponding to a group of memory cells, applying a first sensing voltage to a selected access line to which the group of memory cells is coupled, sensing whether at least one of the memory cells of the group conducts responsive to the first sensing voltage, determining whether a discharge indicator for the at least one of the memory cells has changed responsive to application of the first sensing voltage, and determining that the first sensing voltage is the threshold voltage for a particular program state of the at least one of the memory cells.. ... Micron Technology Inc

12/08/16 / #20160358641

Cross-point memory cells, non-volatile memory arrays, methods of reading a memory cell, methods of programming a memory cell, methods of writing to and reading from a memory cell, and computer systems

Cross-point memory cells, non-volatile memory arrays, methods of reading a memory cell, methods of programming a memory cell, and methods of writing to and reading from a memory cell are described. In one embodiment, a cross-point memory cell includes a word line extending in a first direction, a bit line extending in a second direction different from the first direction, the bit line and the word line crossing without physically contacting each other, and a capacitor formed between the word line and the bit line where such cross. ... Micron Technology Inc

12/08/16 / #20160357704

Methods and devices for reducing array size and complexity in automata processors

A method includes calculating a first position encoded pattern based on a first data pattern, and using an automata processor to compare the first position encoded pattern to a second position encoded pattern to identify a second data pattern within the first data pattern.. . ... Micron Technology Inc

12/08/16 / #20160357441

Sequential memory access operations

Methods of operating a memory include performing a memory access operation, obtaining an address corresponding to a subsequent memory access operation prior to stopping the memory access operation, stopping the memory access operation, sharing charge between access lines used for the memory access operation and access lines to be used for the subsequent memory access operation, and performing the subsequent memory access operation.. . ... Micron Technology Inc

12/01/16 / #20160351793

Magnetic memory cells, semiconductor devices, and methods of operation

A magnetic cell core includes at least one stressor structure proximate to a magnetic region (e.g., a free region or a fixed region). The magnetic region may be formed of a magnetic material exhibiting magnetostriction. ... Micron Technology Inc

12/01/16 / #20160351580

Devices and methods including an etch stop protection material

Protective dielectrics are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory may include a protective dielectric material. ... Micron Technology Inc

12/01/16 / #20160351551

Semiconductor device with modified current distribution

Semiconductor devices having modified current distribution and methods of forming the same are described herein. As an example, a memory die in contact with a logic die can be configured to draw a sum amount of current from a current source. ... Micron Technology Inc

12/01/16 / #20160351530

Semiconductor devices and packages including conductive underfill material and related methods

Semiconductor devices and device packages include at least one semiconductor die electrically coupled to a substrate through a plurality of conductive structures. The at least one semiconductor die may be a plurality of memory dice, and the substrate may be a logic die. ... Micron Technology Inc

12/01/16 / #20160351275

Determining soft data from a hard read

Apparatuses and methods involving the determination of soft data from hard reads are provided. One example method can include determining, using a hard read, a state of a memory cell. ... Micron Technology Inc

12/01/16 / #20160351274

Leakage current detection

A first switch is closed to initialize a circuit by charging a capacitance of the circuit. A second switch is closed to initialize an amplifier in unity-gain configuration. ... Micron Technology Inc

12/01/16 / #20160351265

Functional data programming and reading in a memory

Methods for reading data that was functionally stored include reading a pattern of threshold voltages from a particular group of memory cells, determining which pattern, of a plurality of patterns, matches the read pattern, and determining a group of decoded data associated with the pattern determined to match the read pattern.. . ... Micron Technology Inc

12/01/16 / #20160351263

Apparatuses and methods for performing multiple memory operations

The disclosed technology relates to a memory device configured to perform multiple access operations in response to a single command received through a memory controller and a method of performing the multiple access operations. In one aspect, the memory device includes a memory array comprising a plurality of memory cells and a memory controller. ... Micron Technology Inc

12/01/16 / #20160351253

Programming memory cells to be programmed to different levels to an intermediate level from a lowest level

Embodiments of methods and memory devices for performing the methods are disclosed. In an embodiment, one such method includes programming all memory cells that are to be respectively programmed to different levels other than a lowest level, corresponding to a lowest data state, to an intermediate level from the lowest level and respectively programming all the memory cells that are to be respectively programmed to the different levels other than the lowest level to the different levels other than the lowest level from the intermediate level.. ... Micron Technology Inc

12/01/16 / #20160351246

Semiconductor device suppressing bti deterioration

Disclosed herein is a device includes a command generation circuit that activates first and second command signals, an internal circuit that includes a plurality of transistors that are brought into a first operation state when at least one of the first and second command signals is activated, and an output gate circuit that receives a first signal output from the internal circuit, the output gate circuit being configured to pass the first signal when the second command signal is deactivated and to block the first signal when the second command signal is activated.. . ... Micron Technology Inc

12/01/16 / #20160351233

Interconnection for memory electrodes

Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central points along adjacent lines that are not terminated are made in the gap, and vertical interconnection through can additionally be made through the gap without contacting the lines of that level.. ... Micron Technology Inc

12/01/16 / #20160350617

Histogram creation process for memory devices

A processor-in-memory device includes a memory array, a sense amplifier, and a processing unit that has an accumulator. The processing unit is configured to receive a set of data. ... Micron Technology Inc

12/01/16 / #20160350230

Apparatuses and methods for compute enabled cache

The present disclosure includes apparatuses and methods for compute enabled cache. An example apparatus comprises a compute component, a memory and a controller coupled to the memory. ... Micron Technology Inc

12/01/16 / #20160350184

Methods and apparatuses for error correction

Embodiments of the present invention disclose methods and apparatuses for correcting errors in data stored in a solid state device. The solid state device may have a plurality of bits stored in multi-level memory cells. ... Micron Technology Inc

11/24/16 / #20160343925

Solid state optoelectronic device with preformed metal support substrate

A wafer-level process for manufacturing solid state lighting (“ssl”) devices using large-diameter preformed metal substrates is disclosed. A light emitting structure is formed on a growth substrate, and a preformed metal substrate is bonded to the light emitting structure opposite the growth substrate. ... Micron Technology Inc

11/24/16 / #20160343912

Solid-state radiation transducer devices having at least partially transparent buried-contact elements, and associated systems and methods

Solid-state radiation transducer (ssrt) devices having buried contacts that are at least partially transparent and associated systems and methods are disclosed herein. An ssrt device configured in accordance with a particular embodiment can include a radiation transducer including a first semiconductor material, a second semiconductor material, and an active region between the first semiconductor material and the second semiconductor material. ... Micron Technology Inc

11/24/16 / #20160343699

Stacked semiconductor die assemblies with support members and associated systems and methods

Stacked semiconductor die assemblies with support members and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first semiconductor die attached to the package substrate, and a plurality of support members also attached to the package substrate. ... Micron Technology Inc

11/24/16 / #20160343690

Package-on-package semiconductor assemblies and methods of manufacturing the same

Package-on-package systems for packaging semiconductor devices. In one embodiment, a package-on-package system comprises a first semiconductor package device and a second semiconductor package device. ... Micron Technology Inc

11/24/16 / #20160343689

Interconnect structure with improved conductive properties and associated systems and methods

Interconnect structures with improved conductive properties are disclosed herein. In one embodiment, an interconnect structure can include a first conductive member coupled to a first semiconductor die and a second conductive member coupled to second semiconductor die. ... Micron Technology Inc

11/24/16 / #20160343687

Semiconductor device assembly with heat transfer structure formed from semiconductor material

Semiconductor device assemblies with heat transfer structures formed from semiconductor materials are disclosed herein. In one embodiment, a semiconductor device assembly can include a thermal transfer structure formed from a semiconductor substrate. ... Micron Technology Inc

11/24/16 / #20160343675

Semiconductor device including semiconductor chips mounted over both surfaces of substrate

A semiconductor chip 10 flip-chip mounted on a first surface 32 of a wiring substrate 30, a semiconductor chip 20 flip-chip mounted on a second surface 33 of the wiring substrate 30, a sealing resin 71 covering the semiconductor chip 10, a sealing resin 72 covering the semiconductor chip 20, a plurality of conductive posts provided to penetrate through the sealing resin 72, and a plurality of solder balls mounted on second ends of the plurality of conductive posts exposed from the sealing resin 72 are provided; and the mounting directions of the semiconductor chips 10 and 20 are mutually different by 90°. Both of the planar shapes of the semiconductor chips 10 and 20 are rectangular shapes, the semiconductor chip 10 is mounted so that the long sides thereof are parallel to the long sides of the wiring substrate 30, and the semiconductor chip 20 is mounted so that the long sides thereof are perpendicular to the long sides of the wiring substrate 30.. ... Micron Technology Inc

11/24/16 / #20160343639

Seminconductor device assembly with vapor chamber

Semiconductor device assemblies having stacked semiconductor dies and thermal transfer devices that include vapor chambers are disclosed herein. In one embodiment, a semiconductor device assembly includes a first semiconductor die, a second semiconductor die at a base region of the first die, and a thermal transfer device attached to a peripheral region of the first die and extending over the second die. ... Micron Technology Inc

11/24/16 / #20160343446

Apparatuses and methods using dummy cells programmed to different states

Apparatuses and methods for reducing capacitive loading are described. One apparatus includes a first memory string including first and second dummy memory cells, a second memory string including third and fourth dummy memory cells, and a control unit configured to provide first and second control signals to activate the first and second dummy memory cells of the first memory string and to further deactivate at least one of the third and fourth dummy memory cell of the second memory string.. ... Micron Technology Inc

11/24/16 / #20160343438

Apparatus and methods including source gates

Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor material), a source gate device, and a source select device coupled between the source gate device and the string. Additional apparatus and methods are described.. ... Micron Technology Inc

11/24/16 / #20160343423

Apparatus having dice to perorm refresh operations

Some embodiments include an apparatus that comprise an interface chip having an oscillator to produce an original clock signal, a first memory chip having first memory cells, and a second memory chip having second memory cells. The first memory cells may be refreshed in response to a first clock signal based on the original clock signal. ... Micron Technology Inc

11/24/16 / #20160343422

Virtual ground sensing circuitry and related devices, systems, and methods

Virtual ground sensing circuits, electrical systems, computing devices, and related methods are disclosed. A virtual ground sensing circuit includes a sense circuit configured to compare a reference voltage potential to a sense node voltage potential, and virtual ground circuitry operably coupled to the sense circuit. ... Micron Technology Inc

11/24/16 / #20160342815

Multi-function, modular system for network security, secure communication, and malware protection

Representative embodiments are disclosed for providing network and system security. A representative apparatus includes an input-output connector coupleable to a data network; a network interface circuit having a communication port; a nonvolatile memory storing a configuration bit image; and a field programmable gate array (“fpga”) coupled to the network interface circuit through the communication port, the fpga configurable to appear solely as a communication device to the first network interface circuit, and to bidirectionally monitor all data packets transferred between the input-output connector and the first network interface circuit and any coupled host computing system. ... Micron Technology Inc

11/24/16 / #20160342339

Translation lookaside buffer in memory

Examples of the present disclosure provide apparatuses and methods related to a translation lookaside buffer in memory. An example method comprises receiving a command including a virtual address from a host translating the virtual address to a physical address on volatile memory of a memory device using a translation lookaside buffer (tlb).. ... Micron Technology Inc

11/24/16 / #20160342193

Power management

The present disclosure includes methods and apparatuses for power management. One method includes transferring data between a memory and a controller via an input/output (i/o) bus, and adjusting an amount of power consumed in association with transferring the data by throttling the i/o bus.. ... Micron Technology Inc

11/24/16 / #20160342187

Power management

Apparatus facilitating peak power management are useful in mitigating excessive current levels within a multi-die package. For example, such apparatus may include an array of memory cells, a controller for performing an access operation on the array of memory cells, an input buffer having an input connected to a clock signal line and having an output, a clock generator for generating an internal clock signal, an output buffer having an input connected to receive the internal clock signal and having an output connected to the clock signal line, and a counter for counting pulses of a particular clock signal selected from a group consisting of the internal clock signal from the clock generator and an external clock signal from the output of the input buffer.. ... Micron Technology Inc

11/17/16 / #20160336687

Interconnection systems

Interconnection systems are shown that include communication contacts, and a guide. Configurations are shown with a guide that locates a male portion with respect to a female portion and guides their engagement before any communication contacts are engaged. ... Micron Technology Inc

11/17/16 / #20160336342

Semiconductor constructions and nand unit cells

Some embodiments include methods of forming semiconductor constructions. Alternating layers of n-type doped material and p-type doped material may be formed. ... Micron Technology Inc

11/17/16 / #20160336341

Methods and apparatuses having memory cells including a monolithic semiconductor channel

Methods for forming a string of memory cells, apparatuses having a string of memory cells, and systems are disclosed. One such method for forming a string of memory cells forms a source material over a substrate. ... Micron Technology Inc

11/17/16 / #20160336325

Array of conductive vias, methods of forming a memory array, and methods of forming conductive vias

A method of forming conductive vias comprises forming at least three parallel line constructions elevationally over a substrate. The line constructions individually comprise a dielectric top and dielectric sidewalls. ... Micron Technology Inc

11/17/16 / #20160336302

Discontinuous patterned bonds for semiconductor devices and associated systems and methods

Discontinuous bonds for semiconductor devices are disclosed herein. A device in accordance with a particular embodiment includes a first substrate and a second substrate, with at least one of the first substrate and the second substrate having a plurality of solid-state transducers. ... Micron Technology Inc

11/17/16 / #20160336300

Stacked semiconductor die assemblies with die support members and associated systems and methods

Stacked semiconductor die assemblies with die support members and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first semiconductor die attached to the package substrate, and a support member attached to the package substrate. ... Micron Technology Inc

11/17/16 / #20160336276

Electromagnetic shield and associated methods

Semiconductor devices are described, along with methods and systems that include them. One such device includes a diffusion region in a semiconductor material, a terminal coupled to the diffusion region, and a field plate coupled to the terminal and extending from the terminal over the diffusion region to shield the diffusion region. ... Micron Technology Inc

11/17/16 / #20160336046

Memory arrays

Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines extending perpendicularly from the global bitlines, and wordlines extending along a second horizontal direction which is perpendicular to the first horizontal direction. ... Micron Technology Inc

11/17/16 / #20160335204

Apparatuses and methods for asymmetric input/output interface for a memory

Apparatuses and methods for asymmetric input/output interfaces for memory are disclosed. An example apparatus may include a receiver and a transmitter. ... Micron Technology Inc

11/10/16 / #20160329489

Magnetic tunnel junctions

A magnetic tunnel junction comprises a conductive first magnetic electrode comprising magnetic recording material. A conductive second magnetic electrode is spaced from the first electrode and comprises magnetic reference material. ... Micron Technology Inc

11/10/16 / #20160329486

Magnetic tunnel junctions

A magnetic tunnel junction has a conductive first magnetic electrode comprising magnetic recording material. A conductive second magnetic electrode is spaced from the first electrode and comprises magnetic reference material. ... Micron Technology Inc

11/10/16 / #20160329377

Select device for memory cell applications

The present disclosure includes select devices and methods of using select device for memory cell applications. An example select device includes a first electrode having a particular geometry, a semiconductor material formed on the first electrode and a second electrode having the particular geometry with formed on the semiconductor material, wherein the select device is configured to snap between resistive states in response to signals that are applied to the select device.. ... Micron Technology Inc

11/10/16 / #20160329303

Semiconductor device packages including a controller element and related methods

Semiconductor device packages include a stack of semiconductor memory devices positioned over an interposer substrate, a controller element, and a redistribution substrate positioned laterally adjacent to the controller element. At least a portion of the controller element is positioned directly between the stack and the interposer substrate. ... Micron Technology Inc

11/10/16 / #20160329102

Reduced voltage nonvolatile flash memory

Systems include a first semiconductor die comprising a charge pump to generate power supply signals, a second semiconductor die comprising a memory array and programming circuitry, and a bus connected to the first and second semiconductor dies to carry the power supply signals to the programming circuitry. The programming circuitry is adapted to program memory cells of the memory array so that at least one programmed threshold voltage level is less than a voltage level of the power supply signals. ... Micron Technology Inc

11/10/16 / #20160329090

Frequency synthesis for memory input-output operations

A memory channel including an internal clock circuit is disclosed. The clock circuit may synthesize an internal clock signal for use by one or more components of the memory channel. ... Micron Technology Inc

11/10/16 / #20160328353

Devices, systems, and methods of reducing chip select

Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (id_a and id_m). ... Micron Technology Inc

11/10/16 / #20160328179

Multiple virtually over-provisioned, virtual storage devices created from a single physical storage device

Methods are disclosed for partitioning a solid state storage device to create multiple virtual storage devices, which may include one or more virtual tiers of data. Some examples of the methods address self-tiering of the data between the multiple virtual tiers within the physical device. ... Micron Technology Inc

11/03/16 / #20160322964

Methods and apparatuses including command latency control circuit

Methods and apparatus including a latency control circuit are described. An example apparatus includes a delay line circuit configured to delay a clock signal, and a latch control circuit configured to receive the clock signal and the delayed clock signal. ... Micron Technology Inc

11/03/16 / #20160322564

Resistive memory having confined filament formation

Resistive memory having confined filament formation is described herein. One or more method embodiments include forming an opening in a stack having a silicon material and an oxide material on the silicon material, and forming an oxide material in the opening adjacent the silicon material, wherein the oxide material formed in the opening confines filament formation in the resistive memory cell to an area enclosed by the oxide material formed in the opening.. ... Micron Technology Inc

11/03/16 / #20160322478

Methods of forming transistor gates

Some embodiments include methods of forming charge storage transistor gates and standard fet gates in which common processing is utilized for fabrication of at least some portions of the different types of gates. Fet and charge storage transistor gate stacks may be formed. ... Micron Technology Inc

11/03/16 / #20160322426

Memory structures and arrays, and methods of forming memory structures and arrays

Some embodiments include memory structures having a diode over a memory cell. The memory cell can include programmable material between a pair of electrodes, with the programmable material containing a multivalent metal oxide directly against a high-k dielectric. ... Micron Technology Inc

11/03/16 / #20160322363

Memory cells having a folded digit line architecture

Memory arrays having folded architectures and methods of making the same. Specifically, memory arrays having a portion of the transistors in a row that are reciprocated and shifted with respect to other transistors in the same row. ... Micron Technology Inc

11/03/16 / #20160322340

Semiconductor die assembly and methods of forming the same

Semiconductor die assemblies and methods of forming the same are described herein. As an example, a semiconductor die assembly may include a thermally conductive casing, a first face of a logic die coupled to the thermally conductive casing to form a thermal path that transfers heat away from the logic die to the thermally conductive casing, a substrate coupled to a second face of the logic die, and a die embedded at least partially in a cavity of the substrate.. ... Micron Technology Inc

11/03/16 / #20160320982

Methods and systems for using state vector data in a state machine engine

A state machine engine includes a state vector system. The state vector system includes an input buffer configured to receive state vector data from a restore buffer and to provide state vector data to a state machine lattice. ... Micron Technology Inc

11/03/16 / #20160320829

Method and device to reduce power consumption managment of a pattern-recognition processor

A device includes a pattern-recognition processor. The pattern recognition processor includes blocks, such that each of the blocks include a plurality of feature cells configured to analyze at least a portion of data to be analyzed and to selectively provide a result of the analysis. ... Micron Technology Inc

10/27/16 / #20160316528

Multi-junction solid state transducer devices for direct ac power and associated systems and methods

Multi junction solid-state transducer (sst) devices and associated systems and methods are disclosed herein. In several embodiments, for example, an sst system can include a first multi-junction sst chain having a first drive voltage, a first p-contact, and a first n-contact, and a second multi junction sst chain having a second drive voltage, a second p-contact, and a second n-contact. ... Micron Technology Inc

10/27/16 / #20160315639

Apparatuses and methods for pipelining memory operations with error correction coding

Apparatuses and methods for pipelining memory operations with error correction coding are disclosed. A method for pipelining consecutive write mask operations is disclosed wherein a second read operation of a second write mask operation occurs during error correction code calculation of a first write mask operation. ... Micron Technology Inc

10/27/16 / #20160315258

Resistive ram devices and methods

The present disclosure includes a high density resistive random access memory (rram) device, as well as methods of fabricating a high density rram device. One method of forming an rram device includes forming a resistive element having a metal-metal oxide interface. ... Micron Technology Inc

10/27/16 / #20160315223

Epitaxial devices

Epitaxial growth methods and devices are described that include a textured surface on a substrate. Geometry of the textured surface provides a reduced lattice mismatch between an epitaxial material and the substrate. ... Micron Technology Inc

10/27/16 / #20160314836

Reference voltage generation apparatuses and methods

A method and apparatuses for generating a reference voltage are disclosed. One example apparatus includes a current source coupled to a first power supply. ... Micron Technology Inc

10/27/16 / #20160314824

Apparatuses and methods for providing active and inactive clock signals to a command path circuit

Apparatuses and methods for providing active and inactive clock signals to a command path circuit are described. An example method includes providing an active clock signal to a command path for a first portion of a command cycle for a command of back-to-back commands. ... Micron Technology Inc

10/27/16 / #20160314823

Methods and apparatuses for command shifter reduction

Apparatuses and methods for reducing a number of command shifters are disclosed. An example apparatus includes an encoder circuit, a latency shifter circuit, and a decoder circuit. ... Micron Technology Inc

10/27/16 / #20160314039

Advanced bitwise operations and apparatus in a multi-level system with nonvolatile memory

A digital system, components and method are configured with nonvolatile memory for storing digital data using codewords. The data is stored in the memory using multiple bits per memory cell of the memory. ... Micron Technology Inc

10/20/16 / #20160308126

Methods of forming structures

Some embodiments include methods of forming structures. Spaced-apart features are formed which contain temperature-sensitive material. ... Micron Technology Inc

10/20/16 / #20160308123

Methods of forming a magnetic electrode of a magnetic tunnel junction and methods of forming a magnetic tunnel junction

A method of forming a magnetic electrode of a magnetic tunnel junction comprises forming non-magnetic mgo-comprising material over conductive material of the magnetic electrode being formed. An amorphous metal is formed over the mgo-comprising material. ... Micron Technology Inc

10/20/16 / #20160308122

Magnetic tunnel junctions

A method of forming a magnetic electrode of a magnetic tunnel junction comprises forming non-magnetic mgo-comprising material over conductive material of the magnetic electrode being formed. An amorphous metal is formed over the mgo-comprising material. ... Micron Technology Inc

10/20/16 / #20160308118

Methods of forming memory cells, arrays of magnetic memory cells, and semiconductor devices

Magnetic memory cells, methods of fabrication, semiconductor device structures, and memory systems are disclosed. A magnetic cell core includes at least one magnetic region (e.g., a free region or a fixed region) configured to exhibit a vertical magnetic orientation, at least one oxide-based region, which may be a tunnel junction region or an oxide capping region, and at least one magnetic interface region, which may comprise or consist of iron (fe). ... Micron Technology Inc

10/20/16 / #20160308117

Magnetic memory cell structures, arrays, and semiconductor devices

Methods of forming memory cells, magnetic memory cell structures, and arrays of magnetic memory cell structures are disclosed. Embodiments of the methods include patterning a precursor structure to form a stepped structure including at least an upper discrete feature section and a lower feature section with a broader width, length, or both than the upper discrete feature section. ... Micron Technology Inc

10/20/16 / #20160308018

Gate stacks

Some embodiments disclose a gate stack having a gate (e.g., polysilicon (poly) material) horizontally between shallow trench isolations (stis), a tungsten silicide (wsix) material over the gate and the stis, and a tungsten silicon nitride (wsin) material on a top surface of the wsix material. Some embodiments disclose a gate stack having a gate between stis, a first wsix material over the gate and the stis, a wsin interlayer material on a top surface of the first wsix material, and a second wsix material on a top surface of the wsin interlayer material. ... Micron Technology Inc

10/20/16 / #20160307965

Resistive memory cell structures and methods

Resistive memory cell structures and methods are described herein. One or more memory cell structures comprise a first resistive memory cell comprising a first resistance variable material and a second resistive memory cell comprising a second resistance variable material that is different than the first resistance variable material.. ... Micron Technology Inc

10/20/16 / #20160307963

Array of memory cells, methods associated with forming memory cells that comprise programmable material, and methods associated with forming memory cells that comprise selector device material

In one embodiment, a method associated with forming a memory cell that comprises programmable material comprises forming a stack comprising sacrificial material over lower conductive material. The sacrificial material is first patterned in a first direction to form a sacrificial line. ... Micron Technology Inc

10/20/16 / #20160307839

Semiconductor device structures

A method of forming a semiconductor structure comprises forming pools of acidic or basic material in a substrate structure. A resist is formed over the pools of acidic or basic material and the substrate structure. ... Micron Technology Inc

10/20/16 / #20160307647

Repair of memory devices using volatile and non-volatile memory

Apparatus and methods for hybrid post package repair are disclosed. One such apparatus may include a package including memory cells and volatile memory. ... Micron Technology Inc

10/20/16 / #20160307626

Apparatuses, memories, and methods for address decoding and selecting an access line

Apparatuses, memories, and methods for decoding memory addresses for selecting access lines in a memory are disclosed. An example apparatus includes an address decoder circuit coupled to first and second select lines, a polarity line, and an access line. ... Micron Technology Inc

10/20/16 / #20160307622

Programming memories with multi-level pass signal

Methods of operating a memory include applying a multi-step pass voltage to a plurality of memory cells selected for a programming operation, applying a programming pulse to the plurality of memory cells selected for the programming operation after applying a voltage level of a particular step of the multi-step pass voltage to the plurality of memory cells selected for the programming operation, applying a particular voltage level to any data lines coupled to a first subset of memory cells of the plurality of memory cells selected for the programming operation prior to applying a voltage level of a certain step of the multi-step pass voltage, and applying the particular voltage level to any data lines coupled to a second subset of memory cells of the plurality of memory cells selected for the programming operation only after applying the voltage level of the certain step of the multi-step pass voltage.. . ... Micron Technology Inc

10/20/16 / #20160306740

Memory tile access and selection patterns

In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes multiple memory tiles and selection circuitry. ... Micron Technology Inc

10/20/16 / #20160306614

Target architecture determination

Examples of the present disclosure provide apparatuses and methods for target architecture determination. An example method comprises receiving an indication of a type of target architecture in a portion of source code and creating compiled code for the type of target architecture based on the indication.. ... Micron Technology Inc

10/20/16 / #20160306609

Division operations for memory

Examples of the present disclosure provide apparatuses and methods for performing division operations in a memory. An example apparatus comprises a first address space comprising a first number of memory cells coupled to a sense line and to a first number of select lines wherein the first address space stores a dividend value. ... Micron Technology Inc

10/20/16 / #20160306584

Apparatuses and methods to reverse data stored in memory

Apparatuses and methods are provided for reversing data stored in memory. An example apparatus comprises an array of memory cells, a first plurality of sensing components corresponding to a respective first plurality of columns of the array, a second plurality of sensing components corresponding to a respective second plurality of columns of the array, and a plurality of shared input/output (i/o) lines (which may be referred to as sio lines). ... Micron Technology Inc

10/13/16 / #20160301001

Magnetic tunnel junctions, methods used while forming magnetic tunnel junctions, and methods of forming magnetic tunnel junctions

A method used while forming a magnetic tunnel junction comprises forming non-magnetic tunnel insulator material over magnetic electrode material. The tunnel insulator material comprises mgo and the magnetic electrode material comprises co and fe. ... Micron Technology Inc

10/13/16 / #20160300850

Three dimensional memory and methods of forming the same

Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the memory cells of the first group being formed in a cavity of a first control gate located in one device level of the memory device. ... Micron Technology Inc

10/13/16 / #20160300842

Methods of forming contacts for a semiconductor device structure, related methods of forming a semiconductor structure, and related semiconductor structures

A method of forming contacts for a semiconductor device structure comprises forming contact holes extending into neighboring semiconductive pillars and into a nitride material of nitride-capped electrodes. Composite structures are formed within the contact holes and comprise oxide structures over sidewalls of the contact holes and nitride structures over the oxide structures. ... Micron Technology Inc

10/13/16 / #20160300610

Resistance variable element methods and apparatuses

Apparatus and methods are disclosed, including a method that performs a first operation on a first resistance variable element using a common source voltage, a first data line voltage and a first control gate voltage, and then performs a second operation on a second resistance variable element using the common source voltage, a second data line voltage and a second control gate voltage. Additional apparatus and methods are described.. ... Micron Technology Inc

10/06/16 / #20160293842

Forming self-aligned conductive lines for resistive random access memories

Resistive random access memory elements, such as phase change memory elements, may be defined using a plurality of parallel conductive lines over a stack of layers, at least one of which includes a resistive switching material. The stack may be etched using the conductive lines as a mask. ... Micron Technology Inc

10/06/16 / #20160293623

Integrated structures and methods of forming vertically-stacked memory cells

Some embodiments include a method of forming vertically-stacked memory cells. An opening is formed through a stack of alternating insulative and conductive levels. ... Micron Technology Inc

10/06/16 / #20160293519

Semiconductor device having through-silicon-via and methods of forming the same

Semiconductor devices having a through-silicon-via and methods of forming the same are described herein. As an example, a semiconductor device may include a substrate material, a through-silicon-via protrusion extending from the substrate material, a first dielectric material formed on the substrate material, a second dielectric material formed on the first dielectric material, and an interconnect formed on the through-silicon-via protrusion, where the interconnect formed is in an opening in the second dielectric material.. ... Micron Technology Inc

10/06/16 / #20160293482

Semiconductor constructions and methods of forming intersecting lines of material

Some embodiments include semiconductor constructions having first and second electrically conductive lines that intersect with one another at an intersection. The first line has primarily a first width, and has narrowed regions directly against the second line and on opposing sides of the second line from one another. ... Micron Technology Inc

10/06/16 / #20160293433

Methods of fabricating features associated with semiconductor substrates

Some embodiments include a method of fabricating features associated with a semiconductor substrate. A first region of the semiconductor substrate is altered relative to a second region. ... Micron Technology Inc

10/06/16 / #20160293406

Methods of forming nanostructures using self-assembled nucleic acids, and nanostructures thereof

A method of forming a nanostructure comprises forming a directed self-assembly of nucleic acid structures on a patterned substrate. The patterned substrate comprises multiple regions. ... Micron Technology Inc

10/06/16 / #20160293254

Apparatuses and methods including memory access in cross point memory

Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch configured to apply a signal to one of the first and second conductive lines. In at least one of such embodiments, the switch can include a phase change material. ... Micron Technology Inc

10/06/16 / #20160293242

Systems, methods, and apparatuses for performing refresh operations

Methods, apparatuses, and systems for performing refresh operations on a memory cell array that does not have an nth-power-of-2 number of memory mats are disclosed. An address counter configured to skip the refresh addresses not assigned to a memory mat is disclosed. ... Micron Technology Inc

10/06/16 / #20160292080

Virtual register file

The present disclosure is related to a virtual register file. Source code can be compiled to include references to a virtual register file for data subject to a logical operation. ... Micron Technology Inc

09/29/16 / #20160285584

High-speed wireless serial communication link for a stacked device configuration using near field coupling

In various embodiments, a memory module houses memory devices and, in some embodiments, a memory controller. Each of the devices has a near-field interface coupled to loop antennas to communicate over-the-air data. ... Micron Technology Inc

09/29/16 / #20160284996

Memory cells and methods of forming memory cells

Some embodiments include a memory cell having a first electrode, and an intermediate material over and directly against the first electrode. The intermediate material includes stabilizing species corresponding to one or both of carbon and boron. ... Micron Technology Inc

09/29/16 / #20160284728

Apparatuses and methods for forming multiple decks of memory cells

Some embodiments include apparatuses and methods having multiple decks of memory cells and associated control gates. A method includes forming a first deck having alternating conductor materials and dielectric materials and a hole containing materials extending through the conductor materials and the dielectric materials. ... Micron Technology Inc

09/29/16 / #20160284719

Integrated structures and methods of forming vertically-stacked memory cells

Some embodiments include a method of forming vertically-stacked memory cells. An opening is formed through a stack of alternating insulative and conductive levels. ... Micron Technology Inc

09/29/16 / #20160284675

Semiconductor die assembly

A semiconductor die assembly having a solderball wirebonded to a substrate. As an example, the semiconductor die assembly may include the solderball attached to a bond pad on a face surface of a memory die. ... Micron Technology Inc

09/29/16 / #20160284626

Semiconductor devices having conductive vias and methods of forming the same

Semiconductor devices having a conductive via and methods of forming the same are described herein. As an example, a semiconductor devices may include a conductive via formed in a substrate material, a barrier material, a first dielectric material on the barrier material, a coupling material formed on the substrate material and on at least a portion of the dielectric material, a second dielectric material formed on the coupling material, and an interconnect formed on the conductive via.. ... Micron Technology Inc

09/29/16 / #20160283122

Advanced memory interfaces and methods

Controllers, interfaces, memory devices, methods and systems are disclosed, including a controller configured to interface with a separate memory device and perform an iterative write operation to program a selected memory cell of the memory device to a target state, wherein each iteration of the write operation is configured to successively change a physical state of the selected memory cell. Other controllers, interfaces, memory device, methods and systems are also described, such as those where either a controller or a memory device can throttle a data communication operation, and/or those that utilize customized programming pulses.. ... Micron Technology Inc

09/22/16 / #20160277015

Two-stage phase mixer circuit

Apparatuses and methods are directed to preventing duty cycle distortion in an electronic apparatus. The apparatus generally includes a first phase mixer stage configured to interpolate a first and a second input signal to provide a first intermediate signal and further configured to interpolate the second input signal and a third input signal to provide a second intermediate signal, the first phase mixer stage distorting duty cycle in providing the first intermediate signal. ... Micron Technology Inc

09/22/16 / #20160276587

Memory cell structures

The present disclosure includes memory cell structures and method of forming the same. One such memory cell includes a first electrode having sidewalls angled less than 90 degrees in relation to a bottom surface of the first electrode, a second electrode, including an electrode contact portion of the second electrode, having sidewalls angled less than 90 degrees in relation to the bottom surface of the first electrode, wherein the second electrode is over the first electrode, and a storage element between the first electrode and the electrode contact portion of the second electrode.. ... Micron Technology Inc

09/22/16 / #20160276454

Semiconductor devices and structures and methods of formation

A semiconductor device structure is disclosed. The semiconductor device structure includes a mesa extending above a substrate. ... Micron Technology Inc

09/22/16 / #20160276409

Apparatuses and operation methods associated with resistive memory cell arrays with separate select lines

The present disclosure includes methods and apparatuses that include resistive memory. A number of embodiments include a first memory cell coupled to a data line and including a first resistive storage element and a first access device, a second memory cell coupled to the data line and including a second resistive storage element and a second access device, an isolation device formed between the first access device and the second access device, a first select line coupled to the first resistive storage element, and a second select line coupled to the second resistive storage element, wherein the second select line is separate from the first select line.. ... Micron Technology Inc

09/22/16 / #20160276405

Semiconductor devices comprising magnetic memory cells

Memory cells are disclosed. Magnetic regions within the memory cells include an alternating structure of magnetic sub-regions and coupler sub-regions. ... Micron Technology Inc

09/22/16 / #20160276028

Memory devices and related method incorporating different biasing schemes

Memory devices comprise a plurality of memory cells, each memory cell including a memory element and a selection device. A plurality of first (e.g., row) address lines can be adjacent (e.g., under) a first side of at least some cells of the plurality. ... Micron Technology Inc

09/22/16 / #20160276022

Constructions comprising stacked memory arrays

Some embodiments include a construction having a first memory array deck and a second memory array deck over the first memory array deck. The second memory array deck differs from the first memory array deck in one or more operating characteristics, in pitch, and/or in one or more structural parameters; with the structural parameters including different materials and/or different thicknesses of materials. ... Micron Technology Inc

09/22/16 / #20160276021

Apparatuses and methods for bi-directional access of cross-point arrays

The disclosed technology generally relates to apparatuses and methods of operating the same, and more particularly to cross point memory arrays and methods of accessing memory cells in a cross point memory array. In one aspect, an apparatus comprises a memory array. ... Micron Technology Inc

09/22/16 / #20160276017

Memory refresh methods, memory section control circuits, and apparatuses

Apparatuses, memory section control circuits, and methods of refreshing memory are disclosed. An example apparatus includes a plurality of memory sections and a plurality of memory section control circuits. ... Micron Technology Inc

09/22/16 / #20160274812

Power consumption control

The present disclosure includes apparatuses and methods for power consumption control. A number of embodiments include determining power consumption information for each phase in a combination of phases of a command, and authorizing execution of at least one of the phases in the combination based, at least partially, on the power consumption information determined for the at least one of the phases.. ... Micron Technology Inc

09/22/16 / #20160274614

Voltage regulator with current feedback

Generally discussed herein are apparatuses and methods for a voltage regulator with a current feedback loop. One such apparatus may include an amplifier, a master device electrically coupled to the amplifier, a slave device electrically coupled to the master device, and/or a current feedback device electrically coupled to the amplifier and the slave device to feed back current from the slave device to alter a monitoring voltage input to the amplifier.. ... Micron Technology Inc

09/15/16 / #20160269147

Bitwise operations and apparatus in a multi-level system

A system uses multi-level encoding where each symbol of a plurality of symbols represents more than one bit of information in a user data symbol stream for transfer using a multilevel transmission channel. The user data symbols are represented in a digital bitwise form such that each symbol is presented as a plurality of bits and each bit is subject to a different probability of error. ... Micron Technology Inc

09/15/16 / #20160269012

Synchronized semiconductor device with phase adjustment circuit

According to one embodiment, a synchronous semiconductor device is disclosed according to this embodiment, the synchronous semiconductor device includes a pulse width detection circuit to determine whether at least one of a plurality of delay step sizes is less than at least one of a high pulse width and a low pulse width of a first clock signal and to select one of the delay step sizes and a delay line to delay the first clock signal to produce as second clock signal by a first delay amount that is changed based at least on the one of the delay step sizes.. . ... Micron Technology Inc

09/15/16 / #20160268897

Analog assisted digital switch regulator

A device includes a digital switch regulator to supply an output voltage and a first current to a load based on a reference voltage. The device also includes an analog circuit to supply a second current to the load in addition to the first current based on a duty cycle of the digital switch regulator.. ... Micron Technology Inc

09/15/16 / #20160268428

Electronic device with asymmetric gate strain

The use of strained gate electrodes in integrated circuits results in a transistor having improved carrier mobility, improved drive characteristics, and reduced source drain junction leakage. The gate electrode strain can be obtained through non symmetric placement of stress inducing structures as part of the gate electrode.. ... Micron Technology Inc

09/15/16 / #20160268337

Magnetic memory cells, semiconductor devices, and methods of formation

A magnetic cell includes magnetic, secondary oxide, and getter seed regions. During formation, a diffusive species is transferred from a precursor magnetic material to the getter seed region, due to a chemical affinity elicited by a getter species. ... Micron Technology Inc

09/15/16 / #20160268280

Data line arrangement and pillar arrangement in apparatuses

Some embodiments include an apparatus having semiconductor pillars in a modified hexagonal packing arrangement. The modified hexagonal packing arrangement includes a repeating pattern having at least portions of 7 different pillars. ... Micron Technology Inc

09/15/16 / #20160268235

Interconnect structure with redundant electrical connectors and associated systems and methods

Semiconductor die assemblies having interconnect structures with redundant electrical connectors are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die, a second semiconductor die, and an interconnect structure between the first and the second semiconductor dies. ... Micron Technology Inc

09/15/16 / #20160267998

Memory read apparatus and methods

Apparatus and methods are disclosed, including a method that raises an electrical potential of a plurality of access lines to a raised electrical potential, where each access line is associated with a respective charge storage device of a string of charge storage devices. The electrical potential of a selected one of the access lines is lowered, and a data state of the charge storage device associated with the selected access line is sensed while the electrical potential of the selected access line is being lowered. ... Micron Technology Inc

09/15/16 / #20160267993

Apparatus and methods of operating memory for exact and inexact searching of feature vectors

Apparatus and methods of operating a memory include storing a value of an attribute of a feature vector to a pair of memory cells by programming each of the memory cells to a respective data state of three or more data states, searching for an exact match to a particular value of the attribute by applying respective voltage levels to control gates of the memory cells to activate both memory cells only when the value of the attribute is the particular value, and searching for an inexact match to the particular value of the attribute by applying respective voltage levels to control gates of the memory cells to activate both memory cells when the value of the attribute is within a range of possible values of the attribute including the particular value.. . ... Micron Technology Inc

09/15/16 / #20160267984

Devices including memory arrays, row decoder circuitries and column decoder circuitries

Some embodiments include a device having an array of memory cells, a memory control unit at least partially under the array, row decoder circuitry in data communication with the memory control unit, and column decoder circuitry in data communication with the memory control unit. Some embodiments include a device having an array of memory cells, row decoder circuitry and column decoder circuitry. ... Micron Technology Inc

09/15/16 / #20160267978

Memory devices and memory operational methods

Memory devices and memory operational methods are described. One example memory system includes a common conductor and a plurality of memory cells coupled with the common conductor. ... Micron Technology Inc

09/15/16 / #20160267962

Semiconductor device

A semiconductor device includes a plurality of memory cells, an access circuit configured to perform a data read operation, a data write operation and a data refresh operation on the memory cells, the access circuit to operate in a selected one of a first mode that is ready to perform and a second mode that is not ready to perform, and a judgment circuit configured to respond to first command information, to cause, when the access circuit is in the first mode, the access circuit to perform the data refresh operation, and to cause, when the access circuit is in the second mode, the access circuit to exit from the second mode and then to perform the refresh operation.. . ... Micron Technology Inc

09/15/16 / #20160267953

Single node power management for multiple memory devices

Some embodiments include apparatuses and methods having a node to couple to a plurality of memory devices, memory cells, and a module to perform an operation on the memory cells, to cause at least one change in a level of a signal at the node in order to make a request to perform a particular stage of the operation such that the request is detectable by the memory devices, and to perform the particular stage of the operation after the request is acknowledged. Other embodiments are described.. ... Micron Technology Inc

09/15/16 / #20160267951

Data shift by elements of a vector in memory

Examples of the present disclosure provide apparatuses and methods for performing shift operations in a memory. An example method comprises performing a shift operation a first element stored in a first group of memory cells coupled to a first access line and a number of sense lines of a memory array and a second element stored in a second group of memory cells coupled to a second access line and the number of sense lines of the memory array. ... Micron Technology Inc

09/15/16 / #20160267948

Interconnections for 3d memory

Apparatuses and methods for interconnections for 3d memory are provided. One example apparatus can include a stack of materials including a plurality of pairs of materials, each pair of materials including a conductive line formed over an insulation material. ... Micron Technology Inc

09/15/16 / #20160266966

High performance memory controller

A memory device includes a memory array that includes a buffer data. The memory device also includes a memory controller. ... Micron Technology Inc

09/15/16 / #20160266899

Vector population count determination in memory

Examples of the present disclosure provide apparatuses and methods for determining a vector population count in a memory. An example method comprises determining, using sensing circuitry, a vector population count of a number of fixed length elements of a vector stored in a memory array.. ... Micron Technology Inc

09/15/16 / #20160266873

Division operations on variable length elements in memory

Examples of the present disclosure provide apparatuses and methods for performing variable bit-length division operations in a memory. An example method comprises performing a variable length division operation on a first vector comprising variable length elements representing a number of dividends and stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array and a second vector comprising variable length elements representing a number of divisors stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array. ... Micron Technology Inc

09/08/16 / #20160260899

Methods of forming a non-volatile resistive oxide memory cell and methods of forming a non-volatile resistive oxide memory array

A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. Metal oxide-comprising material is formed over the first conductive electrode. ... Micron Technology Inc

09/08/16 / #20160260897

Forming resistive random access memories together with fuse arrays

A resistive random access memory array may be formed on the same substrate with a fuse array. The random access memory and the fuse array may use the same active material. ... Micron Technology Inc

09/08/16 / #20160260778

Connections for memory electrode lines

Subject matter disclosed herein relates to an integrated circuit device having a socket interconnect region for connecting a plurality of conductive lines at a first vertical level to interconnect structures formed at a second vertical level different from the first vertical level. The conductive lines include a plurality of contacted lines that are vertically connected to the interconnect structures at the socket interconnect region, a plurality of terminating lines terminating at the socket interconnect region, and a plurality of pass-through lines that pass through the socket interconnect region without being vertically connected and without being terminated at the socket interconnect region.. ... Micron Technology Inc

09/08/16 / #20160260777

Array of cross point memory cells and methods of forming an array of cross point memory cells

An array of cross point memory cells comprises spaced elevationally inner first lines, spaced elevationally outer second lines which cross the first lines, and a multi-resistive state region elevationally between the first and second lines where such cross. Individual of the multi-resistive state regions comprise elevationally outer multi-resistive state material and elevationally inner multi-resistive state material that are electrically coupled to one another. ... Micron Technology Inc

09/08/16 / #20160260776

Replacement materials processes for forming cross point memory

Methods of forming memory cells comprising phase change and/or chalcogenide materials are disclosed. In one aspect, the method includes providing a lower line stack extending in a first direction, the lower line stack comprising a sacrificial line over a lower conductive line. ... Micron Technology Inc

09/08/16 / #20160260723

Integrated circuitry components, switches, and memory cells

A switch includes a graphene structure extending longitudinally between a pair of electrodes and being conductively connected to both electrodes of said pair. First and second electrically conductive structures are laterally outward of the graphene structure and on opposing sides of the graphene structure from one another. ... Micron Technology Inc

09/08/16 / #20160260664

Semiconductor structures including rails of dielectric material

Methods of forming semiconductor structures that include bodies of a semiconductor material disposed between rails of a dielectric material are disclosed. Such methods may include filling a plurality of trenches in a substrate with a dielectric material and removing portions of the substrate between the dielectric material to form a plurality of openings. ... Micron Technology Inc

09/08/16 / #20160260503

Switched interface stacked-die memory architecture

Systems and methods disclosed herein include those that may receive a memory request including a requested memory address and may send the memory request directly to an address decoder associated with a stacked-die memory vault without knowing whether a repair address is required. If a subsequent analysis of the memory request shows that a repair address is required, an in-process decode of the requested memory address can be halted and decoding of the repair address initiated.. ... Micron Technology Inc

09/08/16 / #20160260498

Semiconductor device and control method of the same

A semiconductor device comprises a bit determination circuit to count the number of bits at a first level in an input address signal formed of a plurality of bits and to output a result indicating whether or not a value of the count exceeds a predetermined determination threshold value, as a bit determination result signal, and a selection control circuit to select a non-volatile program element to be cut off, based on the bit determination result signal and the address signal. Additional apparatus and methods are described.. ... Micron Technology Inc

09/08/16 / #20160260468

Apparatuses and methods for setting a signal in variable resistance memory

An example of a method reads a spin torque transfer (stt) memory cell, and writes the stt memory cell using information obtained during the reading of the stt memory cell to set a pulse to write the stt memory cell. An example of an apparatus includes a stt memory cell and read/write circuitry coupled to the stt memory cell to determine a read current (iread) through the stt memory cell and to set a pulse to write the stt memory cell using iread. ... Micron Technology Inc

09/08/16 / #20160259721

Systems and methods for memory system management based on thermal information of a memory system

Methods of mapping memory regions to processes based on thermal data of memory regions are described. In some embodiments, a memory controller may receive a memory allocation request. ... Micron Technology Inc

09/08/16 / #20160259686

Updating reliability data

The present disclosure includes apparatuses and methods related to updating reliability data. A number of methods can include receiving, at a variable node, either a first reliability data value with a first hard data value or a second reliability data value with a second hard data value, sending the first hard data value or the second hard data value to each check node coupled to the variable node according to a parity check code, and updating the reliability data based on input from less than all of the check nodes.. ... Micron Technology Inc

09/08/16 / #20160259385

Impedance adjustment

Integrated circuit devices and methods of operating integrated circuit devices are useful in impedance adjustment. Integrated circuit devices include a signal driver circuit having an output node, a voltage node, and a first termination device and a second termination device connected in parallel between the voltage node and the output node. ... Micron Technology Inc

09/08/16 / #20160258997

Testing impedance adjustment

Methods of operating integrated circuit devices are useful in testing impedance adjustment. Methods include connecting a node of the integrated circuit device to a first voltage node through a reference resistance and connecting the node to a second voltage node through a termination device, and comparing a voltage level at the node to a reference voltage for at least one resistance value of the termination device. ... Micron Technology Inc

09/01/16 / #20160254447

Methods of forming and using materials containing silicon and nitrogen

Some embodiments include methods utilizing atomic layer deposition to form material containing silicon and nitrogen (e.g., silicon nitride). The atomic layer deposition uses sil4 as one precursor and uses a nitrogen-containing material as another precursor. ... Micron Technology Inc

09/01/16 / #20160254412

Textured optoelectronic devices and associated methods of manufacture

Textured optoelectronic devices and associated methods of manufacture are disclosed herein. In several embodiments, a method of manufacturing a solid state optoelectronic device can include forming a conductive transparent texturing material on a substrate. ... Micron Technology Inc

09/01/16 / #20160254270

Methods of forming memory devices with isolation structures

A first conductive region having a second conductivity type is formed in a first semiconductor over a first dielectric isolation region and having a first conductivity type. A second semiconductor having the first conductivity type is formed over the first conductive region and the first semiconductor. ... Micron Technology Inc

09/01/16 / #20160254265

Three-dimensional devices having reduced contact length

Various embodiments comprise apparatuses and methods including a memory array having alternating levels of semiconductor materials and dielectric material with strings of memory cells formed on the alternating levels. One such apparatus includes a memory array formed substantially within a cavity of a substrate. ... Micron Technology Inc

09/01/16 / #20160254263

Methods and apparatuses including an active area of a tap intersected by a boundary of a well

Apparatuses and methods are disclosed. One such apparatus includes a well having a first type of conductivity formed within a semiconductor structure having a second type of conductivity. ... Micron Technology Inc

09/01/16 / #20160254204

Packaged semiconductor components having substantially rigid support members and methods of packaging semiconductor components

Packaged semiconductor components having substantially rigid support member are disclosed. The packages can include a semiconductor die and a support member proximate to the semiconductor die. ... Micron Technology Inc

09/01/16 / #20160254187

Disposable pillars for contact information

Sacrificial plugs for forming contacts in integrated circuits, as well as methods of forming connections in integrated circuit arrays are disclosed. Various pattern transfer and etching steps can be used to create densely-packed features and the connections between features. ... Micron Technology Inc

09/01/16 / #20160254159

Methods of forming memory cells with air gaps and other low dielectric constant materials

Various embodiments include apparatuses and methods of forming the same. One such apparatus can include a first dielectric material and a second dielectric material, and a conductive material between the first dielectric material and the second dielectric material. ... Micron Technology Inc

09/01/16 / #20160254051

Memory systems and memory programming methods

Memory systems and memory programming methods are described. In one arrangement, a memory system includes a memory cell configured to have a plurality of different memory states, an access circuit coupled with the memory cell and configured to provide a first signal to a memory element of the memory cell to program the memory cell from a first memory state to a second memory state, and a current source coupled with the memory cell and configured to generate a second signal which is provided to the memory element of the memory cell after the first signal to complete programming of the memory cell from the first memory state to the second memory state.. ... Micron Technology Inc

09/01/16 / #20160254050

Enhancing nucleation in phase-change memory cells

Various embodiments disclosed herein comprise methods and apparatuses for placing phase-change memory (pcm) cells of a memory array into a temperature regime where nucleation probability of the pcm cells is enhanced prior to applying a subsequent set programming signal. In one embodiment, the method includes applying a nucleation signal to the pcm cells to form nucleation sites within the memory array where the nucleation signal has a non-zero rising-edge. ... Micron Technology Inc

09/01/16 / #20160254049

Apparatuses, sense circuits, and methods for compensating for a wordline voltage increase

Apparatuses, sense circuits, and methods for compensating for a voltage increase on a wordline in a memory is described. An example apparatus includes a bitline, a memory cell coupled to the bitline, a bipolar selector device coupled to the memory cell, a wordline coupled to the bipolar selector device, and a wordline driver coupled to the wordline. ... Micron Technology Inc

09/01/16 / #20160253237

Apparatuses and methods including error correction code organization

Some embodiments include apparatuses and methods having first memory cells, a first access line configured to access the first memory cells, second memory cells, and a second access line configured to access the second memory cells. One of such apparatuses can include a controller configured to cause data to be stored in a memory portion of the first memory cells, to cause a first portion of an error correction code associated with the data to be stored in another memory portion of the first memory cells, and to cause a second portion of the error correction code to be stored in the second memory cells. ... Micron Technology Inc

09/01/16 / #20160252920

Apparatuses and methods for temperature independent current generations

Apparatuses and methods for providing a current independent of temperature are described. An example apparatus includes a current generator that includes two components that are configured to respond equally and opposite to changes in temperature. ... Micron Technology Inc

08/25/16 / #20160248424

Level shifters, memory systems, and level shifting methods

Level shifters, memory systems, and level shifting methods are described. According to one arrangement, a level shifter includes an input configured to receive an input signal in a first voltage domain, an output configured to output an output signal from the level shifter in a second voltage domain different than the first voltage domain, a plurality of pull-down devices, and wherein one of the pull-down devices is coupled with the input and the output, a plurality of cross-coupled devices coupled with the pull-down devices and configured to provide transitions in the output signal as a result of transitions in the input signal, a plurality of current limiting devices coupled with the cross-coupled devices and configured to limit a flow of current from a source to the cross-coupled devices, and a plurality of dynamic devices configured to selectively provide charging current from the source to the cross-coupled devices.. ... Micron Technology Inc

08/25/16 / #20160248010

Memory arrays and methods of forming memory arrays

Some embodiments include a memory array having a first series of access/sense lines which extend along a first direction, a second series of access/sense lines over the first series of access/sense lines and which extend along a second direction substantially orthogonal to the first direction, and memory cells vertically between the first and second series of access/sense lines. Each memory cell is uniquely addressed by a combination of an access/sense line from the first series and an access/sense line from the second series. ... Micron Technology Inc

08/25/16 / #20160247878

Isolation trench fill using oxide liner and nitride etch back technique with dual trench depth capability

An oxide layer is formed over a substrate having a smaller isolation trench and a large isolation trench. A nitride layer is formed over the oxide layer such that it completely fills the smaller isolation trench and lines the larger isolation trench. ... Micron Technology Inc

08/25/16 / #20160247749

Semiconductor dies with recesses, associated leadframes, and associated systems and methods

Semiconductor dies with recesses, associated leadframes, and associated systems and methods are disclosed. A semiconductor system in accordance with one embodiment includes a semiconductor die having a first surface and a second surface facing opposite from the first surface, with the first surface having a die recess. ... Micron Technology Inc

08/25/16 / #20160247747

Disabling electrical connections using pass-through 3d interconnects and associated systems and methods

Pass-through 3d interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a backside, an interconnect extending through the first die to the backside, an integrated circuit electrically coupled to the interconnect, and a first electrostatic discharge (esd) device electrically isolated from the interconnect. ... Micron Technology Inc

08/25/16 / #20160247742

Apparatuses and methods for semiconductor die heat dissipation

Apparatuses and methods for semiconductor die heat dissipation are described. For example, an apparatus for semiconductor die heat dissipation may include a substrate and a heat spreader. ... Micron Technology Inc

08/25/16 / #20160247737

Novel build-up package for integrated circuit devices, and methods of making same

A device is disclosed which includes, in one illustrative example, an integrated circuit die having an active surface and a molded body extending around a perimeter of the die, the molded body having lips that are positioned above a portion of the active surface of the die. Another illustrative example includes an integrated circuit die having an active surface, a molded body extending around a perimeter of the die and a cte buffer material formed around at least a portion of the perimeter of the die adjacent the active surface of the die, wherein the cte buffer material is positioned between a portion of the die and a portion of the molded body and wherein the cte buffer material has a coefficient of thermal expansion that is intermediate a coefficient of thermal expansion for the die and a coefficient of thermal expansion for the molded body.. ... Micron Technology Inc

08/25/16 / #20160247562

Apparatuses and methods of reading memory cells

A method is provided for a reading memory even if there is a threshold voltage in an overlapped threshold voltage (vth) region between a first state distribution and a second state distribution. The method includes ramping a bias on a memory cell a first time to determine a first threshold voltage (vth1) of the memory cell and determining whether the vth1 is within the overlapped vth region. ... Micron Technology Inc

08/18/16 / #20160240587

Horizontally oriented and vertically stacked memory cells

Horizontally oriented and vertically stacked memory cells are described herein. One or more method embodiments include forming a vertical stack having a first insulator material, a first memory cell material on the first insulator material, a second insulator material on the first memory cell material, a second memory cell material on the second insulator material, and a third insulator material on the second memory cell material, forming an electrode adjacent a first side of the first memory cell material and a first side of the second memory cell material, and forming an electrode adjacent a second side of the first memory cell material and a second side of the second memory cell material.. ... Micron Technology Inc

08/18/16 / #20160240545

Memory cells

A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor electrodes having ferroelectric material there-between. ... Micron Technology Inc

08/18/16 / #20160240515

Signal delivery in stacked device

Some embodiments include apparatus, systems, and methods having a base, a first die, a second arranged in a stacked with the first die and the base, and a structure located in the stack and outside at least one of the first and second dice and configured to transfer signals between the base and at least one of the first and second dice.. . ... Micron Technology Inc

08/18/16 / #20160240248

Accessing memory cells in parallel in a cross-point array

Methods and structures for accessing memory cells in parallel in a cross-point array include accessing in parallel a first memory cell disposed between a first selected column and a first selected row and a second memory cell disposed between a second selected column different from the first selected column and a second selected row different from the first selected row. Accessing in parallel includes simultaneously applying access biases between the first selected column and the first selected row and between the second selected column and the second selected row. ... Micron Technology Inc

08/18/16 / #20160240230

Signal driver circuit having adjustable output voltage for a high logic level output signal

A signal driver circuit having an adjustable output voltage for a high-logic level output signal. The signal driver circuit includes a signal driver configured to output a first logic level signal having a first voltage and output a second logic level signal having a second voltage according to an input signal. ... Micron Technology Inc

08/18/16 / #20160240227

Semiconductor device package with mirror mode

Semiconductor device assemblies with semiconductor device packages configured to operate in mirror mode are disclosed herein. In one embodiment a semiconductor device assembly includes a first semiconductor device package attached to a front side of a support substrate, and a second semiconductor device package attached to a back side of the support substrate. ... Micron Technology Inc

08/18/16 / #20160239462

Multi-level hierarchical routing matrices for pattern-recognition processors

Multi-level hierarchical routing matrices for pattern-recognition processors are provided. One such routing matrix may include one or more programmable and/or non-programmable connections in and between levels of the matrix. ... Micron Technology Inc

08/18/16 / #20160239440

Methods and systems for routing in a state machine

A device includes a routing buffer. The routing buffer includes a first port configured to receive a signal relating to an analysis of at least a portion of a data stream. ... Micron Technology Inc

08/18/16 / #20160239367

Apparatuses and methods for comparing a current representative of a number of failing memory cells

Apparatuses and methods for comparing a sense current representative of a number of failing memory cells of a group of memory cells and a reference current representative of a reference number of failing memory cells is provided. One such apparatus includes a comparator configured to receive the sense current and to receive the reference current. ... Micron Technology Inc

08/11/16 / #20160233419

Semiconductor device structures including silicon-containing dielectric materials

A method of forming a silicon-containing dielectric material. The method includes forming a plasma comprising nitrogen radicals, absorbing the nitrogen radicals onto a substrate, and exposing the substrate to a silicon-containing precursor in a non-plasma environment to form monolayers of a silicon-containing dielectric material on the substrate. ... Micron Technology Inc

08/11/16 / #20160233297

Semiconductor device having shallow trench isolation structure

A semiconductor device is provided, which prevents a case where the widths of word lines become uneven because of a stress developing at the border between a memory cell area and a peripheral circuit area. The semiconductor device 1 has a semiconductor substrate 2 on which a memory cell area mc defined by a peripheral isolation region 3c. ... Micron Technology Inc

08/11/16 / #20160233225

Drain select gate formation methods and apparatus

Some embodiments include a string of charge storage devices formed along a vertical channel of semiconductor material; a gate region of a drain select gate (sgd) transistor, the gate region at least partially surrounding the vertical channel; a dielectric barrier formed in the gate region; a first isolation layer formed above the gate region and the dielectric barrier; a drain region of the sgd transistor formed above the vertical channel; and a second isolation layer formed above the first isolation layer and the drain region, wherein the second isolation layer includes a conductive contact in electrical contact with the drain region of the sgd transistor. Additional apparatus and methods are disclosed.. ... Micron Technology Inc

08/11/16 / #20160233160

Microelectronic devices with through-silicon vias and associated methods of manufacturing

Microelectronic devices with through-silicon vias and associated methods of manufacturing such devices. One embodiment of a method for forming tungsten through-silicon vias comprising forming an opening having a sidewall such that the opening extends through at least a portion of a substrate on which microelectronic structures have been formed. ... Micron Technology Inc

08/11/16 / #20160233139

Bonding pads with thermal pathways

Apparatuses and methods for providing thermal pathways from a substrate to a thermal bonding pad. The thermal pathways may be metal extensions of the thermal bonding pad that are disposed in channels formed in a backside passivation layer underneath the thermal bonding pad, and may be in direct contact with an underlying substrate. ... Micron Technology Inc

08/11/16 / #20160233136

Apparatus and methods for through substrate via test

A stack of vertically-connected, horizontally-oriented integrated circuits (ics) may have electrical connections from the front side of one ic to the back side of another ic. Electrical signals may be transferred from the back side of one ic to the front side of the same ic by means of through substrate vias (tsvs), which may include through silicon vias. ... Micron Technology Inc

08/11/16 / #20160233110

Semiconductor die assemblies with heat sink and associated systems and methods

Semiconductor die assemblies with heat sinks are disclosed herein. In one embodiment, a semiconductor die assembly includes a stack of semiconductor dies and a mold material surrounding at least a portion of the stack of semiconductor dies. ... Micron Technology Inc

08/11/16 / #20160232987

Soft post package repair of memory devices

Apparatus and methods for soft post package repair are disclosed. One such apparatus can include memory cells in a package, volatile memory configured to store defective address data responsive to entering a soft post-package repair mode, a match logic circuit and a decoder. ... Micron Technology Inc

08/11/16 / #20160232979

Partial page memory operations

Apparatuses may include a memory block with strings of memory cells formed in a plurality of tiers. The apparatus may further comprise access lines and data lines shared by the strings, with the access lines coupled to the memory cells corresponding to a respective tier of the plurality of tiers. ... Micron Technology Inc

08/11/16 / #20160232978

Memory as a programmable logic device

Methods for operating memory cells include applying a respective minterm, comprising a plurality of variables, to control gates of series strings of memory cells, each series string programmed as a plurality of pairs of complementary memory cells such that certain ones of the plurality of variables are enabled, and logically combining each of the minterms into a logic function output. Memories include a plurality of memory cells configured in series strings of memory cells, wherein each series string of memory cells is configured to provide a minterm comprising a plurality of variables, each variable enabled responsive to a state of an associated, respective memory cell.. ... Micron Technology Inc

08/11/16 / #20160232947

Methods and apparatuses including a string of memory cells having a first select transistor coupled to a second select transistor

Generally discussed herein are apparatuses and methods. One such apparatus includes a data line, a first memory cell and a first select transistor. ... Micron Technology Inc

08/11/16 / #20160231943

Flash memory architecture with separate storage of overhead and user data

A memory device has a plurality of dedicated data blocks for storing user data and a plurality of dedicated overhead blocks for storing overhead data. A dedicated overhead block of the plurality of dedicated overhead blocks has a plurality of overhead segments. ... Micron Technology Inc

08/11/16 / #20160231932

Host controlled enablement of automatic background operations in a memory device

A host that is coupled to a memory device is configured to read a status register of the memory device to determine if the memory device supports host controlled enablement of automatic background operations. The memory device responds to the host regarding whether the memory device supports host controlled enablement of automatic background operations. ... Micron Technology Inc

08/11/16 / #20160231930

Methods for operating a distributed controller system in a memory device

Methods for operating a distributed controller system in a memory device include receiving a read command, a master controller generating an indication to a data cache controller in response to the read command, and the data cache controller accepting data from a memory array of the memory device in response to the indication.. . ... Micron Technology Inc

08/11/16 / #20160231519

Apparatus providing simplified alignment of optical fiber in photonic integrated circuits

A structure for optically aligning an optical fiber to a photonic device and method of fabrication of same. The structure optically aligns an optical fiber to the photonic device using a lens between the two which is moveable by actuator heads. ... Micron Technology Inc

08/04/16 / #20160226495

Apparatuses and methods for low power counting circuits

Apparatuses and methods for low power counting circuits are described herein. An example apparatus may include a frequency divider configured to receive an input clock signal and adjust a frequency of the clock signal to provide an intermediate clock signal. ... Micron Technology Inc

08/04/16 / #20160225967

Vertical solid-state transducers and high voltage solid-state transducers having buried contacts and associated systems and methods

Solid-state transducers (“ssts”) and vertical high voltage ssts having buried contacts are disclosed herein. An sst die in accordance with a particular embodiment can include a transducer structure having a first semiconductor material at a first side of the transducer structure, and a second semiconductor material at a second side of the transducer structure. ... Micron Technology Inc

08/04/16 / #20160225948

Solid state lighting devices with reduced crystal lattice dislocations and associated methods of manufacturing

Solid state lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state lighting device includes a substrate material having a substrate surface and a plurality of hemispherical grained silicon (“hsg”) structures on the substrate surface of the substrate material. ... Micron Technology Inc

08/04/16 / #20160225860

Vertical ferroelectric field effect transistor constructions, constructions comprising a pair of vertical ferroelectric field effect transistors, vertical strings of ferroelectric field effect transistors, and vertical strings of laterally opposing pairs of vertical ferroelectric field effect transistors

A vertical ferroelectric field effect transistor construction comprises an isolating core. A transition metal dichalcogenide material encircles the isolating core and has a lateral wall thickness of 1 monolayer to 7 monolayers. ... Micron Technology Inc

08/04/16 / #20160225822

Stack of horizontally extending and vertically overlapping features, methods of forming circuitry components, and methods of forming an array of memory cells

A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The stack has a primary portion and an end portion. ... Micron Technology Inc

08/04/16 / #20160225782

Methods of adjusting flatband voltage of a memory device

Methods for adjusting a flatband voltage of a memory device, including applying a voltage to a control gate of the memory device such that charged species are moved to one of a plurality of different levels in a dielectric material in response to the voltage, wherein the plurality of different levels is greater than two.. . ... Micron Technology Inc

08/04/16 / #20160225734

Semiconductor devices and packages and methods of forming semiconductor device packages

Semiconductor device packages include first and second semiconductor dice in a facing relationship. At least one group of solder bumps is substantially along a centerline between the semiconductor dice and operably coupled with integrated circuitry of the first and second semiconductor dice. ... Micron Technology Inc

08/04/16 / #20160225731

Methods of forming conductive pillars for semiconductor devices, methods of forming electrical interconnects, and semiconductor devices

A method of forming a conductive material on a semiconductor device. The method comprises removing at least a portion of a conductive pad within an aperture in a dielectric material over a substrate. ... Micron Technology Inc

08/04/16 / #20160225723

Engineered carrier wafers

Apparatuses and methods for reducing the warp of semiconductor wafer stacks during manufacturing are disclosed. An engineered carrier wafer is disclosed. ... Micron Technology Inc

08/04/16 / #20160225695

Uniform back side exposure of through-silicon vias

Systems and methods for uniform back side exposure of through-silicon vias (tsvs) are disclosed. In one embodiment, a semiconductor device comprises a substrate having a front side with circuit elements formed thereon, and a back side opposite the front side. ... Micron Technology Inc

08/04/16 / #20160225459

Apparatuses operable in multiple power modes and methods of operating the same

The present disclosure is related to apparatuses operable in multiple power modes and methods of operating the same. An example embodiment includes an apparatus comprising a memory comprising an array of memory cells operable to store single-level cell (slc) data and multi-level cell (mlc) data. ... Micron Technology Inc

08/04/16 / #20160225444

Memory sense amplifiers and memory verification methods

Memory sense amplifiers and memory verification methods are described. According to one aspect, a memory sense amplifier includes a first input coupled with a memory element of a memory cell, wherein the memory element has different memory states at different moments in time, a second input configured to receive a reference signal, modification circuitry configured to provide a data signal at the first input from the memory element having a plurality of different voltages corresponding to respective ones of different memory states of the memory cell at the different moments in time, and comparison circuitry coupled with the modification circuitry and configured to compare the data signal and the reference signal at the different moments in time and to provide an output signal indicative of the memory state of the memory cell at the different moments in time as a result of the comparison to implement a plurality of verify operations of the memory states of the memory cell at the different moments in time.. ... Micron Technology Inc

08/04/16 / #20160225430

Dual event command

A technique to increase transfer rate of command and address signals via a given number of command and address pins in each of one or more integrated circuit memory devices during a clock cycle of a clock signal. In one example embodiment, the command and address signals are sent on both rising and falling edges of a clock cycle of a clock signal to increase the transfer rate and essentially reduce the number of required command and address pins in each integrated circuit memory device.. ... Micron Technology Inc

08/04/16 / #20160225422

Loop structure for operations in memory

Examples of the present disclosure provide apparatuses and methods related to performing a loop structure for operations performed in memory. An example apparatus might also include a controller configured to cause sensing circuitry to iterate through a plurality of first elements and a plurality of second elements via a loop structure to perform an operation using the plurality of first elements and the plurality of second elements, wherein a conditional statement associated with the loop structure is used to determine whether at least one of a plurality of bits stored as an iterator mask has a particular bit-value. ... Micron Technology Inc

08/04/16 / #20160225420

Memory timing self-calibration

Methods for memory input timing self-calibration, apparatuses for input timing self-calibration, and systems are disclosed. One such method includes sequentially programming a plurality of delay trim settings into a delay circuit of a data path. ... Micron Technology Inc

07/28/16 / #20160218740

Estimating an error rate associated with memory

The present disclosure includes apparatuses and methods for estimating an error rate associated with memory. A number of embodiments include sensing data stored in a memory, performing an error detection operation on the sensed data, determining a quantity of parity violations associated with the error detection operation, and estimating an error rate associated with the memory based on the determined quantity of parity violations.. ... Micron Technology Inc

07/28/16 / #20160218282

Phase change memory stack with treated sidewalls

Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming the memory stack out of a plurality of elements. ... Micron Technology Inc

07/28/16 / #20160218085

Semiconductor device packages with improved thermal management and related methods

Semiconductor device packages in accordance with this disclosure may include a substrate and a stack of semiconductor dice attached to the substrate. The stack of semiconductor dice may include vias extending through each semiconductor die of the stack for electrically interconnecting the semiconductor dice in the stack to one another and to the substrate. ... Micron Technology Inc

07/28/16 / #20160218032

Methods of forming a nanostructured polymer material including block copolymer materials

Methods for fabricating sub-lithographic, nanoscale microstructures utilizing self-assembling block copolymers, and films and devices formed from these methods are provided.. . ... Micron Technology Inc

07/28/16 / #20160217867

Inferring threshold voltage distributions associated with memory cells via interpolation

The present disclosure includes apparatuses and methods for inferring threshold voltage distributions associated with memory cells via interpolation. A number of embodiments include determining soft data for a group of memory cells each programmed to one of a number of data states, wherein the soft data comprises a number of different soft data values, determining a quantity of memory cells associated with each of the different soft data values, and inferring at least a portion of a threshold voltage distribution associated with the group of memory cells via an interpolation process using the determined quantities of memory cells associated with each of the different soft data values.. ... Micron Technology Inc

07/28/16 / #20160217834

Low voltage sensing scheme having reduced active power down standby current

A low voltage sensing scheme reduces active power down standby leakage current in a memory device. A clamping device or diode is used between a psense amplifier control line (e.g. ... Micron Technology Inc

07/28/16 / #20160217831

Providing power availability information to memory

The present disclosure includes apparatuses and methods for providing power availability information to memory. A number of embodiments include a memory and a controller. ... Micron Technology Inc

07/28/16 / #20160217365

Methods and devices for programming a state machine engine

A state machine engine having a program buffer. The program buffer is configured to receive configuration data via a bus interface for configuring a state machine lattice. ... Micron Technology Inc

07/28/16 / #20160216465

Method of forming a hermetically sealed fiber to chip connections

Disclosed are methods of providing a hermetically sealed optical connection between an optical fiber and an optical element of a chip and a photonic-integrated chip manufactured using such methods.. . ... Micron Technology Inc

07/21/16 / #20160211448

Memory cells and methods of making memory cells

Some embodiments include a memory cell having a data storage region between a pair of conductive structures. The data storage region is configured to support a transitory structure which alters resistance through the memory cell. ... Micron Technology Inc

07/21/16 / #20160211446

Spin transfer torque memory cells

Spin transfer torque memory cells and methods of forming the same are described herein. As an example, spin transfer torque memory cells may include an amorphous material, a storage material formed on the amorphous material, wherein the storage material is substantially boron free, an interfacial perpendicular magnetic anisotropy material formed on the storage material, a reference material formed on the interfacial perpendicular magnetic anisotropy material, wherein the reference material is substantially boron free, a buffer material formed on the reference material and a pinning material formed on the buffer material.. ... Micron Technology Inc

07/21/16 / #20160211440

Semiconductor devices, magnetic tunnel junctions, and methods of fabrication thereof

A semiconductor device comprises an array of magnetic cell structures each comprising a magnetic tunnel junction over an electrode on a substrate. Each of the magnetic tunnel junctions includes a magnetic material over the substrate, a first tunnel barrier material over the magnetic material, a second tunnel barrier material over the annealed first tunnel barrier material, and another magnetic material over the second tunnel barrier material. ... Micron Technology Inc

07/21/16 / #20160211430

High-voltage solid-state transducers and associated systems and methods

High-voltage solid-state transducer (sst) devices and associated systems and methods are disclosed herein. An sst device in accordance with a particular embodiment of the present technology includes a carrier substrate, a first terminal, a second terminal and a plurality of sst dies connected in series between the first and second terminals. ... Micron Technology Inc

07/21/16 / #20160211423

Wavelength converters, including polarization-enhanced carrier capture converters, for solid state lighting devices, and associated systems and methods

Wavelength converters, including polarization-enhanced carrier capture converters, for solid state lighting devices, and associated systems and methods are disclosed. A solid state radiative semiconductor structure in accordance with a particular embodiment includes a first region having a first value of a material characteristic and being positioned to receive radiation at a first wavelength. ... Micron Technology Inc

07/21/16 / #20160211324

Semiconductor devices, and methods of forming semiconductor devices

Some embodiments include a device having an n-type diffusion region, and having a boron-doped region within the n-type diffusion region. The boron-doped region extends no deeper than about 10 nanometers from an upper surface of the n-type diffusion region. ... Micron Technology Inc

07/21/16 / #20160211034

Apparatus and methods for determining a pass/fail condition of a memory device

Memory devices including an array of memory cells, a first buffer selectively connected to the array of memory cells and corresponding to a particular bit rank of a byte of information of a programming operation of the memory device, and a second buffer selectively connected to the array of memory cells and corresponding to the particular bit rank of a different byte of information of the programming operation of the memory device, wherein an output of the first buffer and an output of the second buffer are connected in parallel to a common line, as well as methods of their operation to indicate a pass/fail condition of the programming operation.. . ... Micron Technology Inc

07/21/16 / #20160211022

Erasable block segmentation for memory

Various embodiments comprise apparatuses such as those having a block of memory divided into sub-blocks that share a common data line. Each of the sub-blocks of the block of memory corresponds to a respective one of a number of segmented sources. ... Micron Technology Inc

07/21/16 / #20160211019

Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and memory devices

Embodiments disclosed include memory cell operating methods, memory cell programming methods, memory cell reading methods, memory cells, and memory devices. In one embodiment, a memory cell includes a wordline, a first bitline, a second bitline, and a memory element. ... Micron Technology Inc

07/21/16 / #20160211017

Heating phase change material

A phase change memory may be formed of two vertically spaced layers of phase change material. An intervening dielectric may space the layers from one another along a substantial portion of their lateral extent. ... Micron Technology Inc

07/21/16 / #20160210236

Dynamic data caches, decoders and decoding methods

Examples described include dynamic data caches (ddcs), decoders and decoding methods that may fit into a smaller width area. The ddcs, decoders and decoding method may be used in flash memory devices. ... Micron Technology Inc

07/21/16 / #20160209859

Apparatuses and related methods for staggering power-up of a stack of semiconductor dies

An apparatus including semiconductor dies in a stack. The semiconductor dies are configured to power-up in a staggered manner. ... Micron Technology Inc

07/14/16 / #20160205737

Self-identifying solid-state transducer modules and associated systems and methods

Self-identifying solid-state transducer (sst) modules and associated systems and methods are disclosed herein. In several embodiments, for example, an sst system can include a driver and at least one sst module electrically coupled to the driver. ... Micron Technology Inc

07/14/16 / #20160204343

Structures incorporating and methods of forming metal lines including carbon

Disclosed technology relates generally to integrated circuits, and more particularly, to structures incorporating and methods of forming metal lines including tungsten and carbon, such as conductive lines for memory arrays. In one aspect, a memory device comprises a lower conductive line extending in a first direction and an upper conductive line extending in a second direction and crossing the lower conductive line, wherein at least one of the upper and lower conductive lines comprises tungsten and carbon. ... Micron Technology Inc

07/14/16 / #20160204205

Source material for electronic device applications

Various embodiments include methods and apparatuses comprising methods for formation of and apparatuses including a source material for electronic devices. One such apparatus includes a vertical string of memory cells comprising a plurality of alternating levels of conductor and dielectric material, a semiconductor material extending through the plurality of alternating levels of conductor material and dielectric material, and a source material coupled to the semiconductor material. ... Micron Technology Inc

07/14/16 / #20160204022

Semiconductor device structures with improved planarization uniformity, and related methods

Semiconductor devices and structures, such as phase change memory devices, include peripheral conductive pads coupled to peripheral conductive contacts in a peripheral region. An array region may include memory cells coupled to conductive lines. ... Micron Technology Inc

07/14/16 / #20160203993

Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same

A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. ... Micron Technology Inc

07/14/16 / #20160203875

Dynamic program window determination in a memory device

A memory device has a controller. The controller is configured to cause the memory device to inhibit programming of a group of memory cells. ... Micron Technology Inc

07/14/16 / #20160203861

Memory cells, memory systems, and memory programming methods

Memory cells, memory systems and methods are described. In one embodiment, a memory cell includes electrodes and a memory element, and a first electrically conductive structure is formed within dielectric material providing the memory element in a low resistance state as a result of a first voltage of a first polarity being applied across the electrodes. ... Micron Technology Inc

07/14/16 / #20160203850

Quantizing circuits having improved sensing

A system including a processor and a memory device. The memory device includes a memory array having a plurality of memory elements connected to a bit-line and a quantizing circuit. ... Micron Technology Inc

07/14/16 / #20160203048

Memory cell coupling compensation

Methods for memory cell coupling compensation and apparatuses configured to perform the same are described. One or more methods for memory cell coupling compensation includes determining a state of a memory cell using a voltage that is changed in accordance with a first memory cell coupling compensation voltage, performing an error check on the state of the memory cell, and determining the state of the memory cell using a voltage that is changed in accordance with a second memory cell coupling compensation voltage in response to the error check failing.. ... Micron Technology Inc

07/14/16 / #20160203045

Semiconductor device having error correction code (ecc) circuit

An apparatus may comprise an ecc circuit configured to receive read data from a memory cell array to correct, an error bit contained in a data portion of the read data responsive, at least in part, to a parity portion of the read data, to generate a plurality of first error determination signals and a plurality of second error determination signals. Each of the plurality of first error determination signals provided in common to n data terminals and corresponding to an associated one of burst data of m bits. ... Micron Technology Inc

07/14/16 / #20160202913

Methods of providing access to i/o devices

A method of providing one or more computing devices with access to a plurality of resources. The plurality of resources are provided by at least one physical device. ... Micron Technology Inc

07/07/16 / #20160197653

Wireless communication link using near field coupling

A memory device may include an array of closely spaced memory integrated circuits that communicate wirelessly over at least two frequencies using near field coupling.. . ... Micron Technology Inc

07/07/16 / #20160197623

Read threshold calibration for ldpc

Apparatuses and methods for soft read threshold location calibration are provided. One example method can include selecting read threshold sets (rtss), and determining log-likelihood-ratios (llrs) based on a number of decisions that correspond to each bin associated with the selected rtss. ... Micron Technology Inc

07/07/16 / #20160197255

Light emitting diodes with enhanced thermal sinking and associated methods of operation

Solid state lighting devices and associated methods of thermal sinking are described below. In one embodiment, a light emitting diode (led) device includes a heat sink, an led die thermally coupled to the heat sink, and a phosphor spaced apart from the led die. ... Micron Technology Inc

07/07/16 / #20160197231

Solid state lighting devices with dielectric insulation and methods of manufacturing

Solid state lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state lighting device includes a first semiconductor material, a second semiconductor material spaced apart from the first semiconductor material, and an active region between the first and second semiconductor materials. ... Micron Technology Inc

07/07/16 / #20160196967

Removal of metal

Methods of removing metal from a portion of a substrate are useful in integrated circuit fabrication. Methods include exposing the substrate to an oxidizing environment comprising at least one oxidizing agent and at least one reducing agent, determining whether metal remaining on the portion of the substrate is less than or equal to a particular level, and if the metal remaining on the portion of the substrate is deemed to be greater than the particular level, exposing the substrate to a reducing environment comprising at least one reducing agent and at least one oxidizing agent.. ... Micron Technology Inc

07/07/16 / #20160196856

Longest element length determination in memory

Examples of the present disclosure provide apparatuses and methods for determining a length of a longest element in a memory. An example method comprises determining, using a controller to control sensing circuitry, a length of a longest element of a plurality of variable length elements of a vector stored in a memory array.. ... Micron Technology Inc

07/07/16 / #20160196181

Synchronized transfer of data and corresponding error correction data

Memory devices having a first plurality of data buffers coupled to sense circuitry, a second plurality of data buffers coupled to sense circuitry, and an error correction controller coupled to the first and second plurality of data buffers and configured to synchronize data from the first and second plurality of data buffers prior to transmitting the data, as well as systems containing such memory devices.. . ... Micron Technology Inc

07/07/16 / #20160196142

Generating and executing a control flow

Examples of the present disclosure provide apparatuses and methods related to generating and executing a control flow. An example apparatus can include a first device configured to generate control flow instructions, and a second device including an array of memory cells, an execution unit to execute the control flow instructions, and a controller configured to control an execution of the control flow instructions on data stored in the array.. ... Micron Technology Inc

07/07/16 / #20160195581

Apparatuses and methods for die seal crack detection

Apparatuses and methods can include a die seal between an integrated circuit region of a die and a periphery of the die. A via chain(s) may be arranged around an inner circumference of the die seal between the die seal and the integrated circuit region and/or around an outer circumference of the die seal between the die seal and the periphery of the die. ... Micron Technology Inc

06/16/16 / #20160172847

Apparatuses and method for over-voltage event protection

Circuits, integrated circuits, apparatuses, and methods, such as those for protecting circuits against electrostatic discharge events are disclosed. An example apparatus comprises a thyristor coupled to a node and configured to limit the voltage and discharge the current associated with an over-voltage event at the node. ... Micron Technology Inc

06/16/16 / #20160172587

Memory cells, integrated devices, and methods of forming memory cells

Some embodiments include integrated devices, such as memory cells. The devices may include chalcogenide material, an electrically conductive material over the chalcogenide material, and a thermal sink between the electrically conductive material and the chalcogenide material. ... Micron Technology Inc

06/16/16 / #20160172586

Method, system, and device for heating a phase change memory cell

Embodiments disclosed herein may relate to heating a phase change memory (pcm) cell.. . ... Micron Technology Inc

06/16/16 / #20160172373

Memory arrays and methods of fabricating integrated structures

Some embodiments include a memory array which has a stack of alternating first and second levels. Channel material pillars extend through the stack, and vertically-stacked memory cell strings are along the channel material pillars. ... Micron Technology Inc

06/16/16 / #20160172363

Method of forming contacts for a memory device

The present invention is generally directed to a method of forming contacts for a memory device. In one illustrative embodiment, the method includes forming a layer of insulating material above an active area of a dual bit memory cell, forming a hard mask layer above the layer of insulating material, the hard mask layer having an original thickness, performing at least two partial etching processes on the hard mask layer to thereby define a patterned hard mask layer above the layer of insulating material, wherein each of the partial etching processes is designed to etch through less than the original thickness of the hard mask layer, the hard mask layer having openings formed therein that correspond to a digitline contact and a plurality of storage node contacts for the dual bit memory cell, and performing at least one etching process to form openings in the layer of insulating material for the digitline contact and the plurality of storage node contacts using the patterned hard mask layer as an etch mask.. ... Micron Technology Inc

06/16/16 / #20160172349

Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices

A stackable microelectronic package includes a first microelectronic die attached to and electrically connecting with a first substrate. A second microelectronic die is attached to the first die on one side, and to a second substrate on the other side. ... Micron Technology Inc

06/16/16 / #20160172336

Independent control of stacked electronic modules

Apparatus and methods are disclosed to allow independent control of stacked memory modules. In one embodiment, an apparatus may comprise first, second, and third modules, each of the first, second and third modules having a plurality of stacked memory dice, at least some of the plurality of stacked memory dice including a chip enable (ce) signal electrically accessible from a bottom surface of a corresponding module of the first, second and third modules. ... Micron Technology Inc

06/16/16 / #20160172242

Semiconductor devices and methods for backside photo alignment

Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for aligning an electronic feature to a through-substrate via includes forming a self-aligned alignment feature having a wall around at least a portion of the tsv and aligning a photolithography tool to the self-aligned alignment feature. ... Micron Technology Inc

06/16/16 / #20160172208

Chemical mechanical planarization topography control via implant

Systems and methods for chemical mechanical planarization topography control via implants are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes increasing the content of at least one of silicon or germanium in at least select regions of a dielectric material thereby reducing the material removal rate for a chemical mechanical polishing (cmp) process at the select regions, and removing material from the dielectric material using the cmp process. ... Micron Technology Inc

06/16/16 / #20160172195

Nanostructures having low defect density and methods of forming thereof

A method of forming nanostructure comprises forming self-assembled nucleic acids on at least a portion of a substrate. The method further comprises contacting the self-assembled nucleic acids on the at least a portion of a substrate with a solution comprising at least one repair enzyme to repair defects in the self-assembled nucleic acids. ... Micron Technology Inc

06/16/16 / #20160172041

Sequential write and sequential write verify in memory device

Some embodiments include apparatuses and methods for performing a first stage of an operation of storing information in a first memory cell and a second memory cell, and performing a second stage of the operation after the first stage to determine whether each of the first and second memory cells reaches a target state. The first memory cell is included in a first memory cell string coupled to a data line through a first select transistor. ... Micron Technology Inc

06/16/16 / #20160172031

Memory systems and memory programming methods

Memory systems and memory programming methods are described. According to one arrangement, a memory system includes a memory array comprising a plurality of memory cells individually configured to have a plurality of different memory states, access circuitry configured to apply signals to the memory cells to program the memory cells to the different memory states, and a controller to configured to control the access circuitry to apply a first of the signals to one of the memory cells to program the one memory cell from a first memory state to a second memory state different than the first memory state, to determine that the one memory cell failed to place into the second memory state as a result of the application of the first signal, and to control the access circuitry to apply a second signal to the one memory cell to program the one memory cell from the first memory state to the second memory state as a result of the determination, wherein the first and second signals have a different electrical characteristic.. ... Micron Technology Inc

06/16/16 / #20160172030

Methods, articles and devices for pulse adjustments to program a memory cell

Embodiments disclosed herein may relate to adjusting an aspect of a programming pulse for one or more memory cells, such as based at least in part on one or more detected programmed resistance values for the one or more memory cells.. . ... Micron Technology Inc

06/16/16 / #20160172020

Optical interconnect in high-speed memory systems

A optical link for achieving electrical isolation between a controller and a memory device is disclosed. The optical link increases the noise immunity of electrical interconnections, and allows the memory device to be placed a greater distance from the processor than is conventional without power-consuming i/o buffers.. ... Micron Technology Inc

06/16/16 / #20160172018

Apparatuses and methods for capturing data using a divided clock

Apparatuses and methods for capturing data using a divided clock are described. An example apparatus includes a clock divider configured to receive a dqs signal, and to provide divided clock signals. ... Micron Technology Inc

06/16/16 / #20160172017

Tracking and correction of timing signals

Various embodiments include apparatus and methods to track and/or correct timing signals. Timing signals generated from an interface can be compared to the timing signals returned to the interface. ... Micron Technology Inc

06/16/16 / #20160172015

Apparatuses and methods for performing logical operations using sensing circuitry

The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry comprising a primary latch coupled to a sense line of the array. ... Micron Technology Inc

06/16/16 / #20160170728

Utilizing special purpose elements to implement a fsm

Apparatus, systems, and methods for a compiler are described. One such compiler generates machine code corresponding to a set of elements including a general purpose element and a special purpose element. ... Micron Technology Inc

06/09/16 / #20160165153

Ambient infrared detection in solid state sensors

An image sensor device has a first region configured to sense only infrared illumination and a second region configured to not sense visible and infrared illumination.. . ... Micron Technology Inc

06/09/16 / #20160164509

Apparatuses and methods for adjusting timing of signals

Apparatuses and methods for adjusting timing of signals are described herein. An example apparatus may include a first signal adjustment cell configured to receive a first clock signal and to adjust skew of rising or falling edges of the first clock signal based on a first control signal. ... Micron Technology Inc

06/09/16 / #20160164508

Apparatuses and methods for adjusting timing of signals

Apparatuses and methods for adjusting timing of signals are described herein. An example method may include providing an output clock signal responsive to an input clock signal, and adjusting a slew rate of the output clock signal by a delayed output clock signal.. ... Micron Technology Inc

06/09/16 / #20160164494

Semiconductor device and method for adjusting impedance of output circuit

An impedance adjustment circuit includes a counter circuit outputting a count value thereof as a plurality of first impedance adjustment signals, a mode selection circuit setting a second impedance adjustment signal to be in an active/inactive state irrespective of the count value, and a level fixing circuit fixing a third impedance adjustment signal to be in an active state. A pre-stage circuit generates a plurality of first output control signals, a second output control signal, and a third output control signal in response to the first impedance adjustment signals, the second impedance adjustment signal, and the third impedance adjustment signal, respectively, and a data signal. ... Micron Technology Inc

06/09/16 / #20160163967

Magnetic tunnel junctions

A magnetic tunnel junction includes a conductive first magnetic electrode that includes magnetic recording material. A conductive second magnetic electrode is spaced from the first electrode and includes magnetic reference material. ... Micron Technology Inc

06/09/16 / #20160163963

Magnetic memory cells and methods of fabrication

A magnetic cell includes a magnetic tunnel junction that comprises magnetic and nonmagnetic materials exhibiting hexagonal crystal structures. The hexagonal crystal structure is enabled by a seed material, proximate to the magnetic tunnel junction, that exhibits a hexagonal crystal structure matching the hexagonal crystal structure of the adjoining magnetic material of the magnetic tunnel junction. ... Micron Technology Inc

06/09/16 / #20160163783

Semiconductor device and semiconductor memory devices having first, second, and third insulating layers

Disclosed herein is a device that includes: a semiconductor substrate; a first insulating layer over a surface of the semiconductor substrate; first and second contact plugs each including side and upper surfaces, the side surfaces of the first and second contact plugs being surrounded by the first insulating film, the upper surfaces of the first and second contact plugs being substantially on the same plane with an upper surface of the first insulating layer; a second insulating layer over the first insulating layer; a first conductive layer including a bottom portion on the first contact plug and a side portion surrounded by the second insulating layer; a third insulating layer over the first conductive layer; and a second conductive layer on the second contact plug, apart of a side surface of the second conductive layer being surrounded by both the second and third insulating layers.. . ... Micron Technology Inc

06/09/16 / #20160163727

Methods and apparatuses including a select transistor having a body region including monocrystalline semiconductor material and/or at least a portion of its gate located in a substrate

Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatuses and a select transistor coupled to the memory cell string. In at least one of such apparatuses, the select transistor can include a body region including a monocrystalline semiconductor material. ... Micron Technology Inc

06/09/16 / #20160163726

Apparatuses including memory arrays with source contacts adjacent edges of sources

Various apparatuses, including three-dimensional (3d) memory devices and systems including the same, are described herein. In one embodiment, a 3d memory device can include at least two sources; at least two memory arrays respectively formed over and coupled to the at least two sources; and a source conductor electrically respectively coupled to the at least two sources using source contacts adjacent one or more edges of the source. ... Micron Technology Inc

06/09/16 / #20160163709

Semiconductor device

Disclosed herein is a method includes: forming first and second cavities, the first cavity having a first width, each of the second cavities having a second width narrower than the first width; forming a first conductive layer buried in the second cavities and formed on bottom and side surface of the semiconductor substrate defined by the first cavity so that a third cavity is defined by the first conductive layer formed on the bottom and side surface of the semiconductor substrate; subjecting an etch back process to the first conductive layer so that a first conductive portion is formed at a bottom corner of the first cavity, further a fourth cavity is formed on the semiconductor substrate uncovered with the first conductive portion in the first cavity; and forming a first insulating layer in the fourth cavity and in the second cavity.. . ... Micron Technology Inc

06/09/16 / #20160163536

Methods of forming semiconductor device structures including metal oxide structures

Methods of forming metal oxide structures and methods of forming metal oxide patterns on a substrate using a block copolymer system formulated for self-assembly. A block copolymer at least within a trench in the substrate and including at least one soluble block and at least one insoluble block may be annealed to form a self-assembled pattern including a plurality of repeating units of the at least one soluble block laterally aligned with the trench and positioned within a matrix of the at least one insoluble block. ... Micron Technology Inc

06/09/16 / #20160163396

Peak current contrl

A low-dropout regulator includes an error amplifier to provide a control signal, a first transistor, and a second transistor. The first transistor receives the control signal and has a source-drain path electrically coupled between a supply voltage node and a load, the first transistor to power the load in response to a voltage on the supply voltage node rising above an absolute value of a threshold voltage of the first transistor. ... Micron Technology Inc

06/09/16 / #20160163388

Applying substantially the same voltage differences across memory cells at different locations along an access line while programming

An embodiment of a method of programing might include applying a first voltage difference across a first memory cell to be programed, where applying the first voltage difference comprises applying a first channel bias voltage to a channel of the first memory cell, and applying a second voltage difference, substantially equal to the first voltage difference, across a second memory cell to be programed while applying the first voltage difference across the first memory-cell, where applying the second voltage difference comprises applying a second channel bias voltage to a channel of the second memory cell. The first channel bias voltage is different than the second channel bias voltage, and the first memory cell and the second memory cell are commonly coupled to an access line and are at different locations along a length of the access line.. ... Micron Technology Inc

06/09/16 / #20160163383

Apparatuses and methods of reading memory cells based on response to a test pulse

The disclosed technology generally relates to memory apparatuses and methods of operating the same, and more particularly to memory arrays and methods of reading memory cells in a memory array, such as a cross point memory array. In one aspect, the method comprises providing a memory array comprising a memory cell in one of a plurality of states. ... Micron Technology Inc

06/02/16 / #20160155936

Memory arrays and methods of forming memory cells

Some embodiments include methods of forming memory cells. A series of rails is formed to include bottom electrode contact material. ... Micron Technology Inc

06/02/16 / #20160155932

Magnetic cell structures, and methods of fabrication

A magnetic cell structure comprises a seed material including tantalum, platinum, and ruthenium. The seed material comprises a platinum portion overlying a tantalum portion, and a ruthenium portion overlying the platinum portion. ... Micron Technology Inc

06/02/16 / #20160155893

Engineered substrates for semiconductor devices and associated systems and methods

Engineered substrates for semiconductor devices are disclosed herein. A device in accordance with a particular embodiment includes a transducer structure having a plurality of semiconductor materials including a radiation-emitting active region. ... Micron Technology Inc

06/02/16 / #20160155855

Ferroelectric field effect transistors, pluralities of ferroelectric field effect transistors arrayed in row lines and column lines, and methods of forming a plurality of ferroelectric field effect transistors

A ferroelectric field effect transistor comprises a semiconductive channel comprising opposing sidewalls and an elevationally outermost top. A source/drain region is at opposite ends of the channel. ... Micron Technology Inc

06/02/16 / #20160155829

Transistors and methods of forming transistors

Some embodiments include a transistor having a drain region and a source region. A conductive gate is between the source and drain regions. ... Micron Technology Inc

06/02/16 / #20160155729

Proximity coupling of interconnect packaging systems and methods

An array of recessed access gate lines includes active area regions having dielectric trench isolation material there-between. The trench isolation material comprises dielectric projections extending into opposing ends of individual active area regions under an elevationally outermost surface of material of the active area regions. Proximity coupling interconnect packaging systems and methods. A semiconductor package assembly comprises a substrate, a first semiconductor die disposed adjacent the substrate, and a second semiconductor die stacked over the first semiconductor die. ... Micron Technology Inc

06/02/16 / #20160155619

Forming memory using high power impulse magnetron sputtering

Forming memory using high power impulse magnetron sputtering is described herein. One or more method embodiments include forming a resistive memory material on a structure using high power impulse magnetron sputtering (hipims), wherein the resistive memory material is formed on the structure in an environment having a temperature of approximately 400 degrees celsius or less.. ... Micron Technology Inc

06/02/16 / #20160155513

Program operations with embedded leak checks

Methods of operating a memory device having embedded leak checks may mitigate data loss events due to access line defects, and may facilitate improved power consumption characteristics. Such methods might include applying a program pulse to a selected access line coupled to a memory cell selected for programming, verifying whether the selected memory cell has reached a desired data state, bringing the selected access line to a first voltage, applying a second voltage to an unselected access line, applying a reference current to the selected access line, and determining if a current flow between the selected access line and the unselected access line is greater than the reference current.. ... Micron Technology Inc

06/02/16 / #20160155507

Memory devices and their operation having trim registers associated with access operation commands

Methods including performing an access operation on a memory device using trims corresponding to trim settings, receiving a command to suspend the access operation, loading updated trim settings into a particular trim register of the memory device, setting updated trims for the access operation in response to the updated trim settings of the particular trim register, and resuming the access operation using the updated trims. Apparatus including an external controller and a memory device having an internal controller configured to set trims in response to trim settings and to perform an access operation on an array of memory cells using the trims in response to receiving the access command, wherein the external controller is configured to select trim settings corresponding to a desired mode of operation, and to transmit the selected trim settings to the memory device. ... Micron Technology Inc

06/02/16 / #20160155482

Apparatuses and methods for converting a mask to an index

The present disclosure includes apparatuses and methods related to converting a mask to an index. An example apparatus comprises an array of memory cells and periphery logic configured to: generate an indicator mask by resetting, in response to a first control signal, a second digit of a mask different from a first digit of the mask that is set; and convert, in response to a second control signal, a digit position in the indicator mask of the first digit that is set to an identifier value as an index.. ... Micron Technology Inc

06/02/16 / #20160155481

Methods and apparatuses for compensating for source voltage

Apparatuses and methods for compensating for source voltage is described. An example apparatus includes a source coupled to a memory cell and a read-write circuit coupled to the memory cell. ... Micron Technology Inc

06/02/16 / #20160154747

State change in systems having devices coupled in a chained configuration

The present disclosure includes methods, devices, and systems for state change in systems having devices coupled in a chained configuration. A number of embodiments include a host and a number of devices coupled to the host in a chained configuration. ... Micron Technology Inc

06/02/16 / #20160154596

Multiple endianness compatibility

Examples of the present disclosure provide apparatuses and methods for multiple endianness compatibility. An example method comprises receiving a plurality of bytes and determining a particular endianness format of the plurality of bytes. ... Micron Technology Inc

05/26/16 / #20160149674

Apparatuses and methods to change information values

Some embodiments include apparatuses and methods having a component to change a value of a bit among a number of m bits of information when the m bits have the same value and when m exceeds a selected value. At least one of such embodiments can include a transmitting component to provide the information to a connection. ... Micron Technology Inc

05/26/16 / #20160149126

Three dimensional memory array architecture

Three dimension memory arrays and methods of forming the same are provided. An example three dimension memory array can include a stack comprising a plurality of first conductive lines separated from one another by at least an insulation material, and at least one conductive extension arranged to extend substantially perpendicular to the plurality of first conductive lines, such that the at least one conductive extension intersects a portion of at least one of the plurality of first conductive lines. ... Micron Technology Inc

05/26/16 / #20160148949

Semiconductor structures including dielectric materials having differing removal rates

Semiconductor structures may include a stack of alternating dielectric materials and control gates, charge storage structures laterally adjacent to the control gates, a charge block material between each of the charge storage structures and the laterally adjacent control gates, and a pillar extending through the stack of alternating oxide materials and control gates. Each of the dielectric materials in the stack has at least two portions of different densities and/or different rates of removal. ... Micron Technology Inc

05/26/16 / #20160148943

Methods and apparatuses with vertical strings of memory cells and support circuitry

Apparatuses and methods have been disclosed. One such apparatus includes strings of memory cells formed on a topside of a substrate. ... Micron Technology Inc

05/26/16 / #20160148918

Memory devices with controllers under memory packages and associated systems and methods

Memory devices with controllers under stacks of memory packages and associated systems and methods are disclosed herein. In one embodiment, a memory device is configured to couple to a host and can include a substrate, a stack of memory packages, and a controller positioned between the stack and the substrate. ... Micron Technology Inc

05/26/16 / #20160148672

Semiconductor device having a reduced footprint of wires connecting a dll circuit with an input/output buffer

An apparatus includes a clock terminal configured to receive an external clock signal, a clock generator configured to generate an internal clock signal in response to the external clock signal, first and second output circuits each coupled to the clock generator, a first clock line coupled between the clock generator and the first output circuit, and the second clock line coupled between the clock generator and the second output circuit. The first clock line represents a first capacitance and a first resistance while the second clock line represents a second capacitance and a second resistance. ... Micron Technology Inc

05/26/16 / #20160147997

Self-measuring nonvolatile memory device systems and methods

One embodiment describes a computing system that includes a boot device. The boot device includes nonvolatile memory that stores startup routine instructions and a first pointer, in which the first pointer identifies a first one or more memory addresses in the nonvolatile memory where at least a portion of the startup routine instructions are stored, and a microcontroller that retrieves the startup routine instructions from the nonvolatile memory using the first pointer and determines whether the startup routine instructions are corrupted before executing any portion of the startup routine instructions. ... Micron Technology Inc

05/19/16 / #20160141495

Memory device constructions, memory cell forming methods, and semiconductor construction forming methods

Memory device constructions include a first column line extending parallel to a second column line, the first column line being above the second column line; a row line above the second column line and extending perpendicular to the first column line and the second column line; memory material disposed to be selectively and reversibly configured in one of two or more different resistive states; a first diode configured to conduct a first current between the first column line and the row line via the memory material; and a second diode configured to conduct a second current between the second column line and the row line via the memory material. In some embodiments, the first diode is a schottky diode having a semiconductor anode and a metal cathode and the second diode is a schottky diode having a metal anode and a semiconductor cathode.. ... Micron Technology Inc

05/19/16 / #20160141416

Semiconductor devices and fabrication methods

Methods of fabricating vertical devices are described, along with apparatuses and systems that include them. In one such method, a vertical device is formed at least partially in a void in a first dielectric material and a second dielectric material. ... Micron Technology Inc

05/19/16 / #20160141336

Field effect transistor constructions and memory arrays

In some embodiments, a transistor includes a stack having a bottom source/drain region, a first insulative material, a conductive gate, a second insulative material, and a top source/drain region. The stack has a vertical sidewall with a bottom portion along the bottom source/drain region, a middle portion along the conductive gate, and a top portion along the top source/drain region. ... Micron Technology Inc

05/19/16 / #20160141270

Stacked semiconductor die assemblies with improved thermal performance and associated systems and methods

Stacked semiconductor die assemblies with improved thermal performance and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a stack of semiconductor dies and a thermally conductive casing at least partially enclosing the stack of semiconductor dies within an enclosure. ... Micron Technology Inc

05/19/16 / #20160141028

Reference voltage generators and sensing circuits

Described examples include sensing circuits and reference voltage generators for providing a reference voltage to a sensing circuit. The sensing circuits may sense a state of a memory cell, which may be a pcm memory cell. ... Micron Technology Inc

05/19/16 / #20160140049

Wireless memory interface

Systems and methods for vendor-agnostic access to non-volatile memory of a wireless memory tag include: detecting, via a wireless memory host, a wireless memory tag; providing a vendor-agnostic command to the wireless memory tag to affect a change in a register-based interface of the wireless memory tag, wherein the change results in reading data from non-volatile memory of the wireless memory tag, writing data to the non-volatile memory of the wireless memory tag, or both.. . ... Micron Technology Inc

05/19/16 / #20160139848

Mapping between program states and data patterns

The present disclosure includes methods and apparatuses for mapping between program states and data patterns. One method includes mapping a data pattern to a number of program state combinations l corresponding to a group of memory cells configured to store a fractional number of data units per cell. ... Micron Technology Inc

05/19/16 / #20160139826

Memory wear leveling

Systems and methods for intra-sector re-ordered wear leveling include: detecting, in a memory device, a high wear sub-sector having a high wear level, the sub-sector residing in a first sector; determining a second sector of the memory device having a low wear level; swapping the first sector with the second sector; and re-ordering a position of at least one sub-sector of the first sector, the second sector, or both.. . ... Micron Technology Inc

05/19/16 / #20160139813

Re-building mapping information for memory devices

Devices and methods storing user data along with a plurality of addresses corresponding to physical pages storing valid data corresponding to a logical data block are useful in re-building mapping information for the logical data block.. . ... Micron Technology Inc

05/12/16 / #20160133835

Integrated circuitry comprising nonvolatile memory cells and methods of forming a nonvolatile memory cell

An integrated circuit has a nonvolatile memory cell that includes a first electrode, a second electrode, and an ion conductive material there-between. At least one of the first and second electrodes has an electrochemically active surface received directly against the ion conductive material. ... Micron Technology Inc

05/12/16 / #20160133752

3d memory

Three-dimensional memory cells and methods of making and using the memory cells are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory can include a memory stack. ... Micron Technology Inc

05/12/16 / #20160133717

Transistors, memory cells and semiconductor constructions

Some embodiments include a semiconductor construction having a gate extending into a semiconductor base. Conductively-doped source and drain regions are within the base adjacent the gate. ... Micron Technology Inc

05/12/16 / #20160133671

Cross-point memory and methods for fabrication of same

A cross-point memory array includes a plurality of variable resistance memory cell pillars. Adjacent memory cell pillars are separated by a partially filled gap that includes a buried void. ... Micron Technology Inc

05/12/16 / #20160133638

Memory cell pillar including source junction plug

Some embodiments include apparatuses and methods having a source material, a dielectric material over the source material, a select gate material over the dielectric material, a memory cell stack over the select gate material, a conductive plug located in an opening of the dielectric material and contacting a portion of the source material, and a channel material extending through the memory cell stack and the select gate material and contacting the conductive plug.. . ... Micron Technology Inc

05/12/16 / #20160133332

Random telegraph signal noise reduction scheme for semiconductor memories

Embodiments are provided that include a method including providing a first voltage to a memory cell prior to an operation, wherein a magnitude of the first voltage is approximately 5 volts. The method further includes providing a second voltage to the memory cell during the operation, wherein a magnitude of the second voltage is in the range of approximately 1.0 and 1.5 volts. ... Micron Technology Inc

05/12/16 / #20160133327

Memory devices and biasing methods for memory devices

Methods of biasing in memory devices facilitate memory device programming operations. In at least one embodiment, a first string of memory cells comprising a selected memory cell and a second string of memory cells are coupled to a common data line and a common source, where the data line is biased to a potential greater than a potential to which the source is biased during a programming operation performed on the selected memory cell.. ... Micron Technology Inc

05/12/16 / #20160133326

Apparatuses and methods for non-volatile memory programming schemes

Apparatuses and methods for a non-volatile memory scheme are described herein. An example apparatus may include a memory block including a plurality of subblocks of memory cells and further may include a control unit. ... Micron Technology Inc

05/12/16 / #20160133319

Apparatuses and methods for accessing variable resistance memory device

The disclosed technology generally relates to memory apparatuses and methods of operating the same, and more particularly to a memory device having a controller configured to cause a write operation to be performed on a variable resistance memory cell, which includes application of two successive access pulses having opposite polarities, and methods of using the same.. . ... Micron Technology Inc

05/12/16 / #20160133310

Apparatuses and methods to perform post package trim

Memory die can be stacked to form a three-dimensional integrated circuit. For example, through-silicon vias (tsvs) can permit signals to pass vertically through the three-dimensional integrated circuit. ... Micron Technology Inc

05/12/16 / #20160133300

Connections for memory electrode lines

Subject matter disclosed herein may relate to word line electrodes and/or digit line electrodes in a cross-point array memory device. One or more word line electrodes may be configured to form a socket area to provide connection points to drivers and/or other circuitry that may be located within a footprint of an array of memory cells.. ... Micron Technology Inc

05/12/16 / #20160132264

Systems, devices, memory controllers, and methods for controlling memory

Systems, devices, memory controllers, and methods for controlling memory are described. One such method includes activating a memory unit of a memory device; after activating the memory unit, providing a command to the memory device; and returning the memory unit to a previous state if the command does not indicate a target memory volume, wherein the memory unit remains active if the command indicates a target memory volume associated with the memory unit.. ... Micron Technology Inc

05/05/16 / #20160126354

Methods of forming transistors

Some embodiments include methods of forming transistors. Recesses are formed to extend into semiconductor material. ... Micron Technology Inc

05/05/16 / #20160126290

Memory arrays and methods of forming an array of memory cell

A method of forming an array of memory cells includes forming lines of covering material that are elevationally over and along lines of spaced sense line contacts. Longitudinal orientation of the lines of covering material is used in forming lines comprising programmable material and outer electrode material that are between and along the lines of covering material. ... Micron Technology Inc

05/05/16 / #20160126181

Methods of fabricating integrated circuitry

A method of fabricating integrated circuitry includes forming a first conductive line. First elemental tungsten is deposited directly against an elevationally outer surface of the first conductive line selectively relative to any exposed non-conductive material. ... Micron Technology Inc

05/05/16 / #20160125919

Apparatuses and methods for performing logical operations using sensing circuitry

The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. ... Micron Technology Inc

05/05/16 / #20160124860

Methods and systems for handling data received by a state machine engine

A data analysis system to analyze data. The data analysis system includes a data buffer configured to receive data to be analyzed. ... Micron Technology Inc

04/28/16 / #20160119169

Apparatuses and methods for adding offset delays to signal lines of multi-level communication architectures

Apparatuses and methods for adding offset delays to signal lines of multi-level communication architectures are disclosed herein. An example method may include comparing a current channel state of a channel of a multi-level communication bus with a next channel state of the channel. ... Micron Technology Inc

04/28/16 / #20160118937

Apparatuses and methods for providing oscillation signals

Apparatuses and methods are disclosed for oscillators that are substantially insensitive to supply voltage variations. In one such example apparatus, a capacitance circuit is configured to be charged and discharged. ... Micron Technology Inc

04/28/16 / #20160118441

Switching components and memory units

Some embodiments include a switching component which includes a selector region between a pair of electrodes. The selector region contains silicon doped with one or more of nitrogen, oxygen, germanium and carbon. ... Micron Technology Inc

04/28/16 / #20160118439

Magnetic tunnel junctions and methods of forming magnetic tunnel junctions

A method of forming a line of magnetic tunnel junctions includes forming magnetic recording material over a substrate, non-magnetic material over the recording material, and magnetic reference material over the non-magnetic material. The substrate has alternating outer regions of reactant source material and insulator material along at least one cross-section. ... Micron Technology Inc

04/28/16 / #20160118405

Apparatuses having a ferroelectric field-effect transistor memory array and related method

An apparatus comprises field-effect transistor (fet) structures stacked horizontally and vertically in a three-dimensional memory array architecture, gates extending vertically and spaced horizontally between the plurality of fet structures, and a ferroelectric material separating the fet structures and the gates. Individual ferroelectric fets (fefets) are formed at intersections of the fet structures, the gates, and the ferroelectric material. ... Micron Technology Inc

04/28/16 / #20160118402

Semiconductor constructions and nand unit cells

Some embodiments include methods of forming semiconductor constructions. Alternating layers of n-type doped material and p-type doped material may be formed. ... Micron Technology Inc

04/28/16 / #20160118392

Charge storage apparatus and methods

Methods of forming multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, an opening is formed in a tier of semiconductor material and a tier of dielectric. ... Micron Technology Inc

04/28/16 / #20160118367

Redistribution layers for microfeature workpieces, and associated systems and methods

Redistribution layers for microfeature workpieces, and associated systems and methods are disclosed. One method for processing a microfeature workpiece system includes positioning a pre-formed redistribution layer as a unit proximate to and spaced apart from a microfeature workpiece having an operable microfeature device. ... Micron Technology Inc

04/28/16 / #20160118340

Low-resistance interconnects and methods of making same

Devices and methods for providing low-resistance interconnects in a semiconductor device are provided. Specifically, one or more embodiments of the present invention relate to disposing a conductive material in a trench without disposing a resistive barrier material between the conductive material and the sidewalls of the trench so that the conductive material takes up the full width of the trench. ... Micron Technology Inc

04/28/16 / #20160118259

Zralon films

Atomic layer deposition (ald) can be used to form a dielectric layer of zirconium aluminum oxynitride (zralon) for use in a variety of electronic devices. Forming the dielectric layer may include depositing zirconium oxide using atomic layer deposition and precursor chemicals, followed by depositing aluminum nitride using precursor chemicals, and repeating. ... Micron Technology Inc

04/28/16 / #20160118143

Threshold voltage margin analysis

The present disclosure is related to a threshold voltage margin analysis. An example embodiment apparatus can include a memory and a controller coupled to the memory. ... Micron Technology Inc

04/28/16 / #20160118129

Read voltage adjustment

The present disclosure includes apparatuses and methods related to adjusting read voltages of charge-trapping flash memory. An example embodiment apparatus can include a memory array and a controller coupled to the memory array. ... Micron Technology Inc

04/28/16 / #20160118119

Memory programming methods and memory systems

Memory programming methods and memory systems are described. One example memory programming method includes first applying a first signal to a memory cell to attempt to program the memory cell to a desired state, wherein the first signal corresponds to the desired state, after the first applying, determining that the memory cell failed to place in the desired state, after the determining, second applying a second signal to the memory cell, wherein the second signal corresponds to another state which is different than the desired state, and after the second applying, third applying a third signal to the memory cell to program the memory cell to the desired state, wherein the third signal corresponds to the desired state. ... Micron Technology Inc

04/28/16 / #20160118118

Memory cells, methods of forming memory cells, and methods of programming memory cells

Some embodiments include methods in which a memory cell is formed to have programmable material between first and second access lines, with the programmable material having two compositionally different regions. A concentration of ions and/or ion-vacancies may be altered in at least one of the regions to change a memory state of the memory cell and to simultaneously form a pn diode. ... Micron Technology Inc

04/28/16 / #20160118101

Apparatuses and methods for setting a signal in variable resistance memory

An example of a method reads a spin torque transfer (stt) memory cell, and writes the stt memory cell using information obtained during the reading of the stt memory cell to set a pulse to write the stt memory cell. An example of an apparatus includes a stt memory cell and read/write circuitry coupled to the stt memory cell to determine a read current (iread) through the stt memory cell and to set a pulse to write the stt memory cell using iread. ... Micron Technology Inc

04/28/16 / #20160118096

Apparatuses, circuits, and methods for biasing signal lines

Apparatuses, circuits, and methods are disclosed for biasing signal lines in a memory array. In one such example the memory array includes a signal line coupled to a plurality of memory cells and is configured to provide access to the plurality of memory cells responsive to a biasing condition of the signal line. ... Micron Technology Inc

04/28/16 / #20160118087

Memory devices, memory device operational methods, and memory device implementation methods

Memory devices, memory device operational methods, and memory device implementation methods are described. According to one arrangement, a memory device includes memory circuitry configured to store data in a plurality of different data states, temperature sensor circuitry configured to sense a temperature of the memory device and to generate an initial temperature output which is indicative of the temperature of the memory device, and conversion circuitry coupled with the temperature sensor circuitry and configured to convert the initial temperature output into a converted temperature output which is indicative of the temperature of the memory device at a selected one of a plurality of possible different temperature resolutions, and wherein the converted temperature output is utilized by the memory circuitry to implement at least one operation with respect to storage of the data.. ... Micron Technology Inc

04/28/16 / #20160117272

Programming interruption management

The present disclosure is related to programming interruption management. An apparatus can be configured to detect an interruption during a programming operation and modify the programming operation to program a portion of the memory array to an uncorrectable state in response to detecting the interruption.. ... Micron Technology Inc

04/28/16 / #20160117216

Temperature related error management

Apparatuses and methods for temperature related error management are described. One or more apparatuses for temperature related error management can include an array of memory cells and a write temperature indicator appended to at least one predetermined number of bytes of the stored data in the array of memory cells. ... Micron Technology Inc

04/28/16 / #20160117108

Non-volatile memory, system, and method

A non volatile memory device includes a first buffer register configured to receive and store the data to be stored into the memory device provided via a memory bus. A command window is activatable for interposing itself for access to a memory matrix between the first buffer element and the memory matrix. ... Micron Technology Inc

04/07/16 / #20160099922

Secure shared key sharing systems and methods

Systems and methods used to securely communicate a shared key to devices. One embodiment describes a method to securely communicate a shared key to a first device and a second device that includes receiving, using the first device, a shared key and unique identifier pairing associated with the first device from a key generator; receiving, using a trusted third party, the shared key and unique identifier pairing from the key generator; generating, using the first device, a signature using the unique identifier and the shared key; transmitting, using the first device, the signature and the unique identifier to the trusted third party; verifying, using the trusted third party, the unique identifier based on the signature; determining, using the trusted third party, the shared key when the unique identifier is verified; and transmitting, using the trusted third party, the shared key to the second device to enable the first device and the second device to communicate securely by encoding and decoding communicated data using the shared key.. ... Micron Technology Inc

04/07/16 / #20160099354

Recessed transistors containing ferroelectric material

Some embodiments include transistor constructions having a first insulative structure lining a recess within a base. A first conductive structure lines an interior of the first insulative structure, and a ferroelectric structure lines an interior of the first conductive structure. ... Micron Technology Inc

04/07/16 / #20160099323

Semiconductor structures and methods of fabrication of same

Methods of fabricating a semiconductor structure comprise forming an opening through a stack of alternating tier dielectric materials and tier control gate materials, and laterally removing a portion of each of the tier control gate materials to form control gate recesses. A charge blocking material comprising a charge trapping portion is formed on exposed surfaces of the tier dielectric materials and tier control gate materials in the opening. ... Micron Technology Inc

04/07/16 / #20160099305

Integrated circuitry and methods of forming transistors

Some embodiments include integrated circuits having first and second transistors. The first transistor is wider than the second transistor. ... Micron Technology Inc

04/07/16 / #20160099252

Memory having a continuous channel

The present disclosure includes memory having a continuous channel, and methods of processing the same. A number of embodiments include forming a vertical stack having memory cells connected in series between a source select gate and a drain select gate, wherein forming the vertical stack includes forming a continuous channel for the source select gate, the memory cells, and the drain select gate, and removing a portion of the continuous channel for the drain select gate such that the continuous channel is thinner for the drain select gate than for the memory cells and the source select gate.. ... Micron Technology Inc

04/07/16 / #20160099237

Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods

Microelectronic die packages, stacked systems of die packages, and methods of manufacturing them are disclosed herein. In one embodiment, a system of stacked packages includes a first die package having a bottom side, a first dielectric casing, and first metal leads; a second die package having a top side attached to the bottom side of the first package, a dielectric casing with a lateral side, and second metal leads aligned with and projecting towards the first metal leads and including an exterior surface and an interior surface region that generally faces the lateral side; and metal solder connectors coupling individual first leads to individual second leads. ... Micron Technology Inc

04/07/16 / #20160099048

Threshold voltage distribution determination

Apparatuses and methods for threshold voltage (vt) distribution determination are described. A number of apparatuses can include sense circuitry configured to determine a first current on a source line of an array of memory cells, the first current corresponding to a first quantity of memory cells of a group of memory cells that conducts in response to a first sensing voltage applied to an access line and determine a second current on the source line, the second current corresponding to a second quantity of memory cells of the group that conducts in response to a second sensing voltage applied to the access line. ... Micron Technology Inc

04/07/16 / #20160098223

Controller to manage nand memories

A single virtualized ecc nand controller executes an ecc algorithm and manages a stack of nand flash memories. The virtualized ecc nand controller allows the host processor to drive the stack of flash memory devices as a single nand chip while the controller redirects the data to the selected nand memory device in the stack.. ... Micron Technology Inc

04/07/16 / #20160098209

Multidimensional contiguous memory allocation

The present disclosure is related to multidimensional contiguous memory allocation. Multidimensional contiguous memory allocation can include receiving an allocation request for an amount of memory that is contiguous in a multiple dimensions of the memory and determining whether the memory includes a region corresponding to the requested amount that is a candidate as being unallocated based on information indicating a maximum number of contiguous unallocated allocable portions of the memory. ... Micron Technology Inc

04/07/16 / #20160098208

Computing reduction and prefix sum operations in memory

The present disclosure includes apparatuses and methods for computing reduction and prefix sum operations in memory. A number of embodiments include processing circuitry configured to compute a reduction operation on data stored in a group of memory cells by splitting the data into a plurality of elements, copying each of the plurality of elements into elements that are wider than before being copied, and performing a logical operation associated with the reduction operation on each of the copied elements.. ... Micron Technology Inc

03/31/16 / #20160094247

Progressive effort decoder architecture

A memory device may include memory components to store data. The memory device may also include a processor that may decode a codeword associated with the data. ... Micron Technology Inc

03/31/16 / #20160093803

Memory cells and methods of forming memory cells

Some embodiments include a memory cell that has an electrode, a switching material over the electrode, a buffer region over the switching material, and an ion reservoir material over the buffer region. The buffer region includes one or more elements from group 14 of the periodic table in combination with one or more chalcogen elements. ... Micron Technology Inc

03/31/16 / #20160093709

Transistor-containing constructions and memory arrays

Some embodiments include transistor-containing constructions having gate material within an opening in a semiconductor material and spaced from the semiconductor material by gate dielectric material. The opening has a wide lower region beneath a narrow upper region. ... Micron Technology Inc

03/31/16 / #20160093708

Methods of forming memory cells

Memory cells having conductive nanodots between a charge storage material and a control gate are useful in non-volatile memory devices and electronic systems.. . ... Micron Technology Inc

03/31/16 / #20160093694

Methods and apparatuses including an active area of a tap intersected by a boundary of a well

Apparatuses and methods are disclosed. One such apparatus includes a well having a first type of conductivity formed within a semiconductor structure having a second type of conductivity. ... Micron Technology Inc

03/31/16 / #20160093583

Bond pad with micro-protrusions for direct metallic bonding

A bond pad with micro-protrusions for direct metallic bonding. In one embodiment, a semiconductor device comprises a semiconductor substrate, a through-silicon via (tsv) extending through the semiconductor substrate, and a copper pad electrically connected to the tsv and having a coupling side. ... Micron Technology Inc

03/31/16 / #20160093484

Methods of forming and using materials containing silicon and nitrogen

Some embodiments include methods utilizing atomic layer deposition to form material containing silicon and nitrogen (e.g., silicon nitride). The atomic layer deposition uses sii4 as one precursor and uses a nitrogen-containing material as another precursor. ... Micron Technology Inc

03/31/16 / #20160093348

Devices, methods, and systems supporting on unit termination

The present disclosure includes devices, methods, and systems supporting on unit termination. A number of embodiments include a number of memory units, wherein a memory unit includes termination circuitry, and a memory unit does not include termination circuitry.. ... Micron Technology Inc

03/24/16 / #20160088250

Pixel array with shared pixels in a single column and associated devices, systems, and methods

Pixel array with shared pixels in a single column and associated devices, systems, and methods are disclosed herein. In one embodiment, a pixel array includes a floating diffusion region, a source a source follower transistor having a gate coupled to the floating diffusion region, a plurality of first pixels associated with a first color, and a plurality of second pixels associated with a second color different than the first color and arranged in a single column with the first pixels. ... Micron Technology Inc

03/24/16 / #20160087204

Devices containing metal chalcogenides

Some embodiments include a device having a conductive material, a metal chalcogenide-containing material, and a region between the metal chalcogenide-containing material and the conductive material. The region contains a composition having a bandgap of at least about 3.5 electronvolts and a dielectric constant within a range of from about 1.8 to 25. ... Micron Technology Inc

03/24/16 / #20160087200

Memory including a selector switch on a variable resistance memory cell

Embodiments include but are not limited to apparatuses and systems including memory having a memory cell including a variable resistance memory layer, and a selector switch in direct contact with the memory cell, and configured to facilitate access to the memory cell. Other embodiments may be described and claimed.. ... Micron Technology Inc

03/24/16 / #20160087152

Epitaxial formation support structures and associated methods

Epitaxial formation support structures and associated methods of manufacturing epitaxial formation support structures and solid state lighting devices are disclosed herein. In several embodiments, a method of manufacturing an epitaxial formation support substrate can include forming an uncured support substrate that has a first side, a second side opposite the first side, and coefficient of thermal expansion substantially similar to n-type gallium nitride. ... Micron Technology Inc

03/24/16 / #20160087144

Solid state lighting devices without converter materials and associated methods of manufacturing

Solid state lighting devices that can produce white light without a phosphor are disclosed herein. In one embodiment, a solid state lighting device includes a first semiconductor material, a second semiconductor material spaced apart from the first semiconductor material, and an active region between the first and second semiconductor materials. ... Micron Technology Inc

03/24/16 / #20160087071

Methods of forming diodes

Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is deposited along an undulating topography that extends across the pedestal and base, and a second electrode is formed over the least one layer. ... Micron Technology Inc

03/24/16 / #20160087010

Semiconductor constructions, and methods of forming cross-point memory arrays

Some embodiments include vertical stacks of memory units, with individual memory units each having a memory element, a wordline, a bitline and at least one diode. The memory units may correspond to cross-point memory, and the diodes may correspond to band-gap engineered diodes containing two or more dielectric layers sandwiched between metal layers. ... Micron Technology Inc

03/24/16 / #20160087007

Diode/superionic conductor/polymer memory structure

A conjugated polymer layer with a built-in diode is formed by providing a first metal-chalcogenide layer over a bottom electrode. Subsequently, a second metal-chalcogenide layer is provided over and in contact with the first metal-chalcogenide layer. ... Micron Technology Inc

03/24/16 / #20160086955

Semiconductor device having a memory cell and method of forming the same

There is provided an apparatus includes a substrate having a main surface, a wordline buried in the substrate and a bitline buried in a shallower area than the wordline in the substrate.. . ... Micron Technology Inc

03/24/16 / #20160086926

Pass-through interconnect structure for microelectronic dies and associated systems and methods

Pass-through interconnect structures for microelectronic dies and associated systems and methods are disclosed herein. In one embodiment, a microelectronic die assembly includes a support substrate, a first microelectronic die positioned at least partially over the support substrate, and a second microelectronic die positioned at least partially over the first die. ... Micron Technology Inc

03/24/16 / #20160086910

Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices

Microelectronic devices and method of forming a plurality of microelectronic devices on a semiconductor workpiece are disclosed herein. One such method includes placing a plurality of first interconnect elements on a side of a semiconductor workpiece, forming a layer on the side of the workpiece, reshaping the first interconnect elements by heating the first interconnect elements, and coupling a first portion of a plurality of individual second interconnect elements to corresponding first interconnect elements with a second portion of the individual second interconnect elements exposed.. ... Micron Technology Inc

03/24/16 / #20160086672

Access line management in a memory device

Memory devices and methods are disclosed, such as devices configured to store a number of access line biasing patterns to be applied during a memory device operation performed on a particular row of memory cells in the memory device. Memory devices are further configured to support modification of the stored bias patterns, providing flexibility in biasing access lines through changes to the bias patterns stored in the memory device. ... Micron Technology Inc

03/24/16 / #20160086666

Memory array with power-efficient read architecture

Various embodiments comprise apparatuses and methods including a three-dimensional memory apparatus having upper strings and lower strings. The upper strings can include a first string of memory cells and a second string of memory cells arranged substantially parallel and adjacent to one another. ... Micron Technology Inc

03/24/16 / #20160086664

Resistive memory devices

Electronic apparatus, systems, and methods can include a resistive memory cell having a structured as an operably variable resistance region between two electrodes and a metallic barrier disposed in a region between the dielectric and one of the two electrodes. The metallic barrier can have a structure and a material composition to provide oxygen diffusivity above a first threshold during program or erase operations of the resistive memory cell and oxygen diffusivity below a second threshold during a retention state of the resistive memory cell. ... Micron Technology Inc

03/24/16 / #20160086662

Timing violation handling in a synchronous interface memory

A memory device includes an operation having a phase to provide an upper row address from a row address buffer, a phase to combine the upper row address with a lower row address to select data for a row data buffer, and a phase to output the data from the row data buffer, wherein an activate command starts and following activate commands are ignored until a preset time has elapsed.. . ... Micron Technology Inc

03/24/16 / #20160086641

Sequential memory operation without deactivating access line signals

Some embodiments include apparatuses and methods for activating a signal associated with an access line coupled to different groups of memory cells during a memory operation of a device, and for sensing data lines of the device during different time intervals of the memory operation to determine the value of information stored in the memory cells. Each of the data lines can be coupled to a respective memory cell of each of the groups of memory cells. ... Micron Technology Inc

03/24/16 / #20160086639

Apparatus power control

The present disclosure includes apparatuses and methods for apparatus power control. A number of embodiments include determining a power profile for each of a number of commands in a command queue that are ready for execution and selecting a portion of the number of commands in the command queue for execution based on the power profiles of the number of commands to control power consumption in the apparatus.. ... Micron Technology Inc

03/24/16 / #20160085625

Self-accumulating exclusive or program

Methods and apparatus for exclusive or (xor) programming of a memory device are described. A program internal to a device calculates parity or other values using an xor program rule. ... Micron Technology Inc

03/24/16 / #20160085599

Efficient operations of components in a wireless communications device

Various embodiments comprise apparatuses and methods including a communications subsystem having an interface module and a protocol module with the communications subsystem being configured to be coupled to an antenna. An applications subsystem includes a software applications module and an abstraction module. ... Micron Technology Inc

03/24/16 / #20160085476

Multi-partitioning of memories

Various embodiments comprise devices to manage multiple memory types and reconfigure partitions in a memory device as directed by a host. In one embodiment, the apparatus is to manage commands through a first interface controller to mapped portions of a first memory not having an attribute enhanced set, and map portions of a second memory having the attribute enhanced set through a second interface controller. ... Micron Technology Inc

03/24/16 / #20160085474

Data deduplication

The present disclosure includes devices and methods for data deduplication. One such method includes receiving a write command, transforming data associated with the write command, determining if a transformation value of the data exists in a transformation table, and responsive to a determination that the transformation value does not exist in the transformation table, writing the data associated with the write command to a memory device.. ... Micron Technology Inc

03/24/16 / #20160085260

Apparatuses and methods for providing clock signals

Apparatuses and methods for providing clock signals are described herein. An example apparatus may include a clock generator circuit. ... Micron Technology Inc

03/24/16 / #20160085153

Methods of forming photonic device structures, and related methods of forming electronic devices

A method of forming a photonic device structure comprises forming a photoresist over a photonic material over a substrate. The photoresist is exposed to radiation through a gray-tone mask to form at least one photoexposed region and at least one non-photoexposed region of the photoresist. ... Micron Technology Inc

03/24/16 / #20160084905

Apparatus for testing stacked die assemblies, and related methods

Apparatus for testing semiconductor devices comprising die stacks, the apparatus comprising a substrate having an array of pockets in a surface thereof arranged to correspond to conductive elements protruding from a semiconductor device to be tested. The pockets include conductive contacts with traces extending to conductive pads, which may be configured as test pads, jumper pads, edge connects or contact pads. ... Micron Technology Inc

03/17/16 / #20160080480

Adaptive communication interface

Embodiments of the invention include a communication interface and protocol for allowing communication between devices, circuits, integrated circuits and similar electronic components having different communication capacities or clock domains. The interface supports communication between any components having any difference in capacity and over any distance. ... Micron Technology Inc

03/17/16 / #20160080170

Computerized apparatus with a high speed data bus

A computerized apparatus configured for high-speed data transactions between components thereof in one embodiment, the computerized apparatus includes a high-speed data bus apparatus; a user interface apparatus in data communication with the high-speed data bus apparatus configured to enable a user to interact with the computerized apparatus; an input/output apparatus in data communication with the high-speed data bus apparatus and configured to interchange data with one or more devices external to the computerized apparatus; a mass storage apparatus in data communication with the high-speed data bus apparatus and configured to store data; a computer program for use by the high-speed data bus apparatus; and a substantially unified data interface in data communication with each of the user interface apparatus, the input/output apparatus, the mass storage apparatus, and the high-speed data bus apparatus.. . ... Micron Technology Inc

03/17/16 / #20160079531

Resistance variable memory device with nanoparticle electrode and method of fabrication

A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a nanoparticle is provided between an electrode and a chalcogenide glass region. The method of forming the nanoparticle utilizes a template over the electrode or random deposition of the nanoparticle.. ... Micron Technology Inc

03/17/16 / #20160079274

Transistors, semiconductor constructions, and methods of forming semiconductor constructions

Some embodiments include a transistor having a first electrically conductive gate portion along a first segment of a channel region and a second electrically conductive gate portion along a second segment of the channel region. The second electrically conductive gate portion is a different composition than the first electrically conductive gate portion. ... Micron Technology Inc

03/17/16 / #20160079094

Methods of protecting peripheries of in-process semiconductor wafers and related in-process wafers and systems

Methods of processing semiconductor wafers may involve, for example, encapsulating an active surface and each side surface of a wafer of semiconductor material, a plurality of semiconductor devices located on the active surface of the wafer, an exposed side surface of an adhesive material located on a back side surface of the wafer, and at least a portion of a side surface of a carrier substrate secured to the wafer by the adhesive material in an encapsulation material. At least a portion of the side surface of the adhesive material may be exposed by removing at least a portion of the encapsulation material. ... Micron Technology Inc

03/17/16 / #20160078936

Variable resistance memory with lattice array using enclosing transistors

A variable resistance memory array, programming a variable resistance memory element and methods of forming the array. A variable resistance memory array is formed with a plurality of word line transistors surrounding each phase change memory element. ... Micron Technology Inc

03/17/16 / #20160078917

Thyristors, methods of programming thyristors, and methods of forming thyristors

Some embodiments include thyristors having first and second electrode regions, first and second base regions, and material having a bandgap of at least 1.2 ev in at least one of the regions. The first base region is between the first electrode region and the second base region, and the second base region is between the second electrode region and the first base region. ... Micron Technology Inc

03/17/16 / #20160078912

Stt-mram cell structure incorporating piezoelectric stress material

A magnetic memory cell including a piezoelectric material, and methods of operating the memory cell are provided. The memory cell includes a stack, and the piezoelectric material may be formed as a layer in the stack or adjacent the layers of the cell stack. ... Micron Technology Inc

03/17/16 / #20160078911

Semiconductor memory device having count value control circuit

A device includes a data storing cell array including a plurality of groups of data storing cells each configured to be accessed responsive to the input of the corresponding one of the row addresses and a count value control circuit coupled to each of the groups of the data storing cells. The count value control circuit is configured to update a count value stored in each of the groups of data storing cells by a first value responsive to the input of the corresponding one of the row addresses in a first operation mode and to set the count value stored in each of the groups of the data storing cells to a second value responsive to the input of the corresponding one of the row addresses in a second operation mode.. ... Micron Technology Inc

03/17/16 / #20160078909

Output buffer circuit with low sub-threshold leakage current

A device includes a cutting circuit that is coupled between power supply lines in series with first and second output circuits which drive an output terminal in a push-pull manner. Each of the first and second output circuits includes a plurality of output transistors. ... Micron Technology Inc

03/17/16 / #20160077560

Power delivery circuitry

Embodiments of the present disclosure are directed to systems and methods for a memory device comprising a memory system and power delivery circuitry comprising an energy storage, wherein the power delivery circuitry is configured to simultaneously deliver a first power from the energy storage and a second power from an external power supply coupled to the memory device.. . ... Micron Technology Inc

03/17/16 / #20160077521

Photolithography systems and associated methods of overlay error correction

Several embodiments of photolithography systems and associated methods of overlay error correction are disclosed herein. In one embodiment, a method for correcting overlay errors in a photolithography system includes measuring a plurality of first overlay errors that individually correspond to a microelectronic substrate in a first batch of microelectronic substrates. ... Micron Technology Inc

03/10/16 / #20160072044

Multi-bit ferroelectric memory device and methods of forming the same

Multi-bit ferroelectric memory devices and methods of forming the same are provided. One example method of forming a multi-bit ferroelectric memory device can include forming a first ferroelectric material on a first side of a via, removing a material to expose a second side of the via, and forming second ferroelectric material on the second side of the via at a different thickness compared to the first side of the via.. ... Micron Technology Inc

03/10/16 / #20160072016

Solid-state light emitters having substrates with thermal and electrical conductivity enhancements and method of manufacture

Solid-state lighting devices (sslds) including a carrier substrate with conductors and methods of manufacturing sslds. The conductors can provide (a) improved thermal conductivity between a solid-state light emitter (ssle) and a package substrate and (b) improved electrical conductivity for the ssle. ... Micron Technology Inc

03/10/16 / #20160071880

Three-dimensional structured memory devices

A 3d structured nonvolatile semiconductor memory devices and methods for manufacturing are disclosed. One such device includes an n+ region at a source/drain region; a p+ region at the source/drain region; and a diffusion barrier material between the n+ region and the p+ region. ... Micron Technology Inc

03/10/16 / #20160071878

Methods of forming semiconductor constructions

Some embodiments include a semiconductor construction having a stack containing alternating levels of control gate material and intervening dielectric material. A channel material panel extends through the stack and along a first direction. ... Micron Technology Inc

03/10/16 / #20160071842

Transistors having one or more dummy lines with different collective widths coupled thereto

In an embodiment, an array of transistors has a first line coupled to a first transistor. The first line extends over a second transistor that is successively adjacent to the first transistor and over a third transistor that is successively adjacent to the second transistor. ... Micron Technology Inc

03/10/16 / #20160071775

Cmos fabrication

A method of manufacturing a memory device includes an nmos region and a pmos region in a substrate. A first gate is defined within the nmos region, and a second gate is defined in the pmos region. ... Micron Technology Inc

03/10/16 / #20160071619

Methods and apparatus for providing redundancy in memory

Methods for providing redundancy in a memory include mapping a portion of first data associated with an address of the memory determined to indicate a defective memory cell to an address of a redundant area of the memory array, and writing second data to the memory array, wherein a portion of the second data is written to a column of the memory array associated with the address of the memory determined to indicate a defective memory cell for the first data. Apparatus include memory control circuitry configured to select a portion of data for mapping to a different address in response to an address indicating a defective memory cell, and further configured to select a different portion of data for a particular row than for a different row, wherein the particular row and the different row are associated with the same columns of the memory array.. ... Micron Technology Inc

03/10/16 / #20160071618

Determining soft data from a hard read

Apparatuses and methods involving the determination of soft data from hard reads are provided. One example method can include determining, using a hard read, a state of a memory cell. ... Micron Technology Inc

03/10/16 / #20160071605

Concurrently reading first and second pages of memory cells having different page addresses

In an embodiment, a first page of memory cells in a first memory plane is read concurrently with a second page of memory cells in a second memory plane. The second memory plane is different than the first memory plane, but is in the same memory array as the first memory plane. ... Micron Technology Inc

03/10/16 / #20160071584

Operational signals generated from capacitive stored charge

Methods, a memory device, and a system are disclosed. One such method includes applying a select pulse to a snapback device of a memory cell. ... Micron Technology Inc

03/10/16 / #20160071556

Apparatuses including a memory array with separate global read and write lines and/or sense amplifier region column select line and related methods

Apparatuses and methods related to memory arrays with separate global read and write lines and/or sense amplifier region column select lines are disclosed. An example apparatus includes first and second memory sections, and further includes a sense amplifier region. ... Micron Technology Inc

03/10/16 / #20160070663

Sequential memory access operations

Methods of operating a memory include performing a memory access operation, obtaining an address corresponding to a subsequent memory access operation prior to stopping the memory access operation, stopping the memory access operation, sharing charge between access lines used for the memory access operation and access lines to be used for the subsequent memory access operation, and performing the subsequent memory access operation.. . ... Micron Technology Inc

03/10/16 / #20160070508

Memory system data management

The present disclosure includes apparatuses and methods for memory system data management. A number of embodiments include writing data from a host to a buffer in the memory system, receiving, at the buffer, a notification from a memory device in the memory system that the memory device is ready to receive data, sending at least a portion of the data from the buffer to the memory device, and writing the portion of the data to the memory device.. ... Micron Technology Inc

03/10/16 / #20160070504

Apparatuses and methods for a memory die architecture including an interface memory

Apparatuses and methods for reducing capacitance on a data bus are disclosed herein. In accordance with one or more described embodiments, an apparatus may comprise a plurality of memories coupled to an internal data bus and a command and address bus, each of the memories configured to receive a command on the command and address bus. ... Micron Technology Inc

03/10/16 / #20160070476

Operation management in a memory device

Methods of operating a memory device include performing a first memory operation having an associated timing requirement; after completing the first memory operation, determining whether a timing margin between completion of the first memory operation and expiration of its associated timing requirement exceeds a length of time to perform a particular portion of a second memory operation; and performing the particular portion of the second memory operation between completion of the first memory operation and the expiration of its associated timing requirement if it is determined that the timing margin between completion of the first memory operation and expiration of its associated timing requirement exceeds the length of time to perform the particular portion of the second memory operation.. . ... Micron Technology Inc

03/03/16 / #20160065868

Anti-eclipse circuitry with tracking of floating diffusion reset level

Imagers and associated devices and systems are disclosed herein. In one embodiment, an imager includes a pixel array and control circuitry operably coupled to the pixel array. ... Micron Technology Inc

03/03/16 / #20160064666

Memory cells including dielectric materials, memory devices including the memory cells, and methods of forming same

A memory cell comprising a threshold switching material over a first electrode on a substrate. The memory cell includes a second electrode over the threshold switching material and at least one dielectric material between the threshold switching material and at least one of the first electrode and the second electrode. ... Micron Technology Inc

03/03/16 / #20160064658

Integrated memory and methods of forming repeating structures

Some embodiments include integrated memory having an array of repeating plates across a plurality of nodes. The array includes rows and columns. ... Micron Technology Inc

03/03/16 / #20160064655

Semiconductor device structures including ferroelectric memory cells

A method of forming a ferroelectric memory cell. The method comprises forming an electrode material exhibiting a desired dominant crystallographic orientation. ... Micron Technology Inc

03/03/16 / #20160064480

Semiconductor constructions, memory arrays and electronic systems

The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. ... Micron Technology Inc

03/03/16 / #20160064366

Semiconductor memory device including output buffer

A semiconductor module includes a module substrate, a line pattern provided to the module substrate, first and second semiconductor chips on the module substrate and coupled to the line pattern, and a termination resister on the module substrate and coupled to the line pattern, the termination resistor being located between the first and second semiconductor chips.. . ... Micron Technology Inc

03/03/16 / #20160064358

Semiconductor device including semiconductor chips stacked over substrate

According to the present invention, a semiconductor device includes a substrate including a first surface and a second surface opposite to the first surface, a first layer formed over the first surface, a second layer thicker than the first layer formed over the first portion of the first layer, the first and second layers being formed of a same material, a first semiconductor chip mounted over a second portion of the first layer; and a second semiconductor chip commonly mounted over the first semiconductor chip and the second layer.. . ... Micron Technology Inc

03/03/16 / #20160064094

Nonconsecutive sensing of multilevel memory cells

Apparatuses and methods for nonconsecutive sensing of multilevel memory cells include methods of sensing a unit of information from a multilevel memory cell (mlc) using a sensing signal. The unit of information can correspond to a page of information. ... Micron Technology Inc

03/03/16 / #20160064085

Memory device having a different source line coupled to each of a plurality of layers of memory cell arrays

A sensing voltage may be applied to a particular memory cell that is in a particular layer of a plurality of layers of memory cells. While the sensing voltage is applied to the particular memory cell, a source voltage may be applied to an end of a string of memory cells that includes the particular memory cell. ... Micron Technology Inc

03/03/16 / #20160064078

Systems, methods and devices for programming a multilevel resistive memory cell

Embodiments disclosed herein may relate to programming a multi-level memory cell with programming pulse sequences that comprise forward-biased and reverse-biased programming pulses.. . ... Micron Technology Inc

03/03/16 / #20160064065

Apparatuses and methods for multi-memory array accesses

Methods and apparatuses are disclosed for multi-memory array access. One example apparatus includes a pair of input/output lines, and a first array coupled to the pair of input/output lines. ... Micron Technology Inc

03/03/16 / #20160064052

Single node power management for multiple memory devices

Some embodiments include apparatuses and methods having a node to couple to a plurality of memory devices, memory cells, and a module to perform an operation on the memory cells, to cause at least one change in a level of a signal at the node in order to make a request to perform a particular stage of the operation such that the request is detectable by the memory devices, and to perform the particular stage of the operation after the request is acknowledged. Other embodiments are described.. ... Micron Technology Inc

03/03/16 / #20160064048

Asynchronous/synchronous interface

The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. ... Micron Technology Inc

03/03/16 / #20160064047

Comparison operations in memory

The present disclosure includes apparatuses and methods related to performing comparison operations in memory. An example apparatus can include a first group of memory cells coupled to a first access line and configured to store a plurality of first elements, and a second group of memory cells coupled to a second access line and configured to store a plurality of second elements. ... Micron Technology Inc

03/03/16 / #20160064045

Apparatuses and methods for storing a data value in multiple columns

An example apparatus comprises an array of memory cells coupled to sensing circuitry. The apparatus can include a control component configured to cause computing of a data value equal to a logical or between the digit of a mask and a data value stored in a memory cell located in a row at a column of the array corresponding to a digit of a vector stored in the array. ... Micron Technology Inc

03/03/16 / #20160063284

Multiplication operations in memory

Examples of the present disclosure provide apparatuses and methods for performing multi-variable bit-length multiplication operations in a memory. An example method comprises performing a multiplication operation on a first vector and a second vector. ... Micron Technology Inc

03/03/16 / #20160062909

Systems and methods for accessing memory

Methods of mapping memory cells to applications, methods of accessing memory cells, systems, and memory controllers are described. In some embodiments, a memory system including multiple physical channels is mapped into regions, such that any region spans each physical channel of the memory system. ... Micron Technology Inc

03/03/16 / #20160062831

Error correction code for unidirectional memory

A memory array and a method of writing to a unidirectional non-volatile storage cell are disclosed whereby a user data word is transformed to an internal data word and written to one or more unidirectional data storage cells according to a cell coding scheme. A check word may be generated that corresponds to the internal data word. ... Micron Technology Inc

03/03/16 / #20160062826

Lee metric error correcting code

A memory device may include memory components for storing data. The memory device may also include a controller that determines whether one or more errors exist in a data packet stored in the memory components. ... Micron Technology Inc

03/03/16 / #20160062733

Multiplication operations in memory

Examples of the present disclosure provide apparatuses and methods for performing multiplication operations in a memory. An example method comprises performing a multiplication operation on a first element stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array and a second element stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array. ... Micron Technology Inc

03/03/16 / #20160062695

Non-volatile memory with lpdram

Low power dram (lpdram) memory devices for communication with a non-volatile memory coupled to the lpdram memory device, and systems containing such lpdram and non-volatile memory facilitate configuring the lpdram memory device using routines stored on the non-volatile memory.. . ... Micron Technology Inc

03/03/16 / #20160062692

Apparatuses and methods for determining population count

The present disclosure includes apparatuses and methods related to determining population count. An example apparatus comprises an array of memory cells coupled to sensing circuitry. ... Micron Technology Inc

03/03/16 / #20160062683

Sub-sector wear leveling in memories

Methods of wear leveling in a memory, and memories configured to perform such methods, are useful in extending cycling endurance in memories. Such methods include transferring data from a first block of the memory to a second block of the memory, erasing the first block, transferring data from a third block of the memory to the first block, erasing the third block, transferring data from the second block to the third block, swapping logical addresses for the first block and the third block with each other, and erasing the second block. ... Micron Technology Inc

03/03/16 / #20160062673

Division operations in memory

Examples of the present disclosure provide apparatuses and methods related to performing division operations in memory. An example apparatus might include a first group of memory cells coupled to a first access line and configured to store a dividend element. ... Micron Technology Inc

03/03/16 / #20160062672

Swap operations in memory

Examples of the present disclosure provide apparatuses and methods related to performing swap operations in a memory. An example apparatus might include a first group of memory cells coupled to a first sense line and configured to store a first element. ... Micron Technology Inc

02/25/16 / #20160056375

Semiconductor constructions and methods of forming memory cells

Some embodiments include semiconductor constructions having stacks containing electrically conductive material over dielectric material. Programmable material structures are directly against both the electrically conductive material and the dielectric material along sidewall surfaces of the stacks. ... Micron Technology Inc

02/25/16 / #20160056208

Cross-point memory and methods for fabrication of same

The disclosed technology generally relates to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. Line stacks are formed, including a storage material line disposed over lower a conductive line. ... Micron Technology Inc

02/25/16 / #20160056175

Circuit structures, memory circuitry, and methods

A circuit structure includes a substrate having an array region and a peripheral region. The substrate in the array and peripheral regions includes insulator material over first semiconductor material, conductive material over the insulator material, and second semiconductor material over the conductive material. ... Micron Technology Inc

02/25/16 / #20160056073

Semiconductor constructions; and methods for providing electrically conductive material within openings

Some embodiments include methods for depositing copper-containing material utilizing physical vapor deposition of the copper-containing material while keeping a temperature of the deposited copper-containing material at greater than 100° c. Some embodiments include methods in which openings are lined with a metal-containing composition, copper-containing material is physical vapor deposited over the metal-containing composition while a temperature of the copper-containing material is no greater than about 0° c., and the copper-containing material is then annealed while the copper-containing material is at a temperature in a range of from about 180° c. ... Micron Technology Inc

02/25/16 / #20160056069

Methods of forming memory arrays

Some embodiments include methods of forming memory arrays. An assembly is formed which has an upper level over a lower level. ... Micron Technology Inc

02/25/16 / #20160056051

External gettering method and device

Disclosed embodiments include external gettering provided by electronic packaging. An external gettering element for a semiconductor substrate, which may be incorporated as part of an electronic packaging for the structure, is disclosed. ... Micron Technology Inc

02/25/16 / #20160056038

Constructions comprising rutile-type titanium oxide; and methods of forming and utilizing rutile-type titanium oxide

Some embodiments include methods of forming rutile-type titanium oxide. A monolayer of titanium nitride may be formed. ... Micron Technology Inc

02/25/16 / #20160055973

Methods of forming capacitors

A method of forming capacitors includes providing first capacitor electrodes within support material. The first capacitor electrodes contain tin and the support material contains polysilicon. ... Micron Technology Inc

02/25/16 / #20160055103

Apparatus, electronic devices and methods associated with an operative transition from a first interface to a second interface

Subject matter disclosed herein relates to an apparatus comprising memory and a controller, such as a controller which determines block locking states in association with operative transitions between two or more interfaces that share at least one block of memory. The apparatus may support single channel or multi-channel memory access, write protection state logic, or various interface priority schemes.. ... Micron Technology Inc

02/18/16 / #20160049565

Vertical solid-state transducers having backside terminals and associated systems and methods

Vertical solid-state transducers (“ssts”) having backside contacts are disclosed herein. An sst in accordance with a particular embodiment can include a transducer structure having a first semiconductor material at a first side of the sst, a second semiconductor material at a second side of the sst opposite the first side, and an active region between the first and second semiconductor materials. ... Micron Technology Inc

02/18/16 / #20160049549

Solid state lighting devices with selected thermal expansion and/or surface characteristics, and associated methods

Solid state lighting devices with selected thermal expansion and/or surface characteristics, and associated methods are disclosed. A method in accordance with a particular embodiment includes forming an ssl (solid state lighting) formation structure having a formation structure coefficient of thermal expansion (cte), selecting a first material of an interlayer structure to have a first material cte greater than the substrate cte, and selecting a second material of the interlayer structure based at least in part on the second material having a second material cte less than the first material cte. ... Micron Technology Inc

02/18/16 / #20160049417

Floating gate memory cells in vertical memory

Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. ... Micron Technology Inc

02/18/16 / #20160049406

Semiconductor devices and systems including memory cells and related methods of fabrication

A memory cell is disclosed. The memory cell includes a transistor and a capacitor. ... Micron Technology Inc

02/18/16 / #20160049404

Array of gated devices and methods of forming an array of gated devices

An array of gated devices includes a plurality of gated devices arranged in rows and columns and individually including an elevationally inner region, a mid region elevationally outward of the inner region, and an elevationally outer region elevationally outward of the mid region. A plurality of access lines are individually laterally proximate the mid regions along individual of the rows. ... Micron Technology Inc

02/18/16 / #20160049387

High voltage solid-state transducers and solid-state transducer arrays having electrical cross-connections and associated systems and methods

Solid-state transducer (“sst”) dies and sst arrays having electrical cross-connections are disclosed herein. An array of sst dies in accordance with a particular embodiment can include a first terminal, a second terminal and a plurality of sst dies coupled between the first and second terminals with at least a pair of the sst dies being coupled in parallel. ... Micron Technology Inc

02/18/16 / #20160049194

Appartuses and methods for sensing using an integration component

The present disclosure includes apparatuses and methods for sensing a resistance variable memory cell. A number of embodiments include circuitry to provide a programming signal to a memory cell in the array, the programming signal associated with programming the memory cell to a particular data state; and determine, via an integration component, if a data state of the memory cell changes to a different data state responsive to the programming signal being provided.. ... Micron Technology Inc

02/18/16 / #20160049180

Semiconductor device including input/output circuit

Disclosed here is an apparatus that comprises a data terminal, a data output circuit including a plurality of output buffers coupled in common to the data terminal, and an impedance control circuit coupled to the data output circuit, wherein the impedance control circuit is configured to generate first impedance code and second impedance code different from the first impedance code and to apply a selected one of the first impedance code and the second impedance code to at least one of the output buffers.. . ... Micron Technology Inc

02/18/16 / #20160048343

Apparatuses and methods for concurrently accessing different memory planes of a memory

Apparatuses and methods for performing concurrent memory access operations for different memory planes are disclosed herein. An example apparatus may include a memory array having a plurality of memory planes. ... Micron Technology Inc

02/18/16 / #20160048338

Memory block quality identification in a memory

Methods of operating electronic systems having a memory include reading indications of memory block quality from a plurality of memory blocks of the memory in which a memory defect has been detected, wherein a value of the indication of memory block quality stored in a respective memory block of the plurality of memory blocks indicates a type of memory defect detected in the respective memory block, and, in response to the values of the indications of memory block quality, deeming a first portion of memory blocks of the plurality of memory blocks as usable, allocating a second portion of memory blocks of the plurality of memory blocks for storing only data of a particular type, and indicating a third portion of memory blocks of the plurality of memory blocks as defective.. . ... Micron Technology Inc

02/18/16 / #20160048074

Methods of forming patterns for semiconductor device structures

Methods of forming a pattern in a semiconductor device structure include deprotecting an outer portion of a first photosensitive resist material, forming a second photosensitive resist material, exposing portions of the first and second photosensitive resist materials to radiation, and removing the deprotected outer portion of the first photosensitive resist material and the exposed portions of the first and second photosensitive resist materials. Additional methods include forming a first resist material over a substrate to include a first portion and a relatively thicker second portion, deprotecting substantially the entire first portion and an outer portion of the second portion while leaving an inner portion of the second portion protected, and forming a second resist material over the substrate. ... Micron Technology Inc

02/11/16 / #20160043885

Multi-level signaling

Apparatus are disclosed, such as those involving a transmitter circuit that is configured to generate multi-level signals based on a plurality of data digits. One such transmitter circuit includes a signal output and an encoder configured to provide control signals based at least partially on the plurality of data digits. ... Micron Technology Inc

02/11/16 / #20160043089

Memory cell support lattice

Memory cell support lattices and methods of forming the same are described herein. As an example, a method of forming a memory cell support lattice includes forming a mask on a number of capacitor elements in an array, such that a space between vertically and horizontally adjacent capacitor elements is fully covered and a space between diagonally adjacent capacitor elements is partially covered and forming a support lattice in a support material by etching the support material to remove portions of the support material below the openings in the mask.. ... Micron Technology Inc

02/11/16 / #20160042995

Interconnect structures for integrated circuits and their formation

An embodiment of an interconnect structure for an integrated circuit may include a first conductor coupled to circuitry, a second conductor, a dielectric between the first and second conductors, and a conductive underpass under and coupled to the first and second conductors and passing under the dielectric or a conductive overpass over and coupled to the first and second conductors and passing over the dielectric. The second conductor would be floating but for its coupling to the conductive underpass or the conductive overpass. ... Micron Technology Inc

02/11/16 / #20160042941

Self-assembled nanostructures including metal oxides, semiconductor structures comprising thereof, and methods of forming same

A self-assembled nanostructure comprises first domains and second domains. The first domains comprise a first block of a block copolymer material and an activatable catalyst. ... Micron Technology Inc

02/11/16 / #20160042799

Methods and apparatus for sensing a memory cell

Methods of operating a memory include selectively discharging a data line through a memory cell selected for sensing, discharging a sense node to the data line while a voltage level of the sense node is greater than a voltage level of the data line, and inhibiting discharging of the data line to the sense node while the voltage level of the data line is greater than the voltage level of the sense node. Sense circuits include a path between an input node and a sense node facilitating current flow from the sense node to the input node when a voltage level of the sense node is greater than a voltage level of the input node and inhibiting current flow from the input node to the sense node when the voltage level of the sense node is less than the voltage level of the input node.. ... Micron Technology Inc

02/11/16 / #20160042791

Methods and apparatuses including a string of memory cells having a first select transistor coupled to a second select transistor

Generally discussed herein are apparatuses and methods. One such apparatus includes a data line, a first memory cell and a first select transistor. ... Micron Technology Inc

02/11/16 / #20160042777

Data paths using a first signal to capture data and a second signal to output data and methods for providing data

Data paths, memories, and methods for providing data from memory are disclosed. An example read data path includes a delay path, and a clocked data register. ... Micron Technology Inc

02/11/16 / #20160041828

Method and system for generating object code to facilitate predictive memory retrieval

A method and system are described for generating reference tables in object code which specify the addresses of branches, routines called, and data references used by routines in the code. In a suitably equipped processing system, the reference tables can be passed to a memory management processor which can open the appropriate memory pages to expedite the retrieval of data referenced in the execution pipeline. ... Micron Technology Inc

02/11/16 / #20160041785

Control of page access in memory

The present techniques provide systems and methods of controlling access to more than one open page in a memory component, such as a memory bank. Several components may request access to the memory banks. ... Micron Technology Inc

02/11/16 / #20160041042

Semiconductor device including a temperature sensor circuit

A semiconductor device including a temperature sensor includes a pull up circuit, a pull down circuit, a first additional current path, and a second additional current path. The pull up circuit is configured to generate a pull up current that contributes to generation of a first output current. ... Micron Technology Inc

02/04/16 / #20160035977

Memory elements using self-aligned phase change material layers and methods of manufacturing same

A memory element and method of forming the same. The memory element includes a first electrode within a via in a first dielectric material. ... Micron Technology Inc

02/04/16 / #20160035974

Memory cells and methods of forming memory cells

Some embodiments include a memory cell having a first electrode, and an intermediate material over and directly against the first electrode. The intermediate material includes stabilizing species corresponding to one or both of carbon and boron. ... Micron Technology Inc

02/04/16 / #20160035791

Resistance variable memory cell structures and methods

Resistance variable memory cell structures and methods are described herein. A number of embodiments include a first resistance variable memory cell comprising a number of resistance variable materials in a super-lattice structure and a second resistance variable memory cell comprising the number of resistance variable materials in a homogeneous structure.. ... Micron Technology Inc

02/04/16 / #20160035681

Semiconductor device structures inlcuding a distributed bragg reflector

A method of forming a semiconductor device structure comprises forming at least one reflective structure comprising at least two dielectric materials having different refractive indices over at least one radiation-sensitive structure, the at least one reflective structure configured to substantially reflect therefrom radiation within a predetermined wavelength range and to substantially transmit therethrough radiation within a different predetermined wavelength range. Additional methods of forming a semiconductor device structure are described. ... Micron Technology Inc

02/04/16 / #20160035648

Semiconductor die assemblies with heat sink and associated systems and methods

Semiconductor die assemblies with heat sinks are disclosed herein. In one embodiment, a semiconductor die assembly includes a stack of semiconductor dies and a mold material surrounding at least a portion of the stack of semiconductor dies. ... Micron Technology Inc

02/04/16 / #20160035578

Method of forming a semiconductor device including a pitch multiplication

Disclosed herein is a manufacturing method of a semiconductor device that includes forming first and second layers over an underlying martial such that the first layer is between the underlying material and the second layer, forming a third layer over the second layer, forming first and second core portions apart from each other over the third layer, forming a gap portion between the first and the second core portions; and removing the second and the third layers by using the first and the second core portions and the gap portion as a mask to expose a part of the first layer.. . ... Micron Technology Inc

02/04/16 / #20160035436

Apparatuses and methods for operating a memory device

Subject matter described pertains to apparatuses and methods for operating a memory device.. . ... Micron Technology Inc

02/04/16 / #20160035418

Memory device architecture

Row electrode drivers and column electrode drivers for a memory device are distributed within a footprint share by a memory cell array.. . ... Micron Technology Inc

02/04/16 / #20160035406

Fixed voltage sensing in a memory device

Methods for sensing ferroelectric memory devices and apparatuses using the same have been disclosed. One such apparatus includes a ferroelectric memory cell coupled to a data line, a reference capacitance, and a common node coupled between the data line and the reference capacitance. ... Micron Technology Inc

02/04/16 / #20160034340

Apparatuses and methods for fixing a logic level of an internal signal line

An apparatus includes a first external terminal, a first circuit, a signal line and a second circuit, the first external terminal receives at least one of data mask information and data bus inversion information. The first circuit performs one of an error check operation and as data bus invasion operation. ... Micron Technology Inc

02/04/16 / #20160031707

Microelectronic devices and methods for manufacturing microelectronic devices

Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. In one embodiment, a method for manufacturing microelectronic devices includes forming a stand-off layer over a plurality of microelectronic dies on a microfeature workpiece, removing selected portions of the stand-off layer to form a plurality of stand-offs on corresponding dies, cutting the workpiece to singulate the dies, attaching a first singulated die to a support member, and coupling a second die to the stand-off on the first singulated die.. ... Micron Technology Inc

01/28/16 / #20160028002

Forming self-aligned conductive lines for resistive random access memories

Resistive random access memory elements, such as phase change memory elements, may be defined using a plurality of parallel conductive lines over a stack of layers, at least one of which includes a resistive switching material. The stack may be etched using the conductive lines as a mask. ... Micron Technology Inc

01/28/16 / #20160027957

Light emitting devices with built-in chromaticity conversion and methods of manufacturing

Various embodiments of light emitting devices with built-in chromaticity conversion and associated methods of manufacturing are described herein. In one embodiment, a method for manufacturing a light emitting device includes forming a first semiconductor material, an active region, and a second semiconductor material on a substrate material in sequence, the active region being configured to produce a first emission. ... Micron Technology Inc

01/28/16 / #20160027883

Methods of forming charge-trapping regions

Some embodiments include methods of forming charge-trapping zones. The methods may include forming nanoparticles, transferring the nanoparticles to a liquid to form a dispersion, forming an aerosol from the dispersion, and then directing the aerosol onto a substrate to form charge-trapping centers comprising the nanoparticles. ... Micron Technology Inc

01/28/16 / #20160027882

Semiconductor devices and structures

Methods of forming semiconductor devices, memory cells, and arrays of memory cells include forming a liner on a conductive material and exposing the liner to a radical oxidation process to densify the liner. The densified liner may protect the conductive material from substantial degradation or damage during a subsequent patterning process. ... Micron Technology Inc

01/28/16 / #20160027865

Memory devices including capacitor structures having improved area efficiency

Semiconductor structures including a plurality of conductive structures having a dielectric material therebetween are disclosed. The thickness of the dielectric material spacing apart the conductive structures may be adjusted to provide optimization of capacitance and voltage threshold. ... Micron Technology Inc

01/28/16 / #20160027863

Integrated circuitry, methods of forming capacitors, and methods of forming integrated circuitry comprising an array of capacitors and circuitry peripheral to the array

A method of forming capacitors includes providing a support material over a substrate. The support material is at least one of semiconductive or conductive. ... Micron Technology Inc

01/28/16 / #20160027793

Semiconductor devices including stair step structures, and related methods

Semiconductor devices, such as three-dimensional memory devices, include a memory array including a stack of conductive tiers and a stair step structure. The stair step structure is positioned between first and second portions of the memory array and includes contact regions for respective conductive tiers of the stack of conductive tiers. ... Micron Technology Inc

01/28/16 / #20160027748

Method of forming a memory device

A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication.. ... Micron Technology Inc

01/28/16 / #20160027706

Through-substrate via (tsv) testing

Various embodiments comprise apparatuses and methods for testing and repairing through-substrate vias in a stack of interconnected dice. In various embodiments, an apparatus is provided that includes a number of through-substrate vias to couple to one or more devices, at least one redundant through-substrate via to allow a repair of the apparatus, and a pair of pull-up devices coupled to the through-substrate vias and the redundant through-substrate via to provide a high-data value to the first end of the respective through-substrate vias. ... Micron Technology Inc

01/28/16 / #20160027701

Semiconductor device and method for manufacturing the same

A semiconductor device includes a first well and a second well provided within a semiconductor substrate, an isolation region disposed between the first well and the second well within the semiconductor substrate, a first wiring disposed on the first well, a second wiring disposed on the second well, a concave third wiring disposed on the isolation region, a buried insulating film disposed on the third wiring so as to fill the concave portion thereof, a plurality of fourth wirings disposed on the buried insulating film, and a contact plug disposed so as to electrically connect to at least one of the first and second wells.. . ... Micron Technology Inc

01/28/16 / #20160027642

Methods of forming capacitors

A method of forming a capacitor includes depositing a dielectric metal oxide layer of a first phase to a thickness no greater than 75 angstroms over an inner conductive capacitor electrode material. The first phase dielectric metal oxide layer has a k of at least 15. ... Micron Technology Inc

01/28/16 / #20160027531

Apparatuses and methods for targeted refreshing of memory

Apparatuses and methods for targeted row refreshes are disclosed herein. In an example apparatus, a predecoder receives a target row address and determines whether a target row of memory associated with the target row address is a primary or a redundant row of memory. ... Micron Technology Inc

01/28/16 / #20160027497

Apparatuses and methods for performing logical operations using sensing circuitry

The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. ... Micron Technology Inc

01/28/16 / #20160027486

Apparatuses and methods for providing strobe signals to memories

Apparatuses and methods for providing strobe signals to memories are described herein. An example apparatus may include a plurality of memories and a memory controller. ... Micron Technology Inc

01/28/16 / #20160026596

Systems, devices, and methods for selective communication through an electrical connector

Electrical systems and related methods are disclosed. An electrical system comprises an electronic device configured to communicate through an electrical connector using one of a plurality of different communication protocols responsive to receiving an indication of the one of the plurality of different communication protocols through the electrical connector from a another electronic device. ... Micron Technology Inc

01/28/16 / #20160026565

Apparatuses and methods for concurrently accessing different memory planes of a memory

Apparatuses and methods for concurrently accessing different memory planes are disclosed herein. An example apparatus may include a controller associated with a queue configured to maintain respective information associated with each of a plurality of memory command and address pairs. ... Micron Technology Inc

01/28/16 / #20160026564

Determining a location of a memory device in a solid state device

A solid state device has a controller. The controller is configured to perform a first division operation that divides a received logical block address that indicates a physical memory block in a memory device of a plurality of memory devices in the solid state device by a number of logical block addresses per page of the physical memory block to obtain a result of the first division operation, configured to perform a second division operation that divides the obtained result of the first division operation by a number of memory devices in the plurality of memory devices, and configured to determine a location of the memory device of the plurality of memory devices within the solid state device from a location in a memory device table, the location in the memory device table identified by a remainder of the second division operation.. ... Micron Technology Inc

01/28/16 / #20160026533

Apparatus including refresh controller controlling refresh operation responsive to data error

A device includes a plurality of memory cells, an error detection circuit configured to detect at least one memory cell storing error data and a refresh control circuit including a register configured to store an error address corresponding to the at least one memory cell storing error data. The refresh control circuit is configured to control a refresh cycle of the error address.. ... Micron Technology Inc

01/21/16 / #20160020356

Vertical solid-state transducers and high voltage solid-state transducers having buried contacts and associated systems and methods

Solid-state transducers (“ssts”) and vertical high voltage ssts having buried contacts are disclosed herein. An sst die in accordance with a particular embodiment can include a transducer structure having a first semiconductor material at a first side of the transducer structure, and a second semiconductor material at a second side of the transducer structure. ... Micron Technology Inc

01/21/16 / #20160020322

Methods of forming strained semiconductor channels

In various method embodiments, a device region in a semiconductor substrate and isolation regions adjacent to the device region are defined. The device region has a channel region and the isolation regions have strain-inducing regions laterally adjacent to the channel regions. ... Micron Technology Inc

01/21/16 / #20160020256

Memory cell with independently-sized elements

Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element formed in series with the switch element. ... Micron Technology Inc

01/21/16 / #20160020218

Multi-tiered semiconductor devices and associated methods

Methods of fabricating multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, a first dielectric is formed, and a second dielectric is formed in contact with the first dielectric. ... Micron Technology Inc

01/21/16 / #20160020129

Methods for temporarily bonding a device wafer to a carrier wafer, and related assemblies

A method of bonding a device wafer to a carrier wafer includes disposing a first adhesive over a central portion of a carrier wafer, the first adhesive having a first glass transition temperature, disposing a second adhesive over a peripheral portion of the carrier wafer, the second adhesive having a second glass transition temperature greater than the first glass transition temperature, and bonding the first adhesive to active front side of the device wafer and the second adhesive to a peripheral portion of the front side of the device wafer. Related assemblies may be used in such methods.. ... Micron Technology Inc

01/21/16 / #20160019974

Memory refresh methods and apparatuses

Apparatuses and memory refresh methods are disclosed, such as those involving checking a portion of a memory device for errors in response to the memory device being powered on, and reprogramming corrected data to the memory device if errors are found in checking the portion of the nonvolatile memory for errors. Other apparatuses and memory refresh methods are disclosed.. ... Micron Technology Inc

01/21/16 / #20160019970

Shielded vertically stacked data line architecture for memory

Apparatuses and methods are disclosed, including an apparatus that includes first and second strings of vertically stacked memory cells, and first and second pluralities of vertically stacked data lines. A data line of the first plurality of data lines is coupled to the first string through a first select device. ... Micron Technology Inc

01/21/16 / #20160019958

Descending set verify for phase change memory

Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a phase change memory.. . ... Micron Technology Inc

01/21/16 / #20160019949

Programming memories with multi-level pass signal

Memories and methods for programming memories with multi-level pass signals are provided. One method includes programming cells of the memory selected to be programmed to a particular target data state of the memory, using program disturb to program cells of the memory selected to be programmed to target data states that are lower than the particular target data state while programming cells of the memory selected to be programmed to the particular target data state, and boosting a channel voltage for cells of the memory selected to be programmed to the target data states that are lower than the particular target data state. ... Micron Technology Inc

01/21/16 / #20160019034

Method and apparatus for compiling regular expressions

Apparatus, systems, and methods for a compiler are described. One such compiler converts source code into an automaton comprising states and transitions between the states, wherein the states in the automaton include a special purpose state that corresponds to a special purpose hardware element. ... Micron Technology Inc

01/21/16 / #20160018993

Data compression and management

The present disclosure includes apparatuses and methods for data compression and management. A number of methods include receiving a number of data segments corresponding to a managed unit amount of data, determining a respective compressibility of each of the number of data segments, compressing each of the number of data segments in accordance with its respective determined compressibility, forming a compressed managed unit that includes compressed and/or uncompressed data segments corresponding to the number of data segments corresponding to the managed unit amount of data, and forming a page of data that comprises at least the compressed managed unit.. ... Micron Technology Inc

01/14/16 / #20160013404

Thermally optimized phase change memory cells and methods of fabricating the same

A thermally optimized phase change memory cell includes a phase change material element disposed between first and second electrodes. The second electrode includes a thermally insulating region having a first thermal resistivity over the first electrode and a metallic contact region interposed between the phase change material element and the thermally insulating region, where the metallic contact layer has a second thermal resistivity lower than the first thermal resistivity.. ... Micron Technology Inc

01/14/16 / #20160013360

Engineered substrates having epitaxial formation structures with enhanced shear strength and associated systems and methods

Engineered substrates having epitaxial formation structures with enhanced shear strength and associated systems and methods are disclosed herein. In several embodiments, for example, an engineered substrate can be manufactured by forming a shear strength enhancement material at a front surface of a donor substrate and implanting ions a depth into the donor substrate through the shear strength enhancement material. ... Micron Technology Inc

01/14/16 / #20160013263

Methods of forming capacitors

A method of forming capacitors includes forming support material over a substrate. A first capacitor electrode is formed within individual openings in the support material. ... Micron Technology Inc

01/14/16 / #20160013204

Memory cell profiles

Examples of the present disclosure provide devices and methods for processing a memory cell. A method embodiment includes removing a key-hole shaped column from a material, to define a profile for the memory cell. ... Micron Technology Inc

01/14/16 / #20160013173

Methods of manufacturing stacked semiconductor die assemblies with high efficiency thermal paths

Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. ... Micron Technology Inc

01/14/16 / #20160013154

Semiconductor devices comprising protected side surfaces and related methods

Methods of protecting semiconductor devices may involve forming trenches in streets between stacks of semiconductor dice on regions of a semiconductor wafer. A protective material may be positioned between the die stacks and in the trenches, after which the wafer is thinned from a side opposite the die stacks to expose the protective material in the trenches. ... Micron Technology Inc

01/14/16 / #20160013134

Semiconductor devices and methods of manufacturing semiconductor devices

Semiconductor devices and methods of manufacturing semiconductor devices. One example of a method of fabricating a semiconductor device comprises forming a conductive feature extending through a semiconductor substrate such that the conductive feature has a first end and a second end opposite the first end, and wherein the second end projects outwardly from a surface of the substrate. ... Micron Technology Inc

01/14/16 / #20160013115

Stacked semiconductor die assemblies with high efficiency thermal paths and associated methods

A semiconductor die assembly having high efficiency thermal paths. In one embodiment, the semiconductor die assembly comprises a package support substrate, a first semiconductor die having a peripheral region and a stacking region, and a second semiconductor die attached to the stacking region of the first die such that the peripheral region is lateral of the second die. ... Micron Technology Inc

01/14/16 / #20160013114

Stacked semiconductor die assemblies with high efficiency thermal paths and associated systems

Semiconductor die assemblies having high efficiency thermal paths. In one embodiment, a semiconductor die assembly comprises a package support substrate, a first semiconductor die electrically mounted to the package support substrate, and a plurality of second semiconductor dies. ... Micron Technology Inc

01/14/16 / #20160012888

Enhancing nucleation in phase-change memory cells

Various embodiments disclosed herein comprise methods and apparatuses for placing phase-change memory (pcm) cells of a memory array into a temperature regime where nucleation probability of the pcm cells is enhanced prior to applying a subsequent set programming signal. In one embodiment, the method includes applying a nucleation signal to the pcm cells to form nucleation sites within the memory array where the nucleation signal has a non-zero rising-edge. ... Micron Technology Inc

01/07/16 / #20160005968

Memory structures and arrays, and methods of forming memory structures and arrays

Some embodiments include memory structures having a diode over a memory cell. The memory cell can include programmable material between a pair of electrodes, with the programmable material containing a multivalent metal oxide directly against a high-k dielectric. ... Micron Technology Inc

01/07/16 / #20160005967

Apparatuses including electrodes having a conductive barrier material and methods of forming same

Apparatuses and methods of manufacture are disclosed for phase change memory cell electrodes having a conductive barrier material. In one example, an apparatus includes a first chalcogenide structure and a second chalcogenide structure stacked together with the first chalcogenide structure. ... Micron Technology Inc

01/07/16 / #20160005966

Methods of forming structures

Some embodiments include methods of forming structures. Spaced-apart features are formed which contain temperature-sensitive material. ... Micron Technology Inc

01/07/16 / #20160005965

Memory cells having a first selecting chalcogenide material and a second selecting chalcogenide material and methods therof

The present disclosure includes memory cells and methods of forming the same. The memory cells disclosed herein can include a first selecting chalcogenide material, a second selecting chalcogenide material, and a storage material.. ... Micron Technology Inc

01/07/16 / #20160005962

Memory cells, methods of forming memory cells and methods of forming memory arrays

Some embodiments include memory cells which have multiple programmable material structures between a pair of electrodes. One of the programmable material structures has a first edge, and another of the programmable material structures has a second edge that contacts the first edge. ... Micron Technology Inc

01/07/16 / #20160005815

Semiconductor constructions

Some embodiments include semiconductor constructions having semiconductor material patterned into two mesas spaced from one another by at least one dummy projection. The dummy projection has a width along a cross-section of x and the mesas have widths along the cross-section of at least 3x. ... Micron Technology Inc

01/07/16 / #20160005761

Data line arrangement and pillar arrangement in apparatuses

Some embodiments include an apparatus having semiconductor pillars in a substantially hexagonally closest packed arrangement. The hexagonally closest packed arrangement includes a repeating pillar pattern which has at least portions of 7 different pillars. ... Micron Technology Inc

01/07/16 / #20160005742

Semiconductor constructions, and semiconductor processing methods

Some embodiments include methods in which a pair of spaced-apart adjacent features is formed over a substrate. The features have silicon dioxide surfaces. ... Micron Technology Inc

01/07/16 / #20160005693

Semiconductor constructions

Some embodiments include a construction having conductive structures spaced from one another by intervening regions. Insulative structures are within the intervening regions. ... Micron Technology Inc

01/07/16 / #20160005601

Integrated circuit fabrication

A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. ... Micron Technology Inc

01/07/16 / #20160005474

Memory devices and programming memory arrays thereof

An embodiment of a method includes decreasing a difference of a voltage applied to a first select gate minus a voltage applied to a source while the first select gate is off, decreasing a difference of a voltage applied to a second select gate minus a voltage applied to a data line while the second select gate is off, and increasing a voltage of a signal applied to a selected access line that is coupled to an untargeted memory cell in a string of memory cells coupled to the first and second select gates to a program voltage after or substantially concurrently with decreasing the difference of the voltage applied to the first select gate minus the voltage applied to the source and with decreasing the difference of the voltage applied to the second select gate minus the voltage applied to the data line.. . ... Micron Technology Inc

01/07/16 / #20160005473

Programming of memory devices

Methods of operating a memory device include programming a page of a memory block of the memory device using a particular starting programming voltage, determining a programming voltage indicative of a programming efficiency of the page of the memory block during programming of the page of the memory block, storing a representation of the programming voltage indicative of the programming efficiency of the page of the memory block, setting a starting programming voltage for a different page of the memory block in response to the stored representation of the programming voltage indicative of the programming efficiency of the page of the memory block, and programming the different page of the memory block using its starting programming voltage.. . ... Micron Technology Inc

01/07/16 / #20160005471

Automatic word line leakage measurement circuitry

The present invention is a circuit and method for measuring leakage on the plurality of word lines in a memory device. In one embodiment, a memory device may include a leakage measurement circuit that is coupled to a plurality of word lines of the memory device. ... Micron Technology Inc

01/07/16 / #20160005467

Command signal management in integrated circuit devices

Methods of operating integrated circuit devices include logically combining an output signal indicating whether an operation is being performed with the logic level of a command signal line to generate a command signal to control circuitry of the integrated circuit device having the logic level of the command signal line when the output signal indicates that the operation is not being performed, and having a particular logic level when the output signal indicates that the operation is being performed. Integrated circuit devices include a command signal management circuit to provide a logic level of a particular command signal to control circuitry of the integrated circuit device when control signals indicate a desire to allow the particular command signal, and to provide a particular logic level to the control circuitry when the control signals indicate a desire to block the particular command signal.. ... Micron Technology Inc

01/07/16 / #20160005447

Independently addressable memory array address spaces

Examples of the present disclosure provide devices and methods for accessing a memory array address space. An example memory array comprising a first address space comprising memory cells coupled to a first number of select lines and to a number of sense lines and a second address space comprising memory cells coupled to a second number of select lines and to the number of sense lines. ... Micron Technology Inc

01/07/16 / #20160005442

Memory programming methods and memory systems

Memory programming methods and memory systems are described. One example memory programming method includes programming a plurality of main cells of a main memory and erasing a plurality of second main cells of the main memory. ... Micron Technology Inc

01/07/16 / #20160004595

Shifting read data

This disclosure relates to avoiding a hard error in memory during write time by shifting data to be programmed to memory to mask the hard error. In one implementation, a method of programming data to a memory array includes obtaining error data corresponding to a selected memory cell, shifting a data pattern such that a value to be stored by the selected memory cell matches a value associated with a hard error, and programming the shifted data pattern to memory array such that the value programmed to the selected memory cell matches the value associated with the hard error.. ... Micron Technology Inc

01/07/16 / #20160004436

Host controller

The present disclosure includes methods, devices, and systems for controlling a memory device. One method for controlling a memory device embodiment includes storing device class dependent information and a command in one or more of host system memory and host controller memory, setting a pointer to the command in a register in a host controller, directing access to the one or more of host system memory and host controller memory with the memory device via the host controller; and executing the command with the memory device.. ... Micron Technology Inc








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